Commit 3fa75c875c960b0b978c63d6ae27fad8d8a0e692
Committed by
Andy Fleming
Andy Fleming
1 parent
04bccc3ab0
Exists in
master
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53 other branches
T4/usb: move usb 2.0 utmi dual phy init code to cpu_init.c
This is what we have done for the UTMI PHY on P3041/P5020. Then the PHY initialization can be reused in kernel without “usb start” command. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Showing 2 changed files with 22 additions and 21 deletions Side-by-side Diff
arch/powerpc/cpu/mpc85xx/cpu_init.c
| ... | ... | @@ -637,6 +637,28 @@ |
| 637 | 637 | } |
| 638 | 638 | #endif |
| 639 | 639 | |
| 640 | +#if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE) | |
| 641 | + ccsr_usb_phy_t *usb_phy = | |
| 642 | + (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; | |
| 643 | + setbits_be32(&usb_phy->pllprg[1], | |
| 644 | + CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN | | |
| 645 | + CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN | | |
| 646 | + CONFIG_SYS_FSL_USB_PLLPRG2_MFI | | |
| 647 | + CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN); | |
| 648 | + setbits_be32(&usb_phy->port1.ctrl, | |
| 649 | + CONFIG_SYS_FSL_USB_CTRL_PHY_EN); | |
| 650 | + setbits_be32(&usb_phy->port1.drvvbuscfg, | |
| 651 | + CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); | |
| 652 | + setbits_be32(&usb_phy->port1.pwrfltcfg, | |
| 653 | + CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); | |
| 654 | + setbits_be32(&usb_phy->port2.ctrl, | |
| 655 | + CONFIG_SYS_FSL_USB_CTRL_PHY_EN); | |
| 656 | + setbits_be32(&usb_phy->port2.drvvbuscfg, | |
| 657 | + CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); | |
| 658 | + setbits_be32(&usb_phy->port2.pwrfltcfg, | |
| 659 | + CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); | |
| 660 | +#endif | |
| 661 | + | |
| 640 | 662 | #ifdef CONFIG_FMAN_ENET |
| 641 | 663 | fman_enet_init(); |
| 642 | 664 | #endif |
drivers/usb/host/ehci-fsl.c
| ... | ... | @@ -89,27 +89,6 @@ |
| 89 | 89 | |
| 90 | 90 | if (!strcmp(phy_type, "utmi")) { |
| 91 | 91 | #if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY) |
| 92 | -#if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE) | |
| 93 | - ccsr_usb_phy_t *usb_phy = | |
| 94 | - (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; | |
| 95 | - setbits_be32(&usb_phy->pllprg[1], | |
| 96 | - CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN | | |
| 97 | - CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN | | |
| 98 | - CONFIG_SYS_FSL_USB_PLLPRG2_MFI | | |
| 99 | - CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN); | |
| 100 | - setbits_be32(&usb_phy->port1.ctrl, | |
| 101 | - CONFIG_SYS_FSL_USB_CTRL_PHY_EN); | |
| 102 | - setbits_be32(&usb_phy->port1.drvvbuscfg, | |
| 103 | - CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); | |
| 104 | - setbits_be32(&usb_phy->port1.pwrfltcfg, | |
| 105 | - CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); | |
| 106 | - setbits_be32(&usb_phy->port2.ctrl, | |
| 107 | - CONFIG_SYS_FSL_USB_CTRL_PHY_EN); | |
| 108 | - setbits_be32(&usb_phy->port2.drvvbuscfg, | |
| 109 | - CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN); | |
| 110 | - setbits_be32(&usb_phy->port2.pwrfltcfg, | |
| 111 | - CONFIG_SYS_FSL_USB_PWRFLT_CR_EN); | |
| 112 | -#endif | |
| 113 | 92 | setbits_be32(&ehci->control, PHY_CLK_SEL_UTMI); |
| 114 | 93 | setbits_be32(&ehci->control, UTMI_PHY_EN); |
| 115 | 94 | udelay(1000); /* delay required for PHY Clk to appear */ |