Eric Lee / smarc-uboot

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Commit 3fe3b4fb1c5adb00502276312696e38e9a7e9b5b

Authored by DrEagle
Committed by Pantelis Antoniou
1 parent 25b4adbba0
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

ARM: kirkwood: add mvsdio driver 

This patch add Marvell kirkwood MVSDIO/MMC driver
and enable it for Sheevaplugs and OpenRD boards.

Signed-off-by: Gerald Kerma <drEagle@doukki.net>
Reviewed-by: Stefan Roese <sr@denx.de>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>

Showing 7 changed files with 669 additions and 0 deletions Side-by-side Diff

arch/arm/cpu/arm926ejs/kirkwood/cpu.c
Diff comments   View file @ 3fe3b4f
... ... @@ -13,6 +13,7 @@
13 13 #include <asm/io.h>
14 14 #include <asm/arch/cpu.h>
15 15 #include <asm/arch/kirkwood.h>
  16 +#include <mvebu_mmc.h>
16 17  
17 18 #define BUFLEN 16
18 19  
... ... @@ -377,4 +378,12 @@
377 378 return 0;
378 379 }
379 380 #endif
  381 +
  382 +#ifdef CONFIG_MVEBU_MMC
  383 +int board_mmc_init(bd_t *bis)
  384 +{
  385 + mvebu_mmc_init(bis);
  386 + return 0;
  387 +}
  388 +#endif /* CONFIG_MVEBU_MMC */
arch/arm/include/asm/arch-kirkwood/kirkwood.h
Diff comments   View file @ 3fe3b4f
... ... @@ -39,6 +39,7 @@
39 39 #define KW_EGIGA0_BASE (KW_REGISTER(0x72000))
40 40 #define KW_EGIGA1_BASE (KW_REGISTER(0x76000))
41 41 #define KW_SATA_BASE (KW_REGISTER(0x80000))
  42 +#define KW_SDIO_BASE (KW_REGISTER(0x90000))
42 43  
43 44 /* Kirkwood Sata controller has two ports */
44 45 #define KW_SATA_PORT0_OFFSET 0x2000
drivers/mmc/Makefile
Diff comments   View file @ 3fe3b4f
... ... @@ -37,4 +37,5 @@
37 37 else
38 38 obj-$(CONFIG_GENERIC_MMC) += mmc_write.o
39 39 endif
  40 +obj-$(CONFIG_MVEBU_MMC) += mvebu_mmc.o
drivers/mmc/mvebu_mmc.c
Diff comments   View file @ 3fe3b4f
  1 +/*
  2 + * Marvell MMC/SD/SDIO driver
  3 + *
  4 + * (C) Copyright 2012
  5 + * Marvell Semiconductor <www.marvell.com>
  6 + * Written-by: Maen Suleiman, Gerald Kerma
  7 + *
  8 + * SPDX-License-Identifier: GPL-2.0+
  9 + */
  10 +
  11 +#include <common.h>
  12 +#include <malloc.h>
  13 +#include <part.h>
  14 +#include <mmc.h>
  15 +#include <asm/io.h>
  16 +#include <asm/arch/cpu.h>
  17 +#include <asm/arch/kirkwood.h>
  18 +#include <mvebu_mmc.h>
  19 +
  20 +#define DRIVER_NAME "MVEBU_MMC"
  21 +
  22 +static void mvebu_mmc_write(u32 offs, u32 val)
  23 +{
  24 + writel(val, CONFIG_SYS_MMC_BASE + (offs));
  25 +}
  26 +
  27 +static u32 mvebu_mmc_read(u32 offs)
  28 +{
  29 + return readl(CONFIG_SYS_MMC_BASE + (offs));
  30 +}
  31 +
  32 +static int mvebu_mmc_setup_data(struct mmc_data *data)
  33 +{
  34 + u32 ctrl_reg;
  35 +
  36 + debug("%s, data %s : blocks=%d blksz=%d\n", DRIVER_NAME,
  37 + (data->flags & MMC_DATA_READ) ? "read" : "write",
  38 + data->blocks, data->blocksize);
  39 +
  40 + /* default to maximum timeout */
  41 + ctrl_reg = mvebu_mmc_read(SDIO_HOST_CTRL);
  42 + ctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX);
  43 + mvebu_mmc_write(SDIO_HOST_CTRL, ctrl_reg);
  44 +
  45 + if (data->flags & MMC_DATA_READ) {
  46 + mvebu_mmc_write(SDIO_SYS_ADDR_LOW, (u32)data->dest & 0xffff);
  47 + mvebu_mmc_write(SDIO_SYS_ADDR_HI, (u32)data->dest >> 16);
  48 + } else {
  49 + mvebu_mmc_write(SDIO_SYS_ADDR_LOW, (u32)data->src & 0xffff);
  50 + mvebu_mmc_write(SDIO_SYS_ADDR_HI, (u32)data->src >> 16);
  51 + }
  52 +
  53 + mvebu_mmc_write(SDIO_BLK_COUNT, data->blocks);
  54 + mvebu_mmc_write(SDIO_BLK_SIZE, data->blocksize);
  55 +
  56 + return 0;
  57 +}
  58 +
  59 +static int mvebu_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
  60 + struct mmc_data *data)
  61 +{
  62 + int timeout = 10;
  63 + ushort waittype = 0;
  64 + ushort resptype = 0;
  65 + ushort xfertype = 0;
  66 + ushort resp_indx = 0;
  67 +
  68 + debug("cmdidx [0x%x] resp_type[0x%x] cmdarg[0x%x]\n",
  69 + cmd->cmdidx, cmd->resp_type, cmd->cmdarg);
  70 +
  71 + udelay(10*1000);
  72 +
  73 + debug("%s: cmd %d (hw state 0x%04x)\n", DRIVER_NAME,
  74 + cmd->cmdidx, mvebu_mmc_read(SDIO_HW_STATE));
  75 +
  76 + /* Checking if card is busy */
  77 + while ((mvebu_mmc_read(SDIO_HW_STATE) & CARD_BUSY)) {
  78 + if (timeout == 0) {
  79 + printf("%s: card busy!\n", DRIVER_NAME);
  80 + return -1;
  81 + }
  82 + timeout--;
  83 + udelay(1000);
  84 + }
  85 +
  86 + /* Set up for a data transfer if we have one */
  87 + if (data) {
  88 + int err = mvebu_mmc_setup_data(data);
  89 +
  90 + if (err)
  91 + return err;
  92 + }
  93 +
  94 + resptype = SDIO_CMD_INDEX(cmd->cmdidx);
  95 +
  96 + /* Analyzing resptype/xfertype/waittype for the command */
  97 + if (cmd->resp_type & MMC_RSP_BUSY)
  98 + resptype |= SDIO_CMD_RSP_48BUSY;
  99 + else if (cmd->resp_type & MMC_RSP_136)
  100 + resptype |= SDIO_CMD_RSP_136;
  101 + else if (cmd->resp_type & MMC_RSP_PRESENT)
  102 + resptype |= SDIO_CMD_RSP_48;
  103 + else
  104 + resptype |= SDIO_CMD_RSP_NONE;
  105 +
  106 + if (cmd->resp_type & MMC_RSP_CRC)
  107 + resptype |= SDIO_CMD_CHECK_CMDCRC;
  108 +
  109 + if (cmd->resp_type & MMC_RSP_OPCODE)
  110 + resptype |= SDIO_CMD_INDX_CHECK;
  111 +
  112 + if (cmd->resp_type & MMC_RSP_PRESENT) {
  113 + resptype |= SDIO_UNEXPECTED_RESP;
  114 + waittype |= SDIO_NOR_UNEXP_RSP;
  115 + }
  116 +
  117 + if (data) {
  118 + resptype |= SDIO_CMD_DATA_PRESENT | SDIO_CMD_CHECK_DATACRC16;
  119 + xfertype |= SDIO_XFER_MODE_HW_WR_DATA_EN;
  120 + if (data->flags & MMC_DATA_READ) {
  121 + xfertype |= SDIO_XFER_MODE_TO_HOST;
  122 + waittype = SDIO_NOR_DMA_INI;
  123 + } else {
  124 + waittype |= SDIO_NOR_XFER_DONE;
  125 + }
  126 + } else {
  127 + waittype |= SDIO_NOR_CMD_DONE;
  128 + }
  129 +
  130 + /* Setting cmd arguments */
  131 + mvebu_mmc_write(SDIO_ARG_LOW, cmd->cmdarg & 0xffff);
  132 + mvebu_mmc_write(SDIO_ARG_HI, cmd->cmdarg >> 16);
  133 +
  134 + /* Setting Xfer mode */
  135 + mvebu_mmc_write(SDIO_XFER_MODE, xfertype);
  136 +
  137 + mvebu_mmc_write(SDIO_NOR_INTR_STATUS, ~SDIO_NOR_CARD_INT);
  138 + mvebu_mmc_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);
  139 +
  140 + /* Sending command */
  141 + mvebu_mmc_write(SDIO_CMD, resptype);
  142 +
  143 + mvebu_mmc_write(SDIO_NOR_INTR_EN, SDIO_POLL_MASK);
  144 + mvebu_mmc_write(SDIO_ERR_INTR_EN, SDIO_POLL_MASK);
  145 +
  146 + /* Waiting for completion */
  147 + timeout = 1000000;
  148 +
  149 + while (!((mvebu_mmc_read(SDIO_NOR_INTR_STATUS)) & waittype)) {
  150 + if (mvebu_mmc_read(SDIO_NOR_INTR_STATUS) & SDIO_NOR_ERROR) {
  151 + debug("%s: error! cmdidx : %d, err reg: %04x\n",
  152 + DRIVER_NAME, cmd->cmdidx,
  153 + mvebu_mmc_read(SDIO_ERR_INTR_STATUS));
  154 + if (mvebu_mmc_read(SDIO_ERR_INTR_STATUS) &
  155 + (SDIO_ERR_CMD_TIMEOUT | SDIO_ERR_DATA_TIMEOUT))
  156 + return TIMEOUT;
  157 + return COMM_ERR;
  158 + }
  159 +
  160 + timeout--;
  161 + udelay(1);
  162 + if (timeout <= 0) {
  163 + printf("%s: command timed out\n", DRIVER_NAME);
  164 + return TIMEOUT;
  165 + }
  166 + }
  167 +
  168 + /* Handling response */
  169 + if (cmd->resp_type & MMC_RSP_136) {
  170 + uint response[8];
  171 +
  172 + for (resp_indx = 0; resp_indx < 8; resp_indx++)
  173 + response[resp_indx]
  174 + = mvebu_mmc_read(SDIO_RSP(resp_indx));
  175 +
  176 + cmd->response[0] = ((response[0] & 0x03ff) << 22) |
  177 + ((response[1] & 0xffff) << 6) |
  178 + ((response[2] & 0xfc00) >> 10);
  179 + cmd->response[1] = ((response[2] & 0x03ff) << 22) |
  180 + ((response[3] & 0xffff) << 6) |
  181 + ((response[4] & 0xfc00) >> 10);
  182 + cmd->response[2] = ((response[4] & 0x03ff) << 22) |
  183 + ((response[5] & 0xffff) << 6) |
  184 + ((response[6] & 0xfc00) >> 10);
  185 + cmd->response[3] = ((response[6] & 0x03ff) << 22) |
  186 + ((response[7] & 0x3fff) << 8);
  187 + } else if (cmd->resp_type & MMC_RSP_PRESENT) {
  188 + uint response[3];
  189 +
  190 + for (resp_indx = 0; resp_indx < 3; resp_indx++)
  191 + response[resp_indx]
  192 + = mvebu_mmc_read(SDIO_RSP(resp_indx));
  193 +
  194 + cmd->response[0] = ((response[2] & 0x003f) << (8 - 8)) |
  195 + ((response[1] & 0xffff) << (14 - 8)) |
  196 + ((response[0] & 0x03ff) << (30 - 8));
  197 + cmd->response[1] = ((response[0] & 0xfc00) >> 10);
  198 + cmd->response[2] = 0;
  199 + cmd->response[3] = 0;
  200 + }
  201 +
  202 + debug("%s: resp[0x%x] ", DRIVER_NAME, cmd->resp_type);
  203 + debug("[0x%x] ", cmd->response[0]);
  204 + debug("[0x%x] ", cmd->response[1]);
  205 + debug("[0x%x] ", cmd->response[2]);
  206 + debug("[0x%x] ", cmd->response[3]);
  207 + debug("\n");
  208 +
  209 + return 0;
  210 +}
  211 +
  212 +static void mvebu_mmc_power_up(void)
  213 +{
  214 + debug("%s: power up\n", DRIVER_NAME);
  215 +
  216 + /* disable interrupts */
  217 + mvebu_mmc_write(SDIO_NOR_INTR_EN, 0);
  218 + mvebu_mmc_write(SDIO_ERR_INTR_EN, 0);
  219 +
  220 + /* SW reset */
  221 + mvebu_mmc_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW);
  222 +
  223 + mvebu_mmc_write(SDIO_XFER_MODE, 0);
  224 +
  225 + /* enable status */
  226 + mvebu_mmc_write(SDIO_NOR_STATUS_EN, SDIO_POLL_MASK);
  227 + mvebu_mmc_write(SDIO_ERR_STATUS_EN, SDIO_POLL_MASK);
  228 +
  229 + /* enable interrupts status */
  230 + mvebu_mmc_write(SDIO_NOR_INTR_STATUS, SDIO_POLL_MASK);
  231 + mvebu_mmc_write(SDIO_ERR_INTR_STATUS, SDIO_POLL_MASK);
  232 +}
  233 +
  234 +static void mvebu_mmc_set_clk(unsigned int clock)
  235 +{
  236 + unsigned int m;
  237 +
  238 + if (clock == 0) {
  239 + debug("%s: clock off\n", DRIVER_NAME);
  240 + mvebu_mmc_write(SDIO_XFER_MODE, SDIO_XFER_MODE_STOP_CLK);
  241 + mvebu_mmc_write(SDIO_CLK_DIV, MVEBU_MMC_BASE_DIV_MAX);
  242 + } else {
  243 + m = MVEBU_MMC_BASE_FAST_CLOCK/(2*clock) - 1;
  244 + if (m > MVEBU_MMC_BASE_DIV_MAX)
  245 + m = MVEBU_MMC_BASE_DIV_MAX;
  246 + mvebu_mmc_write(SDIO_CLK_DIV, m & MVEBU_MMC_BASE_DIV_MAX);
  247 + }
  248 +
  249 + udelay(10*1000);
  250 +}
  251 +
  252 +static void mvebu_mmc_set_bus(unsigned int bus)
  253 +{
  254 + u32 ctrl_reg = 0;
  255 +
  256 + ctrl_reg = mvebu_mmc_read(SDIO_HOST_CTRL);
  257 + ctrl_reg &= ~SDIO_HOST_CTRL_DATA_WIDTH_4_BITS;
  258 +
  259 + switch (bus) {
  260 + case 4:
  261 + ctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_4_BITS;
  262 + break;
  263 + case 1:
  264 + default:
  265 + ctrl_reg |= SDIO_HOST_CTRL_DATA_WIDTH_1_BIT;
  266 + }
  267 +
  268 + /* default transfer mode */
  269 + ctrl_reg |= SDIO_HOST_CTRL_BIG_ENDIAN;
  270 + ctrl_reg &= ~SDIO_HOST_CTRL_LSB_FIRST;
  271 +
  272 + /* default to maximum timeout */
  273 + ctrl_reg |= SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX);
  274 +
  275 + ctrl_reg |= SDIO_HOST_CTRL_PUSH_PULL_EN;
  276 +
  277 + ctrl_reg |= SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY;
  278 +
  279 + debug("%s: ctrl 0x%04x: %s %s %s\n", DRIVER_NAME, ctrl_reg,
  280 + (ctrl_reg & SDIO_HOST_CTRL_PUSH_PULL_EN) ?
  281 + "push-pull" : "open-drain",
  282 + (ctrl_reg & SDIO_HOST_CTRL_DATA_WIDTH_4_BITS) ?
  283 + "4bit-width" : "1bit-width",
  284 + (ctrl_reg & SDIO_HOST_CTRL_HI_SPEED_EN) ?
  285 + "high-speed" : "");
  286 +
  287 + mvebu_mmc_write(SDIO_HOST_CTRL, ctrl_reg);
  288 + udelay(10*1000);
  289 +}
  290 +
  291 +static void mvebu_mmc_set_ios(struct mmc *mmc)
  292 +{
  293 + debug("%s: bus[%d] clock[%d]\n", DRIVER_NAME,
  294 + mmc->bus_width, mmc->clock);
  295 + mvebu_mmc_set_bus(mmc->bus_width);
  296 + mvebu_mmc_set_clk(mmc->clock);
  297 +}
  298 +
  299 +static int mvebu_mmc_initialize(struct mmc *mmc)
  300 +{
  301 + debug("%s: mvebu_mmc_initialize", DRIVER_NAME);
  302 +
  303 + /*
  304 + * Setting host parameters
  305 + * Initial Host Ctrl : Timeout : max , Normal Speed mode,
  306 + * 4-bit data mode, Big Endian, SD memory Card, Push_pull CMD Line
  307 + */
  308 + mvebu_mmc_write(SDIO_HOST_CTRL,
  309 + SDIO_HOST_CTRL_TMOUT(SDIO_HOST_CTRL_TMOUT_MAX) |
  310 + SDIO_HOST_CTRL_DATA_WIDTH_4_BITS |
  311 + SDIO_HOST_CTRL_BIG_ENDIAN |
  312 + SDIO_HOST_CTRL_PUSH_PULL_EN |
  313 + SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY);
  314 +
  315 + mvebu_mmc_write(SDIO_CLK_CTRL, 0);
  316 +
  317 + /* enable status */
  318 + mvebu_mmc_write(SDIO_NOR_STATUS_EN, SDIO_POLL_MASK);
  319 + mvebu_mmc_write(SDIO_ERR_STATUS_EN, SDIO_POLL_MASK);
  320 +
  321 + /* disable interrupts */
  322 + mvebu_mmc_write(SDIO_NOR_INTR_EN, 0);
  323 + mvebu_mmc_write(SDIO_ERR_INTR_EN, 0);
  324 +
  325 + /* SW reset */
  326 + mvebu_mmc_write(SDIO_SW_RESET, SDIO_SW_RESET_NOW);
  327 +
  328 + udelay(10*1000);
  329 +
  330 + return 0;
  331 +}
  332 +
  333 +static const struct mmc_ops mvebu_mmc_ops = {
  334 + .send_cmd = mvebu_mmc_send_cmd,
  335 + .set_ios = mvebu_mmc_set_ios,
  336 + .init = mvebu_mmc_initialize,
  337 +};
  338 +
  339 +static struct mmc_config mvebu_mmc_cfg = {
  340 + .name = DRIVER_NAME,
  341 + .ops = &mvebu_mmc_ops,
  342 + .f_min = MVEBU_MMC_BASE_FAST_CLOCK / MVEBU_MMC_BASE_DIV_MAX,
  343 + .f_max = MVEBU_MMC_CLOCKRATE_MAX,
  344 + .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
  345 + .host_caps = MMC_MODE_4BIT | MMC_MODE_HS,
  346 + .part_type = PART_TYPE_DOS,
  347 + .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
  348 +};
  349 +
  350 +int mvebu_mmc_init(bd_t *bis)
  351 +{
  352 + struct mmc *mmc;
  353 +
  354 + mvebu_mmc_power_up();
  355 +
  356 + mmc = mmc_create(&mvebu_mmc_cfg, bis);
  357 + if (mmc == NULL)
  358 + return -1;
  359 +
  360 + return 0;
  361 +}
include/configs/openrd.h
Diff comments   View file @ 3fe3b4f
... ... @@ -49,6 +49,7 @@
49 49 #define CONFIG_CMD_DHCP
50 50 #define CONFIG_CMD_ENV
51 51 #define CONFIG_CMD_MII
  52 +#define CONFIG_CMD_MMC
52 53 #define CONFIG_CMD_NAND
53 54 #define CONFIG_CMD_PING
54 55 #define CONFIG_CMD_USB
... ... @@ -122,6 +123,13 @@
122 123 #define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
123 124 #define CONFIG_SYS_ATA_IDE1_OFFSET MV_SATA_PORT1_OFFSET
124 125 #endif /*CONFIG_MVSATA_IDE*/
  126 +
  127 +#ifdef CONFIG_CMD_MMC
  128 +#define CONFIG_MMC
  129 +#define CONFIG_GENERIC_MMC
  130 +#define CONFIG_MVEBU_MMC
  131 +#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE
  132 +#endif /* CONFIG_CMD_MMC */
125 133  
126 134 #endif /* _CONFIG_OPENRD_BASE_H */
include/configs/sheevaplug.h
Diff comments   View file @ 3fe3b4f
... ... @@ -31,6 +31,7 @@
31 31 #define CONFIG_CMD_DHCP
32 32 #define CONFIG_CMD_ENV
33 33 #define CONFIG_CMD_MII
  34 +#define CONFIG_CMD_MMC
34 35 #define CONFIG_CMD_NAND
35 36 #define CONFIG_CMD_PING
36 37 #define CONFIG_CMD_USB
... ... @@ -80,6 +81,16 @@
80 81 #define CONFIG_MVGBE_PORTS {1, 0} /* enable port 0 only */
81 82 #define CONFIG_PHY_BASE_ADR 0
82 83 #endif /* CONFIG_CMD_NET */
  84 +
  85 +/*
  86 + * SDIO/MMC Card Configuration
  87 + */
  88 +#ifdef CONFIG_CMD_MMC
  89 +#define CONFIG_MMC
  90 +#define CONFIG_GENERIC_MMC
  91 +#define CONFIG_MVEBU_MMC
  92 +#define CONFIG_SYS_MMC_BASE KW_SDIO_BASE
  93 +#endif /* CONFIG_CMD_MMC */
83 94  
84 95 /*
85 96 * File system
  1 +/*
  2 + * Marvell MMC/SD/SDIO driver
  3 + *
  4 + * (C) Copyright 2012
  5 + * Marvell Semiconductor <www.marvell.com>
  6 + * Written-by: Maen Suleiman, Gerald Kerma
  7 + *
  8 + * SPDX-License-Identifier: GPL-2.0+
  9 + */
  10 +
  11 +#ifndef __MVEBU_MMC_H__
  12 +#define __MVEBU_MMC_H__
  13 +
  14 +/* needed for the mmc_cfg definition */
  15 +#include <mmc.h>
  16 +
  17 +#define MMC_BLOCK_SIZE 512
  18 +
  19 +/*
  20 + * Clock rates
  21 + */
  22 +
  23 +#define MVEBU_MMC_CLOCKRATE_MAX 50000000
  24 +#define MVEBU_MMC_BASE_DIV_MAX 0x7ff
  25 +#define MVEBU_MMC_BASE_FAST_CLOCK CONFIG_SYS_TCLK
  26 +#define MVEBU_MMC_BASE_FAST_CLK_100 100000000
  27 +#define MVEBU_MMC_BASE_FAST_CLK_200 200000000
  28 +
  29 +/* SDIO register */
  30 +#define SDIO_SYS_ADDR_LOW 0x000
  31 +#define SDIO_SYS_ADDR_HI 0x004
  32 +#define SDIO_BLK_SIZE 0x008
  33 +#define SDIO_BLK_COUNT 0x00c
  34 +#define SDIO_ARG_LOW 0x010
  35 +#define SDIO_ARG_HI 0x014
  36 +#define SDIO_XFER_MODE 0x018
  37 +#define SDIO_CMD 0x01c
  38 +#define SDIO_RSP(i) (0x020 + ((i)<<2))
  39 +#define SDIO_RSP0 0x020
  40 +#define SDIO_RSP1 0x024
  41 +#define SDIO_RSP2 0x028
  42 +#define SDIO_RSP3 0x02c
  43 +#define SDIO_RSP4 0x030
  44 +#define SDIO_RSP5 0x034
  45 +#define SDIO_RSP6 0x038
  46 +#define SDIO_RSP7 0x03c
  47 +#define SDIO_BUF_DATA_PORT 0x040
  48 +#define SDIO_RSVED 0x044
  49 +#define SDIO_HW_STATE 0x048
  50 +#define SDIO_PRESENT_STATE0 0x048
  51 +#define SDIO_PRESENT_STATE1 0x04c
  52 +#define SDIO_HOST_CTRL 0x050
  53 +#define SDIO_BLK_GAP_CTRL 0x054
  54 +#define SDIO_CLK_CTRL 0x058
  55 +#define SDIO_SW_RESET 0x05c
  56 +#define SDIO_NOR_INTR_STATUS 0x060
  57 +#define SDIO_ERR_INTR_STATUS 0x064
  58 +#define SDIO_NOR_STATUS_EN 0x068
  59 +#define SDIO_ERR_STATUS_EN 0x06c
  60 +#define SDIO_NOR_INTR_EN 0x070
  61 +#define SDIO_ERR_INTR_EN 0x074
  62 +#define SDIO_AUTOCMD12_ERR_STATUS 0x078
  63 +#define SDIO_CURR_BYTE_LEFT 0x07c
  64 +#define SDIO_CURR_BLK_LEFT 0x080
  65 +#define SDIO_AUTOCMD12_ARG_LOW 0x084
  66 +#define SDIO_AUTOCMD12_ARG_HI 0x088
  67 +#define SDIO_AUTOCMD12_INDEX 0x08c
  68 +#define SDIO_AUTO_RSP(i) (0x090 + ((i)<<2))
  69 +#define SDIO_AUTO_RSP0 0x090
  70 +#define SDIO_AUTO_RSP1 0x094
  71 +#define SDIO_AUTO_RSP2 0x098
  72 +#define SDIO_CLK_DIV 0x128
  73 +
  74 +#define WINDOW_CTRL(i) (0x108 + ((i) << 3))
  75 +#define WINDOW_BASE(i) (0x10c + ((i) << 3))
  76 +
  77 +/* SDIO_PRESENT_STATE */
  78 +#define CARD_BUSY (1 << 1)
  79 +#define CMD_INHIBIT (1 << 0)
  80 +#define CMD_TXACTIVE (1 << 8)
  81 +#define CMD_RXACTIVE (1 << 9)
  82 +#define CMD_AUTOCMD12ACTIVE (1 << 14)
  83 +#define CMD_BUS_BUSY (CMD_AUTOCMD12ACTIVE | \
  84 + CMD_RXACTIVE | \
  85 + CMD_TXACTIVE | \
  86 + CMD_INHIBIT | \
  87 + CARD_BUSY)
  88 +
  89 +/*
  90 + * SDIO_CMD
  91 + */
  92 +
  93 +#define SDIO_CMD_RSP_NONE (0 << 0)
  94 +#define SDIO_CMD_RSP_136 (1 << 0)
  95 +#define SDIO_CMD_RSP_48 (2 << 0)
  96 +#define SDIO_CMD_RSP_48BUSY (3 << 0)
  97 +
  98 +#define SDIO_CMD_CHECK_DATACRC16 (1 << 2)
  99 +#define SDIO_CMD_CHECK_CMDCRC (1 << 3)
  100 +#define SDIO_CMD_INDX_CHECK (1 << 4)
  101 +#define SDIO_CMD_DATA_PRESENT (1 << 5)
  102 +#define SDIO_UNEXPECTED_RESP (1 << 7)
  103 +
  104 +#define SDIO_CMD_INDEX(x) ((x) << 8)
  105 +
  106 +/*
  107 + * SDIO_XFER_MODE
  108 + */
  109 +
  110 +#define SDIO_XFER_MODE_STOP_CLK (1 << 5)
  111 +#define SDIO_XFER_MODE_HW_WR_DATA_EN (1 << 1)
  112 +#define SDIO_XFER_MODE_AUTO_CMD12 (1 << 2)
  113 +#define SDIO_XFER_MODE_INT_CHK_EN (1 << 3)
  114 +#define SDIO_XFER_MODE_TO_HOST (1 << 4)
  115 +#define SDIO_XFER_MODE_DMA (0 << 6)
  116 +
  117 +/*
  118 + * SDIO_HOST_CTRL
  119 + */
  120 +
  121 +#define SDIO_HOST_CTRL_PUSH_PULL_EN (1 << 0)
  122 +
  123 +#define SDIO_HOST_CTRL_CARD_TYPE_MEM_ONLY (0 << 1)
  124 +#define SDIO_HOST_CTRL_CARD_TYPE_IO_ONLY (1 << 1)
  125 +#define SDIO_HOST_CTRL_CARD_TYPE_IO_MEM_COMBO (2 << 1)
  126 +#define SDIO_HOST_CTRL_CARD_TYPE_IO_MMC (3 << 1)
  127 +#define SDIO_HOST_CTRL_CARD_TYPE_MASK (3 << 1)
  128 +
  129 +#define SDIO_HOST_CTRL_BIG_ENDIAN (1 << 3)
  130 +#define SDIO_HOST_CTRL_LSB_FIRST (1 << 4)
  131 +#define SDIO_HOST_CTRL_DATA_WIDTH_1_BIT (0 << 9)
  132 +#define SDIO_HOST_CTRL_DATA_WIDTH_4_BITS (1 << 9)
  133 +#define SDIO_HOST_CTRL_HI_SPEED_EN (1 << 10)
  134 +
  135 +#define SDIO_HOST_CTRL_TMOUT_MAX 0xf
  136 +#define SDIO_HOST_CTRL_TMOUT_MASK (0xf << 11)
  137 +#define SDIO_HOST_CTRL_TMOUT(x) ((x) << 11)
  138 +#define SDIO_HOST_CTRL_TMOUT_EN (1 << 15)
  139 +
  140 +/*
  141 + * SDIO_SW_RESET
  142 + */
  143 +
  144 +#define SDIO_SW_RESET_NOW (1 << 8)
  145 +
  146 +/*
  147 + * Normal interrupt status bits
  148 + */
  149 +
  150 +#define SDIO_NOR_ERROR (1 << 15)
  151 +#define SDIO_NOR_UNEXP_RSP (1 << 14)
  152 +#define SDIO_NOR_AUTOCMD12_DONE (1 << 13)
  153 +#define SDIO_NOR_SUSPEND_ON (1 << 12)
  154 +#define SDIO_NOR_LMB_FF_8W_AVAIL (1 << 11)
  155 +#define SDIO_NOR_LMB_FF_8W_FILLED (1 << 10)
  156 +#define SDIO_NOR_READ_WAIT_ON (1 << 9)
  157 +#define SDIO_NOR_CARD_INT (1 << 8)
  158 +#define SDIO_NOR_READ_READY (1 << 5)
  159 +#define SDIO_NOR_WRITE_READY (1 << 4)
  160 +#define SDIO_NOR_DMA_INI (1 << 3)
  161 +#define SDIO_NOR_BLK_GAP_EVT (1 << 2)
  162 +#define SDIO_NOR_XFER_DONE (1 << 1)
  163 +#define SDIO_NOR_CMD_DONE (1 << 0)
  164 +
  165 +/*
  166 + * Error status bits
  167 + */
  168 +
  169 +#define SDIO_ERR_CRC_STATUS (1 << 14)
  170 +#define SDIO_ERR_CRC_STARTBIT (1 << 13)
  171 +#define SDIO_ERR_CRC_ENDBIT (1 << 12)
  172 +#define SDIO_ERR_RESP_TBIT (1 << 11)
  173 +#define SDIO_ERR_XFER_SIZE (1 << 10)
  174 +#define SDIO_ERR_CMD_STARTBIT (1 << 9)
  175 +#define SDIO_ERR_AUTOCMD12 (1 << 8)
  176 +#define SDIO_ERR_DATA_ENDBIT (1 << 6)
  177 +#define SDIO_ERR_DATA_CRC (1 << 5)
  178 +#define SDIO_ERR_DATA_TIMEOUT (1 << 4)
  179 +#define SDIO_ERR_CMD_INDEX (1 << 3)
  180 +#define SDIO_ERR_CMD_ENDBIT (1 << 2)
  181 +#define SDIO_ERR_CMD_CRC (1 << 1)
  182 +#define SDIO_ERR_CMD_TIMEOUT (1 << 0)
  183 +/* enable all for polling */
  184 +#define SDIO_POLL_MASK 0xffff
  185 +
  186 +/*
  187 + * CMD12 error status bits
  188 + */
  189 +
  190 +#define SDIO_AUTOCMD12_ERR_NOTEXE (1 << 0)
  191 +#define SDIO_AUTOCMD12_ERR_TIMEOUT (1 << 1)
  192 +#define SDIO_AUTOCMD12_ERR_CRC (1 << 2)
  193 +#define SDIO_AUTOCMD12_ERR_ENDBIT (1 << 3)
  194 +#define SDIO_AUTOCMD12_ERR_INDEX (1 << 4)
  195 +#define SDIO_AUTOCMD12_ERR_RESP_T_BIT (1 << 5)
  196 +#define SDIO_AUTOCMD12_ERR_RESP_STARTBIT (1 << 6)
  197 +
  198 +#define MMC_RSP_PRESENT (1 << 0)
  199 +/* 136 bit response */
  200 +#define MMC_RSP_136 (1 << 1)
  201 +/* expect valid crc */
  202 +#define MMC_RSP_CRC (1 << 2)
  203 +/* card may send busy */
  204 +#define MMC_RSP_BUSY (1 << 3)
  205 +/* response contains opcode */
  206 +#define MMC_RSP_OPCODE (1 << 4)
  207 +
  208 +#define MMC_BUSMODE_OPENDRAIN 1
  209 +#define MMC_BUSMODE_PUSHPULL 2
  210 +
  211 +#define MMC_BUS_WIDTH_1 0
  212 +#define MMC_BUS_WIDTH_4 2
  213 +#define MMC_BUS_WIDTH_8 3
  214 +
  215 +/* Can the host do 4 bit transfers */
  216 +#define MMC_CAP_4_BIT_DATA (1 << 0)
  217 +/* Can do MMC high-speed timing */
  218 +#define MMC_CAP_MMC_HIGHSPEED (1 << 1)
  219 +/* Can do SD high-speed timing */
  220 +#define MMC_CAP_SD_HIGHSPEED (1 << 2)
  221 +/* Can signal pending SDIO IRQs */
  222 +#define MMC_CAP_SDIO_IRQ (1 << 3)
  223 +/* Talks only SPI protocols */
  224 +#define MMC_CAP_SPI (1 << 4)
  225 +/* Needs polling for card-detection */
  226 +#define MMC_CAP_NEEDS_POLL (1 << 5)
  227 +/* Can the host do 8 bit transfers */
  228 +#define MMC_CAP_8_BIT_DATA (1 << 6)
  229 +
  230 +/* Nonremovable e.g. eMMC */
  231 +#define MMC_CAP_NONREMOVABLE (1 << 8)
  232 +/* Waits while card is busy */
  233 +#define MMC_CAP_WAIT_WHILE_BUSY (1 << 9)
  234 +/* Allow erase/trim commands */
  235 +#define MMC_CAP_ERASE (1 << 10)
  236 +/* can support DDR mode at 1.8V */
  237 +#define MMC_CAP_1_8V_DDR (1 << 11)
  238 +/* can support DDR mode at 1.2V */
  239 +#define MMC_CAP_1_2V_DDR (1 << 12)
  240 +/* Can power off after boot */
  241 +#define MMC_CAP_POWER_OFF_CARD (1 << 13)
  242 +/* CMD14/CMD19 bus width ok */
  243 +#define MMC_CAP_BUS_WIDTH_TEST (1 << 14)
  244 +/* Host supports UHS SDR12 mode */
  245 +#define MMC_CAP_UHS_SDR12 (1 << 15)
  246 +/* Host supports UHS SDR25 mode */
  247 +#define MMC_CAP_UHS_SDR25 (1 << 16)
  248 +/* Host supports UHS SDR50 mode */
  249 +#define MMC_CAP_UHS_SDR50 (1 << 17)
  250 +/* Host supports UHS SDR104 mode */
  251 +#define MMC_CAP_UHS_SDR104 (1 << 18)
  252 +/* Host supports UHS DDR50 mode */
  253 +#define MMC_CAP_UHS_DDR50 (1 << 19)
  254 +/* Host supports Driver Type A */
  255 +#define MMC_CAP_DRIVER_TYPE_A (1 << 23)
  256 +/* Host supports Driver Type C */
  257 +#define MMC_CAP_DRIVER_TYPE_C (1 << 24)
  258 +/* Host supports Driver Type D */
  259 +#define MMC_CAP_DRIVER_TYPE_D (1 << 25)
  260 +/* CMD23 supported. */
  261 +#define MMC_CAP_CMD23 (1 << 30)
  262 +/* Hardware reset */
  263 +#define MMC_CAP_HW_RESET (1 << 31)
  264 +
  265 +struct mvebu_mmc_cfg {
  266 + u32 mvebu_mmc_base;
  267 + u32 mvebu_mmc_clk;
  268 + u8 max_bus_width;
  269 + struct mmc_config cfg;
  270 +};
  271 +
  272 +/*
  273 + * Functions prototypes
  274 + */
  275 +
  276 +int mvebu_mmc_init(bd_t *bis);
  277 +
  278 +#endif /* __MVEBU_MMC_H__ */