Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit 406e94c21e1b393bcdbcbaa971db749bf2cfec10

Authored by Ye Li
1 parent 795f90f99b
Exists in smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga and in 5 other branches smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga

MLK-18288 imx8mm_evk: Fix USDHC2 CD issue 

The CD pin on SD2 socket is not connected by hardware, because this pin
is used as ALERT pin of PTN5110. So we have to use DAT3 for CD detection.

Since the USDHC driver does not support using DAT3 for CD, we have set this
port to non-removable in DTS. In SPL, we switch the pad setting of DAT3 for
CD detecting.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit a5dd1efd639e65e026b3175735329a3aaaaab7a0)

Showing 1 changed file with 42 additions and 20 deletions Side-by-side Diff

board/freescale/imx8mm_evk/spl.c
Diff comments   View file @ 406e94c
... ... @@ -30,29 +30,12 @@
30 30 ddr_init();
31 31 }
32 32  
33   -#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
  33 +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 18)
34 34 #define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
35 35  
36   -int board_mmc_getcd(struct mmc *mmc)
37   -{
38   - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
39   - int ret = 0;
40   -
41   - switch (cfg->esdhc_base) {
42   - case USDHC3_BASE_ADDR:
43   - ret = 1;
44   - break;
45   - case USDHC2_BASE_ADDR:
46   - ret = !gpio_get_value(USDHC2_CD_GPIO);
47   - return ret;
48   - }
49   -
50   - return 1;
51   -}
52   -
53 36 #define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE |PAD_CTL_PE | \
54 37 PAD_CTL_FSEL2)
55   -#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PE | PAD_CTL_DSE1)
  38 +#define USDHC_GPIO_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_DSE1)
56 39  
57 40 static iomux_v3_cfg_t const usdhc3_pads[] = {
58 41 IMX8MM_PAD_NAND_WE_B_USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
59 42  
... ... @@ -74,10 +57,21 @@
74 57 IMX8MM_PAD_SD2_DATA1_USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
75 58 IMX8MM_PAD_SD2_DATA2_USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
76 59 IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
77   - IMX8MM_PAD_SD2_CD_B_GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
78 60 IMX8MM_PAD_SD2_RESET_B_GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
79 61 };
80 62  
  63 +/*
  64 + * The evk board uses DAT3 to detect CD card plugin,
  65 + * in u-boot we mux the pin to GPIO when doing board_mmc_getcd.
  66 + */
  67 +static iomux_v3_cfg_t const usdhc2_cd_pad =
  68 + IMX8MM_PAD_SD2_DATA3_GPIO2_IO18 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL);
  69 +
  70 +static iomux_v3_cfg_t const usdhc2_dat3_pad =
  71 + IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 |
  72 + MUX_PAD_CTRL(USDHC_PAD_CTRL);
  73 +
  74 +
81 75 static struct fsl_esdhc_cfg usdhc_cfg[2] = {
82 76 {USDHC2_BASE_ADDR, 0, 1},
83 77 {USDHC3_BASE_ADDR, 0, 1},
... ... @@ -121,6 +115,34 @@
121 115  
122 116 return 0;
123 117 }
  118 +
  119 +int board_mmc_getcd(struct mmc *mmc)
  120 +{
  121 + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  122 + int ret = 0;
  123 +
  124 + switch (cfg->esdhc_base) {
  125 + case USDHC3_BASE_ADDR:
  126 + ret = 1;
  127 + break;
  128 + case USDHC2_BASE_ADDR:
  129 + imx_iomux_v3_setup_pad(usdhc2_cd_pad);
  130 + gpio_request(USDHC2_CD_GPIO, "usdhc2 cd");
  131 + gpio_direction_input(USDHC2_CD_GPIO);
  132 +
  133 + /*
  134 + * Since it is the DAT3 pin, this pin is pulled to
  135 + * low voltage if no card
  136 + */
  137 + ret = gpio_get_value(USDHC2_CD_GPIO);
  138 +
  139 + imx_iomux_v3_setup_pad(usdhc2_dat3_pad);
  140 + return ret;
  141 + }
  142 +
  143 + return 1;
  144 +}
  145 +
124 146  
125 147 void spl_board_init(void)
126 148 {