Eric Lee / smarc-uboot

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Commit 40df6b3e1882c55dd34b9177a42e21a591d668ee

Authored by Tom Rini
2 parents f4df1f7678 f369e1564c
Exists in smarc_8mq_lf_v2020.04 and in 11 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

Merge git://git.denx.de/u-boot-socfpga

Showing 25 changed files Side-by-side Diff

arch/arm/dts/Makefile
Diff comments   View file @ 40df6b3
... ... @@ -193,6 +193,7 @@
193 193 socfpga_cyclone5_sockit.dtb \
194 194 socfpga_cyclone5_socrates.dtb \
195 195 socfpga_cyclone5_sr1500.dtb \
  196 + socfpga_stratix10_socdk.dtb \
196 197 socfpga_cyclone5_vining_fpga.dtb
197 198  
198 199 dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \
arch/arm/dts/socfpga.dtsi
Diff comments   View file @ 40df6b3
... ... @@ -14,6 +14,10 @@
14 14 aliases {
15 15 ethernet0 = &gmac0;
16 16 ethernet1 = &gmac1;
  17 + i2c0 = &i2c0;
  18 + i2c1 = &i2c1;
  19 + i2c2 = &i2c2;
  20 + i2c3 = &i2c3;
17 21 serial0 = &uart0;
18 22 serial1 = &uart1;
19 23 timer0 = &timer0;
... ... @@ -505,6 +509,8 @@
505 509 compatible = "snps,designware-i2c";
506 510 reg = <0xffc04000 0x1000>;
507 511 clocks = <&l4_sp_clk>;
  512 + resets = <&rst I2C0_RESET>;
  513 + reset-names = "i2c";
508 514 interrupts = <0 158 0x4>;
509 515 status = "disabled";
510 516 };
... ... @@ -515,6 +521,8 @@
515 521 compatible = "snps,designware-i2c";
516 522 reg = <0xffc05000 0x1000>;
517 523 clocks = <&l4_sp_clk>;
  524 + resets = <&rst I2C1_RESET>;
  525 + reset-names = "i2c";
518 526 interrupts = <0 159 0x4>;
519 527 status = "disabled";
520 528 };
... ... @@ -525,6 +533,8 @@
525 533 compatible = "snps,designware-i2c";
526 534 reg = <0xffc06000 0x1000>;
527 535 clocks = <&l4_sp_clk>;
  536 + resets = <&rst I2C2_RESET>;
  537 + reset-names = "i2c";
528 538 interrupts = <0 160 0x4>;
529 539 status = "disabled";
530 540 };
... ... @@ -535,6 +545,8 @@
535 545 compatible = "snps,designware-i2c";
536 546 reg = <0xffc07000 0x1000>;
537 547 clocks = <&l4_sp_clk>;
  548 + resets = <&rst I2C3_RESET>;
  549 + reset-names = "i2c";
538 550 interrupts = <0 161 0x4>;
539 551 status = "disabled";
540 552 };
arch/arm/dts/socfpga_cyclone5_de0_nano_soc.dts
Diff comments   View file @ 40df6b3
... ... @@ -56,6 +56,18 @@
56 56 status = "okay";
57 57 };
58 58  
  59 +&i2c0 {
  60 + status = "okay";
  61 +
  62 + dxl345: adxl345@0 {
  63 + compatible = "adi,adxl345";
  64 + reg = <0x53>;
  65 +
  66 + interrupt-parent = <&portc>;
  67 + interrupts = <3 2>;
  68 + };
  69 +};
  70 +
59 71 &mmc0 {
60 72 status = "okay";
61 73 u-boot,dm-pre-reloc;
arch/arm/dts/socfpga_stratix10.dtsi
Diff comments   View file @ 40df6b3
  1 +/*
  2 + * Copyright (C) 2018 Intel Corporation
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0
  5 + */
  6 +
  7 +/dts-v1/;
  8 +#include <dt-bindings/reset/altr,rst-mgr-s10.h>
  9 +#include <dt-bindings/gpio/gpio.h>
  10 +
  11 +/ {
  12 + compatible = "altr,socfpga-stratix10";
  13 + #address-cells = <2>;
  14 + #size-cells = <2>;
  15 +
  16 + cpus {
  17 + #address-cells = <1>;
  18 + #size-cells = <0>;
  19 +
  20 + cpu0: cpu@0 {
  21 + compatible = "arm,cortex-a53", "arm,armv8";
  22 + device_type = "cpu";
  23 + enable-method = "psci";
  24 + reg = <0x0>;
  25 + };
  26 +
  27 + cpu1: cpu@1 {
  28 + compatible = "arm,cortex-a53", "arm,armv8";
  29 + device_type = "cpu";
  30 + enable-method = "psci";
  31 + reg = <0x1>;
  32 + };
  33 +
  34 + cpu2: cpu@2 {
  35 + compatible = "arm,cortex-a53", "arm,armv8";
  36 + device_type = "cpu";
  37 + enable-method = "psci";
  38 + reg = <0x2>;
  39 + };
  40 +
  41 + cpu3: cpu@3 {
  42 + compatible = "arm,cortex-a53", "arm,armv8";
  43 + device_type = "cpu";
  44 + enable-method = "psci";
  45 + reg = <0x3>;
  46 + };
  47 + };
  48 +
  49 + pmu {
  50 + compatible = "arm,armv8-pmuv3";
  51 + interrupts = <0 120 8>,
  52 + <0 121 8>,
  53 + <0 122 8>,
  54 + <0 123 8>;
  55 + interrupt-affinity = <&cpu0>,
  56 + <&cpu1>,
  57 + <&cpu2>,
  58 + <&cpu3>;
  59 + interrupt-parent = <&intc>;
  60 + };
  61 +
  62 + psci {
  63 + compatible = "arm,psci-0.2";
  64 + method = "smc";
  65 + };
  66 +
  67 + intc: intc@fffc1000 {
  68 + compatible = "arm,gic-400", "arm,cortex-a15-gic";
  69 + #interrupt-cells = <3>;
  70 + interrupt-controller;
  71 + reg = <0x0 0xfffc1000 0x0 0x1000>,
  72 + <0x0 0xfffc2000 0x0 0x2000>,
  73 + <0x0 0xfffc4000 0x0 0x2000>,
  74 + <0x0 0xfffc6000 0x0 0x2000>;
  75 + };
  76 +
  77 + soc {
  78 + #address-cells = <1>;
  79 + #size-cells = <1>;
  80 + compatible = "simple-bus";
  81 + device_type = "soc";
  82 + interrupt-parent = <&intc>;
  83 + ranges = <0 0 0 0xffffffff>;
  84 +
  85 + clkmgr@ffd1000 {
  86 + compatible = "altr,clk-mgr";
  87 + reg = <0xffd10000 0x1000>;
  88 + };
  89 +
  90 + gmac0: ethernet@ff800000 {
  91 + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
  92 + reg = <0xff800000 0x2000>;
  93 + interrupts = <0 90 4>;
  94 + interrupt-names = "macirq";
  95 + mac-address = [00 00 00 00 00 00];
  96 + resets = <&rst EMAC0_RESET>;
  97 + reset-names = "stmmaceth";
  98 + status = "disabled";
  99 + };
  100 +
  101 + gmac1: ethernet@ff802000 {
  102 + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
  103 + reg = <0xff802000 0x2000>;
  104 + interrupts = <0 91 4>;
  105 + interrupt-names = "macirq";
  106 + mac-address = [00 00 00 00 00 00];
  107 + resets = <&rst EMAC1_RESET>;
  108 + reset-names = "stmmaceth";
  109 + status = "disabled";
  110 + };
  111 +
  112 + gmac2: ethernet@ff804000 {
  113 + compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
  114 + reg = <0xff804000 0x2000>;
  115 + interrupts = <0 92 4>;
  116 + interrupt-names = "macirq";
  117 + mac-address = [00 00 00 00 00 00];
  118 + resets = <&rst EMAC2_RESET>;
  119 + reset-names = "stmmaceth";
  120 + status = "disabled";
  121 + };
  122 +
  123 + gpio0: gpio@ffc03200 {
  124 + #address-cells = <1>;
  125 + #size-cells = <0>;
  126 + compatible = "snps,dw-apb-gpio";
  127 + reg = <0xffc03200 0x100>;
  128 + resets = <&rst GPIO0_RESET>;
  129 + status = "disabled";
  130 +
  131 + porta: gpio-controller@0 {
  132 + compatible = "snps,dw-apb-gpio-port";
  133 + gpio-controller;
  134 + #gpio-cells = <2>;
  135 + snps,nr-gpios = <24>;
  136 + reg = <0>;
  137 + interrupt-controller;
  138 + #interrupt-cells = <2>;
  139 + interrupts = <0 110 4>;
  140 + };
  141 + };
  142 +
  143 + gpio1: gpio@ffc03300 {
  144 + #address-cells = <1>;
  145 + #size-cells = <0>;
  146 + compatible = "snps,dw-apb-gpio";
  147 + reg = <0xffc03300 0x100>;
  148 + resets = <&rst GPIO1_RESET>;
  149 + status = "disabled";
  150 +
  151 + portb: gpio-controller@0 {
  152 + compatible = "snps,dw-apb-gpio-port";
  153 + gpio-controller;
  154 + #gpio-cells = <2>;
  155 + snps,nr-gpios = <24>;
  156 + reg = <0>;
  157 + interrupt-controller;
  158 + #interrupt-cells = <2>;
  159 + interrupts = <0 111 4>;
  160 + };
  161 + };
  162 +
  163 + i2c0: i2c@ffc02800 {
  164 + #address-cells = <1>;
  165 + #size-cells = <0>;
  166 + compatible = "snps,designware-i2c";
  167 + reg = <0xffc02800 0x100>;
  168 + interrupts = <0 103 4>;
  169 + resets = <&rst I2C0_RESET>;
  170 + status = "disabled";
  171 + };
  172 +
  173 + i2c1: i2c@ffc02900 {
  174 + #address-cells = <1>;
  175 + #size-cells = <0>;
  176 + compatible = "snps,designware-i2c";
  177 + reg = <0xffc02900 0x100>;
  178 + interrupts = <0 104 4>;
  179 + resets = <&rst I2C1_RESET>;
  180 + status = "disabled";
  181 + };
  182 +
  183 + i2c2: i2c@ffc02a00 {
  184 + #address-cells = <1>;
  185 + #size-cells = <0>;
  186 + compatible = "snps,designware-i2c";
  187 + reg = <0xffc02a00 0x100>;
  188 + interrupts = <0 105 4>;
  189 + resets = <&rst I2C2_RESET>;
  190 + status = "disabled";
  191 + };
  192 +
  193 + i2c3: i2c@ffc02b00 {
  194 + #address-cells = <1>;
  195 + #size-cells = <0>;
  196 + compatible = "snps,designware-i2c";
  197 + reg = <0xffc02b00 0x100>;
  198 + interrupts = <0 106 4>;
  199 + resets = <&rst I2C3_RESET>;
  200 + status = "disabled";
  201 + };
  202 +
  203 + i2c4: i2c@ffc02c00 {
  204 + #address-cells = <1>;
  205 + #size-cells = <0>;
  206 + compatible = "snps,designware-i2c";
  207 + reg = <0xffc02c00 0x100>;
  208 + interrupts = <0 107 4>;
  209 + resets = <&rst I2C4_RESET>;
  210 + status = "disabled";
  211 + };
  212 +
  213 + mmc: dwmmc0@ff808000 {
  214 + #address-cells = <1>;
  215 + #size-cells = <0>;
  216 + compatible = "altr,socfpga-dw-mshc";
  217 + reg = <0xff808000 0x1000>;
  218 + interrupts = <0 96 4>;
  219 + fifo-depth = <0x400>;
  220 + resets = <&rst SDMMC_RESET>;
  221 + reset-names = "reset";
  222 + status = "disabled";
  223 + };
  224 +
  225 + ocram: sram@ffe00000 {
  226 + compatible = "mmio-sram";
  227 + reg = <0xffe00000 0x100000>;
  228 + };
  229 +
  230 + rst: rstmgr@ffd11000 {
  231 + #reset-cells = <1>;
  232 + compatible = "altr,rst-mgr";
  233 + reg = <0xffd11000 0x1000>;
  234 + altr,modrst-offset = <0x20>;
  235 + };
  236 +
  237 + spi0: spi@ffda4000 {
  238 + compatible = "snps,dw-apb-ssi";
  239 + #address-cells = <1>;
  240 + #size-cells = <0>;
  241 + reg = <0xffda4000 0x1000>;
  242 + interrupts = <0 99 4>;
  243 + resets = <&rst SPIM0_RESET>;
  244 + reg-io-width = <4>;
  245 + num-chipselect = <4>;
  246 + bus-num = <0>;
  247 + status = "disabled";
  248 + };
  249 +
  250 + spi1: spi@ffda5000 {
  251 + compatible = "snps,dw-apb-ssi";
  252 + #address-cells = <1>;
  253 + #size-cells = <0>;
  254 + reg = <0xffda5000 0x1000>;
  255 + interrupts = <0 100 4>;
  256 + resets = <&rst SPIM1_RESET>;
  257 + reg-io-width = <4>;
  258 + num-chipselect = <4>;
  259 + bus-num = <0>;
  260 + status = "disabled";
  261 + };
  262 +
  263 + sysmgr: sysmgr@ffd12000 {
  264 + compatible = "altr,sys-mgr", "syscon";
  265 + reg = <0xffd12000 0x1000>;
  266 + };
  267 +
  268 + /* Local timer */
  269 + timer {
  270 + compatible = "arm,armv8-timer";
  271 + interrupts = <1 13 0xf08>,
  272 + <1 14 0xf08>,
  273 + <1 11 0xf08>,
  274 + <1 10 0xf08>;
  275 + };
  276 +
  277 + timer0: timer0@ffc03000 {
  278 + compatible = "snps,dw-apb-timer";
  279 + interrupts = <0 113 4>;
  280 + reg = <0xffc03000 0x100>;
  281 + };
  282 +
  283 + timer1: timer1@ffc03100 {
  284 + compatible = "snps,dw-apb-timer";
  285 + interrupts = <0 114 4>;
  286 + reg = <0xffc03100 0x100>;
  287 + };
  288 +
  289 + timer2: timer2@ffd00000 {
  290 + compatible = "snps,dw-apb-timer";
  291 + interrupts = <0 115 4>;
  292 + reg = <0xffd00000 0x100>;
  293 + };
  294 +
  295 + timer3: timer3@ffd00100 {
  296 + compatible = "snps,dw-apb-timer";
  297 + interrupts = <0 116 4>;
  298 + reg = <0xffd00100 0x100>;
  299 + };
  300 +
  301 + uart0: serial0@ffc02000 {
  302 + compatible = "snps,dw-apb-uart";
  303 + reg = <0xffc02000 0x100>;
  304 + interrupts = <0 108 4>;
  305 + reg-shift = <2>;
  306 + reg-io-width = <4>;
  307 + resets = <&rst UART0_RESET>;
  308 + status = "disabled";
  309 + };
  310 +
  311 + uart1: serial1@ffc02100 {
  312 + compatible = "snps,dw-apb-uart";
  313 + reg = <0xffc02100 0x100>;
  314 + interrupts = <0 109 4>;
  315 + reg-shift = <2>;
  316 + reg-io-width = <4>;
  317 + resets = <&rst UART1_RESET>;
  318 + status = "disabled";
  319 + };
  320 +
  321 + usbphy0: usbphy@0 {
  322 + #phy-cells = <0>;
  323 + compatible = "usb-nop-xceiv";
  324 + status = "okay";
  325 + };
  326 +
  327 + usb0: usb@ffb00000 {
  328 + compatible = "snps,dwc2";
  329 + reg = <0xffb00000 0x40000>;
  330 + interrupts = <0 93 4>;
  331 + phys = <&usbphy0>;
  332 + phy-names = "usb2-phy";
  333 + resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
  334 + reset-names = "dwc2", "dwc2-ecc";
  335 + status = "disabled";
  336 + };
  337 +
  338 + usb1: usb@ffb40000 {
  339 + compatible = "snps,dwc2";
  340 + reg = <0xffb40000 0x40000>;
  341 + interrupts = <0 94 4>;
  342 + phys = <&usbphy0>;
  343 + phy-names = "usb2-phy";
  344 + resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
  345 + reset-names = "dwc2", "dwc2-ecc";
  346 + status = "disabled";
  347 + };
  348 +
  349 + watchdog0: watchdog@ffd00200 {
  350 + compatible = "snps,dw-wdt";
  351 + reg = <0xffd00200 0x100>;
  352 + interrupts = <0 117 4>;
  353 + resets = <&rst WATCHDOG0_RESET>;
  354 + status = "disabled";
  355 + };
  356 +
  357 + watchdog1: watchdog@ffd00300 {
  358 + compatible = "snps,dw-wdt";
  359 + reg = <0xffd00300 0x100>;
  360 + interrupts = <0 118 4>;
  361 + resets = <&rst WATCHDOG1_RESET>;
  362 + status = "disabled";
  363 + };
  364 +
  365 + watchdog2: watchdog@ffd00400 {
  366 + compatible = "snps,dw-wdt";
  367 + reg = <0xffd00400 0x100>;
  368 + interrupts = <0 125 4>;
  369 + resets = <&rst WATCHDOG2_RESET>;
  370 + status = "disabled";
  371 + };
  372 +
  373 + watchdog3: watchdog@ffd00500 {
  374 + compatible = "snps,dw-wdt";
  375 + reg = <0xffd00500 0x100>;
  376 + interrupts = <0 126 4>;
  377 + resets = <&rst WATCHDOG3_RESET>;
  378 + status = "disabled";
  379 + };
  380 + };
  381 +};
arch/arm/dts/socfpga_stratix10_socdk.dts
Diff comments   View file @ 40df6b3
  1 +/*
  2 + * Copyright (C) 2018 Intel Corporation
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0
  5 + */
  6 +
  7 +#include "socfpga_stratix10.dtsi"
  8 +
  9 +/ {
  10 + model = "SoCFPGA Stratix 10 SoCDK";
  11 +
  12 + aliases {
  13 + serial0 = &uart0;
  14 + };
  15 +
  16 + chosen {
  17 + stdout-path = "serial0:115200n8";
  18 + };
  19 +
  20 + leds {
  21 + compatible = "gpio-leds";
  22 + hps0 {
  23 + label = "hps_led0";
  24 + gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
  25 + };
  26 +
  27 + hps1 {
  28 + label = "hps_led1";
  29 + gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
  30 + };
  31 +
  32 + hps2 {
  33 + label = "hps_led2";
  34 + gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
  35 + };
  36 + };
  37 +
  38 + memory {
  39 + device_type = "memory";
  40 + /* We expect the bootloader to fill in the reg */
  41 + reg = <0 0 0 0>;
  42 + };
  43 +};
  44 +
  45 +&gpio1 {
  46 + status = "okay";
  47 +};
  48 +
  49 +&gmac0 {
  50 + status = "okay";
  51 + phy-mode = "rgmii";
  52 + phy-handle = <&phy0>;
  53 +
  54 + max-frame-size = <3800>;
  55 +
  56 + mdio0 {
  57 + #address-cells = <1>;
  58 + #size-cells = <0>;
  59 + compatible = "snps,dwmac-mdio";
  60 + phy0: ethernet-phy@0 {
  61 + reg = <4>;
  62 +
  63 + txd0-skew-ps = <0>; /* -420ps */
  64 + txd1-skew-ps = <0>; /* -420ps */
  65 + txd2-skew-ps = <0>; /* -420ps */
  66 + txd3-skew-ps = <0>; /* -420ps */
  67 + rxd0-skew-ps = <420>; /* 0ps */
  68 + rxd1-skew-ps = <420>; /* 0ps */
  69 + rxd2-skew-ps = <420>; /* 0ps */
  70 + rxd3-skew-ps = <420>; /* 0ps */
  71 + txen-skew-ps = <0>; /* -420ps */
  72 + txc-skew-ps = <1860>; /* 960ps */
  73 + rxdv-skew-ps = <420>; /* 0ps */
  74 + rxc-skew-ps = <1680>; /* 780ps */
  75 + };
  76 + };
  77 +};
  78 +
  79 +&mmc {
  80 + status = "okay";
  81 + cap-sd-highspeed;
  82 + broken-cd;
  83 + bus-width = <4>;
  84 +};
  85 +
  86 +&uart0 {
  87 + status = "okay";
  88 +};
  89 +
  90 +&usb0 {
  91 + status = "okay";
  92 +};
arch/arm/mach-socfpga/include/mach/base_addr_s10.h
Diff comments   View file @ 40df6b3
  1 +/*
  2 + * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0
  5 + */
  6 +
  7 +#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
  8 +#define _SOCFPGA_S10_BASE_HARDWARE_H_
  9 +
  10 +#define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400
  11 +#define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf8010000
  12 +#define SOCFPGA_SDR_ADDRESS 0xf8011000
  13 +#define SOCFPGA_SMMU_ADDRESS 0xfa000000
  14 +#define SOCFPGA_MAILBOX_ADDRESS 0xffa30000
  15 +#define SOCFPGA_UART0_ADDRESS 0xffc02000
  16 +#define SOCFPGA_UART1_ADDRESS 0xffc02100
  17 +#define SOCFPGA_SPTIMER0_ADDRESS 0xffc03000
  18 +#define SOCFPGA_SPTIMER1_ADDRESS 0xffc03100
  19 +#define SOCFPGA_SYSTIMER0_ADDRESS 0xffd00000
  20 +#define SOCFPGA_SYSTIMER1_ADDRESS 0xffd00100
  21 +#define SOCFPGA_GTIMER_SEC_ADDRESS 0xffd01000
  22 +#define SOCFPGA_GTIMER_NSEC_ADDRESS 0xffd02000
  23 +#define SOCFPGA_CLKMGR_ADDRESS 0xffd10000
  24 +#define SOCFPGA_RSTMGR_ADDRESS 0xffd11000
  25 +#define SOCFPGA_SYSMGR_ADDRESS 0xffd12000
  26 +#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS 0xffd13000
  27 +#define SOCFPGA_DMANONSECURE_ADDRESS 0xffda0000
  28 +#define SOCFPGA_DMASECURE_ADDRESS 0xffda1000
  29 +#define SOCFPGA_OCRAM_ADDRESS 0xffe00000
  30 +#define GICD_BASE 0xfffc1000
  31 +#define GICC_BASE 0xfffc2000
  32 +
  33 +#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */
configs/socfpga_arria10_defconfig
Diff comments   View file @ 40df6b3
... ... @@ -17,6 +17,8 @@
17 17 CONFIG_CMD_ASKENV=y
18 18 CONFIG_CMD_GREPENV=y
19 19 # CONFIG_CMD_FLASH is not set
  20 +# CONFIG_ISO_PARTITION is not set
  21 +# CONFIG_EFI_PARTITION is not set
20 22 CONFIG_CMD_GPIO=y
21 23 CONFIG_CMD_MMC=y
22 24 CONFIG_CMD_CACHE=y
configs/socfpga_arria5_defconfig
Diff comments   View file @ 40df6b3
... ... @@ -23,6 +23,8 @@
23 23 CONFIG_CMD_GREPENV=y
24 24 CONFIG_CMD_DFU=y
25 25 # CONFIG_CMD_FLASH is not set
  26 +# CONFIG_ISO_PARTITION is not set
  27 +# CONFIG_EFI_PARTITION is not set
26 28 CONFIG_CMD_GPIO=y
27 29 CONFIG_CMD_I2C=y
28 30 CONFIG_CMD_MMC=y
... ... @@ -42,6 +44,7 @@
42 44 CONFIG_FPGA_SOCFPGA=y
43 45 CONFIG_DM_GPIO=y
44 46 CONFIG_DWAPB_GPIO=y
  47 +CONFIG_DM_I2C=y
45 48 CONFIG_SYS_I2C_DW=y
46 49 CONFIG_DM_MMC=y
47 50 CONFIG_MMC_DW=y
... ... @@ -54,6 +57,7 @@
54 57 CONFIG_PHY_MICREL_KSZ90X1=y
55 58 CONFIG_DM_ETH=y
56 59 CONFIG_ETH_DESIGNWARE=y
  60 +CONFIG_DM_RESET=y
57 61 CONFIG_SYS_NS16550=y
58 62 CONFIG_CADENCE_QSPI=y
59 63 CONFIG_DESIGNWARE_SPI=y
configs/socfpga_cyclone5_defconfig
Diff comments   View file @ 40df6b3
... ... @@ -23,6 +23,8 @@
23 23 CONFIG_CMD_GREPENV=y
24 24 CONFIG_CMD_DFU=y
25 25 # CONFIG_CMD_FLASH is not set
  26 +# CONFIG_ISO_PARTITION is not set
  27 +# CONFIG_EFI_PARTITION is not set
26 28 CONFIG_CMD_GPIO=y
27 29 CONFIG_CMD_I2C=y
28 30 CONFIG_CMD_MMC=y
... ... @@ -42,6 +44,7 @@
42 44 CONFIG_FPGA_SOCFPGA=y
43 45 CONFIG_DM_GPIO=y
44 46 CONFIG_DWAPB_GPIO=y
  47 +CONFIG_DM_I2C=y
45 48 CONFIG_SYS_I2C_DW=y
46 49 CONFIG_DM_MMC=y
47 50 CONFIG_MMC_DW=y
... ... @@ -55,6 +58,7 @@
55 58 CONFIG_PHY_MICREL_KSZ90X1=y
56 59 CONFIG_DM_ETH=y
57 60 CONFIG_ETH_DESIGNWARE=y
  61 +CONFIG_DM_RESET=y
58 62 CONFIG_SYS_NS16550=y
59 63 CONFIG_CADENCE_QSPI=y
60 64 CONFIG_DESIGNWARE_SPI=y
configs/socfpga_dbm_soc1_defconfig
Diff comments   View file @ 40df6b3
... ... @@ -24,6 +24,8 @@
24 24 CONFIG_CMD_GREPENV=y
25 25 CONFIG_CMD_DFU=y
26 26 # CONFIG_CMD_FLASH is not set
  27 +# CONFIG_ISO_PARTITION is not set
  28 +# CONFIG_EFI_PARTITION is not set
27 29 CONFIG_CMD_GPIO=y
28 30 CONFIG_CMD_I2C=y
29 31 CONFIG_CMD_MMC=y
30 32  
... ... @@ -45,12 +47,14 @@
45 47 CONFIG_FPGA_SOCFPGA=y
46 48 CONFIG_DM_GPIO=y
47 49 CONFIG_DWAPB_GPIO=y
  50 +CONFIG_DM_I2C=y
48 51 CONFIG_SYS_I2C_DW=y
49 52 CONFIG_DM_MMC=y
50 53 CONFIG_MMC_DW=y
51 54 CONFIG_DM_ETH=y
52 55 CONFIG_PHY_GIGE=y
53 56 CONFIG_ETH_DESIGNWARE=y
  57 +CONFIG_DM_RESET=y
54 58 CONFIG_SYS_NS16550=y
55 59 CONFIG_USB=y
56 60 CONFIG_DM_USB=y
configs/socfpga_de0_nano_soc_defconfig
Diff comments   View file @ 40df6b3
... ... @@ -24,6 +24,8 @@
24 24 CONFIG_CMD_GREPENV=y
25 25 CONFIG_CMD_DFU=y
26 26 # CONFIG_CMD_FLASH is not set
  27 +# CONFIG_ISO_PARTITION is not set
  28 +# CONFIG_EFI_PARTITION is not set
27 29 CONFIG_CMD_GPIO=y
28 30 CONFIG_CMD_I2C=y
29 31 CONFIG_CMD_MMC=y
... ... @@ -42,6 +44,7 @@
42 44 CONFIG_FPGA_SOCFPGA=y
43 45 CONFIG_DM_GPIO=y
44 46 CONFIG_DWAPB_GPIO=y
  47 +CONFIG_DM_I2C=y
45 48 CONFIG_SYS_I2C_DW=y
46 49 CONFIG_DM_MMC=y
47 50 CONFIG_MMC_DW=y
... ... @@ -49,6 +52,7 @@
49 52 CONFIG_PHY_MICREL_KSZ90X1=y
50 53 CONFIG_DM_ETH=y
51 54 CONFIG_ETH_DESIGNWARE=y
  55 +CONFIG_DM_RESET=y
52 56 CONFIG_SYS_NS16550=y
53 57 CONFIG_CADENCE_QSPI=y
54 58 CONFIG_DESIGNWARE_SPI=y
configs/socfpga_de10_nano_defconfig
Diff comments   View file @ 40df6b3
... ... @@ -23,6 +23,8 @@
23 23 CONFIG_CMD_GREPENV=y
24 24 CONFIG_CMD_DFU=y
25 25 # CONFIG_CMD_FLASH is not set
  26 +# CONFIG_ISO_PARTITION is not set
  27 +# CONFIG_EFI_PARTITION is not set
26 28 CONFIG_CMD_GPIO=y
27 29 CONFIG_CMD_I2C=y
28 30 CONFIG_CMD_MMC=y
... ... @@ -38,6 +40,7 @@
38 40 CONFIG_FPGA_SOCFPGA=y
39 41 CONFIG_DM_GPIO=y
40 42 CONFIG_DWAPB_GPIO=y
  43 +CONFIG_DM_I2C=y
41 44 CONFIG_SYS_I2C_DW=y
42 45 CONFIG_DM_MMC=y
43 46 CONFIG_MMC_DW=y
... ... @@ -45,6 +48,7 @@
45 48 CONFIG_PHY_MICREL_KSZ90X1=y
46 49 CONFIG_DM_ETH=y
47 50 CONFIG_ETH_DESIGNWARE=y
  51 +CONFIG_DM_RESET=y
48 52 CONFIG_SYS_NS16550=y
49 53 CONFIG_CADENCE_QSPI=y
50 54 CONFIG_DESIGNWARE_SPI=y
configs/socfpga_de1_soc_defconfig
Diff comments   View file @ 40df6b3
... ... @@ -24,6 +24,8 @@
24 24 CONFIG_CMD_ASKENV=y
25 25 CONFIG_CMD_GREPENV=y
26 26 # CONFIG_CMD_FLASH is not set
  27 +# CONFIG_ISO_PARTITION is not set
  28 +# CONFIG_EFI_PARTITION is not set
27 29 CONFIG_CMD_GPIO=y
28 30 CONFIG_CMD_I2C=y
29 31 CONFIG_CMD_MMC=y
... ... @@ -38,6 +40,7 @@
38 40 CONFIG_FPGA_SOCFPGA=y
39 41 CONFIG_DM_GPIO=y
40 42 CONFIG_DWAPB_GPIO=y
  43 +CONFIG_DM_I2C=y
41 44 CONFIG_SYS_I2C_DW=y
42 45 CONFIG_DM_MMC=y
43 46 CONFIG_MMC_DW=y
... ... @@ -45,6 +48,7 @@
45 48 CONFIG_PHY_MICREL_KSZ90X1=y
46 49 CONFIG_DM_ETH=y
47 50 CONFIG_ETH_DESIGNWARE=y
  51 +CONFIG_DM_RESET=y
48 52 CONFIG_SYS_NS16550=y
49 53 CONFIG_USB=y
50 54 CONFIG_DM_USB=y
configs/socfpga_is1_defconfig
Diff comments   View file @ 40df6b3
... ... @@ -22,6 +22,8 @@
22 22 CONFIG_CMD_ASKENV=y
23 23 CONFIG_CMD_GREPENV=y
24 24 # CONFIG_CMD_FLASH is not set
  25 +# CONFIG_ISO_PARTITION is not set
  26 +# CONFIG_EFI_PARTITION is not set
25 27 CONFIG_CMD_GPIO=y
26 28 CONFIG_CMD_I2C=y
27 29 CONFIG_CMD_SF=y
... ... @@ -40,6 +42,7 @@
40 42 CONFIG_FPGA_SOCFPGA=y
41 43 CONFIG_DM_GPIO=y
42 44 CONFIG_DWAPB_GPIO=y
  45 +CONFIG_DM_I2C=y
43 46 CONFIG_SYS_I2C_DW=y
44 47 # CONFIG_MMC is not set
45 48 CONFIG_SPI_FLASH=y
... ... @@ -49,6 +52,7 @@
49 52 CONFIG_PHY_MICREL_KSZ90X1=y
50 53 CONFIG_DM_ETH=y
51 54 CONFIG_ETH_DESIGNWARE=y
  55 +CONFIG_DM_RESET=y
52 56 CONFIG_SYS_NS16550=y
53 57 CONFIG_CADENCE_QSPI=y
configs/socfpga_mcvevk_defconfig
Diff comments   View file @ 40df6b3
... ... @@ -24,6 +24,8 @@
24 24 CONFIG_CMD_GREPENV=y
25 25 CONFIG_CMD_DFU=y
26 26 # CONFIG_CMD_FLASH is not set
  27 +# CONFIG_ISO_PARTITION is not set
  28 +# CONFIG_EFI_PARTITION is not set
27 29 CONFIG_CMD_GPIO=y
28 30 CONFIG_CMD_I2C=y
29 31 CONFIG_CMD_MMC=y
30 32  
... ... @@ -42,12 +44,14 @@
42 44 CONFIG_FPGA_SOCFPGA=y
43 45 CONFIG_DM_GPIO=y
44 46 CONFIG_DWAPB_GPIO=y
  47 +CONFIG_DM_I2C=y
45 48 CONFIG_SYS_I2C_DW=y
46 49 CONFIG_DM_MMC=y
47 50 CONFIG_MMC_DW=y
48 51 CONFIG_DM_ETH=y
49 52 CONFIG_PHY_GIGE=y
50 53 CONFIG_ETH_DESIGNWARE=y
  54 +CONFIG_DM_RESET=y
51 55 CONFIG_SYS_NS16550=y
52 56 CONFIG_CADENCE_QSPI=y
53 57 CONFIG_DESIGNWARE_SPI=y
configs/socfpga_sockit_defconfig
Diff comments   View file @ 40df6b3
... ... @@ -23,6 +23,8 @@
23 23 CONFIG_CMD_GREPENV=y
24 24 CONFIG_CMD_DFU=y
25 25 # CONFIG_CMD_FLASH is not set
  26 +# CONFIG_ISO_PARTITION is not set
  27 +# CONFIG_EFI_PARTITION is not set
26 28 CONFIG_CMD_GPIO=y
27 29 CONFIG_CMD_I2C=y
28 30 CONFIG_CMD_MMC=y
... ... @@ -42,6 +44,7 @@
42 44 CONFIG_FPGA_SOCFPGA=y
43 45 CONFIG_DM_GPIO=y
44 46 CONFIG_DWAPB_GPIO=y
  47 +CONFIG_DM_I2C=y
45 48 CONFIG_SYS_I2C_DW=y
46 49 CONFIG_DM_MMC=y
47 50 CONFIG_MMC_DW=y
... ... @@ -55,6 +58,7 @@
55 58 CONFIG_PHY_MICREL_KSZ90X1=y
56 59 CONFIG_DM_ETH=y
57 60 CONFIG_ETH_DESIGNWARE=y
  61 +CONFIG_DM_RESET=y
58 62 CONFIG_SYS_NS16550=y
59 63 CONFIG_CADENCE_QSPI=y
60 64 CONFIG_DESIGNWARE_SPI=y
configs/socfpga_socrates_defconfig
Diff comments   View file @ 40df6b3
... ... @@ -23,6 +23,8 @@
23 23 CONFIG_CMD_GREPENV=y
24 24 CONFIG_CMD_DFU=y
25 25 # CONFIG_CMD_FLASH is not set
  26 +# CONFIG_ISO_PARTITION is not set
  27 +# CONFIG_EFI_PARTITION is not set
26 28 CONFIG_CMD_GPIO=y
27 29 CONFIG_CMD_I2C=y
28 30 CONFIG_CMD_MMC=y
... ... @@ -43,6 +45,7 @@
43 45 CONFIG_FPGA_SOCFPGA=y
44 46 CONFIG_DM_GPIO=y
45 47 CONFIG_DWAPB_GPIO=y
  48 +CONFIG_DM_I2C=y
46 49 CONFIG_SYS_I2C_DW=y
47 50 CONFIG_DM_MMC=y
48 51 CONFIG_MMC_DW=y
... ... @@ -55,6 +58,7 @@
55 58 CONFIG_PHY_MICREL_KSZ90X1=y
56 59 CONFIG_DM_ETH=y
57 60 CONFIG_ETH_DESIGNWARE=y
  61 +CONFIG_DM_RESET=y
58 62 CONFIG_SYS_NS16550=y
59 63 CONFIG_CADENCE_QSPI=y
60 64 CONFIG_DESIGNWARE_SPI=y
configs/socfpga_sr1500_defconfig
Diff comments   View file @ 40df6b3
... ... @@ -25,6 +25,8 @@
25 25 CONFIG_CMD_GREPENV=y
26 26 CONFIG_CMD_MEMTEST=y
27 27 # CONFIG_CMD_FLASH is not set
  28 +# CONFIG_ISO_PARTITION is not set
  29 +# CONFIG_EFI_PARTITION is not set
28 30 CONFIG_CMD_GPIO=y
29 31 CONFIG_CMD_I2C=y
30 32 CONFIG_CMD_MMC=y
... ... @@ -44,6 +46,7 @@
44 46 CONFIG_FPGA_SOCFPGA=y
45 47 CONFIG_DM_GPIO=y
46 48 CONFIG_DWAPB_GPIO=y
  49 +CONFIG_DM_I2C=y
47 50 CONFIG_SYS_I2C_DW=y
48 51 CONFIG_DM_MMC=y
49 52 CONFIG_MMC_DW=y
... ... @@ -54,6 +57,7 @@
54 57 CONFIG_DM_ETH=y
55 58 CONFIG_PHY_GIGE=y
56 59 CONFIG_ETH_DESIGNWARE=y
  60 +CONFIG_DM_RESET=y
57 61 CONFIG_SYS_NS16550=y
58 62 CONFIG_CADENCE_QSPI=y
59 63 CONFIG_USE_TINY_PRINTF=y
configs/socfpga_vining_fpga_defconfig
Diff comments   View file @ 40df6b3
... ... @@ -26,6 +26,8 @@
26 26 CONFIG_CMD_EEPROM=y
27 27 CONFIG_CMD_DFU=y
28 28 # CONFIG_CMD_FLASH is not set
  29 +# CONFIG_ISO_PARTITION is not set
  30 +# CONFIG_EFI_PARTITION is not set
29 31 CONFIG_CMD_GPIO=y
30 32 CONFIG_CMD_I2C=y
31 33 CONFIG_CMD_MMC=y
... ... @@ -71,6 +73,7 @@
71 73 CONFIG_PHY_MICREL_KSZ90X1=y
72 74 CONFIG_DM_ETH=y
73 75 CONFIG_ETH_DESIGNWARE=y
  76 +CONFIG_DM_RESET=y
74 77 CONFIG_SYS_NS16550=y
75 78 CONFIG_CADENCE_QSPI=y
76 79 CONFIG_DESIGNWARE_SPI=y
drivers/i2c/designware_i2c.c
Diff comments   View file @ 40df6b3
... ... @@ -9,6 +9,7 @@
9 9 #include <dm.h>
10 10 #include <i2c.h>
11 11 #include <pci.h>
  12 +#include <reset.h>
12 13 #include <asm/io.h>
13 14 #include "designware_i2c.h"
14 15  
... ... @@ -34,6 +35,7 @@
34 35 struct dw_i2c {
35 36 struct i2c_regs *regs;
36 37 struct dw_scl_sda_cfg *scl_sda_cfg;
  38 + struct reset_ctl reset_ctl;
37 39 };
38 40  
39 41 #ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
... ... @@ -534,6 +536,7 @@
534 536 static int designware_i2c_probe(struct udevice *bus)
535 537 {
536 538 struct dw_i2c *priv = dev_get_priv(bus);
  539 + int ret;
537 540  
538 541 if (device_is_on_pci_bus(bus)) {
539 542 #ifdef CONFIG_DM_PCI
... ... @@ -548,6 +551,13 @@
548 551 } else {
549 552 priv->regs = (struct i2c_regs *)devfdt_get_addr_ptr(bus);
550 553 }
  554 +
  555 + ret = reset_get_by_name(bus, "i2c", &priv->reset_ctl);
  556 + if (ret)
  557 + pr_info("reset_get_by_name() failed: %d\n", ret);
  558 +
  559 + if (&priv->reset_ctl)
  560 + reset_deassert(&priv->reset_ctl);
551 561  
552 562 __dw_i2c_init(priv->regs, 0, 0);
553 563  
drivers/reset/Kconfig
Diff comments   View file @ 40df6b3
... ... @@ -91,5 +91,12 @@
91 91 help
92 92 Support for reset controller on Amlogic Meson SoC.
93 93  
  94 +config RESET_SOCFPGA
  95 + bool "Reset controller driver for SoCFPGA"
  96 + depends on DM_RESET && ARCH_SOCFPGA
  97 + default y
  98 + help
  99 + Support for reset controller on SoCFPGA platform.
  100 +
94 101 endmenu
drivers/reset/Makefile
Diff comments   View file @ 40df6b3
... ... @@ -14,4 +14,5 @@
14 14 obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o
15 15 obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o
16 16 obj-$(CONFIG_RESET_MESON) += reset-meson.o
  17 +obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
drivers/reset/reset-socfpga.c
Diff comments   View file @ 40df6b3
  1 +/*
  2 + * Socfpga Reset Controller Driver
  3 + *
  4 + * Copyright 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
  5 + *
  6 + * based on
  7 + * Allwinner SoCs Reset Controller driver
  8 + *
  9 + * Copyright 2013 Maxime Ripard
  10 + *
  11 + * Maxime Ripard <maxime.ripard@free-electrons.com>
  12 + *
  13 + * SPDX-License-Identifier: GPL-2.0+
  14 + */
  15 +
  16 +#include <common.h>
  17 +#include <dm.h>
  18 +#include <dm/of_access.h>
  19 +#include <reset-uclass.h>
  20 +#include <linux/bitops.h>
  21 +#include <linux/io.h>
  22 +#include <linux/sizes.h>
  23 +
  24 +#define BANK_INCREMENT 4
  25 +#define NR_BANKS 8
  26 +
  27 +struct socfpga_reset_data {
  28 + void __iomem *membase;
  29 +};
  30 +
  31 +static int socfpga_reset_assert(struct reset_ctl *reset_ctl)
  32 +{
  33 + struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev);
  34 + int id = reset_ctl->id;
  35 + int reg_width = sizeof(u32);
  36 + int bank = id / (reg_width * BITS_PER_BYTE);
  37 + int offset = id % (reg_width * BITS_PER_BYTE);
  38 +
  39 + setbits_le32(data->membase + (bank * BANK_INCREMENT), BIT(offset));
  40 + return 0;
  41 +}
  42 +
  43 +static int socfpga_reset_deassert(struct reset_ctl *reset_ctl)
  44 +{
  45 + struct socfpga_reset_data *data = dev_get_priv(reset_ctl->dev);
  46 + int id = reset_ctl->id;
  47 + int reg_width = sizeof(u32);
  48 + int bank = id / (reg_width * BITS_PER_BYTE);
  49 + int offset = id % (reg_width * BITS_PER_BYTE);
  50 +
  51 + clrbits_le32(data->membase + (bank * BANK_INCREMENT), BIT(offset));
  52 + return 0;
  53 +}
  54 +
  55 +static int socfpga_reset_request(struct reset_ctl *reset_ctl)
  56 +{
  57 + debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__,
  58 + reset_ctl, reset_ctl->dev, reset_ctl->id);
  59 +
  60 + return 0;
  61 +}
  62 +
  63 +static int socfpga_reset_free(struct reset_ctl *reset_ctl)
  64 +{
  65 + debug("%s(reset_ctl=%p) (dev=%p, id=%lu)\n", __func__, reset_ctl,
  66 + reset_ctl->dev, reset_ctl->id);
  67 +
  68 + return 0;
  69 +}
  70 +
  71 +static const struct reset_ops socfpga_reset_ops = {
  72 + .request = socfpga_reset_request,
  73 + .free = socfpga_reset_free,
  74 + .rst_assert = socfpga_reset_assert,
  75 + .rst_deassert = socfpga_reset_deassert,
  76 +};
  77 +
  78 +static int socfpga_reset_probe(struct udevice *dev)
  79 +{
  80 + struct socfpga_reset_data *data = dev_get_priv(dev);
  81 + const void *blob = gd->fdt_blob;
  82 + int node = dev_of_offset(dev);
  83 + u32 modrst_offset;
  84 +
  85 + data->membase = devfdt_get_addr_ptr(dev);
  86 +
  87 + modrst_offset = fdtdec_get_int(blob, node, "altr,modrst-offset", 0x10);
  88 + data->membase += modrst_offset;
  89 +
  90 + return 0;
  91 +}
  92 +
  93 +static const struct udevice_id socfpga_reset_match[] = {
  94 + { .compatible = "altr,rst-mgr" },
  95 + { /* sentinel */ },
  96 +};
  97 +
  98 +U_BOOT_DRIVER(socfpga_reset) = {
  99 + .name = "socfpga-reset",
  100 + .id = UCLASS_RESET,
  101 + .of_match = socfpga_reset_match,
  102 + .probe = socfpga_reset_probe,
  103 + .priv_auto_alloc_size = sizeof(struct socfpga_reset_data),
  104 + .ops = &socfpga_reset_ops,
  105 +};
include/configs/socfpga_common.h
Diff comments   View file @ 40df6b3
... ... @@ -137,6 +137,7 @@
137 137 /*
138 138 * I2C support
139 139 */
  140 +#ifndef CONFIG_DM_I2C
140 141 #define CONFIG_SYS_I2C
141 142 #define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS
142 143 #define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS
... ... @@ -157,6 +158,7 @@
157 158 unsigned int cm_get_l4_sp_clk_hz(void);
158 159 #define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000)
159 160 #endif
  161 +#endif /* CONFIG_DM_I2C */
160 162  
161 163 /*
162 164 * QSPI support
include/dt-bindings/reset/altr,rst-mgr-s10.h
Diff comments   View file @ 40df6b3
  1 +/*
  2 + * Copyright (C) 2016-2018 Intel Corporation. All rights reserved
  3 + * Copyright (C) 2016 Altera Corporation. All rights reserved
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0
  6 + * derived from Steffen Trumtrar's "altr,rst-mgr-a10.h"
  7 + */
  8 +
  9 +#ifndef _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H
  10 +#define _DT_BINDINGS_RESET_ALTR_RST_MGR_S10_H
  11 +
  12 +/* MPUMODRST */
  13 +#define CPU0_RESET 0
  14 +#define CPU1_RESET 1
  15 +#define CPU2_RESET 2
  16 +#define CPU3_RESET 3
  17 +
  18 +/* PER0MODRST */
  19 +#define EMAC0_RESET 32
  20 +#define EMAC1_RESET 33
  21 +#define EMAC2_RESET 34
  22 +#define USB0_RESET 35
  23 +#define USB1_RESET 36
  24 +#define NAND_RESET 37
  25 +/* 38 is empty */
  26 +#define SDMMC_RESET 39
  27 +#define EMAC0_OCP_RESET 40
  28 +#define EMAC1_OCP_RESET 41
  29 +#define EMAC2_OCP_RESET 42
  30 +#define USB0_OCP_RESET 43
  31 +#define USB1_OCP_RESET 44
  32 +#define NAND_OCP_RESET 45
  33 +/* 46 is empty */
  34 +#define SDMMC_OCP_RESET 47
  35 +#define DMA_RESET 48
  36 +#define SPIM0_RESET 49
  37 +#define SPIM1_RESET 50
  38 +#define SPIS0_RESET 51
  39 +#define SPIS1_RESET 52
  40 +#define DMA_OCP_RESET 53
  41 +#define EMAC_PTP_RESET 54
  42 +/* 55 is empty*/
  43 +#define DMAIF0_RESET 56
  44 +#define DMAIF1_RESET 57
  45 +#define DMAIF2_RESET 58
  46 +#define DMAIF3_RESET 59
  47 +#define DMAIF4_RESET 60
  48 +#define DMAIF5_RESET 61
  49 +#define DMAIF6_RESET 62
  50 +#define DMAIF7_RESET 63
  51 +
  52 +/* PER1MODRST */
  53 +#define WATCHDOG0_RESET 64
  54 +#define WATCHDOG1_RESET 65
  55 +#define WATCHDOG2_RESET 66
  56 +#define WATCHDOG3_RESET 67
  57 +#define L4SYSTIMER0_RESET 68
  58 +#define L4SYSTIMER1_RESET 69
  59 +#define SPTIMER0_RESET 70
  60 +#define SPTIMER1_RESET 71
  61 +#define I2C0_RESET 72
  62 +#define I2C1_RESET 73
  63 +#define I2C2_RESET 74
  64 +#define I2C3_RESET 75
  65 +#define I2C4_RESET 76
  66 +/* 77-79 is empty */
  67 +#define UART0_RESET 80
  68 +#define UART1_RESET 81
  69 +/* 82-87 is empty */
  70 +#define GPIO0_RESET 88
  71 +#define GPIO1_RESET 89
  72 +
  73 +/* BRGMODRST */
  74 +#define SOC2FPGA_RESET 96
  75 +#define LWHPS2FPGA_RESET 97
  76 +#define FPGA2SOC_RESET 98
  77 +#define F2SSDRAM0_RESET 99
  78 +#define F2SSDRAM1_RESET 100
  79 +#define F2SSDRAM2_RESET 101
  80 +#define DDRSCH_RESET 102
  81 +
  82 +/* COLDMODRST */
  83 +#define CPUPO0_RESET 160
  84 +#define CPUPO1_RESET 161
  85 +#define CPUPO2_RESET 162
  86 +#define CPUPO3_RESET 163
  87 +/* 164-167 is empty */
  88 +#define L2_RESET 168
  89 +
  90 +/* DBGMODRST */
  91 +#define DBG_RESET 224
  92 +#define CSDAP_RESET 225
  93 +
  94 +/* TAPMODRST */
  95 +#define TAP_RESET 256
  96 +
  97 +#endif