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dt-bindings: timer: Add andestech atcpit100 timer
Add a document to describe Andestech atcpit100 timer and binding information. Signed-off-by: rick <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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doc/device-tree-bindings/timer/atcpit100_timer.txt
| 1 | +Andestech ATCPIT100 timer | |
| 2 | +------------------------------------------------------------------ | |
| 3 | +ATCPIT100 is a generic IP block from Andes Technology, embedded in | |
| 4 | +Andestech AE3XX, AE250 platforms and other designs. | |
| 5 | + | |
| 6 | +This timer is a set of compact multi-function timers, which can be | |
| 7 | +used as pulse width modulators (PWM) as well as simple timers. | |
| 8 | + | |
| 9 | +It supports up to 4 PIT channels. Each PIT channel is a | |
| 10 | +multi-function timer and provide the following usage scenarios: | |
| 11 | +One 32-bit timer | |
| 12 | +Two 16-bit timers | |
| 13 | +Four 8-bit timers | |
| 14 | +One 16-bit PWM | |
| 15 | +One 16-bit timer and one 8-bit PWM | |
| 16 | +Two 8-bit timer and one 8-bit PWM | |
| 17 | + | |
| 18 | +Required properties: | |
| 19 | +- compatible : Should be "andestech,atcpit100" | |
| 20 | +- reg : Address and length of the register set | |
| 21 | +- interrupts : Reference to the timer interrupt | |
| 22 | +- clock-frequency : The rate in HZ in input of the Andestech ATCPIT100 timer | |
| 23 | + | |
| 24 | +Examples: | |
| 25 | + | |
| 26 | +timer0: timer@f0400000 { | |
| 27 | + compatible = "andestech,atcpit100"; | |
| 28 | + reg = <0xf0400000 0x1000>; | |
| 29 | + interrupts = <2 4>; | |
| 30 | + clock-frequency = <30000000>; | |
| 31 | +}: |