Eric Lee / smarc-uboot

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Commit 4124382de029d361162a4b8cecc773eb8f26e2a8

Authored by Jean-Christophe PLAGNIOL-VILLARD
Committed by Wolfgang Denk
1 parent 6f4abee789
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

xsengine: fix typo and few coding style 

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

Showing 1 changed file with 9 additions and 9 deletions Side-by-side Diff

include/configs/xsengine.h
Diff comments   View file @ 4124382
... ... @@ -33,7 +33,7 @@
33 33 #define CONFIG_XSENGINE 1
34 34 #define CONFIG_MMC 1
35 35 #define CONFIG_DOS_PARTITION 1
36   -#define OARD_LATE_INIT 1
  36 +#define BOARD_LATE_INIT 1
37 37 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
38 38 #define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
39 39  
... ... @@ -86,8 +86,8 @@
86 86 #define CFG_ENV_SIZE 0x4000 /* 16kB Total Size of Environment Sector */
87 87  
88 88 /* timeout values are in ticks */
89   -#define CFG_FLASH_ERASE_TOUT (75*CFG_HZ) /* Timeout for Flash Erase */
90   -#define CFG_FLASH_WRITE_TOUT (50*CFG_HZ) /* Timeout for Flash Write */
  89 +#define CFG_FLASH_ERASE_TOUT (75*CFG_HZ) /* Timeout for Flash Erase */
  90 +#define CFG_FLASH_WRITE_TOUT (50*CFG_HZ) /* Timeout for Flash Write */
91 91  
92 92 /* Size of malloc() pool */
93 93 #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 256*1024)
... ... @@ -96,7 +96,7 @@
96 96 /* Hardware drivers */
97 97 #define CONFIG_DRIVER_SMC91111
98 98 #define CONFIG_SMC91111_BASE 0x04000300
99   -#define CONFIG_SMC_USE_32_BIT 1
  99 +#define CONFIG_SMC_USE_32_BIT 1
100 100  
101 101 /* select serial console configuration */
102 102 #define CONFIG_FFUART 1
103 103  
104 104  
... ... @@ -138,15 +138,15 @@
138 138 #define CFG_LONGHELP /* undef to save memory */
139 139 #define CFG_PROMPT "XS-Engine u-boot> " /* Monitor Command Prompt */
140 140 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
141   -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  141 +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
142 142 #define CFG_MAXARGS 16 /* max number of command args */
143 143 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
144 144 #define CFG_MEMTEST_START 0xA0400000 /* memtest works on */
145 145 #define CFG_MEMTEST_END 0xA0800000 /* 4 ... 8 MB in DRAM */
146   -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
  146 +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
147 147 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } /* valid baudrates */
148 148 #define CFG_MMC_BASE 0xF0000000
149   -#define CFG_LOAD_ADDR 0xA0000000 /* load kernel to this address */
  149 +#define CFG_LOAD_ADDR 0xA0000000 /* load kernel to this address */
150 150  
151 151 /* Stack sizes - The stack sizes are set up in start.S using the settings below */
152 152 #define CONFIG_STACKSIZE (128*1024) /* regular stack */
... ... @@ -168,7 +168,7 @@
168 168 /* GP direction register */
169 169 #define CFG_GPDR0_VAL 0x0000A000 /* CS1, PROG(FPGA) */
170 170 #define CFG_GPDR1_VAL 0x00022A80 /* nPWE, FFUART + BTUART pins */
171   -#define CFG_GPDR2_VAL 0x0000C000 /* CS2, CS3 */
  171 +#define CFG_GPDR2_VAL 0x0000C000 /* CS2, CS3 */
172 172  
173 173 /* GP rising edge detect register */
174 174 #define CFG_GRER0_VAL 0x00000000
... ... @@ -185,7 +185,7 @@
185 185 #define CFG_GAFR0_U_VAL 0x00000010 /* RDY */
186 186 #define CFG_GAFR1_L_VAL 0x09988050 /* FFUART + BTUART pins */
187 187 #define CFG_GAFR1_U_VAL 0x00000008 /* nPWE */
188   -#define CFG_GAFR2_L_VAL 0xA0000000 /* CS2, CS3 */
  188 +#define CFG_GAFR2_L_VAL 0xA0000000 /* CS2, CS3 */
189 189 #define CFG_GAFR2_U_VAL 0x00000000
190 190  
191 191 #define CFG_PSSR_VAL 0x00000020 /* Power manager sleep status */