Commit 412ae53aadb53cd63e754d638bafe6e426aeafee
Committed by
Albert ARIBAUD
1 parent
8c80eb3b53
Exists in
v2017.01-smarct4x
and in
37 other branches
lpc32xx: add support for board work_92105
Work_92105 from Work Microwave is an LPC3250- based board with the following features: - 64MB or 128MB SDR DRAM - 1 GB SLC NAND, managed through MLC controller. - Ethernet - Ethernet + PHY SMSC8710 - I2C: - EEPROM (24M01-compatible) - RTC (DS1374-compatible) - Temperature sensor (DS620) - DACs (2 x MAX518) - SPI (through SSP interface) - Port expander MAX6957 - LCD display (HD44780-compatible), controlled through the port expander and DACs This board has SPL support, and uses the LPC32XX boot image format. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
Showing 22 changed files with 1129 additions and 1 deletions Side-by-side Diff
- Makefile
- arch/arm/Kconfig
- arch/arm/cpu/arm926ejs/lpc32xx/Makefile
- arch/arm/cpu/arm926ejs/lpc32xx/clk.c
- arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
- arch/arm/cpu/arm926ejs/lpc32xx/dram.c
- arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S
- arch/arm/include/asm/arch-lpc32xx/clk.h
- arch/arm/include/asm/arch-lpc32xx/cpu.h
- arch/arm/include/asm/arch-lpc32xx/emc.h
- arch/arm/include/asm/arch-lpc32xx/mux.h
- arch/arm/include/asm/arch-lpc32xx/sys_proto.h
- board/work-microwave/work_92105/Kconfig
- board/work-microwave/work_92105/MAINTAINERS
- board/work-microwave/work_92105/Makefile
- board/work-microwave/work_92105/README
- board/work-microwave/work_92105/work_92105.c
- board/work-microwave/work_92105/work_92105_display.c
- board/work-microwave/work_92105/work_92105_display.h
- board/work-microwave/work_92105/work_92105_spl.c
- configs/work_92105_defconfig
- include/configs/work_92105.h
Makefile
... | ... | @@ -909,6 +909,26 @@ |
909 | 909 | u-boot-with-spl.bin: spl/u-boot-spl.bin $(SPL_PAYLOAD) FORCE |
910 | 910 | $(call if_changed,pad_cat) |
911 | 911 | |
912 | +MKIMAGEFLAGS_lpc32xx-spl.img = -T lpc32xximage -a $(CONFIG_SPL_TEXT_BASE) | |
913 | + | |
914 | +lpc32xx-spl.img: spl/u-boot-spl.bin FORCE | |
915 | + $(call if_changed,mkimage) | |
916 | + | |
917 | +OBJCOPYFLAGS_lpc32xx-boot-0.bin = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) | |
918 | + | |
919 | +lpc32xx-boot-0.bin: lpc32xx-spl.img | |
920 | + $(call if_changed,objcopy) | |
921 | + | |
922 | +OBJCOPYFLAGS_lpc32xx-boot-1.bin = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) | |
923 | + | |
924 | +lpc32xx-boot-1.bin: lpc32xx-spl.img | |
925 | + $(call if_changed,objcopy) | |
926 | + | |
927 | +lpc32xx-full.bin: lpc32xx-boot-0.bin lpc32xx-boot-1.bin u-boot.img | |
928 | + $(call if_changed,cat) | |
929 | + | |
930 | +CLEAN_FILES += lpc32xx-* | |
931 | + | |
912 | 932 | OBJCOPYFLAGS_u-boot-with-tpl.bin = -I binary -O binary \ |
913 | 933 | --pad-to=$(CONFIG_TPL_PAD_TO) |
914 | 934 | tpl/u-boot-with-tpl.bin: tpl/u-boot-tpl.bin u-boot.bin FORCE |
arch/arm/Kconfig
... | ... | @@ -132,6 +132,11 @@ |
132 | 132 | bool "Support devkit3250" |
133 | 133 | select CPU_ARM926EJS |
134 | 134 | |
135 | +config TARGET_WORK_92105 | |
136 | + bool "Support work_92105" | |
137 | + select CPU_ARM926EJS | |
138 | + select SUPPORT_SPL | |
139 | + | |
135 | 140 | config TARGET_MX25PDK |
136 | 141 | bool "Support mx25pdk" |
137 | 142 | select CPU_ARM926EJS |
... | ... | @@ -872,6 +877,7 @@ |
872 | 877 | source "board/wandboard/Kconfig" |
873 | 878 | source "board/warp/Kconfig" |
874 | 879 | source "board/woodburn/Kconfig" |
880 | +source "board/work-microwave/work_92105/Kconfig" | |
875 | 881 | source "board/xaeniax/Kconfig" |
876 | 882 | source "board/xilinx/zynqmp/Kconfig" |
877 | 883 | source "board/zipitz2/Kconfig" |
arch/arm/cpu/arm926ejs/lpc32xx/Makefile
arch/arm/cpu/arm926ejs/lpc32xx/clk.c
... | ... | @@ -98,6 +98,40 @@ |
98 | 98 | return get_hclk_pll_rate() / get_periph_clk_div(); |
99 | 99 | } |
100 | 100 | |
101 | +unsigned int get_sdram_clk_rate(void) | |
102 | +{ | |
103 | + unsigned int src_clk; | |
104 | + | |
105 | + if (!(readl(&clk->pwr_ctrl) & CLK_PWR_NORMAL_RUN)) | |
106 | + return get_sys_clk_rate(); | |
107 | + | |
108 | + src_clk = get_hclk_pll_rate(); | |
109 | + | |
110 | + if (readl(&clk->sdramclk_ctrl) & CLK_SDRAM_DDR_SEL) { | |
111 | + /* using DDR */ | |
112 | + switch (readl(&clk->hclkdiv_ctrl) & CLK_HCLK_DDRAM_MASK) { | |
113 | + case CLK_HCLK_DDRAM_HALF: | |
114 | + return src_clk/2; | |
115 | + case CLK_HCLK_DDRAM_NOMINAL: | |
116 | + return src_clk; | |
117 | + default: | |
118 | + return 0; | |
119 | + } | |
120 | + } else { | |
121 | + /* using SDR */ | |
122 | + switch (readl(&clk->hclkdiv_ctrl) & CLK_HCLK_ARM_PLL_DIV_MASK) { | |
123 | + case CLK_HCLK_ARM_PLL_DIV_4: | |
124 | + return src_clk/4; | |
125 | + case CLK_HCLK_ARM_PLL_DIV_2: | |
126 | + return src_clk/2; | |
127 | + case CLK_HCLK_ARM_PLL_DIV_1: | |
128 | + return src_clk; | |
129 | + default: | |
130 | + return 0; | |
131 | + } | |
132 | + } | |
133 | +} | |
134 | + | |
101 | 135 | int get_serial_clock(void) |
102 | 136 | { |
103 | 137 | return get_periph_clk_rate(); |
arch/arm/cpu/arm926ejs/lpc32xx/cpu.c
arch/arm/cpu/arm926ejs/lpc32xx/dram.c
1 | +/* | |
2 | + * LPC32xx dram init | |
3 | + * | |
4 | + * (C) Copyright 2014 DENX Software Engineering GmbH | |
5 | + * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> | |
6 | + * | |
7 | + * This is called by SPL to gain access to the SDR DRAM. | |
8 | + * | |
9 | + * This code runs from SRAM. | |
10 | + * | |
11 | + * Actual CONFIG_LPC32XX_SDRAM_* parameters must be provided | |
12 | + * by the board configuration file. | |
13 | + * | |
14 | + * SPDX-License-Identifier: GPL-2.0+ | |
15 | + */ | |
16 | + | |
17 | +#include <common.h> | |
18 | +#include <netdev.h> | |
19 | +#include <asm/arch/cpu.h> | |
20 | +#include <asm/arch/clk.h> | |
21 | +#include <asm/arch/wdt.h> | |
22 | +#include <asm/arch/emc.h> | |
23 | +#include <asm/io.h> | |
24 | + | |
25 | +static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE; | |
26 | +static struct emc_regs *emc = (struct emc_regs *)EMC_BASE; | |
27 | + | |
28 | +void ddr_init(struct emc_dram_settings *dram) | |
29 | +{ | |
30 | + uint32_t ck; | |
31 | + | |
32 | + /* Enable EMC interface and choose little endian mode */ | |
33 | + writel(1, &emc->ctrl); | |
34 | + writel(0, &emc->config); | |
35 | + /* Select maximum EMC Dynamic Memory Refresh Time */ | |
36 | + writel(0x7FF, &emc->refresh); | |
37 | + /* Determine CLK */ | |
38 | + ck = get_sdram_clk_rate(); | |
39 | + /* Configure SDRAM */ | |
40 | + writel(dram->cmddelay, &clk->sdramclk_ctrl); | |
41 | + writel(dram->config0, &emc->config0); | |
42 | + writel(dram->rascas0, &emc->rascas0); | |
43 | + writel(dram->rdconfig, &emc->read_config); | |
44 | + /* Set timings */ | |
45 | + writel((ck / dram->trp) & 0x0000000F, &emc->t_rp); | |
46 | + writel((ck / dram->tras) & 0x0000000F, &emc->t_ras); | |
47 | + writel((ck / dram->tsrex) & 0x0000007F, &emc->t_srex); | |
48 | + writel((ck / dram->twr) & 0x0000000F, &emc->t_wr); | |
49 | + writel((ck / dram->trc) & 0x0000001F, &emc->t_rc); | |
50 | + writel((ck / dram->trfc) & 0x0000001F, &emc->t_rfc); | |
51 | + writel((ck / dram->txsr) & 0x000000FF, &emc->t_xsr); | |
52 | + writel(dram->trrd, &emc->t_rrd); | |
53 | + writel(dram->tmrd, &emc->t_mrd); | |
54 | + writel(dram->tcdlr, &emc->t_cdlr); | |
55 | + /* Dynamic refresh */ | |
56 | + writel((((ck / dram->refresh) >> 4) & 0x7FF), &emc->refresh); | |
57 | + udelay(10); | |
58 | + /* Force all clocks, enable inverted ck, issue NOP command */ | |
59 | + writel(0x00000193, &emc->control); | |
60 | + udelay(100); | |
61 | + /* Keep all clocks enabled, issue a PRECHARGE ALL command */ | |
62 | + writel(0x00000113, &emc->control); | |
63 | + /* Fast dynamic refresh for at least a few SDRAM ck cycles */ | |
64 | + writel((((128) >> 4) & 0x7FF), &emc->refresh); | |
65 | + udelay(10); | |
66 | + /* set correct dynamic refresh timing */ | |
67 | + writel((((ck / dram->refresh) >> 4) & 0x7FF), &emc->refresh); | |
68 | + udelay(10); | |
69 | + /* set normal mode to CAS=3 */ | |
70 | + writel(0x00000093, &emc->control); | |
71 | + readl(EMC_DYCS0_BASE | dram->mode); | |
72 | + /* set extended mode to all zeroes */ | |
73 | + writel(0x00000093, &emc->control); | |
74 | + readl(EMC_DYCS0_BASE | dram->emode); | |
75 | + /* stop forcing clocks, keep inverted clock, issue normal mode */ | |
76 | + writel(0x00000010, &emc->control); | |
77 | +} |
arch/arm/cpu/arm926ejs/lpc32xx/lowlevel_init.S
1 | +/* | |
2 | + * WORK Microwave work_92105 board low level init | |
3 | + * | |
4 | + * (C) Copyright 2014 DENX Software Engineering GmbH | |
5 | + * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> | |
6 | + * | |
7 | + * Low level init is called from SPL to set up the clocks. | |
8 | + * On entry, the LPC3250 is in Direct Run mode with all clocks | |
9 | + * running at 13 MHz; on exit, ARM clock is 208 MHz, HCLK is | |
10 | + * 104 MHz and PCLK is 13 MHz. | |
11 | + * | |
12 | + * This code must run from SRAM so that the clock changes do | |
13 | + * not prevent it from executing. | |
14 | + * | |
15 | + * SPDX-License-Identifier: GPL-2.0+ | |
16 | + */ | |
17 | + | |
18 | +.globl lowlevel_init | |
19 | + | |
20 | +lowlevel_init: | |
21 | + | |
22 | + /* Set ARM, HCLK, PCLK dividers for normal mode */ | |
23 | + ldr r0, =0x0000003D | |
24 | + ldr r1, =0x40004040 | |
25 | + str r0, [r1] | |
26 | + | |
27 | + /* Start HCLK PLL for 208 MHz */ | |
28 | + ldr r0, =0x0001401E | |
29 | + ldr r1, =0x40004058 | |
30 | + str r0, [r1] | |
31 | + | |
32 | + /* wait for HCLK PLL to lock */ | |
33 | +1: | |
34 | + ldr r0, [r1] | |
35 | + ands r0, r0, #1 | |
36 | + beq 1b | |
37 | + | |
38 | + /* switch to normal mode */ | |
39 | + ldr r1, =0x40004044 | |
40 | + ldr r0, [r1] | |
41 | + orr r0, #0x00000004 | |
42 | + str r0, [r1] | |
43 | + | |
44 | + /* Return to U-boot via saved link register */ | |
45 | + mov pc, lr |
arch/arm/include/asm/arch-lpc32xx/clk.h
... | ... | @@ -71,6 +71,7 @@ |
71 | 71 | }; |
72 | 72 | |
73 | 73 | /* HCLK Divider Control Register bits */ |
74 | +#define CLK_HCLK_DDRAM_MASK (0x3 << 7) | |
74 | 75 | #define CLK_HCLK_DDRAM_HALF (0x2 << 7) |
75 | 76 | #define CLK_HCLK_DDRAM_NOMINAL (0x1 << 7) |
76 | 77 | #define CLK_HCLK_DDRAM_STOPPED (0x0 << 7) |
77 | 78 | |
... | ... | @@ -158,12 +159,16 @@ |
158 | 159 | /* SSP Clock Control Register bits */ |
159 | 160 | #define CLK_SSP0_ENABLE_CLOCK (1 << 0) |
160 | 161 | |
162 | +/* SDRAMCLK register bits */ | |
163 | +#define CLK_SDRAM_DDR_SEL (1 << 1) | |
164 | + | |
161 | 165 | unsigned int get_sys_clk_rate(void); |
162 | 166 | unsigned int get_hclk_pll_rate(void); |
163 | 167 | unsigned int get_hclk_clk_div(void); |
164 | 168 | unsigned int get_hclk_clk_rate(void); |
165 | 169 | unsigned int get_periph_clk_div(void); |
166 | 170 | unsigned int get_periph_clk_rate(void); |
171 | +unsigned int get_sdram_clk_rate(void); | |
167 | 172 | |
168 | 173 | #endif /* _LPC32XX_CLK_H */ |
arch/arm/include/asm/arch-lpc32xx/cpu.h
... | ... | @@ -27,6 +27,7 @@ |
27 | 27 | #define HS_UART7_BASE 0x4001C000 /* High speed UART 7 registers base */ |
28 | 28 | #define RTC_BASE 0x40024000 /* RTC registers base */ |
29 | 29 | #define GPIO_BASE 0x40028000 /* GPIO registers base */ |
30 | +#define MUX_BASE 0x40028100 /* MUX registers base */ | |
30 | 31 | #define WDT_BASE 0x4003C000 /* Watchdog timer registers base */ |
31 | 32 | #define TIMER0_BASE 0x40044000 /* Timer0 registers base */ |
32 | 33 | #define TIMER1_BASE 0x4004C000 /* Timer1 registers base */ |
arch/arm/include/asm/arch-lpc32xx/emc.h
... | ... | @@ -76,5 +76,26 @@ |
76 | 76 | #define EMC_STAT_WAITWR(n) (((n) - 2) & 0x1F) |
77 | 77 | #define EMC_STAT_WAITTURN(n) (((n) - 1) & 0x0F) |
78 | 78 | |
79 | +/* EMC settings for DRAM */ | |
80 | +struct emc_dram_settings { | |
81 | + u32 cmddelay; | |
82 | + u32 config0; | |
83 | + u32 rascas0; | |
84 | + u32 rdconfig; | |
85 | + u32 trp; | |
86 | + u32 tras; | |
87 | + u32 tsrex; | |
88 | + u32 twr; | |
89 | + u32 trc; | |
90 | + u32 trfc; | |
91 | + u32 txsr; | |
92 | + u32 trrd; | |
93 | + u32 tmrd; | |
94 | + u32 tcdlr; | |
95 | + u32 refresh; | |
96 | + u32 mode; | |
97 | + u32 emode; | |
98 | +}; | |
99 | + | |
79 | 100 | #endif /* _LPC32XX_EMC_H */ |
arch/arm/include/asm/arch-lpc32xx/mux.h
1 | +/* | |
2 | + * LPC32xx MUX interface | |
3 | + * | |
4 | + * (C) Copyright 2015 DENX Software Engineering GmbH | |
5 | + * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> | |
6 | + * | |
7 | + * SPDX-License-Identifier: GPL-2.0+ | |
8 | + */ | |
9 | + | |
10 | +/** | |
11 | + * MUX register map for LPC32xx | |
12 | + */ | |
13 | + | |
14 | +struct mux_regs { | |
15 | + u32 p_mux_set; | |
16 | + u32 p_mux_clr; | |
17 | + u32 p_mux_state; | |
18 | +}; |
arch/arm/include/asm/arch-lpc32xx/sys_proto.h
... | ... | @@ -7,11 +7,15 @@ |
7 | 7 | #ifndef _LPC32XX_SYS_PROTO_H |
8 | 8 | #define _LPC32XX_SYS_PROTO_H |
9 | 9 | |
10 | +#include <asm/arch/emc.h> | |
11 | + | |
10 | 12 | void lpc32xx_uart_init(unsigned int uart_id); |
11 | 13 | void lpc32xx_mac_init(void); |
12 | 14 | void lpc32xx_mlc_nand_init(void); |
13 | 15 | void lpc32xx_i2c_init(unsigned int devnum); |
14 | 16 | void lpc32xx_ssp_init(void); |
15 | - | |
17 | +#if defined(CONFIG_SPL_BUILD) | |
18 | +void ddr_init(const struct emc_dram_settings *dram); | |
19 | +#endif | |
16 | 20 | #endif /* _LPC32XX_SYS_PROTO_H */ |
board/work-microwave/work_92105/Kconfig
board/work-microwave/work_92105/MAINTAINERS
board/work-microwave/work_92105/Makefile
board/work-microwave/work_92105/README
1 | +Work_92105 from Work Microwave is an LPC3250- based board with the | |
2 | +following features: | |
3 | + | |
4 | + - 64MB SDR DRAM | |
5 | + - 1 GB SLC NAND, managed through MLC controller. | |
6 | + - Ethernet | |
7 | + - Ethernet + PHY SMSC8710 | |
8 | + - I2C: | |
9 | + - EEPROM (24M01-compatible) | |
10 | + - RTC (DS1374-compatible) | |
11 | + - Temperature sensor (DS620) | |
12 | + - DACs (2 x MAX518) | |
13 | + - SPI (through SSP interface) | |
14 | + - Port expander MAX6957 | |
15 | + - LCD display (HD44780-compatible), controlled | |
16 | + through the port expander and DACs | |
17 | + | |
18 | +Standard SPL and U-Boot binaries | |
19 | +-------------------------------- | |
20 | + | |
21 | +The default 'make' (or the 'make all') command will produce the | |
22 | +following files: | |
23 | + | |
24 | +1. spl/u-boot-spl.bin SPL, intended to run from SRAM at address 0. | |
25 | + This file can be loaded in SRAM through a JTAG | |
26 | + debugger or through the LPC32XX Service Boot | |
27 | + mechanism. | |
28 | + | |
29 | +2. u-boot.bin The raw U-Boot image, which can be loaded in | |
30 | + DDR through a JTAG debugger (for instance by | |
31 | + breaking SPL after DDR init), or by a running | |
32 | + U-Boot through e.g. 'loady' or 'tftp' and then | |
33 | + executed with 'go'. | |
34 | + | |
35 | +3. u-boot.img A U-Boot image with a mkimage header prepended. | |
36 | + SPL assumes (even when loaded through JTAG or | |
37 | + Service Boot) that such an image will be found | |
38 | + at offset 0x00040000 in NAND. | |
39 | + | |
40 | +NAND cold-boot binaries | |
41 | +----------------------- | |
42 | + | |
43 | +The board can boot entirely from power-on with only SPL and U-Boot in | |
44 | +NAND. The LPC32XX-specific 'make lpc32xx-full.bin' command will produce | |
45 | +(in addition to spl/u-boot-spl.bin and u-boot.img if they were not made | |
46 | +already) the following files: | |
47 | + | |
48 | +4. lpc32xx-spl.img spl/u-boot-spl.bin, with a LPC32XX boot header | |
49 | + prepended. This header is required for the ROM | |
50 | + code to load SPL into SRAM and branch into it. | |
51 | + The content of this file is expected to reside | |
52 | + in NAND at addresses 0x00000000 and 0x00020000 | |
53 | + (two copies). | |
54 | + | |
55 | +5. lpc32xx-boot-0.bin lpc32xx-spl.img, padded with 0xFF bytes to a | |
56 | + size of 0x20000 bytes. This file covers exactly | |
57 | + the reserved area for the first bootloader copy | |
58 | + in NAND. | |
59 | + | |
60 | +6. lpc32xx-boot-1.bin Same as lpc32xx-boot-0.bin. This is intended to | |
61 | + be used as the second bootloader copy. | |
62 | + | |
63 | +7. lpc32xx-full.bin lpc32xx-boot-0.bin, lpc32xx-boot-1.bin and | |
64 | + u-boot.img concatenated. This file represents | |
65 | + the content of whole bootloader as present in | |
66 | + NAND at offset 00x00000000. | |
67 | + | |
68 | +Flashing instructions | |
69 | +--------------------- | |
70 | + | |
71 | +The following assumes a working U-Boot on the target, with the ability | |
72 | +to load files into DDR. | |
73 | + | |
74 | +To update the whole bootloader: | |
75 | + | |
76 | + nand erase 0x00000000 0x80000 | |
77 | + (load lpc32xx-full.bin at location $loadaddr) | |
78 | + nand write $loadaddr 0x00000000 $filesize | |
79 | + | |
80 | +To update SPL only (note the double nand write) : | |
81 | + | |
82 | + nand erase 0x00000000 0x40000 | |
83 | + (load lpc32xx-spl.img or lpc32xx-boot-N.bin at location $loadaddr) | |
84 | + nand write $loadaddr 0x00000000 $filesize | |
85 | + nand write $loadaddr 0x00020000 $filesize | |
86 | + | |
87 | +To update U-Boot only: | |
88 | + | |
89 | + nand erase 0x00040000 0x40000 | |
90 | + (load u-boot.img at location $loadaddr) | |
91 | + nand write $loadaddr 0x00040000 $filesize |
board/work-microwave/work_92105/work_92105.c
1 | +/* | |
2 | + * WORK Microwave work_92105 board support | |
3 | + * | |
4 | + * (C) Copyright 2014 DENX Software Engineering GmbH | |
5 | + * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> | |
6 | + * | |
7 | + * SPDX-License-Identifier: GPL-2.0+ | |
8 | + */ | |
9 | + | |
10 | +#include <common.h> | |
11 | +#include <asm/io.h> | |
12 | +#include <asm/arch/sys_proto.h> | |
13 | +#include <asm/arch/cpu.h> | |
14 | +#include <asm/arch/clk.h> | |
15 | +#include <asm/arch/emc.h> | |
16 | +#include <asm/arch/wdt.h> | |
17 | +#include <asm/gpio.h> | |
18 | +#include <spl.h> | |
19 | +#include "work_92105_display.h" | |
20 | + | |
21 | +DECLARE_GLOBAL_DATA_PTR; | |
22 | + | |
23 | +static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE; | |
24 | +static struct wdt_regs *wdt = (struct wdt_regs *)WDT_BASE; | |
25 | + | |
26 | +void reset_periph(void) | |
27 | +{ | |
28 | + setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG); | |
29 | + writel(WDTIM_MCTRL_RESFRC1, &wdt->mctrl); | |
30 | + udelay(150); | |
31 | + writel(0, &wdt->mctrl); | |
32 | + clrbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG); | |
33 | +} | |
34 | + | |
35 | +int board_early_init_f(void) | |
36 | +{ | |
37 | + /* initialize serial port for console */ | |
38 | + lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART); | |
39 | + /* enable I2C, SSP, MAC, NAND */ | |
40 | + lpc32xx_i2c_init(1); /* only I2C1 has devices, I2C2 has none */ | |
41 | + lpc32xx_ssp_init(); | |
42 | + lpc32xx_mac_init(); | |
43 | + lpc32xx_mlc_nand_init(); | |
44 | + /* Display must wait until after relocation and devices init */ | |
45 | + return 0; | |
46 | +} | |
47 | + | |
48 | +#define GPO_19 115 | |
49 | + | |
50 | +int board_early_init_r(void) | |
51 | +{ | |
52 | + /* Set NAND !WP to 1 through GPO_19 */ | |
53 | + gpio_request(GPO_19, "NAND_nWP"); | |
54 | + gpio_direction_output(GPO_19, 1); | |
55 | + | |
56 | + /* initialize display */ | |
57 | + work_92105_display_init(); | |
58 | + | |
59 | + return 0; | |
60 | +} | |
61 | + | |
62 | +int board_init(void) | |
63 | +{ | |
64 | + reset_periph(); | |
65 | + /* adress of boot parameters */ | |
66 | + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; | |
67 | + | |
68 | + return 0; | |
69 | +} | |
70 | + | |
71 | +int dram_init(void) | |
72 | +{ | |
73 | + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, | |
74 | + CONFIG_SYS_SDRAM_SIZE); | |
75 | + | |
76 | + return 0; | |
77 | +} |
board/work-microwave/work_92105/work_92105_display.c
1 | +/* | |
2 | + * work_92105 display support | |
3 | + * | |
4 | + * (C) Copyright 2014 DENX Software Engineering GmbH | |
5 | + * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> | |
6 | + * | |
7 | + * The work_92105 display is a HD44780-compatible module | |
8 | + * controlled through a MAX6957AAX SPI port expander, two | |
9 | + * MAX518 I2C DACs and native LPC32xx GPO 15. | |
10 | + * | |
11 | + * SPDX-License-Identifier: GPL-2.0+ | |
12 | + */ | |
13 | + | |
14 | +#include <common.h> | |
15 | +#include <asm/arch/sys_proto.h> | |
16 | +#include <asm/arch/cpu.h> | |
17 | +#include <asm/arch/emc.h> | |
18 | +#include <asm/gpio.h> | |
19 | +#include <spi.h> | |
20 | +#include <i2c.h> | |
21 | +#include <version.h> | |
22 | +#include <vsprintf.h> | |
23 | + | |
24 | +/* | |
25 | + * GPO 15 in port 3 is gpio 3*32+15 = 111 | |
26 | + */ | |
27 | + | |
28 | +#define GPO_15 111 | |
29 | + | |
30 | +/** | |
31 | + * MAX6957AAX registers that we will be using | |
32 | + */ | |
33 | + | |
34 | +#define MAX6957_CONF 0x04 | |
35 | + | |
36 | +#define MAX6957_CONF_08_11 0x0A | |
37 | +#define MAX6957_CONF_12_15 0x0B | |
38 | +#define MAX6957_CONF_16_19 0x0C | |
39 | + | |
40 | +/** | |
41 | + * Individual gpio ports (one per gpio) to HD44780 | |
42 | + */ | |
43 | + | |
44 | +#define MAX6957AAX_HD44780_RS 0x29 | |
45 | +#define MAX6957AAX_HD44780_R_W 0x2A | |
46 | +#define MAX6957AAX_HD44780_EN 0x2B | |
47 | +#define MAX6957AAX_HD44780_DATA 0x4C | |
48 | + | |
49 | +/** | |
50 | + * Display controller instructions | |
51 | + */ | |
52 | + | |
53 | +/* Function set: eight bits, two lines, 8-dot font */ | |
54 | +#define HD44780_FUNCTION_SET 0x38 | |
55 | + | |
56 | +/* Display ON / OFF: turn display on */ | |
57 | +#define HD44780_DISPLAY_ON_OFF_CONTROL 0x0C | |
58 | + | |
59 | +/* Entry mode: increment */ | |
60 | +#define HD44780_ENTRY_MODE_SET 0x06 | |
61 | + | |
62 | +/* Clear */ | |
63 | +#define HD44780_CLEAR_DISPLAY 0x01 | |
64 | + | |
65 | +/* Set DDRAM addr (to be ORed with exact address) */ | |
66 | +#define HD44780_SET_DDRAM_ADDR 0x80 | |
67 | + | |
68 | +/* Set CGRAM addr (to be ORed with exact address) */ | |
69 | +#define HD44780_SET_CGRAM_ADDR 0x40 | |
70 | + | |
71 | +/** | |
72 | + * Default value for contrats | |
73 | + */ | |
74 | + | |
75 | +#define CONTRAST_DEFAULT 25 | |
76 | + | |
77 | +/** | |
78 | + * Define slave as a module-wide local to save passing it around, | |
79 | + * plus we will need it after init for the "hd44780" command. | |
80 | + */ | |
81 | + | |
82 | +static struct spi_slave *slave; | |
83 | + | |
84 | +/* | |
85 | + * Write a value into a MAX6957AAX register. | |
86 | + */ | |
87 | + | |
88 | +static void max6957aax_write(uint8_t reg, uint8_t value) | |
89 | +{ | |
90 | + uint8_t dout[2]; | |
91 | + | |
92 | + dout[0] = reg; | |
93 | + dout[1] = value; | |
94 | + gpio_set_value(GPO_15, 0); | |
95 | + /* do SPI read/write (passing din==dout is OK) */ | |
96 | + spi_xfer(slave, 16, dout, dout, SPI_XFER_BEGIN | SPI_XFER_END); | |
97 | + gpio_set_value(GPO_15, 1); | |
98 | +} | |
99 | + | |
100 | +/* | |
101 | + * Read a value from a MAX6957AAX register. | |
102 | + * | |
103 | + * According to the MAX6957AAX datasheet, we should release the chip | |
104 | + * select halfway through the read sequence, when the actual register | |
105 | + * value is read; but the WORK_92105 hardware prevents the MAX6957AAX | |
106 | + * SPI OUT from reaching the LPC32XX SIP MISO if chip is not selected. | |
107 | + * so let's release the CS an hold it again while reading the result. | |
108 | + */ | |
109 | + | |
110 | +static uint8_t max6957aax_read(uint8_t reg) | |
111 | +{ | |
112 | + uint8_t dout[2], din[2]; | |
113 | + | |
114 | + /* send read command */ | |
115 | + dout[0] = reg | 0x80; /* set bit 7 to indicate read */ | |
116 | + dout[1] = 0; | |
117 | + gpio_set_value(GPO_15, 0); | |
118 | + /* do SPI read/write (passing din==dout is OK) */ | |
119 | + spi_xfer(slave, 16, dout, dout, SPI_XFER_BEGIN | SPI_XFER_END); | |
120 | + /* latch read command */ | |
121 | + gpio_set_value(GPO_15, 1); | |
122 | + /* read register -- din = noop on xmit, din[1] = reg on recv */ | |
123 | + din[0] = 0; | |
124 | + din[1] = 0; | |
125 | + gpio_set_value(GPO_15, 0); | |
126 | + /* do SPI read/write (passing din==dout is OK) */ | |
127 | + spi_xfer(slave, 16, din, din, SPI_XFER_BEGIN | SPI_XFER_END); | |
128 | + /* end of read. */ | |
129 | + gpio_set_value(GPO_15, 1); | |
130 | + return din[1]; | |
131 | +} | |
132 | + | |
133 | +static void hd44780_instruction(unsigned long instruction) | |
134 | +{ | |
135 | + max6957aax_write(MAX6957AAX_HD44780_RS, 0); | |
136 | + max6957aax_write(MAX6957AAX_HD44780_R_W, 0); | |
137 | + max6957aax_write(MAX6957AAX_HD44780_EN, 1); | |
138 | + max6957aax_write(MAX6957AAX_HD44780_DATA, instruction); | |
139 | + max6957aax_write(MAX6957AAX_HD44780_EN, 0); | |
140 | + /* HD44780 takes 37 us for most instructions, 1520 for clear */ | |
141 | + if (instruction == HD44780_CLEAR_DISPLAY) | |
142 | + udelay(2000); | |
143 | + else | |
144 | + udelay(100); | |
145 | +} | |
146 | + | |
147 | +static void hd44780_write_char(char c) | |
148 | +{ | |
149 | + max6957aax_write(MAX6957AAX_HD44780_RS, 1); | |
150 | + max6957aax_write(MAX6957AAX_HD44780_R_W, 0); | |
151 | + max6957aax_write(MAX6957AAX_HD44780_EN, 1); | |
152 | + max6957aax_write(MAX6957AAX_HD44780_DATA, c); | |
153 | + max6957aax_write(MAX6957AAX_HD44780_EN, 0); | |
154 | + /* HD44780 takes 37 us to write to DDRAM or CGRAM */ | |
155 | + udelay(100); | |
156 | +} | |
157 | + | |
158 | +static void hd44780_write_str(char *s) | |
159 | +{ | |
160 | + max6957aax_write(MAX6957AAX_HD44780_RS, 1); | |
161 | + max6957aax_write(MAX6957AAX_HD44780_R_W, 0); | |
162 | + while (*s) { | |
163 | + max6957aax_write(MAX6957AAX_HD44780_EN, 1); | |
164 | + max6957aax_write(MAX6957AAX_HD44780_DATA, *s); | |
165 | + max6957aax_write(MAX6957AAX_HD44780_EN, 0); | |
166 | + s++; | |
167 | + /* HD44780 takes 37 us to write to DDRAM or CGRAM */ | |
168 | + udelay(100); | |
169 | + } | |
170 | +} | |
171 | + | |
172 | +/* | |
173 | + * Existing user code might expect these custom characters to be | |
174 | + * recognized and displayed on the LCD | |
175 | + */ | |
176 | + | |
177 | +static u8 char_gen_chars[] = { | |
178 | + /* #8, empty rectangle */ | |
179 | + 0x1F, 0x11, 0x11, 0x11, 0x11, 0x11, 0x11, 0x1F, | |
180 | + /* #9, filled right arrow */ | |
181 | + 0x10, 0x18, 0x1C, 0x1E, 0x1C, 0x18, 0x10, 0x00, | |
182 | + /* #10, filled left arrow */ | |
183 | + 0x01, 0x03, 0x07, 0x0F, 0x07, 0x03, 0x01, 0x00, | |
184 | + /* #11, up and down arrow */ | |
185 | + 0x04, 0x0E, 0x1F, 0x00, 0x00, 0x1F, 0x0E, 0x04, | |
186 | + /* #12, plus/minus */ | |
187 | + 0x04, 0x04, 0x1F, 0x04, 0x04, 0x00, 0x1F, 0x00, | |
188 | + /* #13, fat exclamation mark */ | |
189 | + 0x06, 0x06, 0x06, 0x06, 0x00, 0x06, 0x06, 0x00, | |
190 | + /* #14, empty square */ | |
191 | + 0x00, 0x1F, 0x11, 0x11, 0x11, 0x1F, 0x00, 0x00, | |
192 | + /* #15, struck out square */ | |
193 | + 0x00, 0x1F, 0x19, 0x15, 0x13, 0x1F, 0x00, 0x00, | |
194 | +}; | |
195 | + | |
196 | +static void hd44780_init_char_gen(void) | |
197 | +{ | |
198 | + int i; | |
199 | + | |
200 | + hd44780_instruction(HD44780_SET_CGRAM_ADDR); | |
201 | + | |
202 | + for (i = 0; i < sizeof(char_gen_chars); i++) | |
203 | + hd44780_write_char(char_gen_chars[i]); | |
204 | + | |
205 | + hd44780_instruction(HD44780_SET_DDRAM_ADDR); | |
206 | +} | |
207 | + | |
208 | +void work_92105_display_init(void) | |
209 | +{ | |
210 | + int claim_err; | |
211 | + char *display_contrast_str; | |
212 | + uint8_t display_contrast = CONTRAST_DEFAULT; | |
213 | + uint8_t enable_backlight = 0x96; | |
214 | + | |
215 | + slave = spi_setup_slave(0, 0, 500000, 0); | |
216 | + | |
217 | + if (!slave) { | |
218 | + printf("Failed to set up SPI slave\n"); | |
219 | + return; | |
220 | + } | |
221 | + | |
222 | + claim_err = spi_claim_bus(slave); | |
223 | + | |
224 | + if (claim_err) | |
225 | + debug("Failed to claim SPI bus: %d\n", claim_err); | |
226 | + | |
227 | + /* enable backlight */ | |
228 | + i2c_write(0x2c, 0x01, 1, &enable_backlight, 1); | |
229 | + | |
230 | + /* set display contrast */ | |
231 | + display_contrast_str = getenv("fwopt_dispcontrast"); | |
232 | + if (display_contrast_str) | |
233 | + display_contrast = simple_strtoul(display_contrast_str, | |
234 | + NULL, 10); | |
235 | + i2c_write(0x2c, 0x00, 1, &display_contrast, 1); | |
236 | + | |
237 | + /* request GPO_15 as an output initially set to 1 */ | |
238 | + gpio_request(GPO_15, "MAX6957_nCS"); | |
239 | + gpio_direction_output(GPO_15, 1); | |
240 | + | |
241 | + /* enable MAX6957 portexpander */ | |
242 | + max6957aax_write(MAX6957_CONF, 0x01); | |
243 | + /* configure pin 8 as input, pins 9..19 as outputs */ | |
244 | + max6957aax_write(MAX6957_CONF_08_11, 0x56); | |
245 | + max6957aax_write(MAX6957_CONF_12_15, 0x55); | |
246 | + max6957aax_write(MAX6957_CONF_16_19, 0x55); | |
247 | + | |
248 | + /* initialize HD44780 */ | |
249 | + max6957aax_write(MAX6957AAX_HD44780_EN, 0); | |
250 | + hd44780_instruction(HD44780_FUNCTION_SET); | |
251 | + hd44780_instruction(HD44780_DISPLAY_ON_OFF_CONTROL); | |
252 | + hd44780_instruction(HD44780_ENTRY_MODE_SET); | |
253 | + | |
254 | + /* write custom character glyphs */ | |
255 | + hd44780_init_char_gen(); | |
256 | + | |
257 | + /* Show U-Boot version, date and time as a sign-of-life */ | |
258 | + hd44780_instruction(HD44780_CLEAR_DISPLAY); | |
259 | + hd44780_instruction(HD44780_SET_DDRAM_ADDR | 0); | |
260 | + hd44780_write_str(U_BOOT_VERSION); | |
261 | + hd44780_instruction(HD44780_SET_DDRAM_ADDR | 64); | |
262 | + hd44780_write_str(U_BOOT_DATE); | |
263 | + hd44780_instruction(HD44780_SET_DDRAM_ADDR | 64 | 20); | |
264 | + hd44780_write_str(U_BOOT_TIME); | |
265 | +} | |
266 | + | |
267 | +#ifdef CONFIG_CMD_MAX6957 | |
268 | + | |
269 | +static int do_max6957aax(cmd_tbl_t *cmdtp, int flag, int argc, | |
270 | + char *const argv[]) | |
271 | +{ | |
272 | + int reg, val; | |
273 | + | |
274 | + if (argc != 3) | |
275 | + return CMD_RET_USAGE; | |
276 | + switch (argv[1][0]) { | |
277 | + case 'r': | |
278 | + case 'R': | |
279 | + reg = simple_strtoul(argv[2], NULL, 0); | |
280 | + val = max6957aax_read(reg); | |
281 | + printf("MAX6957 reg 0x%02x read 0x%02x\n", reg, val); | |
282 | + return 0; | |
283 | + default: | |
284 | + reg = simple_strtoul(argv[1], NULL, 0); | |
285 | + val = simple_strtoul(argv[2], NULL, 0); | |
286 | + max6957aax_write(reg, val); | |
287 | + printf("MAX6957 reg 0x%02x wrote 0x%02x\n", reg, val); | |
288 | + return 0; | |
289 | + } | |
290 | + return 1; | |
291 | +} | |
292 | + | |
293 | +#ifdef CONFIG_SYS_LONGHELP | |
294 | +static char max6957aax_help_text[] = | |
295 | + "max6957aax - write or read display register:\n" | |
296 | + "\tmax6957aax R|r reg - read display register;\n" | |
297 | + "\tmax6957aax reg val - write display register."; | |
298 | +#endif | |
299 | + | |
300 | +U_BOOT_CMD( | |
301 | + max6957aax, 6, 1, do_max6957aax, | |
302 | + "SPI MAX6957 display write/read", | |
303 | + max6957aax_help_text | |
304 | +); | |
305 | +#endif /* CONFIG_CMD_MAX6957 */ | |
306 | + | |
307 | +#ifdef CONFIG_CMD_HD44760 | |
308 | + | |
309 | +/* | |
310 | + * We need the HUSH parser because we need string arguments, and | |
311 | + * only HUSH can understand them. | |
312 | + */ | |
313 | + | |
314 | +#if !defined(CONFIG_SYS_HUSH_PARSER) | |
315 | +#error CONFIG_CMD_HD44760 requires CONFIG_SYS_HUSH_PARSER | |
316 | +#endif | |
317 | + | |
318 | +static int do_hd44780(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) | |
319 | +{ | |
320 | + char *cmd; | |
321 | + | |
322 | + if (argc != 3) | |
323 | + return CMD_RET_USAGE; | |
324 | + | |
325 | + cmd = argv[1]; | |
326 | + | |
327 | + if (strcasecmp(cmd, "cmd") == 0) | |
328 | + hd44780_instruction(simple_strtol(argv[2], NULL, 0)); | |
329 | + else if (strcasecmp(cmd, "data") == 0) | |
330 | + hd44780_write_char(simple_strtol(argv[2], NULL, 0)); | |
331 | + else if (strcasecmp(cmd, "str") == 0) | |
332 | + hd44780_write_str(argv[2]); | |
333 | + return 0; | |
334 | +} | |
335 | + | |
336 | +#ifdef CONFIG_SYS_LONGHELP | |
337 | +static char hd44780_help_text[] = | |
338 | + "hd44780 - control LCD driver:\n" | |
339 | + "\thd44780 cmd <val> - send command <val> to driver;\n" | |
340 | + "\thd44780 data <val> - send data <val> to driver;\n" | |
341 | + "\thd44780 str \"<text>\" - send \"<text>\" to driver."; | |
342 | +#endif | |
343 | + | |
344 | +U_BOOT_CMD( | |
345 | + hd44780, 6, 1, do_hd44780, | |
346 | + "HD44780 LCD driver control", | |
347 | + hd44780_help_text | |
348 | +); | |
349 | +#endif /* CONFIG_CMD_HD44780 */ |
board/work-microwave/work_92105/work_92105_display.h
1 | +/* | |
2 | + * work_92105 display support interface | |
3 | + * | |
4 | + * (C) Copyright 2014 DENX Software Engineering GmbH | |
5 | + * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> | |
6 | + * | |
7 | + * The work_92105 display is a HD44780-compatible module | |
8 | + * controlled through a MAX6957AAX SPI port expander, two | |
9 | + * MAX518 I2C DACs and native LPC32xx GPO 15. | |
10 | + * | |
11 | + * SPDX-License-Identifier: GPL-2.0+ | |
12 | + */ | |
13 | + | |
14 | +void work_92105_display_init(void); |
board/work-microwave/work_92105/work_92105_spl.c
1 | +/* | |
2 | + * WORK Microwave work_92105 board support | |
3 | + * | |
4 | + * (C) Copyright 2014 DENX Software Engineering GmbH | |
5 | + * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> | |
6 | + * | |
7 | + * SPDX-License-Identifier: GPL-2.0+ | |
8 | + */ | |
9 | + | |
10 | +#include <common.h> | |
11 | +#include <asm/io.h> | |
12 | +#include <asm/arch/sys_proto.h> | |
13 | +#include <asm/arch/cpu.h> | |
14 | +#include <asm/arch/emc.h> | |
15 | +#include <asm/gpio.h> | |
16 | +#include <spl.h> | |
17 | +#include "work_92105_display.h" | |
18 | + | |
19 | +struct emc_dram_settings dram_64mb = { | |
20 | + .cmddelay = 0x0001C000, | |
21 | + .config0 = 0x00005682, | |
22 | + .rascas0 = 0x00000302, | |
23 | + .rdconfig = 0x00000011, | |
24 | + .trp = 52631578, | |
25 | + .tras = 20833333, | |
26 | + .tsrex = 12500000, | |
27 | + .twr = 66666666, | |
28 | + .trc = 13888888, | |
29 | + .trfc = 10256410, | |
30 | + .txsr = 12500000, | |
31 | + .trrd = 1, | |
32 | + .tmrd = 1, | |
33 | + .tcdlr = 0, | |
34 | + .refresh = 128000, | |
35 | + .mode = 0x00018000, | |
36 | + .emode = 0x02000000 | |
37 | +}; | |
38 | + | |
39 | +const struct emc_dram_settings dram_128mb = { | |
40 | + .cmddelay = 0x0001C000, | |
41 | + .config0 = 0x00005882, | |
42 | + .rascas0 = 0x00000302, | |
43 | + .rdconfig = 0x00000011, | |
44 | + .trp = 52631578, | |
45 | + .tras = 22222222, | |
46 | + .tsrex = 8333333, | |
47 | + .twr = 66666666, | |
48 | + .trc = 14814814, | |
49 | + .trfc = 10256410, | |
50 | + .txsr = 8333333, | |
51 | + .trrd = 1, | |
52 | + .tmrd = 1, | |
53 | + .tcdlr = 0, | |
54 | + .refresh = 128000, | |
55 | + .mode = 0x00030000, | |
56 | + .emode = 0x02000000 | |
57 | +}; | |
58 | + | |
59 | +void spl_board_init(void) | |
60 | +{ | |
61 | + /* initialize serial port for console */ | |
62 | + lpc32xx_uart_init(CONFIG_SYS_LPC32XX_UART); | |
63 | + /* initialize console */ | |
64 | + preloader_console_init(); | |
65 | + /* init DDR and NAND to chainload U-Boot */ | |
66 | + ddr_init(&dram_128mb); | |
67 | + /* | |
68 | + * If this is actually a 64MB module, then the highest column | |
69 | + * bit in any address will be ignored, and thus address 0x80000000 | |
70 | + * should be mirrored at address 0x80000800. Test this. | |
71 | + */ | |
72 | + writel(0x31415926, 0x80000000); /* write Pi at 0x80000000 */ | |
73 | + writel(0x16180339, 0x80000800); /* write Phi at 0x80000800 */ | |
74 | + if (readl(0x80000000) == 0x16180339) /* check 0x80000000 */ { | |
75 | + /* actually 64MB mirrored: reconfigure controller */ | |
76 | + ddr_init(&dram_64mb); | |
77 | + } | |
78 | + /* initialize NAND controller to load U-Boot from NAND */ | |
79 | + lpc32xx_mlc_nand_init(); | |
80 | +} | |
81 | + | |
82 | +u32 spl_boot_device(void) | |
83 | +{ | |
84 | + return BOOT_DEVICE_NAND; | |
85 | +} |
configs/work_92105_defconfig
include/configs/work_92105.h
1 | +/* | |
2 | + * WORK Microwave work_92105 board configuration file | |
3 | + * | |
4 | + * (C) Copyright 2014 DENX Software Engineering GmbH | |
5 | + * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr> | |
6 | + * | |
7 | + * SPDX-License-Identifier: GPL-2.0+ | |
8 | + */ | |
9 | + | |
10 | +#ifndef __CONFIG_WORK_92105_H__ | |
11 | +#define __CONFIG_WORK_92105_H__ | |
12 | + | |
13 | +/* SoC and board defines */ | |
14 | +#include <linux/sizes.h> | |
15 | +#include <asm/arch/cpu.h> | |
16 | + | |
17 | +/* | |
18 | + * Define work_92105 machine type by hand -- done only for compatibility | |
19 | + * with original board code | |
20 | + */ | |
21 | +#define MACH_TYPE_WORK_92105 736 | |
22 | +#define CONFIG_MACH_TYPE MACH_TYPE_WORK_92105 | |
23 | + | |
24 | +#define CONFIG_SYS_ICACHE_OFF | |
25 | +#define CONFIG_SYS_DCACHE_OFF | |
26 | +#if !defined(CONFIG_SPL_BUILD) | |
27 | +#define CONFIG_SKIP_LOWLEVEL_INIT | |
28 | +#endif | |
29 | +#define CONFIG_BOARD_EARLY_INIT_F | |
30 | +#define CONFIG_BOARD_EARLY_INIT_R | |
31 | + | |
32 | +/* generate LPC32XX-specific SPL image */ | |
33 | +#define CONFIG_LPC32XX_SPL | |
34 | + | |
35 | +/* | |
36 | + * Memory configurations | |
37 | + */ | |
38 | +#define CONFIG_NR_DRAM_BANKS 1 | |
39 | +#define CONFIG_SYS_MALLOC_LEN SZ_1M | |
40 | +#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE | |
41 | +#define CONFIG_SYS_SDRAM_SIZE SZ_128M | |
42 | +#define CONFIG_SYS_TEXT_BASE 0x80100000 | |
43 | +#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + SZ_32K) | |
44 | +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - SZ_1M) | |
45 | + | |
46 | +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K) | |
47 | + | |
48 | +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_512K \ | |
49 | + - GENERATED_GBL_DATA_SIZE) | |
50 | + | |
51 | +/* | |
52 | + * Serial Driver | |
53 | + */ | |
54 | +#define CONFIG_SYS_LPC32XX_UART 5 /* UART5 - NS16550 */ | |
55 | +#define CONFIG_BAUDRATE 115200 | |
56 | + | |
57 | +/* | |
58 | + * Ethernet Driver | |
59 | + */ | |
60 | + | |
61 | +#define CONFIG_PHY_SMSC | |
62 | +#define CONFIG_LPC32XX_ETH | |
63 | +#define CONFIG_PHYLIB | |
64 | +#define CONFIG_PHY_ADDR 0 | |
65 | +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
66 | +#define CONFIG_CMD_MII | |
67 | +#define CONFIG_CMD_PING | |
68 | +#define CONFIG_CMD_DHCP | |
69 | +/* FIXME: remove "Waiting for PHY auto negotiation to complete..." message */ | |
70 | + | |
71 | +/* | |
72 | + * I2C driver | |
73 | + */ | |
74 | + | |
75 | +#define CONFIG_SYS_I2C_LPC32XX | |
76 | +#define CONFIG_SYS_I2C | |
77 | +#define CONFIG_CMD_I2C | |
78 | +#define CONFIG_SYS_I2C_SPEED 350000 | |
79 | + | |
80 | +/* | |
81 | + * I2C EEPROM | |
82 | + */ | |
83 | + | |
84 | +#define CONFIG_CMD_EEPROM | |
85 | +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x56 | |
86 | +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
87 | + | |
88 | +/* | |
89 | + * I2C RTC | |
90 | + */ | |
91 | + | |
92 | +#define CONFIG_CMD_DATE | |
93 | +#define CONFIG_RTC_DS1374 | |
94 | + | |
95 | +/* | |
96 | + * I2C Temperature Sensor (DTT) | |
97 | + */ | |
98 | + | |
99 | +#define CONFIG_CMD_DTT | |
100 | +#define CONFIG_DTT_SENSORS { 0, 1 } | |
101 | +#define CONFIG_DTT_DS620 | |
102 | + | |
103 | +/* | |
104 | + * U-Boot General Configurations | |
105 | + */ | |
106 | +#define CONFIG_SYS_GENERIC_BOARD | |
107 | +#define CONFIG_SYS_LONGHELP | |
108 | +#define CONFIG_SYS_CBSIZE 1024 | |
109 | +#define CONFIG_SYS_PBSIZE \ | |
110 | + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
111 | +#define CONFIG_SYS_MAXARGS 16 | |
112 | +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
113 | + | |
114 | +#define CONFIG_SYS_HUSH_PARSER | |
115 | + | |
116 | +#define CONFIG_AUTO_COMPLETE | |
117 | +#define CONFIG_CMDLINE_EDITING | |
118 | +#define CONFIG_VERSION_VARIABLE | |
119 | +#define CONFIG_DISPLAY_CPUINFO | |
120 | +#define CONFIG_DOS_PARTITION | |
121 | + | |
122 | +/* | |
123 | + * No NOR | |
124 | + */ | |
125 | + | |
126 | +#define CONFIG_SYS_NO_FLASH | |
127 | + | |
128 | +/* | |
129 | + * NAND chip timings for FIXME: which one? | |
130 | + */ | |
131 | + | |
132 | +#define CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY 333333333 | |
133 | +#define CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY 10000000 | |
134 | +#define CONFIG_LPC32XX_NAND_MLC_NAND_TA 18181818 | |
135 | +#define CONFIG_LPC32XX_NAND_MLC_RD_HIGH 31250000 | |
136 | +#define CONFIG_LPC32XX_NAND_MLC_RD_LOW 45454545 | |
137 | +#define CONFIG_LPC32XX_NAND_MLC_WR_HIGH 40000000 | |
138 | +#define CONFIG_LPC32XX_NAND_MLC_WR_LOW 83333333 | |
139 | + | |
140 | +/* | |
141 | + * NAND | |
142 | + */ | |
143 | + | |
144 | +/* driver configuration */ | |
145 | +#define CONFIG_SYS_NAND_SELF_INIT | |
146 | +#define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
147 | +#define CONFIG_SYS_MAX_NAND_CHIPS 1 | |
148 | +#define CONFIG_SYS_NAND_BASE MLC_NAND_BASE | |
149 | +#define CONFIG_NAND_LPC32XX_MLC | |
150 | + | |
151 | +#define CONFIG_CMD_NAND | |
152 | + | |
153 | +/* | |
154 | + * GPIO | |
155 | + */ | |
156 | + | |
157 | +#define CONFIG_CMD_GPIO | |
158 | +#define CONFIG_LPC32XX_GPIO | |
159 | + | |
160 | +/* | |
161 | + * SSP/SPI/DISPLAY | |
162 | + */ | |
163 | + | |
164 | +#define CONFIG_CMD_SPI | |
165 | +#define CONFIG_LPC32XX_SSP | |
166 | +#define CONFIG_LPC32XX_SSP_TIMEOUT 100000 | |
167 | +#define CONFIG_CMD_MAX6957 | |
168 | +#define CONFIG_CMD_HD44760 | |
169 | +/* | |
170 | + * Environment | |
171 | + */ | |
172 | + | |
173 | +#define CONFIG_ENV_IS_IN_NAND 1 | |
174 | +#define CONFIG_ENV_SIZE 0x00020000 | |
175 | +#define CONFIG_ENV_OFFSET 0x00100000 | |
176 | +#define CONFIG_ENV_OFFSET_REDUND 0x00120000 | |
177 | +#define CONFIG_ENV_ADDR 0x80000100 | |
178 | + | |
179 | +/* | |
180 | + * Provide default ethernet address | |
181 | + * | |
182 | + * THIS IS NORMALLY NOT DONE. HERE WE KEEP WHAT WAS IN THE PORTED | |
183 | + * BOARD CONFIG IN CASE SOME PROVISIONING PROCESS OUT THERE EXPECTS | |
184 | + * THIS MAC ADDRESS WHEN THE DEVICE HAS STILL ITS DEFAULT CONFIG. | |
185 | + */ | |
186 | + | |
187 | +#define CONFIG_ETHADDR 00:12:B4:00:AF:FE | |
188 | +#define CONFIG_OVERWRITE_ETHADDR_ONCE | |
189 | + | |
190 | +/* | |
191 | + * U-Boot Commands | |
192 | + */ | |
193 | +#include <config_cmd_default.h> | |
194 | + | |
195 | +/* | |
196 | + * Boot Linux | |
197 | + */ | |
198 | +#define CONFIG_CMDLINE_TAG | |
199 | +#define CONFIG_SETUP_MEMORY_TAGS | |
200 | +#define CONFIG_INITRD_TAG | |
201 | + | |
202 | +#define CONFIG_ZERO_BOOTDELAY_CHECK | |
203 | +#define CONFIG_BOOTDELAY 3 | |
204 | + | |
205 | +#define CONFIG_BOOTFILE "uImage" | |
206 | +#define CONFIG_BOOTARGS "console=ttyS2,115200n8" | |
207 | +#define CONFIG_LOADADDR 0x80008000 | |
208 | + | |
209 | +/* | |
210 | + * SPL | |
211 | + */ | |
212 | + | |
213 | +/* SPL will be executed at offset 0 */ | |
214 | +#define CONFIG_SPL_TEXT_BASE 0x00000000 | |
215 | +/* SPL will use SRAM as stack */ | |
216 | +#define CONFIG_SPL_STACK 0x0000FFF8 | |
217 | +#define CONFIG_SPL_BOARD_INIT | |
218 | +/* Use the framework and generic lib */ | |
219 | +#define CONFIG_SPL_FRAMEWORK | |
220 | +#define CONFIG_SPL_LIBGENERIC_SUPPORT | |
221 | +#define CONFIG_SPL_LIBCOMMON_SUPPORT | |
222 | +/* SPL will use serial */ | |
223 | +#define CONFIG_SPL_SERIAL_SUPPORT | |
224 | +/* SPL will load U-Boot from NAND offset 0x40000 */ | |
225 | +#define CONFIG_SPL_NAND_SUPPORT | |
226 | +#define CONFIG_SPL_NAND_DRIVERS | |
227 | +#define CONFIG_SPL_NAND_BASE | |
228 | +#define CONFIG_SPL_NAND_BOOT | |
229 | +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00040000 | |
230 | +#define CONFIG_SPL_PAD_TO 0x20000 | |
231 | +/* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */ | |
232 | +#define CONFIG_SYS_MONITOR_LEN 0x40000 /* actually, MAX size */ | |
233 | +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE | |
234 | +#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE | |
235 | + | |
236 | +/* | |
237 | + * Include SoC specific configuration | |
238 | + */ | |
239 | +#include <asm/arch/config.h> | |
240 | + | |
241 | +#endif /* __CONFIG_WORK_92105_H__*/ |