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Commit 41702bac01c585cc11fa5dd1f38dea1e5a7c642d

Authored by Bin Meng
Committed by Simon Glass
1 parent aada6276c6
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

x86: Rename coreboot-serial to x86-serial 

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>

Showing 7 changed files with 43 additions and 43 deletions Side-by-side Diff

arch/x86/dts/coreboot.dtsi
Diff comments   View file @ 41702ba
... ... @@ -6,7 +6,7 @@
6 6 };
7 7  
8 8 serial {
9   - compatible = "coreboot-uart";
  9 + compatible = "x86-uart";
10 10 reg = <0x3f8 0x10>;
11 11 reg-shift = <0>;
12 12 io-mapped = <1>;
drivers/serial/Makefile
Diff comments   View file @ 41702ba
... ... @@ -43,7 +43,7 @@
43 43 obj-$(CONFIG_TEGRA_SERIAL) += serial_tegra.o
44 44 obj-$(CONFIG_UNIPHIER_SERIAL) += serial_uniphier.o
45 45 obj-$(CONFIG_OMAP_SERIAL) += serial_omap.o
46   -obj-$(CONFIG_COREBOOT_SERIAL) += serial_coreboot.o
  46 +obj-$(CONFIG_X86_SERIAL) += serial_x86.o
47 47  
48 48 ifndef CONFIG_SPL_BUILD
49 49 obj-$(CONFIG_USB_TTY) += usbtty.o
drivers/serial/serial_coreboot.c
View file @ 41702ba
1   -/*
2   - * Copyright (c) 2014 Google, Inc
3   - *
4   - * SPDX-License-Identifier: GPL-2.0+
5   - */
6   -
7   -#include <common.h>
8   -#include <dm.h>
9   -#include <ns16550.h>
10   -#include <serial.h>
11   -
12   -static const struct udevice_id coreboot_serial_ids[] = {
13   - { .compatible = "coreboot-uart" },
14   - { }
15   -};
16   -
17   -static int coreboot_serial_ofdata_to_platdata(struct udevice *dev)
18   -{
19   - struct ns16550_platdata *plat = dev_get_platdata(dev);
20   - int ret;
21   -
22   - ret = ns16550_serial_ofdata_to_platdata(dev);
23   - if (ret)
24   - return ret;
25   - plat->clock = 1843200;
26   -
27   - return 0;
28   -}
29   -U_BOOT_DRIVER(serial_ns16550) = {
30   - .name = "serial_coreboot",
31   - .id = UCLASS_SERIAL,
32   - .of_match = coreboot_serial_ids,
33   - .ofdata_to_platdata = coreboot_serial_ofdata_to_platdata,
34   - .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
35   - .priv_auto_alloc_size = sizeof(struct NS16550),
36   - .probe = ns16550_serial_probe,
37   - .ops = &ns16550_serial_ops,
38   -};
drivers/serial/serial_x86.c
Diff comments   View file @ 41702ba
  1 +/*
  2 + * Copyright (c) 2014 Google, Inc
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <dm.h>
  9 +#include <ns16550.h>
  10 +#include <serial.h>
  11 +
  12 +static const struct udevice_id x86_serial_ids[] = {
  13 + { .compatible = "x86-uart" },
  14 + { }
  15 +};
  16 +
  17 +static int x86_serial_ofdata_to_platdata(struct udevice *dev)
  18 +{
  19 + struct ns16550_platdata *plat = dev_get_platdata(dev);
  20 + int ret;
  21 +
  22 + ret = ns16550_serial_ofdata_to_platdata(dev);
  23 + if (ret)
  24 + return ret;
  25 + plat->clock = 1843200;
  26 +
  27 + return 0;
  28 +}
  29 +U_BOOT_DRIVER(serial_ns16550) = {
  30 + .name = "serial_x86",
  31 + .id = UCLASS_SERIAL,
  32 + .of_match = x86_serial_ids,
  33 + .ofdata_to_platdata = x86_serial_ofdata_to_platdata,
  34 + .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
  35 + .priv_auto_alloc_size = sizeof(struct NS16550),
  36 + .probe = ns16550_serial_probe,
  37 + .ops = &ns16550_serial_ops,
  38 +};
include/configs/chromebook_link.h
Diff comments   View file @ 41702ba
... ... @@ -28,7 +28,7 @@
28 28 #define CONFIG_X86_MRC_ADDR 0xfffa0000
29 29 #define CONFIG_CACHE_MRC_SIZE_KB 512
30 30  
31   -#define CONFIG_COREBOOT_SERIAL
  31 +#define CONFIG_X86_SERIAL
32 32  
33 33 #define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \
34 34 PCI_DEVICE_ID_INTEL_NM10_AHCI}, \
include/configs/coreboot.h
Diff comments   View file @ 41702ba
... ... @@ -49,7 +49,7 @@
49 49 {PCI_VENDOR_ID_INTEL, \
50 50 PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}
51 51  
52   -#define CONFIG_COREBOOT_SERIAL
  52 +#define CONFIG_X86_SERIAL
53 53  
54 54 #define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \
55 55 "stdout=vga,serial,cbmem\0" \
include/configs/crownbay.h
Diff comments   View file @ 41702ba
... ... @@ -20,7 +20,7 @@
20 20 #define CONFIG_X86_RESET_VECTOR
21 21 #define CONFIG_NR_DRAM_BANKS 1
22 22  
23   -#define CONFIG_COREBOOT_SERIAL
  23 +#define CONFIG_X86_SERIAL
24 24 #define CONFIG_SMSC_LPC47M
25 25  
26 26 #define CONFIG_PCI_MEM_BUS 0x40000000