ARM: atmel: at91sam9m10g45ek: enable spl support

Supports boot up from NAND flash with software ECC eanbled. And supports boot up from SD/MMC card with FAT file system. As the boot from SD/MMC card with FAT file system, the BSS segment is too big to fit into SRAM, so, use the lds to put it into SDRAM. Signed-off-by: Bo Shen <voice.shen@atmel.com>

ARM: atmel: at91sam9m10g45ek: enable spl support
Supports boot up from NAND flash with software ECC eanbled. And supports boot up from SD/MMC card with FAT file system. As the boot from SD/MMC card with FAT file system, the BSS segment is too big to fit into SRAM, so, use the lds to put it into SDRAM. Signed-off-by: Bo Shen <voice.shen@atmel.com>
Bo Shen · Andreas Bießmann
1 parent 72cb3b6b54
Showing 7 changed files with 194 additions and 1 deletions Side-by-side Diff
arch/arm/mach-at91/Kconfig
arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
arch/arm/mach-at91/spl_at91.c
board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c
configs/at91sam9m10g45ek_mmc_defconfig
configs/at91sam9m10g45ek_nandflash_defconfig
include/configs/at91sam9m10g45ek.h
@@ -66,6 +66,7 @@
 config TARGET_AT91SAM9M10G45EK
 	bool "Atmel AT91SAM9M10G45-EK board"
 	select CPU_ARM926EJS
+	select SUPPORT_SPL
  
 config TARGET_PM9G45
 	bool "Ronetix pm9g45 board"
+/*
+ * Copyright (C) 2015 Atmel Corporation
+ *		      Bo Shen <voice.shen@atmel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE, \
+		LENGTH = CONFIG_SPL_MAX_SIZE }
+MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
+		LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	.text      :
+	{
+		__start = .;
+		*(.vectors)
+		arch/arm/cpu/arm926ejs/start.o	(.text*)
+		*(.text*)
+	} >.sram
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram
+
+	. = ALIGN(4);
+	.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+
+	. = ALIGN(4);
+	__image_copy_end = .;
+
+	.end :
+	{
+		*(.__end)
+	} >.sram
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start = .;
+		*(.bss*)
+		. = ALIGN(4);
+		__bss_end = .;
+	} >.sdram
+}
@@ -71,7 +71,11 @@
 {
 }
  
-void spl_board_init(void)
+void __weak spl_board_init(void)
+{
+}
+
+void board_init_f(ulong dummy)
 {
 	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  
@@ -8,6 +8,7 @@
  
 #include <common.h>
 #include <asm/io.h>
+#include <asm/arch/clk.h>
 #include <asm/arch/at91sam9g45_matrix.h>
 #include <asm/arch/at91sam9_smc.h>
 #include <asm/arch/at91_common.h>
@@ -15,6 +16,7 @@
 #include <asm/arch/gpio.h>
 #include <asm/arch/clk.h>
 #include <lcd.h>
+#include <linux/mtd/nand.h>
 #include <atmel_lcdc.h>
 #include <atmel_mci.h>
 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
@@ -68,6 +70,84 @@
  
 	/* Enable NandFlash */
 	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif
+
+#if defined(CONFIG_SPL_BUILD)
+#include <spl.h>
+#include <nand.h>
+
+void at91_spl_board_init(void)
+{
+	/*
+	 * On the at91sam9m10g45ek board, the chip wm9711 stays in the
+	 * test mode, so it needs do some action to exit test mode.
+	 */
+	at91_periph_clk_enable(ATMEL_ID_PIODE);
+	at91_set_gpio_output(AT91_PIN_PD7, 0);
+	at91_set_gpio_output(AT91_PIN_PD8, 0);
+	at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1);
+	at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1);
+
+#ifdef CONFIG_SYS_USE_MMC
+	at91_mci_hw_init();
+#elif CONFIG_SYS_USE_NANDFLASH
+	at91sam9m10g45ek_nand_hw_init();
+#endif
+}
+
+#include <asm/arch/atmel_mpddrc.h>
+static void ddr2_conf(struct atmel_mpddr *ddr2)
+{
+	ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+	ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+		    ATMEL_MPDDRC_CR_NR_ROW_14 |
+		    ATMEL_MPDDRC_CR_DQMS_SHARED |
+		    ATMEL_MPDDRC_CR_CAS_DDR_CAS3);
+
+	ddr2->rtr = 0x24b;
+
+	ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |/* 6*7.5 = 45 ns */
+		      2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |/* 2*7.5 = 15 ns */
+		      2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | /* 2*7.5 = 15 ns */
+		      8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | /* 8*7.5 = 60 ns */
+		      2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | /* 2*7.5 = 15 ns */
+		      1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | /* 1*7.5= 7.5 ns*/
+		      1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | /* 1 clk cycle */
+		      2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */
+
+	ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | /* 2*7.5 = 15 ns */
+		      200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+		      16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+		      14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+	ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+		      0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+		      7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+		      2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
+	struct at91_matrix *mat = (struct at91_matrix *)ATMEL_BASE_MATRIX;
+	struct atmel_mpddr ddr2;
+	unsigned long csa;
+
+	ddr2_conf(&ddr2);
+
+	/* enable DDR2 clock */
+	writel(0x4, &pmc->scer);
+
+	/* Chip select 1 is for DDR2/SDRAM */
+	csa = readl(&mat->ebicsa);
+	csa |= AT91_MATRIX_EBI_CS1A_SDRAMC;
+	csa &= ~AT91_MATRIX_EBI_VDDIOMSEL_3_3V;
+	writel(csa, &mat->ebicsa);
+
+	/* DDRAM2 Controller initialize */
+	ddr2_init(ATMEL_BASE_CS6, &ddr2);
 }
 #endif
  
+CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC"
 CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
+CONFIG_SPL=y
 CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_NANDFLASH"
 CONFIG_ARM=y
 CONFIG_ARCH_AT91=y
@@ -203,5 +203,63 @@
  */
 #define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
  
+/* Defines for SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE		0x300000
+#define CONFIG_SPL_MAX_SIZE		0x010000
+#define CONFIG_SPL_STACK		0x310000
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+
+#define CONFIG_SYS_MONITOR_LEN		0x80000
+
+#ifdef CONFIG_SYS_USE_MMC
+
+#define CONFIG_SPL_BSS_START_ADDR	0x70000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x00080000
+#define CONFIG_SYS_SPL_MALLOC_START	0x70080000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00080000
+
+#define CONFIG_SPL_LDSCRIPT		arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x400
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot.img"
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+
+#elif CONFIG_SYS_USE_NANDFLASH
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_NAND_SOFTECC
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x80000
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+
+#define CONFIG_SYS_NAND_PAGE_SIZE	0x800
+#define CONFIG_SYS_NAND_BLOCK_SIZE	0x20000
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCSIZE		256
+#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
+					  48, 49, 50, 51, 52, 53, 54, 55, \
+					  56, 57, 58, 59, 60, 61, 62, 63, }
+#endif
+
+#define CONFIG_SPL_ATMEL_SIZE
+#define CONFIG_SYS_MASTER_CLOCK		132096000
+#define CONFIG_SYS_AT91_PLLA		0x20c73f03
+#define CONFIG_SYS_MCKR			0x1301
+#define CONFIG_SYS_MCKR_CSS		0x1302
+
+#define ATMEL_BASE_MPDDRC		ATMEL_BASE_DDRSDRC0
 #endif
...	...	@@ -66,6 +66,7 @@
66	66	config TARGET_AT91SAM9M10G45EK
67	67	bool "Atmel AT91SAM9M10G45-EK board"
68	68	select CPU_ARM926EJS
	69	+ select SUPPORT_SPL
69	70
70	71	config TARGET_PM9G45
71	72	bool "Ronetix pm9g45 board"
	1	+/*
	2	+ * Copyright (C) 2015 Atmel Corporation
	3	+ * Bo Shen <voice.shen@atmel.com>
	4	+ *
	5	+ * SPDX-License-Identifier: GPL-2.0+
	6	+ */
	7	+
	8	+MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE, \
	9	+ LENGTH = CONFIG_SPL_MAX_SIZE }
	10	+MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \
	11	+ LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
	12	+
	13	+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
	14	+OUTPUT_ARCH(arm)
	15	+ENTRY(_start)
	16	+SECTIONS
	17	+{
	18	+ .text :
	19	+ {
	20	+ __start = .;
	21	+ *(.vectors)
	22	+ arch/arm/cpu/arm926ejs/start.o (.text*)
	23	+ (.text)
	24	+ } >.sram
	25	+
	26	+ . = ALIGN(4);
	27	+ .rodata : { (SORT_BY_ALIGNMENT(.rodata)) } >.sram
	28	+
	29	+ . = ALIGN(4);
	30	+ .data : { (SORT_BY_ALIGNMENT(.data)) } >.sram
	31	+
	32	+ . = ALIGN(4);
	33	+ __image_copy_end = .;
	34	+
	35	+ .end :
	36	+ {
	37	+ *(.__end)
	38	+ } >.sram
	39	+
	40	+ .bss :
	41	+ {
	42	+ . = ALIGN(4);
	43	+ __bss_start = .;
	44	+ (.bss)
	45	+ . = ALIGN(4);
	46	+ __bss_end = .;
	47	+ } >.sdram
	48	+}
...	...	@@ -71,7 +71,11 @@
71	71	{
72	72	}
73	73
74		-void spl_board_init(void)
	74	+void __weak spl_board_init(void)
	75	+{
	76	+}
	77	+
	78	+void board_init_f(ulong dummy)
75	79	{
76	80	struct at91_pmc pmc = (struct at91_pmc )ATMEL_BASE_PMC;
77	81
...	...	@@ -8,6 +8,7 @@
8	8
9	9	#include <common.h>
10	10	#include <asm/io.h>
	11	+#include <asm/arch/clk.h>
11	12	#include <asm/arch/at91sam9g45_matrix.h>
12	13	#include <asm/arch/at91sam9_smc.h>
13	14	#include <asm/arch/at91_common.h>
...	...	@@ -15,6 +16,7 @@
15	16	#include <asm/arch/gpio.h>
16	17	#include <asm/arch/clk.h>
17	18	#include <lcd.h>
	19	+#include <linux/mtd/nand.h>
18	20	#include <atmel_lcdc.h>
19	21	#include <atmel_mci.h>
20	22	#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
...	...	@@ -68,6 +70,84 @@
68	70
69	71	/* Enable NandFlash */
70	72	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
	73	+}
	74	+#endif
	75	+
	76	+#if defined(CONFIG_SPL_BUILD)
	77	+#include <spl.h>
	78	+#include <nand.h>
	79	+
	80	+void at91_spl_board_init(void)
	81	+{
	82	+ /*
	83	+ * On the at91sam9m10g45ek board, the chip wm9711 stays in the
	84	+ * test mode, so it needs do some action to exit test mode.
	85	+ */
	86	+ at91_periph_clk_enable(ATMEL_ID_PIODE);
	87	+ at91_set_gpio_output(AT91_PIN_PD7, 0);
	88	+ at91_set_gpio_output(AT91_PIN_PD8, 0);
	89	+ at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1);
	90	+ at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1);
	91	+
	92	+#ifdef CONFIG_SYS_USE_MMC
	93	+ at91_mci_hw_init();
	94	+#elif CONFIG_SYS_USE_NANDFLASH
	95	+ at91sam9m10g45ek_nand_hw_init();
	96	+#endif
	97	+}
	98	+
	99	+#include <asm/arch/atmel_mpddrc.h>
	100	+static void ddr2_conf(struct atmel_mpddr *ddr2)
	101	+{
	102	+ ddr2->md = (ATMEL_MPDDRC_MD_DBW_16_BITS \| ATMEL_MPDDRC_MD_DDR2_SDRAM);
	103	+
	104	+ ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 \|
	105	+ ATMEL_MPDDRC_CR_NR_ROW_14 \|
	106	+ ATMEL_MPDDRC_CR_DQMS_SHARED \|
	107	+ ATMEL_MPDDRC_CR_CAS_DDR_CAS3);
	108	+
	109	+ ddr2->rtr = 0x24b;
	110	+
	111	+ ddr2->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET \|/* 67.5 = 45 ns /
	112	+ 2 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET \|/* 27.5 = 15 ns /
	113	+ 2 << ATMEL_MPDDRC_TPR0_TWR_OFFSET \| /* 27.5 = 15 ns /
	114	+ 8 << ATMEL_MPDDRC_TPR0_TRC_OFFSET \| /* 87.5 = 60 ns /
	115	+ 2 << ATMEL_MPDDRC_TPR0_TRP_OFFSET \| /* 27.5 = 15 ns /
	116	+ 1 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET \| /* 17.5= 7.5 ns/
	117	+ 1 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET \| /* 1 clk cycle */
	118	+ 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); /* 2 clk cycles */
	119	+
	120	+ ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET \| /* 27.5 = 15 ns /
	121	+ 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET \|
	122	+ 16 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET \|
	123	+ 14 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
	124	+
	125	+ ddr2->tpr2 = (1 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET \|
	126	+ 0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET \|
	127	+ 7 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET \|
	128	+ 2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
	129	+}
	130	+
	131	+void mem_init(void)
	132	+{
	133	+ struct at91_pmc pmc = (struct at91_pmc )ATMEL_BASE_PMC;
	134	+ struct at91_matrix mat = (struct at91_matrix )ATMEL_BASE_MATRIX;
	135	+ struct atmel_mpddr ddr2;
	136	+ unsigned long csa;
	137	+
	138	+ ddr2_conf(&ddr2);
	139	+
	140	+ /* enable DDR2 clock */
	141	+ writel(0x4, &pmc->scer);
	142	+
	143	+ /* Chip select 1 is for DDR2/SDRAM */
	144	+ csa = readl(&mat->ebicsa);
	145	+ csa \|= AT91_MATRIX_EBI_CS1A_SDRAMC;
	146	+ csa &= ~AT91_MATRIX_EBI_VDDIOMSEL_3_3V;
	147	+ writel(csa, &mat->ebicsa);
	148	+
	149	+ /* DDRAM2 Controller initialize */
	150	+ ddr2_init(ATMEL_BASE_CS6, &ddr2);
71	151	}
72	152	#endif
73	153
	1	+CONFIG_SPL=y
1	2	CONFIG_SYS_EXTRA_OPTIONS="AT91SAM9M10G45,SYS_USE_MMC"
2	3	CONFIG_ARM=y
3	4	CONFIG_ARCH_AT91=y
...	...	@@ -203,5 +203,63 @@
203	203	*/
204	204	#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
205	205
	206	+/* Defines for SPL */
	207	+#define CONFIG_SPL_FRAMEWORK
	208	+#define CONFIG_SPL_TEXT_BASE 0x300000
	209	+#define CONFIG_SPL_MAX_SIZE 0x010000
	210	+#define CONFIG_SPL_STACK 0x310000
	211	+
	212	+#define CONFIG_SPL_LIBCOMMON_SUPPORT
	213	+#define CONFIG_SPL_LIBGENERIC_SUPPORT
	214	+#define CONFIG_SPL_SERIAL_SUPPORT
	215	+#define CONFIG_SPL_GPIO_SUPPORT
	216	+
	217	+#define CONFIG_SYS_MONITOR_LEN 0x80000
	218	+
	219	+#ifdef CONFIG_SYS_USE_MMC
	220	+
	221	+#define CONFIG_SPL_BSS_START_ADDR 0x70000000
	222	+#define CONFIG_SPL_BSS_MAX_SIZE 0x00080000
	223	+#define CONFIG_SYS_SPL_MALLOC_START 0x70080000
	224	+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000
	225	+
	226	+#define CONFIG_SPL_LDSCRIPT arch/arm/mach-at91/arm926ejs/u-boot-spl.lds
	227	+#define CONFIG_SPL_MMC_SUPPORT
	228	+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
	229	+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
	230	+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
	231	+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
	232	+#define CONFIG_SPL_FAT_SUPPORT
	233	+#define CONFIG_SPL_LIBDISK_SUPPORT
	234	+
	235	+#elif CONFIG_SYS_USE_NANDFLASH
	236	+#define CONFIG_SPL_NAND_SUPPORT
	237	+#define CONFIG_SPL_NAND_DRIVERS
	238	+#define CONFIG_SPL_NAND_BASE
	239	+#define CONFIG_SPL_NAND_ECC
	240	+#define CONFIG_SPL_NAND_SOFTECC
	241	+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
	242	+#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
	243	+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	244	+
	245	+#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
	246	+#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
	247	+#define CONFIG_SYS_NAND_PAGE_COUNT 64
	248	+#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
	249	+#define CONFIG_SYS_NAND_ECCSIZE 256
	250	+#define CONFIG_SYS_NAND_ECCBYTES 3
	251	+#define CONFIG_SYS_NAND_OOBSIZE 64
	252	+#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
	253	+ 48, 49, 50, 51, 52, 53, 54, 55, \
	254	+ 56, 57, 58, 59, 60, 61, 62, 63, }
	255	+#endif
	256	+
	257	+#define CONFIG_SPL_ATMEL_SIZE
	258	+#define CONFIG_SYS_MASTER_CLOCK 132096000
	259	+#define CONFIG_SYS_AT91_PLLA 0x20c73f03
	260	+#define CONFIG_SYS_MCKR 0x1301
	261	+#define CONFIG_SYS_MCKR_CSS 0x1302
	262	+
	263	+#define ATMEL_BASE_MPDDRC ATMEL_BASE_DDRSDRC0
206	264	#endif