powerpc: mpc5xxx: remove galaxy5200 board support

This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Eric Millbrandt <emillbrandt@dekaresearch.com>

powerpc: mpc5xxx: remove galaxy5200 board support
This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Eric Millbrandt <emillbrandt@dekaresearch.com>
Masahiro Yamada · Tom Rini
1 parent 6beecd5d09
Showing 9 changed files with 1 additions and 652 deletions Side-by-side Diff
arch/powerpc/cpu/mpc5xxx/Kconfig
board/galaxy5200/Kconfig
board/galaxy5200/MAINTAINERS
board/galaxy5200/Makefile
board/galaxy5200/galaxy5200.c
configs/galaxy5200_LOWBOOT_defconfig
configs/galaxy5200_defconfig
doc/README.scrapyard
include/configs/galaxy5200.h
@@ -20,9 +20,6 @@
 config TARGET_CM5200
 	bool "Support cm5200"
  
-config TARGET_GALAXY5200
-	bool "Support galaxy5200"
-
 config TARGET_INKA4X0
 	bool "Support inka4x0"
  
@@ -77,7 +74,6 @@
 source "board/a4m072/Kconfig"
 source "board/canmb/Kconfig"
 source "board/cm5200/Kconfig"
-source "board/galaxy5200/Kconfig"
 source "board/ifm/o2dnt2/Kconfig"
 source "board/inka4x0/Kconfig"
 source "board/intercontrol/digsy_mtc/Kconfig"
-if TARGET_GALAXY5200
-
-config SYS_BOARD
-	default "galaxy5200"
-
-config SYS_CONFIG_NAME
-	default "galaxy5200"
-
-endif
-GALAXY5200 BOARD
-#M:	Eric Millbrandt <emillbrandt@dekaresearch.com>
-S:	Orphan (since 2014-06)
-F:	board/galaxy5200/
-F:	include/configs/galaxy5200.h
-F:	configs/galaxy5200_defconfig
-F:	configs/galaxy5200_LOWBOOT_defconfig
-#
-# (C) Copyright 2003-2007
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-obj-y	:= galaxy5200.o
-/*
- * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2004
- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
- *
- * (C) Copyright 2006
- * Eric Schumann, Phytec Messtechnik GmbH
- *
- * (C) Copyright 2009
- * Eric Millbrandt, DEKA Research and Development Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc5xxx.h>
-#include <pci.h>
-#include <asm/io.h>
-
-#ifndef CONFIG_SYS_RAMBOOT
-static void sdram_start(int hi_addr)
-{
-	volatile struct mpc5xxx_cdm *cdm =
-		(struct mpc5xxx_cdm *)MPC5XXX_CDM;
-	volatile struct mpc5xxx_sdram *sdram =
-		(struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
-
-	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
-
-	/* unlock mode register */
-	out_be32 (&sdram->ctrl,
-		(SDRAM_CONTROL | 0x80000000 | hi_addr_bit));
-
-	/* precharge all banks */
-	out_be32 (&sdram->ctrl,
-		(SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
-
-#ifdef SDRAM_DDR
-	/* set mode register: extended mode */
-	out_be32 (&sdram->mode, (SDRAM_EMODE));
-
-	/* set mode register: reset DLL */
-	out_be32 (&sdram->mode, (SDRAM_MODE | 0x04000000));
-#endif
-
-	/* precharge all banks */
-	out_be32 (&sdram->ctrl,
-		(SDRAM_CONTROL | 0x80000002 | hi_addr_bit));
-
-	/* auto refresh */
-	out_be32 (&sdram->ctrl,
-		(SDRAM_CONTROL | 0x80000004 | hi_addr_bit));
-
-	/* set mode register */
-	out_be32 (&sdram->mode, (SDRAM_MODE));
-
-	/* normal operation */
-	out_be32 (&sdram->ctrl,
-		(SDRAM_CONTROL | hi_addr_bit));
-
-	/* set CDM clock enable register, set MPC5200B SDRAM bus */
-	/* to reduced driver strength */
-	out_be32 (&cdm->clock_enable, (0x00CFFFFF));
-}
-#endif
-
-/*
- * ATTENTION: Although partially referenced initdram does NOT make
- *	real use of CONFIG_SYS_SDRAM_BASE. The code does not
- *	work if CONFIG_SYS_SDRAM_BASE
- *	is something else than 0x00000000.
- */
-
-phys_size_t initdram(int board_type)
-{
-	volatile struct mpc5xxx_mmap_ctl *mm =
-		(struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
-	volatile struct mpc5xxx_sdram *sdram =
-		(struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
-	ulong dramsize = 0;
-	ulong dramsize2 = 0;
-#ifndef CONFIG_SYS_RAMBOOT
-	ulong test1, test2;
-
-	/* setup SDRAM chip selects */
-							 /* 256MB at 0x0 */
-	out_be32 (&mm->sdram0, 0x0000001b);
-							 /* disabled */
-	out_be32 (&mm->sdram1, 0x10000000);
-
-	/* setup config registers */
-	out_be32 (&sdram->config1, SDRAM_CONFIG1);
-	out_be32 (&sdram->config2, SDRAM_CONFIG2);
-
-	/* find RAM size using SDRAM CS0 only */
-	sdram_start(0);
-	test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000);
-	sdram_start(1);
-	test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000);
-	if (test1 > test2) {
-		sdram_start(0);
-		dramsize = test1;
-	} else
-		dramsize = test2;
-
-	/* memory smaller than 1MB is impossible */
-	if (dramsize < (1 << 20))
-		dramsize = 0;
-
-	/* set SDRAM CS0 size according to the amount of RAM found */
-	if (dramsize > 0) {
-		out_be32 (&mm->sdram0,
-			(0x13 + __builtin_ffs(dramsize >> 20) - 1));
-	} else {
-							/* disabled */
-		out_be32 (&mm->sdram0, 0);
-	}
-
-#else /* CONFIG_SYS_RAMBOOT */
-
-	/* retrieve size of memory connected to SDRAM CS0 */
-	dramsize = in_be32(&mm->sdram0) & 0xFF;
-	if (dramsize >= 0x13)
-		dramsize = (1 << (dramsize - 0x13)) << 20;
-	else
-		dramsize = 0;
-
-	/* retrieve size of memory connected to SDRAM CS1 */
-	dramsize2 = in_be32(&mm->sdram1) & 0xFF;
-	if (dramsize2 >= 0x13)
-		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
-	else
-		dramsize2 = 0;
-
-#endif /* CONFIG_SYS_RAMBOOT */
-
-	return dramsize + dramsize2;
-}
-
-int checkboard(void)
-{
-	puts("Board: galaxy5200\n");
-	return 0;
-}
-
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-int ft_board_setup(void *blob, bd_t *bd)
-{
-	ft_cpu_setup(blob, bd);
-
-	return 0;
-}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
-
-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
-
-void init_ide_reset (void)
-{
-	volatile struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT;
-	debug ("init_ide_reset\n");
-
-	/* Configure TIMER_5 as GPIO output for ATA reset */
-	/* Deassert reset */
-	gpt[5].emsr = MPC5XXX_GPT_GPIO_OUT1 | MPC5XXX_GPT_TMS_GPIO;
-}
-
-void ide_set_reset (int idereset)
-{
-	volatile struct mpc5xxx_gpt *gpt = (struct mpc5xxx_gpt *)MPC5XXX_GPT;
-	debug ("ide_reset(%d)\n", idereset);
-
-	/* Configure TIMER_5 as GPIO output for ATA reset */
-	if (idereset) {
-		gpt[5].emsr = MPC5XXX_GPT_GPIO_OUT0 | MPC5XXX_GPT_TMS_GPIO;
-
-		/* Make a delay. MPC5200 spec says 25 usec min */
-		udelay(50);
-	} else {
-		gpt[5].emsr = MPC5XXX_GPT_GPIO_OUT1 | MPC5XXX_GPT_TMS_GPIO;
-		udelay(50);
-	}
-}
-#endif /* defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) */
-CONFIG_SYS_EXTRA_OPTIONS="galaxy5200_LOWBOOT"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_GALAXY5200=y
-CONFIG_SYS_EXTRA_OPTIONS="galaxy5200"
-CONFIG_PPC=y
-CONFIG_MPC5xxx=y
-CONFIG_TARGET_GALAXY5200=y
@@ -12,6 +12,7 @@
  
 Board            Arch        CPU            Commit      Removed     Last known maintainer/contact
 =================================================================================================
+galaxy5200       powerpc     mpc5xxx        -           -           Eric Millbrandt <emillbrandt@dekaresearch.com>
 W7OLMC           powerpc     ppc4xx         -           -           Erik Theisen <etheisen@mindspring.com>
 W7OLMG           powerpc     ppc4xx         -           -           Erik Theisen <etheisen@mindspring.com>
 aev              powerpc     mpc5xxx        -           -
-/*
- * (C) Copyright 2003-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2006
- * Eric Schumann, Phytec Messatechnik GmbH
- *
- * (C) Copyright 2009
- * Jon Smirl <jonsmirl@gmail.com>
- *
- * (C) Copyright 2009
- * Eric Millbrandt, DEKA Research and Development Corporation
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_BOARDINFO	 "galaxy5200"
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU */
-#define CONFIG_SYS_MPC5XXX_CLKIN 33333333	/* ... running at 33.333333MHz */
-
-/*
- * Valid values for CONFIG_SYS_TEXT_BASE are:
- * 0xFFF00000	boot high (standard configuration)
- * 0xFE000000	boot low
- * 0x00100000	boot from RAM (for testing only) does not work
- */
-#ifdef CONFIG_galaxy5200_LOWBOOT
-#define	CONFIG_SYS_TEXT_BASE	0xFE000000
-#endif
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE	0xFFF00000	/* Standard: boot high */
-#endif
-
-/*
- * Serial console configuration
- */
-#define CONFIG_PSC_CONSOLE	4	/* console is on PSC4 -> */
-					/* define gps port conf. */
-					/* register later on to  */
-					/* enable UART function! */
-#define CONFIG_BAUDRATE		115200	/* ... at 115200 bps */
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_SNTP
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_USB
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_FAT
-
-#define	CONFIG_TIMESTAMP	1	/* Print image info with timestamp */
-
-#if (CONFIG_SYS_TEXT_BASE == 0xFE000000)		/* Boot low */
-#define CONFIG_SYS_LOWBOOT 1
-#endif
-/* RAMBOOT will be defined automatically in memory section */
-
-#define MTDIDS_DEFAULT		"nor0=physmap-flash.0"
-#define MTDPARTS_DEFAULT	"mtdparts=physmap-flash.0:256k(ubootl)," \
-	"1792k(kernel),13312k(jffs2),256k(uboot)ro,256k(oftree),-(space)"
-
-/*
- * Autobooting
- */
-#define CONFIG_BOOTDELAY	10	/* autoboot after 10 seconds */
-#define CONFIG_ZERO_BOOTDELAY_CHECK	/* allow stopping of boot process */
-					/* even with bootdelay=0 */
-#define CONFIG_BOOT_RETRY_TIME 120	/* Reset if no command is entered  */
-#define CONFIG_RESET_TO_RETRY
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Welcome to U-Boot;"\
-	"echo"
-
-#define CONFIG_BOOTCOMMAND     "go ff300004 0; go ff300004 2 2;" \
-	"bootm ff040000 ff900000 fffc0000"
-#define CONFIG_BOOTARGS        "console=ttyPSC0,115200"
-#define CONFIG_EXTRA_ENV_SETTINGS "epson=yes\0"
-
-/*
- * IPB Bus clocking configuration.
- */
-#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK	/* define for 133MHz speed */
-#define CONFIG_SYS_XLB_PIPELINING	1
-
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C 1		/* I2C with hardware support */
-#define CONFIG_SYS_I2C_MODULE 2		/* Select I2C module #1 or #2 */
-#define CONFIG_SYS_I2C_SPEED 100000	/* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_INIT_MPC5XXX	/* Reset devices on i2c bus */
-
-/*
- * EEPROM CAT24WC32 configuration
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR	0x52	/* 1010100x */
-#define CONFIG_SYS_I2C_FACT_ADDR	0x52	/* EEPROM CAT24WC32 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	2	/* Bytes of address */
-#define CONFIG_SYS_EEPROM_SIZE		4096
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 15
-
-/*
- * RTC configuration
- */
-#define RTC
-#define CONFIG_RTC_DS3231		1
-#define CONFIG_SYS_I2C_RTC_ADDR		0x68
-
-/*
- * Flash configuration
- */
-
-#define CONFIG_SYS_FLASH_BASE		0xfe000000
-/*
- * The flash size is autoconfigured, but arch/powerpc/cpu/mpc5xxx/cpu_init.c needs this
- * variable defined
- */
-#define CONFIG_SYS_FLASH_SIZE		0x02000000
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
-
-#define CONFIG_SYS_FLASH_CFI 1		/* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_MAX_FLASH_SECT 259	/* max num of sects on one chip */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1	/* max num of flash banks */
-					/* (= chip selects) */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-
-/*
- * Use hardware protection. This seems required, as the BDI uses hardware
- * protection. Without this, U-Boot can't work with this sectors as its
- * protection is software only by default.
- */
-#define CONFIG_SYS_FLASH_PROTECTION	1
-
-/*
- * Environment settings
- */
-
-#define CONFIG_ENV_IS_IN_EEPROM	1
-#define CONFIG_ENV_OFFSET	0x00	/* environment starts at the */
-					/* beginning of the EEPROM */
-#define CONFIG_ENV_SIZE		CONFIG_SYS_EEPROM_SIZE
-
-#define CONFIG_ENV_OVERWRITE	1
-
-/*
- * SDRAM configuration
- */
-#define SDRAM_DDR	1
-#define SDRAM_MODE	0x018D0000
-#define SDRAM_EMODE	0x40090000
-#define SDRAM_CONTROL	0x71500F00
-#define SDRAM_CONFIG1	0x73711930
-#define SDRAM_CONFIG2	0x47770000
-
-/*
- * Memory map
- */
-#define CONFIG_SYS_MBAR	0xF0000000	/* MBAR has to be switched by other */
-					/* bootloader or debugger config */
-#define CONFIG_SYS_SDRAM_BASE		0x00000000
-#define CONFIG_SYS_DEFAULT_MBAR		0x80000000
-
-/* Use SRAM until RAM will be available */
-#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
-
-/* End of used area in SPRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE		MPC5XXX_SRAM_SIZE
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
-						GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#	define CONFIG_SYS_RAMBOOT		1
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (192 << 10)	/* Reserve 192 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10)	/* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20)	/* Initial Memory map for Linux */
-
-/* Chip Select configuration for NAND flash */
-#define CONFIG_SYS_CS1_START		0x20000000
-#define CONFIG_SYS_CS1_SIZE		0x90000
-#define CONFIG_SYS_CS1_CFG		0x00025b00
-
-/* Chip Select configuration for Epson S1D13513 */
-#define CONFIG_SYS_CS3_START		0x10000000
-#define CONFIG_SYS_CS3_SIZE		0x400000
-#define CONFIG_SYS_CS3_CFG		0xffff3d10
-
-/*
- * Ethernet configuration
- */
-#define CONFIG_MPC5xxx_FEC		1
-#define CONFIG_MPC5xxx_FEC_MII100
-#define CONFIG_PHY_ADDR			0x01
-#define CONFIG_NO_AUTOLOAD		1
-
-/*
- * GPIO configuration
- *
- * GPS port configuration
- *
- * [29:31] = 01x
- * AC97 on PSC1
- * PSC1_0 -> AC97 SDATA out
- * PSC1_1 -> AC97 SDTA in
- * PSC1_2 -> AC97 SYNC out
- * PSC1_3 -> AC97 bitclock out
- * PSC1_4 -> AC97 reset out
- *
- * [28] = Reserved
- *
- * [25:27] = 110
- * SPI on PSC2
- * PSC2_0 -> MOSI
- * PSC2_1 -> MISO
- * PSC2_2 -> n/a
- * PSC2_3 -> CLK
- * PSC2_4 -> SS
- *
- * [24] = Reserved
- *
- * [20:23] = 0001
- * USB on PSC3
- * PSC3_0 -> USB_OE OE out
- * PSC3_1 -> USB_TXN Tx- out
- * PSC3_2 -> USB_TXP Tx+ out
- * PSC3_3 -> USB_TXD
- * PSC3_4 -> USB_RXP Rx+ in
- * PSC3_5 -> USB_RXN Rx- in
- * PSC3_6 -> USB_PWR PortPower out
- * PSC3_7 -> USB_SPEED speed out
- * PSC3_8 -> USB_SUSPEND suspend
- * PSC3_9 -> USB_OVRCURNT overcurrent in
- *
- * [18:19] = 10
- * Two UARTs
- *
- * [17] = 0
- * USB differential mode
- *
- * [16] = 1
- * PCI disabled
- *
- * [12:15] = 0101
- * Ethernet 100Mbit with MD
- * ETH_0 -> ETH Txen
- * ETH_1 -> ETH TxD0
- * ETH_2 -> ETH TxD1
- * ETH_3 -> ETH TxD2
- * ETH_4 -> ETH TxD3
- * ETH_5 -> ETH Txerr
- * ETH_6 -> ETH MDC
- * ETH_7 -> ETH MDIO
- * ETH_8 -> ETH RxDv
- * ETH_9 -> ETH RxCLK
- * ETH_10 -> ETH Collision
- * ETH_11 -> ETH TxD
- * ETH_12 -> ETH RxD0
- * ETH_13 -> ETH RxD1
- * ETH_14 -> ETH RxD2
- * ETH_15 -> ETH RxD3
- * ETH_16 -> ETH Rxerr
- * ETH_17 -> ETH CRS
- *
- * [9:11] = 111
- * SPI on PSC6
- * PSC6_0 -> MISO
- * PSC6_1 -> SS#
- * PSC6_2 -> MOSI
- * PSC6_3 -> CLK
- *
- * [8] = 0
- * IrDA/USB 48MHz clock generated internally
- *
- * [6:7] = 01
- * ATA chip selects on csb_4/5
- * CSB_4 -> ATA_CS0 out
- * CSB_5 -> ATA_CS1 out
- *
- * [5] = 1
- * PSC3_4 is used as CS6
- *
- * [4] = 1
- * PSC3_5 is used as CS7
- *
- * [2:3] = 00
- * No Alternatives
- *
- * [1] = 0
- * gpio_wkup_7 is GPIO
- *
- * [0] = 0
- * gpio_wkup_6 is GPIO
- *
- */
-#define CONFIG_SYS_GPS_PORT_CONFIG	0x0d75a162
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory */
-#define CONFIG_SYS_PROMPT "uboot> "		/* Monitor Command Prompt */
-
-#define CONFIG_CMDLINE_EDITING 1		/* add command line history */
-
-#define CONFIG_SYS_CACHELINE_SIZE 32		/* For MPC5xxx CPUs */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CACHELINE_SHIFT 5		/* log base 2 of the above value */
-#endif
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024			/* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 512			/* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-						/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 32			/* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000	/* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000	/* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x400000		/* default load address */
-
-#define CONFIG_DISPLAY_BOARDINFO 1
-
-#define CONFIG_SYS_HUSH_PARSER 1
-
-#define CONFIG_CRC32_VERIFY  1
-
-#define CONFIG_BOOTP_DNS
-#define CONFIG_BOOTP_DNS2
-#define CONFIG_BOOTP_SEND_HOSTNAME
-
-#define CONFIG_VERSION_VARIABLE 1
-
-/*
- * Various low-level settings
- */
-#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
-#define CONFIG_SYS_HID0_FINAL		HID0_ICE
-
-/* no burst access on the LPB */
-#define CONFIG_SYS_CS_BURST		0x00000000
-/* one deadcycle for the 33MHz statemachine */
-#define CONFIG_SYS_CS_DEADCYCLE		0x33333331
-
-#define CONFIG_SYS_BOOTCS_CFG		0x0002d900
-#define CONFIG_SYS_BOOTCS_START		CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
-
-#define CONFIG_SYS_RESET_ADDRESS	0xff000000
-
-/*
- * USB settings
- */
-#define CONFIG_USB_CLOCK		0x0001bbbb
-/* USB is on PSC3 */
-#define CONFIG_PSC3_USB
-#define CONFIG_USB_CONFIG		0x00000100
-#define CONFIG_USB_OHCI
-#define CONFIG_USB_STORAGE
-
-/*
- * IDE/ATA stuff Supports IDE harddisk
- */
-#undef  CONFIG_IDE_8xx_PCCARD	/* Use IDE with PC Card Adapter */
-#undef	CONFIG_IDE_8xx_DIRECT	/* Direct IDE not supported */
-#undef	CONFIG_IDE_LED		/* LED for ide not supported */
-
-#define	CONFIG_IDE_RESET 1	/* reset for ide supported */
-#define CONFIG_IDE_PREINIT
-#define CONFIG_SYS_IDE_MAXBUS 1	/* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 2	/* max. 2 drives per IDE bus */
-#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
-#define CONFIG_SYS_ATA_BASE_ADDR	MPC5XXX_ATA
-/* Offset for data I/O			*/
-#define CONFIG_SYS_ATA_DATA_OFFSET	(0x0060)
-/* Offset for normal register accesses	*/
-#define CONFIG_SYS_ATA_REG_OFFSET	(CONFIG_SYS_ATA_DATA_OFFSET)
-/* Offset for alternate registers	*/
-#define CONFIG_SYS_ATA_ALT_OFFSET	(0x005C)
-/* Interval between registers */
-#define CONFIG_SYS_ATA_STRIDE		4
-#define CONFIG_ATAPI			1
-
-/* we enable IDE and FAT support, so we also need partition support */
-#define CONFIG_DOS_PARTITION 1
-
-/*
- * Open Firmware flat tree
- */
-#define CONFIG_OF_LIBFDT		1
-#define CONFIG_OF_BOARD_SETUP		1
-
-#define OF_CPU				"PowerPC,5200@0"
-#define OF_TBCLK			CONFIG_SYS_MPC5XXX_CLKIN
-#define OF_SOC				"soc5200@f0000000"
-#define OF_STDOUT_PATH			"/soc5200@f0000000/serial@2600"
-
-#endif /* __CONFIG_H */
...	...	@@ -20,9 +20,6 @@
20	20	config TARGET_CM5200
21	21	bool "Support cm5200"
22	22
23		-config TARGET_GALAXY5200
24		- bool "Support galaxy5200"
25		-
26	23	config TARGET_INKA4X0
27	24	bool "Support inka4x0"
28	25
...	...	@@ -77,7 +74,6 @@
77	74	source "board/a4m072/Kconfig"
78	75	source "board/canmb/Kconfig"
79	76	source "board/cm5200/Kconfig"
80		-source "board/galaxy5200/Kconfig"
81	77	source "board/ifm/o2dnt2/Kconfig"
82	78	source "board/inka4x0/Kconfig"
83	79	source "board/intercontrol/digsy_mtc/Kconfig"
1		-if TARGET_GALAXY5200
2		-
3		-config SYS_BOARD
4		- default "galaxy5200"
5		-
6		-config SYS_CONFIG_NAME
7		- default "galaxy5200"
8		-
9		-endif
1		-GALAXY5200 BOARD
2		-#M: Eric Millbrandt <emillbrandt@dekaresearch.com>
3		-S: Orphan (since 2014-06)
4		-F: board/galaxy5200/
5		-F: include/configs/galaxy5200.h
6		-F: configs/galaxy5200_defconfig
7		-F: configs/galaxy5200_LOWBOOT_defconfig
1		-#
2		-# (C) Copyright 2003-2007
3		-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4		-#
5		-# SPDX-License-Identifier: GPL-2.0+
6		-#
7		-
8		-obj-y := galaxy5200.o
1		-/*
2		- * (C) Copyright 2003
3		- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4		- *
5		- * (C) Copyright 2004
6		- * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
7		- *
8		- * (C) Copyright 2006
9		- * Eric Schumann, Phytec Messtechnik GmbH
10		- *
11		- * (C) Copyright 2009
12		- * Eric Millbrandt, DEKA Research and Development Corporation
13		- *
14		- * SPDX-License-Identifier: GPL-2.0+
15		- */
16		-
17		-#include <common.h>
18		-#include <mpc5xxx.h>
19		-#include <pci.h>
20		-#include <asm/io.h>
21		-
22		-#ifndef CONFIG_SYS_RAMBOOT
23		-static void sdram_start(int hi_addr)
24		-{
25		- volatile struct mpc5xxx_cdm *cdm =
26		- (struct mpc5xxx_cdm *)MPC5XXX_CDM;
27		- volatile struct mpc5xxx_sdram *sdram =
28		- (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
29		-
30		- long hi_addr_bit = hi_addr ? 0x01000000 : 0;
31		-
32		- /* unlock mode register */
33		- out_be32 (&sdram->ctrl,
34		- (SDRAM_CONTROL \| 0x80000000 \| hi_addr_bit));
35		-
36		- /* precharge all banks */
37		- out_be32 (&sdram->ctrl,
38		- (SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit));
39		-
40		-#ifdef SDRAM_DDR
41		- /* set mode register: extended mode */
42		- out_be32 (&sdram->mode, (SDRAM_EMODE));
43		-
44		- /* set mode register: reset DLL */
45		- out_be32 (&sdram->mode, (SDRAM_MODE \| 0x04000000));
46		-#endif
47		-
48		- /* precharge all banks */
49		- out_be32 (&sdram->ctrl,
50		- (SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit));
51		-
52		- /* auto refresh */
53		- out_be32 (&sdram->ctrl,
54		- (SDRAM_CONTROL \| 0x80000004 \| hi_addr_bit));
55		-
56		- /* set mode register */
57		- out_be32 (&sdram->mode, (SDRAM_MODE));
58		-
59		- /* normal operation */
60		- out_be32 (&sdram->ctrl,
61		- (SDRAM_CONTROL \| hi_addr_bit));
62		-
63		- /* set CDM clock enable register, set MPC5200B SDRAM bus */
64		- /* to reduced driver strength */
65		- out_be32 (&cdm->clock_enable, (0x00CFFFFF));
66		-}
67		-#endif
68		-
69		-/*
70		- * ATTENTION: Although partially referenced initdram does NOT make
71		- * real use of CONFIG_SYS_SDRAM_BASE. The code does not
72		- * work if CONFIG_SYS_SDRAM_BASE
73		- * is something else than 0x00000000.
74		- */
75		-
76		-phys_size_t initdram(int board_type)
77		-{
78		- volatile struct mpc5xxx_mmap_ctl *mm =
79		- (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
80		- volatile struct mpc5xxx_sdram *sdram =
81		- (struct mpc5xxx_sdram *)MPC5XXX_SDRAM;
82		- ulong dramsize = 0;
83		- ulong dramsize2 = 0;
84		-#ifndef CONFIG_SYS_RAMBOOT
85		- ulong test1, test2;
86		-
87		- /* setup SDRAM chip selects */
88		- /* 256MB at 0x0 */
89		- out_be32 (&mm->sdram0, 0x0000001b);
90		- /* disabled */
91		- out_be32 (&mm->sdram1, 0x10000000);
92		-
93		- /* setup config registers */
94		- out_be32 (&sdram->config1, SDRAM_CONFIG1);
95		- out_be32 (&sdram->config2, SDRAM_CONFIG2);
96		-
97		- /* find RAM size using SDRAM CS0 only */
98		- sdram_start(0);
99		- test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000);
100		- sdram_start(1);
101		- test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x10000000);
102		- if (test1 > test2) {
103		- sdram_start(0);
104		- dramsize = test1;
105		- } else
106		- dramsize = test2;
107		-
108		- /* memory smaller than 1MB is impossible */
109		- if (dramsize < (1 << 20))
110		- dramsize = 0;
111		-
112		- /* set SDRAM CS0 size according to the amount of RAM found */
113		- if (dramsize > 0) {
114		- out_be32 (&mm->sdram0,
115		- (0x13 + __builtin_ffs(dramsize >> 20) - 1));
116		- } else {
117		- /* disabled */
118		- out_be32 (&mm->sdram0, 0);
119		- }
120		-
121		-#else /* CONFIG_SYS_RAMBOOT */
122		-
123		- /* retrieve size of memory connected to SDRAM CS0 */
124		- dramsize = in_be32(&mm->sdram0) & 0xFF;
125		- if (dramsize >= 0x13)
126		- dramsize = (1 << (dramsize - 0x13)) << 20;
127		- else
128		- dramsize = 0;
129		-
130		- /* retrieve size of memory connected to SDRAM CS1 */
131		- dramsize2 = in_be32(&mm->sdram1) & 0xFF;
132		- if (dramsize2 >= 0x13)
133		- dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
134		- else
135		- dramsize2 = 0;
136		-
137		-#endif /* CONFIG_SYS_RAMBOOT */
138		-
139		- return dramsize + dramsize2;
140		-}
141		-
142		-int checkboard(void)
143		-{
144		- puts("Board: galaxy5200\n");
145		- return 0;
146		-}
147		-
148		-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
149		-int ft_board_setup(void blob, bd_t bd)
150		-{
151		- ft_cpu_setup(blob, bd);
152		-
153		- return 0;
154		-}
155		-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
156		-
157		-#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
158		-
159		-void init_ide_reset (void)
160		-{
161		- volatile struct mpc5xxx_gpt gpt = (struct mpc5xxx_gpt )MPC5XXX_GPT;
162		- debug ("init_ide_reset\n");
163		-
164		- /* Configure TIMER_5 as GPIO output for ATA reset */
165		- /* Deassert reset */
166		- gpt[5].emsr = MPC5XXX_GPT_GPIO_OUT1 \| MPC5XXX_GPT_TMS_GPIO;
167		-}
168		-
169		-void ide_set_reset (int idereset)
170		-{
171		- volatile struct mpc5xxx_gpt gpt = (struct mpc5xxx_gpt )MPC5XXX_GPT;
172		- debug ("ide_reset(%d)\n", idereset);
173		-
174		- /* Configure TIMER_5 as GPIO output for ATA reset */
175		- if (idereset) {
176		- gpt[5].emsr = MPC5XXX_GPT_GPIO_OUT0 \| MPC5XXX_GPT_TMS_GPIO;
177		-
178		- /* Make a delay. MPC5200 spec says 25 usec min */
179		- udelay(50);
180		- } else {
181		- gpt[5].emsr = MPC5XXX_GPT_GPIO_OUT1 \| MPC5XXX_GPT_TMS_GPIO;
182		- udelay(50);
183		- }
184		-}
185		-#endif /* defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) */
1		-CONFIG_SYS_EXTRA_OPTIONS="galaxy5200_LOWBOOT"
2		-CONFIG_PPC=y
3		-CONFIG_MPC5xxx=y
4		-CONFIG_TARGET_GALAXY5200=y
1		-CONFIG_SYS_EXTRA_OPTIONS="galaxy5200"
2		-CONFIG_PPC=y
3		-CONFIG_MPC5xxx=y
4		-CONFIG_TARGET_GALAXY5200=y
...	...	@@ -12,6 +12,7 @@
12	12
13	13	Board Arch CPU Commit Removed Last known maintainer/contact
14	14	=================================================================================================
	15	+galaxy5200 powerpc mpc5xxx - - Eric Millbrandt <emillbrandt@dekaresearch.com>
15	16	W7OLMC powerpc ppc4xx - - Erik Theisen <etheisen@mindspring.com>
16	17	W7OLMG powerpc ppc4xx - - Erik Theisen <etheisen@mindspring.com>
17	18	aev powerpc mpc5xxx - -
1		-/*
2		- * (C) Copyright 2003-2005
3		- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4		- *
5		- * (C) Copyright 2006
6		- * Eric Schumann, Phytec Messatechnik GmbH
7		- *
8		- * (C) Copyright 2009
9		- * Jon Smirl <jonsmirl@gmail.com>
10		- *
11		- * (C) Copyright 2009
12		- * Eric Millbrandt, DEKA Research and Development Corporation
13		- *
14		- * SPDX-License-Identifier: GPL-2.0+
15		- */
16		-
17		-#ifndef __CONFIG_H
18		-#define __CONFIG_H
19		-
20		-#define CONFIG_BOARDINFO "galaxy5200"
21		-
22		-/*
23		- * High Level Configuration Options
24		- * (easy to change)
25		- */
26		-#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
27		-#define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */
28		-
29		-/*
30		- * Valid values for CONFIG_SYS_TEXT_BASE are:
31		- * 0xFFF00000 boot high (standard configuration)
32		- * 0xFE000000 boot low
33		- * 0x00100000 boot from RAM (for testing only) does not work
34		- */
35		-#ifdef CONFIG_galaxy5200_LOWBOOT
36		-#define CONFIG_SYS_TEXT_BASE 0xFE000000
37		-#endif
38		-
39		-#ifndef CONFIG_SYS_TEXT_BASE
40		-#define CONFIG_SYS_TEXT_BASE 0xFFF00000 /* Standard: boot high */
41		-#endif
42		-
43		-/*
44		- * Serial console configuration
45		- */
46		-#define CONFIG_PSC_CONSOLE 4 /* console is on PSC4 -> */
47		- /* define gps port conf. */
48		- /* register later on to */
49		- /* enable UART function! */
50		-#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
51		-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
52		-
53		-/*
54		- * Command line configuration.
55		- */
56		-#include <config_cmd_default.h>
57		-
58		-#define CONFIG_CMD_DATE
59		-#define CONFIG_CMD_DHCP
60		-#define CONFIG_CMD_EEPROM
61		-#define CONFIG_CMD_I2C
62		-#define CONFIG_CMD_JFFS2
63		-#define CONFIG_CMD_MII
64		-#define CONFIG_CMD_NFS
65		-#define CONFIG_CMD_SNTP
66		-#define CONFIG_CMD_PING
67		-#define CONFIG_CMD_ASKENV
68		-#define CONFIG_CMD_USB
69		-#define CONFIG_CMD_CACHE
70		-#define CONFIG_CMD_FAT
71		-
72		-#define CONFIG_TIMESTAMP 1 /* Print image info with timestamp */
73		-
74		-#if (CONFIG_SYS_TEXT_BASE == 0xFE000000) /* Boot low */
75		-#define CONFIG_SYS_LOWBOOT 1
76		-#endif
77		-/* RAMBOOT will be defined automatically in memory section */
78		-
79		-#define MTDIDS_DEFAULT "nor0=physmap-flash.0"
80		-#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:256k(ubootl)," \
81		- "1792k(kernel),13312k(jffs2),256k(uboot)ro,256k(oftree),-(space)"
82		-
83		-/*
84		- * Autobooting
85		- */
86		-#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */
87		-#define CONFIG_ZERO_BOOTDELAY_CHECK /* allow stopping of boot process */
88		- /* even with bootdelay=0 */
89		-#define CONFIG_BOOT_RETRY_TIME 120 /* Reset if no command is entered */
90		-#define CONFIG_RESET_TO_RETRY
91		-
92		-#define CONFIG_PREBOOT "echo;" \
93		- "echo Welcome to U-Boot;"\
94		- "echo"
95		-
96		-#define CONFIG_BOOTCOMMAND "go ff300004 0; go ff300004 2 2;" \
97		- "bootm ff040000 ff900000 fffc0000"
98		-#define CONFIG_BOOTARGS "console=ttyPSC0,115200"
99		-#define CONFIG_EXTRA_ENV_SETTINGS "epson=yes\0"
100		-
101		-/*
102		- * IPB Bus clocking configuration.
103		- */
104		-#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
105		-#define CONFIG_SYS_XLB_PIPELINING 1
106		-
107		-/*
108		- * I2C configuration
109		- */
110		-#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
111		-#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
112		-#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
113		-#define CONFIG_SYS_I2C_SLAVE 0x7F
114		-#define CONFIG_SYS_I2C_INIT_MPC5XXX /* Reset devices on i2c bus */
115		-
116		-/*
117		- * EEPROM CAT24WC32 configuration
118		- */
119		-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* 1010100x */
120		-#define CONFIG_SYS_I2C_FACT_ADDR 0x52 /* EEPROM CAT24WC32 */
121		-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
122		-#define CONFIG_SYS_EEPROM_SIZE 4096
123		-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
124		-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 15
125		-
126		-/*
127		- * RTC configuration
128		- */
129		-#define RTC
130		-#define CONFIG_RTC_DS3231 1
131		-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
132		-
133		-/*
134		- * Flash configuration
135		- */
136		-
137		-#define CONFIG_SYS_FLASH_BASE 0xfe000000
138		-/*
139		- * The flash size is autoconfigured, but arch/powerpc/cpu/mpc5xxx/cpu_init.c needs this
140		- * variable defined
141		- */
142		-#define CONFIG_SYS_FLASH_SIZE 0x02000000
143		-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
144		-
145		-#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
146		-#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
147		-#define CONFIG_SYS_FLASH_EMPTY_INFO
148		-#define CONFIG_SYS_MAX_FLASH_SECT 259 /* max num of sects on one chip */
149		-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
150		- /* (= chip selects) */
151		-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
152		-
153		-/*
154		- * Use hardware protection. This seems required, as the BDI uses hardware
155		- * protection. Without this, U-Boot can't work with this sectors as its
156		- * protection is software only by default.
157		- */
158		-#define CONFIG_SYS_FLASH_PROTECTION 1
159		-
160		-/*
161		- * Environment settings
162		- */
163		-
164		-#define CONFIG_ENV_IS_IN_EEPROM 1
165		-#define CONFIG_ENV_OFFSET 0x00 /* environment starts at the */
166		- /* beginning of the EEPROM */
167		-#define CONFIG_ENV_SIZE CONFIG_SYS_EEPROM_SIZE
168		-
169		-#define CONFIG_ENV_OVERWRITE 1
170		-
171		-/*
172		- * SDRAM configuration
173		- */
174		-#define SDRAM_DDR 1
175		-#define SDRAM_MODE 0x018D0000
176		-#define SDRAM_EMODE 0x40090000
177		-#define SDRAM_CONTROL 0x71500F00
178		-#define SDRAM_CONFIG1 0x73711930
179		-#define SDRAM_CONFIG2 0x47770000
180		-
181		-/*
182		- * Memory map
183		- */
184		-#define CONFIG_SYS_MBAR 0xF0000000 /* MBAR has to be switched by other */
185		- /* bootloader or debugger config */
186		-#define CONFIG_SYS_SDRAM_BASE 0x00000000
187		-#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
188		-
189		-/* Use SRAM until RAM will be available */
190		-#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
191		-
192		-/* End of used area in SPRAM */
193		-#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
194		-
195		-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
196		- GENERATED_GBL_DATA_SIZE)
197		-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
198		-
199		-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
200		-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
201		-# define CONFIG_SYS_RAMBOOT 1
202		-#endif
203		-
204		-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
205		-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
206		-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
207		-
208		-/* Chip Select configuration for NAND flash */
209		-#define CONFIG_SYS_CS1_START 0x20000000
210		-#define CONFIG_SYS_CS1_SIZE 0x90000
211		-#define CONFIG_SYS_CS1_CFG 0x00025b00
212		-
213		-/* Chip Select configuration for Epson S1D13513 */
214		-#define CONFIG_SYS_CS3_START 0x10000000
215		-#define CONFIG_SYS_CS3_SIZE 0x400000
216		-#define CONFIG_SYS_CS3_CFG 0xffff3d10
217		-
218		-/*
219		- * Ethernet configuration
220		- */
221		-#define CONFIG_MPC5xxx_FEC 1
222		-#define CONFIG_MPC5xxx_FEC_MII100
223		-#define CONFIG_PHY_ADDR 0x01
224		-#define CONFIG_NO_AUTOLOAD 1
225		-
226		-/*
227		- * GPIO configuration
228		- *
229		- * GPS port configuration
230		- *
231		- * [29:31] = 01x
232		- * AC97 on PSC1
233		- * PSC1_0 -> AC97 SDATA out
234		- * PSC1_1 -> AC97 SDTA in
235		- * PSC1_2 -> AC97 SYNC out
236		- * PSC1_3 -> AC97 bitclock out
237		- * PSC1_4 -> AC97 reset out
238		- *
239		- * [28] = Reserved
240		- *
241		- * [25:27] = 110
242		- * SPI on PSC2
243		- * PSC2_0 -> MOSI
244		- * PSC2_1 -> MISO
245		- * PSC2_2 -> n/a
246		- * PSC2_3 -> CLK
247		- * PSC2_4 -> SS
248		- *
249		- * [24] = Reserved
250		- *
251		- * [20:23] = 0001
252		- * USB on PSC3
253		- * PSC3_0 -> USB_OE OE out
254		- * PSC3_1 -> USB_TXN Tx- out
255		- * PSC3_2 -> USB_TXP Tx+ out
256		- * PSC3_3 -> USB_TXD
257		- * PSC3_4 -> USB_RXP Rx+ in
258		- * PSC3_5 -> USB_RXN Rx- in
259		- * PSC3_6 -> USB_PWR PortPower out
260		- * PSC3_7 -> USB_SPEED speed out
261		- * PSC3_8 -> USB_SUSPEND suspend
262		- * PSC3_9 -> USB_OVRCURNT overcurrent in
263		- *
264		- * [18:19] = 10
265		- * Two UARTs
266		- *
267		- * [17] = 0
268		- * USB differential mode
269		- *
270		- * [16] = 1
271		- * PCI disabled
272		- *
273		- * [12:15] = 0101
274		- * Ethernet 100Mbit with MD
275		- * ETH_0 -> ETH Txen
276		- * ETH_1 -> ETH TxD0
277		- * ETH_2 -> ETH TxD1
278		- * ETH_3 -> ETH TxD2
279		- * ETH_4 -> ETH TxD3
280		- * ETH_5 -> ETH Txerr
281		- * ETH_6 -> ETH MDC
282		- * ETH_7 -> ETH MDIO
283		- * ETH_8 -> ETH RxDv
284		- * ETH_9 -> ETH RxCLK
285		- * ETH_10 -> ETH Collision
286		- * ETH_11 -> ETH TxD
287		- * ETH_12 -> ETH RxD0
288		- * ETH_13 -> ETH RxD1
289		- * ETH_14 -> ETH RxD2
290		- * ETH_15 -> ETH RxD3
291		- * ETH_16 -> ETH Rxerr
292		- * ETH_17 -> ETH CRS
293		- *
294		- * [9:11] = 111
295		- * SPI on PSC6
296		- * PSC6_0 -> MISO
297		- * PSC6_1 -> SS#
298		- * PSC6_2 -> MOSI
299		- * PSC6_3 -> CLK
300		- *
301		- * [8] = 0
302		- * IrDA/USB 48MHz clock generated internally
303		- *
304		- * [6:7] = 01
305		- * ATA chip selects on csb_4/5
306		- * CSB_4 -> ATA_CS0 out
307		- * CSB_5 -> ATA_CS1 out
308		- *
309		- * [5] = 1
310		- * PSC3_4 is used as CS6
311		- *
312		- * [4] = 1
313		- * PSC3_5 is used as CS7
314		- *
315		- * [2:3] = 00
316		- * No Alternatives
317		- *
318		- * [1] = 0
319		- * gpio_wkup_7 is GPIO
320		- *
321		- * [0] = 0
322		- * gpio_wkup_6 is GPIO
323		- *
324		- */
325		-#define CONFIG_SYS_GPS_PORT_CONFIG 0x0d75a162
326		-
327		-/*
328		- * Miscellaneous configurable options
329		- */
330		-#define CONFIG_SYS_LONGHELP /* undef to save memory */
331		-#define CONFIG_SYS_PROMPT "uboot> " /* Monitor Command Prompt */
332		-
333		-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
334		-
335		-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
336		-#if defined(CONFIG_CMD_KGDB)
337		-#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
338		-#endif
339		-
340		-#if defined(CONFIG_CMD_KGDB)
341		-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
342		-#else
343		-#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
344		-#endif
345		-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
346		- /* Print Buffer Size */
347		-#define CONFIG_SYS_MAXARGS 32 /* max number of command args */
348		-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
349		-
350		-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
351		-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
352		-
353		-#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
354		-
355		-#define CONFIG_DISPLAY_BOARDINFO 1
356		-
357		-#define CONFIG_SYS_HUSH_PARSER 1
358		-
359		-#define CONFIG_CRC32_VERIFY 1
360		-
361		-#define CONFIG_BOOTP_DNS
362		-#define CONFIG_BOOTP_DNS2
363		-#define CONFIG_BOOTP_SEND_HOSTNAME
364		-
365		-#define CONFIG_VERSION_VARIABLE 1
366		-
367		-/*
368		- * Various low-level settings
369		- */
370		-#define CONFIG_SYS_HID0_INIT HID0_ICE \| HID0_ICFI
371		-#define CONFIG_SYS_HID0_FINAL HID0_ICE
372		-
373		-/* no burst access on the LPB */
374		-#define CONFIG_SYS_CS_BURST 0x00000000
375		-/* one deadcycle for the 33MHz statemachine */
376		-#define CONFIG_SYS_CS_DEADCYCLE 0x33333331
377		-
378		-#define CONFIG_SYS_BOOTCS_CFG 0x0002d900
379		-#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
380		-#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
381		-
382		-#define CONFIG_SYS_RESET_ADDRESS 0xff000000
383		-
384		-/*
385		- * USB settings
386		- */
387		-#define CONFIG_USB_CLOCK 0x0001bbbb
388		-/* USB is on PSC3 */
389		-#define CONFIG_PSC3_USB
390		-#define CONFIG_USB_CONFIG 0x00000100
391		-#define CONFIG_USB_OHCI
392		-#define CONFIG_USB_STORAGE
393		-
394		-/*
395		- * IDE/ATA stuff Supports IDE harddisk
396		- */
397		-#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
398		-#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
399		-#undef CONFIG_IDE_LED /* LED for ide not supported */
400		-
401		-#define CONFIG_IDE_RESET 1 /* reset for ide supported */
402		-#define CONFIG_IDE_PREINIT
403		-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
404		-#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
405		-#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
406		-#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
407		-/* Offset for data I/O */
408		-#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
409		-/* Offset for normal register accesses */
410		-#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
411		-/* Offset for alternate registers */
412		-#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
413		-/* Interval between registers */
414		-#define CONFIG_SYS_ATA_STRIDE 4
415		-#define CONFIG_ATAPI 1
416		-
417		-/* we enable IDE and FAT support, so we also need partition support */
418		-#define CONFIG_DOS_PARTITION 1
419		-
420		-/*
421		- * Open Firmware flat tree
422		- */
423		-#define CONFIG_OF_LIBFDT 1
424		-#define CONFIG_OF_BOARD_SETUP 1
425		-
426		-#define OF_CPU "PowerPC,5200@0"
427		-#define OF_TBCLK CONFIG_SYS_MPC5XXX_CLKIN
428		-#define OF_SOC "soc5200@f0000000"
429		-#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2600"
430		-
431		-#endif /* __CONFIG_H */