Commit 41fbbbbc71161e0c0479d7c6c5598e760d70f624
Committed by
Tom Rini
Tom Rini
1 parent
d648964fc2
Exists in
v2017.01-smarct4x
and in
37 other branches
ARM: remove jadecpu board support
This is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Matthias Weisser <weisserm@arcor.de> Acked-by: Marek Vasut <marex@denx.de>
Showing 20 changed files with 19 additions and 1745 deletions Side-by-side Diff
- arch/arm/Kconfig
- arch/arm/cpu/arm926ejs/Makefile
- arch/arm/cpu/arm926ejs/mb86r0x/Makefile
- arch/arm/cpu/arm926ejs/mb86r0x/clock.c
- arch/arm/cpu/arm926ejs/mb86r0x/reset.c
- arch/arm/cpu/arm926ejs/mb86r0x/timer.c
- arch/arm/include/asm/arch-mb86r0x/hardware.h
- arch/arm/include/asm/arch-mb86r0x/mb86r0x.h
- arch/arm/lib/asm-offsets.c
- board/syteco/jadecpu/Kconfig
- board/syteco/jadecpu/MAINTAINERS
- board/syteco/jadecpu/Makefile
- board/syteco/jadecpu/jadecpu.c
- board/syteco/jadecpu/lowlevel_init.S
- configs/jadecpu_defconfig
- doc/README.scrapyard
- drivers/video/Makefile
- drivers/video/mb86r0xgdc.c
- include/configs/jadecpu.h
- include/serial.h
arch/arm/Kconfig
| ... | ... | @@ -144,10 +144,6 @@ |
| 144 | 144 | bool "Support devkit3250" |
| 145 | 145 | select CPU_ARM926EJS |
| 146 | 146 | |
| 147 | -config TARGET_JADECPU | |
| 148 | - bool "Support jadecpu" | |
| 149 | - select CPU_ARM926EJS | |
| 150 | - | |
| 151 | 147 | config TARGET_MX25PDK |
| 152 | 148 | bool "Support mx25pdk" |
| 153 | 149 | select CPU_ARM926EJS |
| ... | ... | @@ -852,7 +848,6 @@ |
| 852 | 848 | source "board/st-ericsson/u8500/Kconfig" |
| 853 | 849 | source "board/st/stv0991/Kconfig" |
| 854 | 850 | source "board/sunxi/Kconfig" |
| 855 | -source "board/syteco/jadecpu/Kconfig" | |
| 856 | 851 | source "board/syteco/zmx25/Kconfig" |
| 857 | 852 | source "board/tbs/tbs2910/Kconfig" |
| 858 | 853 | source "board/ti/am335x/Kconfig" |
arch/arm/cpu/arm926ejs/Makefile
arch/arm/cpu/arm926ejs/mb86r0x/Makefile
arch/arm/cpu/arm926ejs/mb86r0x/clock.c
| 1 | -/* | |
| 2 | - * (C) Copyright 2010 | |
| 3 | - * Matthias Weisser <weisserm@arcor.de> | |
| 4 | - * | |
| 5 | - * SPDX-License-Identifier: GPL-2.0+ | |
| 6 | - */ | |
| 7 | - | |
| 8 | -#include <common.h> | |
| 9 | -#include <asm/io.h> | |
| 10 | -#include <asm/arch/hardware.h> | |
| 11 | - | |
| 12 | -/* | |
| 13 | - * Get the peripheral bus frequency depending on pll pin settings | |
| 14 | - */ | |
| 15 | -ulong get_bus_freq(ulong dummy) | |
| 16 | -{ | |
| 17 | - struct mb86r0x_crg * crg = (struct mb86r0x_crg *) | |
| 18 | - MB86R0x_CRG_BASE; | |
| 19 | - uint32_t pllmode; | |
| 20 | - | |
| 21 | - pllmode = readl(&crg->crpr) & MB86R0x_CRG_CRPR_PLLMODE; | |
| 22 | - | |
| 23 | - if (pllmode == MB86R0x_CRG_CRPR_PLLMODE_X20) | |
| 24 | - return 40000000; | |
| 25 | - | |
| 26 | - return 41164767; | |
| 27 | -} |
arch/arm/cpu/arm926ejs/mb86r0x/reset.c
| 1 | -/* | |
| 2 | - * (C) Copyright 2010 | |
| 3 | - * Matthias Weisser <weisserm@arcor.de> | |
| 4 | - * | |
| 5 | - * SPDX-License-Identifier: GPL-2.0+ | |
| 6 | - */ | |
| 7 | - | |
| 8 | -#include <common.h> | |
| 9 | -#include <asm/io.h> | |
| 10 | -#include <asm/arch/hardware.h> | |
| 11 | - | |
| 12 | -/* | |
| 13 | - * Reset the cpu by setting software reset request bit | |
| 14 | - */ | |
| 15 | -void reset_cpu(ulong ignored) | |
| 16 | -{ | |
| 17 | - struct mb86r0x_crg * crg = (struct mb86r0x_crg *) | |
| 18 | - MB86R0x_CRG_BASE; | |
| 19 | - | |
| 20 | - writel(MB86R0x_CRSR_SWRSTREQ, &crg->crsr); | |
| 21 | - while (1) | |
| 22 | - /* NOP */; | |
| 23 | - /* Never reached */ | |
| 24 | -} |
arch/arm/cpu/arm926ejs/mb86r0x/timer.c
| 1 | -/* | |
| 2 | - * (C) Copyright 2007-2008 | |
| 3 | - * Stelian Pop <stelian@popies.net> | |
| 4 | - * Lead Tech Design <www.leadtechdesign.com> | |
| 5 | - * | |
| 6 | - * (C) Copyright 2010 | |
| 7 | - * Matthias Weisser, Graf-Syteco <weisserm@arcor.de> | |
| 8 | - * | |
| 9 | - * SPDX-License-Identifier: GPL-2.0+ | |
| 10 | - */ | |
| 11 | - | |
| 12 | -#include <div64.h> | |
| 13 | -#include <common.h> | |
| 14 | -#include <asm/io.h> | |
| 15 | -#include <asm/arch/hardware.h> | |
| 16 | - | |
| 17 | -#define TIMER_LOAD_VAL 0xffffffff | |
| 18 | -#define TIMER_FREQ (CONFIG_MB86R0x_IOCLK / 256) | |
| 19 | - | |
| 20 | -DECLARE_GLOBAL_DATA_PTR; | |
| 21 | - | |
| 22 | -#define timestamp gd->arch.tbl | |
| 23 | -#define lastdec gd->arch.lastinc | |
| 24 | - | |
| 25 | -static inline unsigned long long tick_to_time(unsigned long long tick) | |
| 26 | -{ | |
| 27 | - tick *= CONFIG_SYS_HZ; | |
| 28 | - do_div(tick, TIMER_FREQ); | |
| 29 | - | |
| 30 | - return tick; | |
| 31 | -} | |
| 32 | - | |
| 33 | -static inline unsigned long long usec_to_tick(unsigned long long usec) | |
| 34 | -{ | |
| 35 | - usec *= TIMER_FREQ; | |
| 36 | - do_div(usec, 1000000); | |
| 37 | - | |
| 38 | - return usec; | |
| 39 | -} | |
| 40 | - | |
| 41 | -/* nothing really to do with interrupts, just starts up a counter. */ | |
| 42 | -int timer_init(void) | |
| 43 | -{ | |
| 44 | - struct mb86r0x_timer * timer = (struct mb86r0x_timer *) | |
| 45 | - MB86R0x_TIMER_BASE; | |
| 46 | - ulong ctrl = readl(&timer->control); | |
| 47 | - | |
| 48 | - writel(TIMER_LOAD_VAL, &timer->load); | |
| 49 | - | |
| 50 | - ctrl |= MB86R0x_TIMER_ENABLE | MB86R0x_TIMER_PRS_8S | | |
| 51 | - MB86R0x_TIMER_SIZE_32; | |
| 52 | - | |
| 53 | - writel(ctrl, &timer->control); | |
| 54 | - | |
| 55 | - /* capture current value time */ | |
| 56 | - lastdec = readl(&timer->value); | |
| 57 | - timestamp = 0; /* start "advancing" time stamp from 0 */ | |
| 58 | - | |
| 59 | - return 0; | |
| 60 | -} | |
| 61 | - | |
| 62 | -/* | |
| 63 | - * timer without interrupts | |
| 64 | - */ | |
| 65 | -unsigned long long get_ticks(void) | |
| 66 | -{ | |
| 67 | - struct mb86r0x_timer * timer = (struct mb86r0x_timer *) | |
| 68 | - MB86R0x_TIMER_BASE; | |
| 69 | - ulong now = readl(&timer->value); | |
| 70 | - | |
| 71 | - if (now <= lastdec) { | |
| 72 | - /* normal mode (non roll) */ | |
| 73 | - /* move stamp forward with absolut diff ticks */ | |
| 74 | - timestamp += lastdec - now; | |
| 75 | - } else { | |
| 76 | - /* we have rollover of incrementer */ | |
| 77 | - timestamp += lastdec + TIMER_LOAD_VAL - now; | |
| 78 | - } | |
| 79 | - lastdec = now; | |
| 80 | - return timestamp; | |
| 81 | -} | |
| 82 | - | |
| 83 | -ulong get_timer_masked(void) | |
| 84 | -{ | |
| 85 | - return tick_to_time(get_ticks()); | |
| 86 | -} | |
| 87 | - | |
| 88 | -void __udelay(unsigned long usec) | |
| 89 | -{ | |
| 90 | - unsigned long long tmp; | |
| 91 | - ulong tmo; | |
| 92 | - | |
| 93 | - tmo = usec_to_tick(usec); | |
| 94 | - tmp = get_ticks(); /* get current timestamp */ | |
| 95 | - | |
| 96 | - while ((get_ticks() - tmp) < tmo) /* loop till event */ | |
| 97 | - /*NOP*/; | |
| 98 | -} | |
| 99 | - | |
| 100 | -ulong get_timer(ulong base) | |
| 101 | -{ | |
| 102 | - return get_timer_masked() - base; | |
| 103 | -} | |
| 104 | - | |
| 105 | -/* | |
| 106 | - * This function is derived from PowerPC code (timebase clock frequency). | |
| 107 | - * On ARM it returns the number of timer ticks per second. | |
| 108 | - */ | |
| 109 | -ulong get_tbclk(void) | |
| 110 | -{ | |
| 111 | - ulong tbclk; | |
| 112 | - | |
| 113 | - tbclk = TIMER_FREQ; | |
| 114 | - return tbclk; | |
| 115 | -} |
arch/arm/include/asm/arch-mb86r0x/hardware.h
| 1 | -/* | |
| 2 | - * (C) Copyright 2007 | |
| 3 | - * | |
| 4 | - * Author : Carsten Schneider, mycable GmbH | |
| 5 | - * <cs@mycable.de> | |
| 6 | - * | |
| 7 | - * SPDX-License-Identifier: GPL-2.0+ | |
| 8 | - */ | |
| 9 | -#ifndef __ASM_ARCH_HARDWARE_H | |
| 10 | -#define __ASM_ARCH_HARDWARE_H | |
| 11 | - | |
| 12 | -#include <linux/sizes.h> | |
| 13 | -#include <asm/arch/mb86r0x.h> | |
| 14 | - | |
| 15 | -#endif |
arch/arm/include/asm/arch-mb86r0x/mb86r0x.h
| 1 | -/* | |
| 2 | - * (C) Copyright 2007 | |
| 3 | - * | |
| 4 | - * mb86r0x definitions | |
| 5 | - * | |
| 6 | - * Author : Carsten Schneider, mycable GmbH | |
| 7 | - * <cs@mycable.de> | |
| 8 | - * | |
| 9 | - * (C) Copyright 2010 | |
| 10 | - * Matthias Weisser <weisserm@arcor.de> | |
| 11 | - * | |
| 12 | - * SPDX-License-Identifier: GPL-2.0+ | |
| 13 | - */ | |
| 14 | - | |
| 15 | -#ifndef MB86R0X_H | |
| 16 | -#define MB86R0X_H | |
| 17 | - | |
| 18 | -#ifndef __ASSEMBLY__ | |
| 19 | - | |
| 20 | -/* GPIO registers */ | |
| 21 | -struct mb86r0x_gpio { | |
| 22 | - uint32_t gpdr0; | |
| 23 | - uint32_t gpdr1; | |
| 24 | - uint32_t gpdr2; | |
| 25 | - uint32_t res; | |
| 26 | - uint32_t gpddr0; | |
| 27 | - uint32_t gpddr1; | |
| 28 | - uint32_t gpddr2; | |
| 29 | -}; | |
| 30 | - | |
| 31 | -/* PWM registers */ | |
| 32 | -struct mb86r0x_pwm { | |
| 33 | - uint32_t bcr; | |
| 34 | - uint32_t tpr; | |
| 35 | - uint32_t pr; | |
| 36 | - uint32_t dr; | |
| 37 | - uint32_t cr; | |
| 38 | - uint32_t sr; | |
| 39 | - uint32_t ccr; | |
| 40 | - uint32_t ir; | |
| 41 | -}; | |
| 42 | - | |
| 43 | -/* The mb86r0x chip control (CCNT) register set. */ | |
| 44 | -struct mb86r0x_ccnt { | |
| 45 | - uint32_t ccid; | |
| 46 | - uint32_t csrst; | |
| 47 | - uint32_t pad0[2]; | |
| 48 | - uint32_t cist; | |
| 49 | - uint32_t cistm; | |
| 50 | - uint32_t cgpio_ist; | |
| 51 | - uint32_t cgpio_istm; | |
| 52 | - uint32_t cgpio_ip; | |
| 53 | - uint32_t cgpio_im; | |
| 54 | - uint32_t caxi_bw; | |
| 55 | - uint32_t caxi_ps; | |
| 56 | - uint32_t cmux_md; | |
| 57 | - uint32_t cex_pin_st; | |
| 58 | - uint32_t cmlb; | |
| 59 | - uint32_t pad1[1]; | |
| 60 | - uint32_t cusb; | |
| 61 | - uint32_t pad2[41]; | |
| 62 | - uint32_t cbsc; | |
| 63 | - uint32_t cdcrc; | |
| 64 | - uint32_t cmsr0; | |
| 65 | - uint32_t cmsr1; | |
| 66 | - uint32_t pad3[2]; | |
| 67 | -}; | |
| 68 | - | |
| 69 | -/* The mb86r0x clock reset generator */ | |
| 70 | -struct mb86r0x_crg { | |
| 71 | - uint32_t crpr; | |
| 72 | - uint32_t pad0; | |
| 73 | - uint32_t crwr; | |
| 74 | - uint32_t crsr; | |
| 75 | - uint32_t crda; | |
| 76 | - uint32_t crdb; | |
| 77 | - uint32_t crha; | |
| 78 | - uint32_t crpa; | |
| 79 | - uint32_t crpb; | |
| 80 | - uint32_t crhb; | |
| 81 | - uint32_t cram; | |
| 82 | -}; | |
| 83 | - | |
| 84 | -/* The mb86r0x timer */ | |
| 85 | -struct mb86r0x_timer { | |
| 86 | - uint32_t load; | |
| 87 | - uint32_t value; | |
| 88 | - uint32_t control; | |
| 89 | - uint32_t intclr; | |
| 90 | - uint32_t ris; | |
| 91 | - uint32_t mis; | |
| 92 | - uint32_t bgload; | |
| 93 | -}; | |
| 94 | - | |
| 95 | -/* mb86r0x gdc display controller */ | |
| 96 | -struct mb86r0x_gdc_dsp { | |
| 97 | - /* Display settings */ | |
| 98 | - uint32_t dcm0; | |
| 99 | - uint16_t pad00; | |
| 100 | - uint16_t htp; | |
| 101 | - uint16_t hdp; | |
| 102 | - uint16_t hdb; | |
| 103 | - uint16_t hsp; | |
| 104 | - uint8_t hsw; | |
| 105 | - uint8_t vsw; | |
| 106 | - uint16_t pad01; | |
| 107 | - uint16_t vtr; | |
| 108 | - uint16_t vsp; | |
| 109 | - uint16_t vdp; | |
| 110 | - uint16_t wx; | |
| 111 | - uint16_t wy; | |
| 112 | - uint16_t ww; | |
| 113 | - uint16_t wh; | |
| 114 | - | |
| 115 | - /* Layer 0 */ | |
| 116 | - uint32_t l0m; | |
| 117 | - uint32_t l0oa; | |
| 118 | - uint32_t l0da; | |
| 119 | - uint16_t l0dx; | |
| 120 | - uint16_t l0dy; | |
| 121 | - | |
| 122 | - /* Layer 1 */ | |
| 123 | - uint32_t l1m; | |
| 124 | - uint32_t cbda0; | |
| 125 | - uint32_t cbda1; | |
| 126 | - uint32_t pad02; | |
| 127 | - | |
| 128 | - /* Layer 2 */ | |
| 129 | - uint32_t l2m; | |
| 130 | - uint32_t l2oa0; | |
| 131 | - uint32_t l2da0; | |
| 132 | - uint32_t l2oa1; | |
| 133 | - uint32_t l2da1; | |
| 134 | - uint16_t l2dx; | |
| 135 | - uint16_t l2dy; | |
| 136 | - | |
| 137 | - /* Layer 3 */ | |
| 138 | - uint32_t l3m; | |
| 139 | - uint32_t l3oa0; | |
| 140 | - uint32_t l3da0; | |
| 141 | - uint32_t l3oa1; | |
| 142 | - uint32_t l3da1; | |
| 143 | - uint16_t l3dx; | |
| 144 | - uint16_t l3dy; | |
| 145 | - | |
| 146 | - /* Layer 4 */ | |
| 147 | - uint32_t l4m; | |
| 148 | - uint32_t l4oa0; | |
| 149 | - uint32_t l4da0; | |
| 150 | - uint32_t l4oa1; | |
| 151 | - uint32_t l4da1; | |
| 152 | - uint16_t l4dx; | |
| 153 | - uint16_t l4dy; | |
| 154 | - | |
| 155 | - /* Layer 5 */ | |
| 156 | - uint32_t l5m; | |
| 157 | - uint32_t l5oa0; | |
| 158 | - uint32_t l5da0; | |
| 159 | - uint32_t l5oa1; | |
| 160 | - uint32_t l5da1; | |
| 161 | - uint16_t l5dx; | |
| 162 | - uint16_t l5dy; | |
| 163 | - | |
| 164 | - /* Cursor */ | |
| 165 | - uint16_t cutc; | |
| 166 | - uint8_t cpm; | |
| 167 | - uint8_t csize; | |
| 168 | - uint32_t cuoa0; | |
| 169 | - uint16_t cux0; | |
| 170 | - uint16_t cuy0; | |
| 171 | - uint32_t cuoa1; | |
| 172 | - uint16_t cux1; | |
| 173 | - uint16_t cuy1; | |
| 174 | - | |
| 175 | - /* Layer blending */ | |
| 176 | - uint32_t l0bld; | |
| 177 | - uint32_t pad03; | |
| 178 | - uint32_t l0tc; | |
| 179 | - uint16_t l3tc; | |
| 180 | - uint16_t l2tc; | |
| 181 | - uint32_t pad04[15]; | |
| 182 | - | |
| 183 | - /* Display settings */ | |
| 184 | - uint32_t dcm1; | |
| 185 | - uint32_t dcm2; | |
| 186 | - uint32_t dcm3; | |
| 187 | - uint32_t pad05; | |
| 188 | - | |
| 189 | - /* Layer 0 extended */ | |
| 190 | - uint32_t l0em; | |
| 191 | - uint16_t l0wx; | |
| 192 | - uint16_t l0wy; | |
| 193 | - uint16_t l0ww; | |
| 194 | - uint16_t l0wh; | |
| 195 | - uint32_t pad06; | |
| 196 | - | |
| 197 | - /* Layer 1 extended */ | |
| 198 | - uint32_t l1em; | |
| 199 | - uint16_t l1wx; | |
| 200 | - uint16_t l1wy; | |
| 201 | - uint16_t l1ww; | |
| 202 | - uint16_t l1wh; | |
| 203 | - uint32_t pad07; | |
| 204 | - | |
| 205 | - /* Layer 2 extended */ | |
| 206 | - uint32_t l2em; | |
| 207 | - uint16_t l2wx; | |
| 208 | - uint16_t l2wy; | |
| 209 | - uint16_t l2ww; | |
| 210 | - uint16_t l2wh; | |
| 211 | - uint32_t pad08; | |
| 212 | - | |
| 213 | - /* Layer 3 extended */ | |
| 214 | - uint32_t l3em; | |
| 215 | - uint16_t l3wx; | |
| 216 | - uint16_t l3wy; | |
| 217 | - uint16_t l3ww; | |
| 218 | - uint16_t l3wh; | |
| 219 | - uint32_t pad09; | |
| 220 | - | |
| 221 | - /* Layer 4 extended */ | |
| 222 | - uint32_t l4em; | |
| 223 | - uint16_t l4wx; | |
| 224 | - uint16_t l4wy; | |
| 225 | - uint16_t l4ww; | |
| 226 | - uint16_t l4wh; | |
| 227 | - uint32_t pad10; | |
| 228 | - | |
| 229 | - /* Layer 5 extended */ | |
| 230 | - uint32_t l5em; | |
| 231 | - uint16_t l5wx; | |
| 232 | - uint16_t l5wy; | |
| 233 | - uint16_t l5ww; | |
| 234 | - uint16_t l5wh; | |
| 235 | - uint32_t pad11; | |
| 236 | - | |
| 237 | - /* Multi screen control */ | |
| 238 | - uint32_t msc; | |
| 239 | - uint32_t pad12[3]; | |
| 240 | - uint32_t dls; | |
| 241 | - uint32_t dbgc; | |
| 242 | - | |
| 243 | - /* Layer blending */ | |
| 244 | - uint32_t l1bld; | |
| 245 | - uint32_t l2bld; | |
| 246 | - uint32_t l3bld; | |
| 247 | - uint32_t l4bld; | |
| 248 | - uint32_t l5bld; | |
| 249 | - uint32_t pad13; | |
| 250 | - | |
| 251 | - /* Extended transparency control */ | |
| 252 | - uint32_t l0etc; | |
| 253 | - uint32_t l1etc; | |
| 254 | - uint32_t l2etc; | |
| 255 | - uint32_t l3etc; | |
| 256 | - uint32_t l4etc; | |
| 257 | - uint32_t l5etc; | |
| 258 | - uint32_t pad14[10]; | |
| 259 | - | |
| 260 | - /* YUV coefficients */ | |
| 261 | - uint32_t l1ycr0; | |
| 262 | - uint32_t l1ycr1; | |
| 263 | - uint32_t l1ycg0; | |
| 264 | - uint32_t l1ycg1; | |
| 265 | - uint32_t l1ycb0; | |
| 266 | - uint32_t l1ycb1; | |
| 267 | - uint32_t pad15[130]; | |
| 268 | - | |
| 269 | - /* Layer palletes */ | |
| 270 | - uint32_t l0pal[256]; | |
| 271 | - uint32_t l1pal[256]; | |
| 272 | - uint32_t pad16[256]; | |
| 273 | - uint32_t l2pal[256]; | |
| 274 | - uint32_t l3pal[256]; | |
| 275 | - uint32_t pad17[256]; | |
| 276 | - | |
| 277 | - /* PWM settings */ | |
| 278 | - uint32_t vpwmm; | |
| 279 | - uint16_t vpwms; | |
| 280 | - uint16_t vpwme; | |
| 281 | - uint32_t vpwmc; | |
| 282 | - uint32_t pad18[253]; | |
| 283 | -}; | |
| 284 | - | |
| 285 | -/* mb86r0x gdc capture controller */ | |
| 286 | -struct mb86r0x_gdc_cap { | |
| 287 | - uint32_t vcm; | |
| 288 | - uint32_t csc; | |
| 289 | - uint32_t vcs; | |
| 290 | - uint32_t pad01; | |
| 291 | - | |
| 292 | - uint32_t cbm; | |
| 293 | - uint32_t cboa; | |
| 294 | - uint32_t cbla; | |
| 295 | - uint16_t cihstr; | |
| 296 | - uint16_t civstr; | |
| 297 | - uint16_t cihend; | |
| 298 | - uint16_t civend; | |
| 299 | - uint32_t pad02; | |
| 300 | - | |
| 301 | - uint32_t chp; | |
| 302 | - uint32_t cvp; | |
| 303 | - uint32_t pad03[4]; | |
| 304 | - | |
| 305 | - uint32_t clpf; | |
| 306 | - uint32_t pad04; | |
| 307 | - uint32_t cmss; | |
| 308 | - uint32_t cmds; | |
| 309 | - uint32_t pad05[12]; | |
| 310 | - | |
| 311 | - uint32_t rgbhc; | |
| 312 | - uint32_t rgbhen; | |
| 313 | - uint32_t rgbven; | |
| 314 | - uint32_t pad06; | |
| 315 | - uint32_t rgbs; | |
| 316 | - uint32_t pad07[11]; | |
| 317 | - | |
| 318 | - uint32_t rgbcmy; | |
| 319 | - uint32_t rgbcmcb; | |
| 320 | - uint32_t rgbcmcr; | |
| 321 | - uint32_t rgbcmb; | |
| 322 | - uint32_t pad08[12 + 1984]; | |
| 323 | -}; | |
| 324 | - | |
| 325 | -/* mb86r0x gdc draw */ | |
| 326 | -struct mb86r0x_gdc_draw { | |
| 327 | - uint32_t ys; | |
| 328 | - uint32_t xs; | |
| 329 | - uint32_t dxdy; | |
| 330 | - uint32_t xus; | |
| 331 | - uint32_t dxudy; | |
| 332 | - uint32_t xls; | |
| 333 | - uint32_t dxldy; | |
| 334 | - uint32_t usn; | |
| 335 | - uint32_t lsn; | |
| 336 | - uint32_t pad01[7]; | |
| 337 | - uint32_t rs; | |
| 338 | - uint32_t drdx; | |
| 339 | - uint32_t drdy; | |
| 340 | - uint32_t gs; | |
| 341 | - uint32_t dgdx; | |
| 342 | - uint32_t dgdy; | |
| 343 | - uint32_t bs; | |
| 344 | - uint32_t dbdx; | |
| 345 | - uint32_t dbdy; | |
| 346 | - uint32_t pad02[7]; | |
| 347 | - uint32_t zs; | |
| 348 | - uint32_t dzdx; | |
| 349 | - uint32_t dzdy; | |
| 350 | - uint32_t pad03[13]; | |
| 351 | - uint32_t ss; | |
| 352 | - uint32_t dsdx; | |
| 353 | - uint32_t dsdy; | |
| 354 | - uint32_t ts; | |
| 355 | - uint32_t dtdx; | |
| 356 | - uint32_t dtdy; | |
| 357 | - uint32_t qs; | |
| 358 | - uint32_t dqdx; | |
| 359 | - uint32_t dqdy; | |
| 360 | - uint32_t pad04[23]; | |
| 361 | - uint32_t lpn; | |
| 362 | - uint32_t lxs; | |
| 363 | - uint32_t lxde; | |
| 364 | - uint32_t lys; | |
| 365 | - uint32_t lyde; | |
| 366 | - uint32_t lzs; | |
| 367 | - uint32_t lzde; | |
| 368 | - uint32_t pad05[13]; | |
| 369 | - uint32_t pxdc; | |
| 370 | - uint32_t pydc; | |
| 371 | - uint32_t pzdc; | |
| 372 | - uint32_t pad06[25]; | |
| 373 | - uint32_t rxs; | |
| 374 | - uint32_t rys; | |
| 375 | - uint32_t rsizex; | |
| 376 | - uint32_t rsizey; | |
| 377 | - uint32_t pad07[12]; | |
| 378 | - uint32_t saddr; | |
| 379 | - uint32_t sstride; | |
| 380 | - uint32_t srx; | |
| 381 | - uint32_t sry; | |
| 382 | - uint32_t daddr; | |
| 383 | - uint32_t dstride; | |
| 384 | - uint32_t drx; | |
| 385 | - uint32_t dry; | |
| 386 | - uint32_t brsizex; | |
| 387 | - uint32_t brsizey; | |
| 388 | - uint32_t tcolor; | |
| 389 | - uint32_t pad08[93]; | |
| 390 | - uint32_t blpo; | |
| 391 | - uint32_t pad09[7]; | |
| 392 | - uint32_t ctr; | |
| 393 | - uint32_t ifsr; | |
| 394 | - uint32_t ifcnt; | |
| 395 | - uint32_t sst; | |
| 396 | - uint32_t ds; | |
| 397 | - uint32_t pst; | |
| 398 | - uint32_t est; | |
| 399 | - uint32_t pad10; | |
| 400 | - uint32_t mdr0; | |
| 401 | - uint32_t mdr1; | |
| 402 | - uint32_t mdr2; | |
| 403 | - uint32_t mdr3; | |
| 404 | - uint32_t mdr4; | |
| 405 | - uint32_t pad14[2]; | |
| 406 | - uint32_t mdr7; | |
| 407 | - uint32_t fbr; | |
| 408 | - uint32_t xres; | |
| 409 | - uint32_t zbr; | |
| 410 | - uint32_t tbr; | |
| 411 | - uint32_t pfbr; | |
| 412 | - uint32_t cxmin; | |
| 413 | - uint32_t cxmax; | |
| 414 | - uint32_t cymin; | |
| 415 | - uint32_t cymax; | |
| 416 | - uint32_t txs; | |
| 417 | - uint32_t tis; | |
| 418 | - uint32_t toa; | |
| 419 | - uint32_t sho; | |
| 420 | - uint32_t abr; | |
| 421 | - uint32_t pad15[2]; | |
| 422 | - uint32_t fc; | |
| 423 | - uint32_t bc; | |
| 424 | - uint32_t alf; | |
| 425 | - uint32_t blp; | |
| 426 | - uint32_t pad16; | |
| 427 | - uint32_t tbc; | |
| 428 | - uint32_t pad11[42]; | |
| 429 | - uint32_t lx0dc; | |
| 430 | - uint32_t ly0dc; | |
| 431 | - uint32_t lx1dc; | |
| 432 | - uint32_t ly1dc; | |
| 433 | - uint32_t pad12[12]; | |
| 434 | - uint32_t x0dc; | |
| 435 | - uint32_t y0dc; | |
| 436 | - uint32_t x1dc; | |
| 437 | - uint32_t y1dc; | |
| 438 | - uint32_t x2dc; | |
| 439 | - uint32_t y2dc; | |
| 440 | - uint32_t pad13[666]; | |
| 441 | -}; | |
| 442 | - | |
| 443 | -/* mb86r0x gdc geometry engine */ | |
| 444 | -struct mb86r0x_gdc_geom { | |
| 445 | - uint32_t gctr; | |
| 446 | - uint32_t pad00[15]; | |
| 447 | - uint32_t gmdr0; | |
| 448 | - uint32_t gmdr1; | |
| 449 | - uint32_t gmdr2; | |
| 450 | - uint32_t pad01[237]; | |
| 451 | - uint32_t dfifog; | |
| 452 | - uint32_t pad02[767]; | |
| 453 | -}; | |
| 454 | - | |
| 455 | -/* mb86r0x gdc */ | |
| 456 | -struct mb86r0x_gdc { | |
| 457 | - uint32_t pad00[2]; | |
| 458 | - uint32_t lts; | |
| 459 | - uint32_t pad01; | |
| 460 | - uint32_t lsta; | |
| 461 | - uint32_t pad02[3]; | |
| 462 | - uint32_t ist; | |
| 463 | - uint32_t imask; | |
| 464 | - uint32_t pad03[6]; | |
| 465 | - uint32_t lsa; | |
| 466 | - uint32_t lco; | |
| 467 | - uint32_t lreq; | |
| 468 | - | |
| 469 | - uint32_t pad04[16*1024 - 19]; | |
| 470 | - struct mb86r0x_gdc_dsp dsp0; | |
| 471 | - struct mb86r0x_gdc_dsp dsp1; | |
| 472 | - uint32_t pad05[4*1024 - 2]; | |
| 473 | - uint32_t vccc; | |
| 474 | - uint32_t vcsr; | |
| 475 | - struct mb86r0x_gdc_cap cap0; | |
| 476 | - struct mb86r0x_gdc_cap cap1; | |
| 477 | - uint32_t pad06[4*1024]; | |
| 478 | - uint32_t texture_base[16*1024]; | |
| 479 | - struct mb86r0x_gdc_draw draw; | |
| 480 | - uint32_t pad07[7*1024]; | |
| 481 | - struct mb86r0x_gdc_geom geom; | |
| 482 | - uint32_t pad08[7*1024]; | |
| 483 | -}; | |
| 484 | - | |
| 485 | -/* mb86r0x ddr2c */ | |
| 486 | -struct mb86r0x_ddr2c { | |
| 487 | - uint16_t dric; | |
| 488 | - uint16_t dric1; | |
| 489 | - uint16_t dric2; | |
| 490 | - uint16_t drca; | |
| 491 | - uint16_t drcm; | |
| 492 | - uint16_t drcst1; | |
| 493 | - uint16_t drcst2; | |
| 494 | - uint16_t drcr; | |
| 495 | - uint16_t pad00[8]; | |
| 496 | - uint16_t drcf; | |
| 497 | - uint16_t pad01[7]; | |
| 498 | - uint16_t drasr; | |
| 499 | - uint16_t pad02[15]; | |
| 500 | - uint16_t drims; | |
| 501 | - uint16_t pad03[7]; | |
| 502 | - uint16_t dros; | |
| 503 | - uint16_t pad04; | |
| 504 | - uint16_t dribsodt1; | |
| 505 | - uint16_t dribsocd; | |
| 506 | - uint16_t dribsocd2; | |
| 507 | - uint16_t pad05[3]; | |
| 508 | - uint16_t droaba; | |
| 509 | - uint16_t pad06[9]; | |
| 510 | - uint16_t drobs; | |
| 511 | - uint16_t pad07[5]; | |
| 512 | - uint16_t drimr1; | |
| 513 | - uint16_t drimr2; | |
| 514 | - uint16_t drimr3; | |
| 515 | - uint16_t drimr4; | |
| 516 | - uint16_t droisr1; | |
| 517 | - uint16_t droisr2; | |
| 518 | -}; | |
| 519 | - | |
| 520 | -/* mb86r0x memc */ | |
| 521 | -struct mb86r0x_memc { | |
| 522 | - uint32_t mcfmode[8]; | |
| 523 | - uint32_t mcftim[8]; | |
| 524 | - uint32_t mcfarea[8]; | |
| 525 | -}; | |
| 526 | - | |
| 527 | -#endif /* __ASSEMBLY__ */ | |
| 528 | - | |
| 529 | -/* | |
| 530 | - * Physical Address Defines | |
| 531 | - */ | |
| 532 | -#define MB86R0x_DDR2_BASE 0xf3000000 | |
| 533 | -#define MB86R0x_GDC_BASE 0xf1fc0000 | |
| 534 | -#define MB86R0x_CCNT_BASE 0xfff42000 | |
| 535 | -#define MB86R0x_CAN0_BASE 0xfff54000 | |
| 536 | -#define MB86R0x_CAN1_BASE 0xfff55000 | |
| 537 | -#define MB86R0x_I2C0_BASE 0xfff56000 | |
| 538 | -#define MB86R0x_I2C1_BASE 0xfff57000 | |
| 539 | -#define MB86R0x_EHCI_BASE 0xfff80000 | |
| 540 | -#define MB86R0x_OHCI_BASE 0xfff81000 | |
| 541 | -#define MB86R0x_IRC1_BASE 0xfffb0000 | |
| 542 | -#define MB86R0x_MEMC_BASE 0xfffc0000 | |
| 543 | -#define MB86R0x_TIMER_BASE 0xfffe0000 | |
| 544 | -#define MB86R0x_UART0_BASE 0xfffe1000 | |
| 545 | -#define MB86R0x_UART1_BASE 0xfffe2000 | |
| 546 | -#define MB86R0x_IRCE_BASE 0xfffe4000 | |
| 547 | -#define MB86R0x_CRG_BASE 0xfffe7000 | |
| 548 | -#define MB86R0x_IRC0_BASE 0xfffe8000 | |
| 549 | -#define MB86R0x_GPIO_BASE 0xfffe9000 | |
| 550 | -#define MB86R0x_PWM0_BASE 0xfff41000 | |
| 551 | -#define MB86R0x_PWM1_BASE 0xfff41100 | |
| 552 | - | |
| 553 | -#define MB86R0x_CRSR_SWRSTREQ (1 << 1) | |
| 554 | - | |
| 555 | -/* | |
| 556 | - * Timer register bits | |
| 557 | - */ | |
| 558 | -#define MB86R0x_TIMER_ENABLE (1 << 7) | |
| 559 | -#define MB86R0x_TIMER_MODE_MSK (1 << 6) | |
| 560 | -#define MB86R0x_TIMER_MODE_FR (0 << 6) | |
| 561 | -#define MB86R0x_TIMER_MODE_PD (1 << 6) | |
| 562 | - | |
| 563 | -#define MB86R0x_TIMER_INT_EN (1 << 5) | |
| 564 | -#define MB86R0x_TIMER_PRS_MSK (3 << 2) | |
| 565 | -#define MB86R0x_TIMER_PRS_4S (1 << 2) | |
| 566 | -#define MB86R0x_TIMER_PRS_8S (1 << 3) | |
| 567 | -#define MB86R0x_TIMER_SIZE_32 (1 << 1) | |
| 568 | -#define MB86R0x_TIMER_ONE_SHT (1 << 0) | |
| 569 | - | |
| 570 | -/* | |
| 571 | - * Clock reset generator bits | |
| 572 | - */ | |
| 573 | -#define MB86R0x_CRG_CRPR_PLLRDY (1 << 8) | |
| 574 | -#define MB86R0x_CRG_CRPR_PLLMODE (0x1f << 0) | |
| 575 | -#define MB86R0x_CRG_CRPR_PLLMODE_X49 (0 << 0) | |
| 576 | -#define MB86R0x_CRG_CRPR_PLLMODE_X46 (1 << 0) | |
| 577 | -#define MB86R0x_CRG_CRPR_PLLMODE_X37 (2 << 0) | |
| 578 | -#define MB86R0x_CRG_CRPR_PLLMODE_X20 (3 << 0) | |
| 579 | -#define MB86R0x_CRG_CRPR_PLLMODE_X47 (4 << 0) | |
| 580 | -#define MB86R0x_CRG_CRPR_PLLMODE_X44 (5 << 0) | |
| 581 | -#define MB86R0x_CRG_CRPR_PLLMODE_X36 (6 << 0) | |
| 582 | -#define MB86R0x_CRG_CRPR_PLLMODE_X19 (7 << 0) | |
| 583 | -#define MB86R0x_CRG_CRPR_PLLMODE_X39 (8 << 0) | |
| 584 | -#define MB86R0x_CRG_CRPR_PLLMODE_X38 (9 << 0) | |
| 585 | -#define MB86R0x_CRG_CRPR_PLLMODE_X30 (10 << 0) | |
| 586 | -#define MB86R0x_CRG_CRPR_PLLMODE_X15 (11 << 0) | |
| 587 | -/* | |
| 588 | - * DDR2 controller bits | |
| 589 | - */ | |
| 590 | -#define MB86R0x_DDR2_DRCI_DRINI (1 << 15) | |
| 591 | -#define MB86R0x_DDR2_DRCI_CKEN (1 << 14) | |
| 592 | -#define MB86R0x_DDR2_DRCI_DRCMD (1 << 0) | |
| 593 | -#define MB86R0x_DDR2_DRCI_CMD (MB86R0x_DDR2_DRCI_DRINI | \ | |
| 594 | - MB86R0x_DDR2_DRCI_CKEN | \ | |
| 595 | - MB86R0x_DDR2_DRCI_DRCMD) | |
| 596 | -#define MB86R0x_DDR2_DRCI_INIT (MB86R0x_DDR2_DRCI_DRINI | \ | |
| 597 | - MB86R0x_DDR2_DRCI_CKEN) | |
| 598 | -#define MB86R0x_DDR2_DRCI_NORMAL MB86R0x_DDR2_DRCI_CKEN | |
| 599 | -#endif /* MB86R0X_H */ |
arch/arm/lib/asm-offsets.c
| ... | ... | @@ -15,9 +15,6 @@ |
| 15 | 15 | #include <common.h> |
| 16 | 16 | #include <linux/kbuild.h> |
| 17 | 17 | |
| 18 | -#if defined(CONFIG_MB86R0x) | |
| 19 | -#include <asm/arch/mb86r0x.h> | |
| 20 | -#endif | |
| 21 | 18 | #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) \ |
| 22 | 19 | || defined(CONFIG_MX51) || defined(CONFIG_MX53) |
| 23 | 20 | #include <asm/arch/imx-regs.h> |
| ... | ... | @@ -27,8 +24,6 @@ |
| 27 | 24 | { |
| 28 | 25 | /* |
| 29 | 26 | * TODO : Check if each entry in this file is really necessary. |
| 30 | - * - struct mb86r0x_ddr2 | |
| 31 | - * - struct mb86r0x_memc | |
| 32 | 27 | * - struct esdramc_regs |
| 33 | 28 | * - struct max_regs |
| 34 | 29 | * - struct aips_regs |
| ... | ... | @@ -39,47 +34,6 @@ |
| 39 | 34 | * It means their offset addresses are referenced only from assembly |
| 40 | 35 | * code. Is it better to define the macros directly in headers? |
| 41 | 36 | */ |
| 42 | - | |
| 43 | -#if defined(CONFIG_MB86R0x) | |
| 44 | - /* ddr2 controller */ | |
| 45 | - DEFINE(DDR2_DRIC, offsetof(struct mb86r0x_ddr2c, dric)); | |
| 46 | - DEFINE(DDR2_DRIC1, offsetof(struct mb86r0x_ddr2c, dric1)); | |
| 47 | - DEFINE(DDR2_DRIC2, offsetof(struct mb86r0x_ddr2c, dric2)); | |
| 48 | - DEFINE(DDR2_DRCA, offsetof(struct mb86r0x_ddr2c, drca)); | |
| 49 | - DEFINE(DDR2_DRCM, offsetof(struct mb86r0x_ddr2c, drcm)); | |
| 50 | - DEFINE(DDR2_DRCST1, offsetof(struct mb86r0x_ddr2c, drcst1)); | |
| 51 | - DEFINE(DDR2_DRCST2, offsetof(struct mb86r0x_ddr2c, drcst2)); | |
| 52 | - DEFINE(DDR2_DRCR, offsetof(struct mb86r0x_ddr2c, drcr)); | |
| 53 | - DEFINE(DDR2_DRCF, offsetof(struct mb86r0x_ddr2c, drcf)); | |
| 54 | - DEFINE(DDR2_DRASR, offsetof(struct mb86r0x_ddr2c, drasr)); | |
| 55 | - DEFINE(DDR2_DRIMS, offsetof(struct mb86r0x_ddr2c, drims)); | |
| 56 | - DEFINE(DDR2_DROS, offsetof(struct mb86r0x_ddr2c, dros)); | |
| 57 | - DEFINE(DDR2_DRIBSODT1, offsetof(struct mb86r0x_ddr2c, dribsodt1)); | |
| 58 | - DEFINE(DDR2_DROABA, offsetof(struct mb86r0x_ddr2c, droaba)); | |
| 59 | - DEFINE(DDR2_DROBS, offsetof(struct mb86r0x_ddr2c, drobs)); | |
| 60 | - | |
| 61 | - /* clock reset generator */ | |
| 62 | - DEFINE(CRG_CRPR, offsetof(struct mb86r0x_crg, crpr)); | |
| 63 | - DEFINE(CRG_CRHA, offsetof(struct mb86r0x_crg, crha)); | |
| 64 | - DEFINE(CRG_CRPA, offsetof(struct mb86r0x_crg, crpa)); | |
| 65 | - DEFINE(CRG_CRPB, offsetof(struct mb86r0x_crg, crpb)); | |
| 66 | - DEFINE(CRG_CRHB, offsetof(struct mb86r0x_crg, crhb)); | |
| 67 | - DEFINE(CRG_CRAM, offsetof(struct mb86r0x_crg, cram)); | |
| 68 | - | |
| 69 | - /* chip control module */ | |
| 70 | - DEFINE(CCNT_CDCRC, offsetof(struct mb86r0x_ccnt, cdcrc)); | |
| 71 | - | |
| 72 | - /* external bus interface */ | |
| 73 | - DEFINE(MEMC_MCFMODE0, offsetof(struct mb86r0x_memc, mcfmode[0])); | |
| 74 | - DEFINE(MEMC_MCFMODE2, offsetof(struct mb86r0x_memc, mcfmode[2])); | |
| 75 | - DEFINE(MEMC_MCFMODE4, offsetof(struct mb86r0x_memc, mcfmode[4])); | |
| 76 | - DEFINE(MEMC_MCFTIM0, offsetof(struct mb86r0x_memc, mcftim[0])); | |
| 77 | - DEFINE(MEMC_MCFTIM2, offsetof(struct mb86r0x_memc, mcftim[2])); | |
| 78 | - DEFINE(MEMC_MCFTIM4, offsetof(struct mb86r0x_memc, mcftim[4])); | |
| 79 | - DEFINE(MEMC_MCFAREA0, offsetof(struct mb86r0x_memc, mcfarea[0])); | |
| 80 | - DEFINE(MEMC_MCFAREA2, offsetof(struct mb86r0x_memc, mcfarea[2])); | |
| 81 | - DEFINE(MEMC_MCFAREA4, offsetof(struct mb86r0x_memc, mcfarea[4])); | |
| 82 | -#endif | |
| 83 | 37 | |
| 84 | 38 | #if defined(CONFIG_MX25) |
| 85 | 39 | /* Clock Control Module */ |
board/syteco/jadecpu/Kconfig
board/syteco/jadecpu/MAINTAINERS
board/syteco/jadecpu/Makefile
| 1 | -# | |
| 2 | -# (C) Copyright 2003-2008 | |
| 3 | -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
| 4 | -# | |
| 5 | -# (C) Copyright 2008 | |
| 6 | -# Stelian Pop <stelian@popies.net> | |
| 7 | -# Lead Tech Design <www.leadtechdesign.com> | |
| 8 | -# | |
| 9 | -# SPDX-License-Identifier: GPL-2.0+ | |
| 10 | -# | |
| 11 | - | |
| 12 | -obj-y += jadecpu.o | |
| 13 | -obj-y += lowlevel_init.o |
board/syteco/jadecpu/jadecpu.c
| 1 | -/* | |
| 2 | - * (c) 2010 Graf-Syteco, Matthias Weisser | |
| 3 | - * <weisserm@arcor.de> | |
| 4 | - * | |
| 5 | - * (C) Copyright 2007, mycable GmbH | |
| 6 | - * Carsten Schneider <cs@mycable.de>, Alexander Bigga <ab@mycable.de> | |
| 7 | - * | |
| 8 | - * SPDX-License-Identifier: GPL-2.0+ | |
| 9 | - */ | |
| 10 | - | |
| 11 | -#include <common.h> | |
| 12 | -#include <netdev.h> | |
| 13 | -#include <asm/io.h> | |
| 14 | -#include <asm/arch/mb86r0x.h> | |
| 15 | - | |
| 16 | -DECLARE_GLOBAL_DATA_PTR; | |
| 17 | - | |
| 18 | -/* | |
| 19 | - * Miscellaneous platform dependent initialisations | |
| 20 | - */ | |
| 21 | -int board_init(void) | |
| 22 | -{ | |
| 23 | - struct mb86r0x_ccnt * ccnt = (struct mb86r0x_ccnt *) | |
| 24 | - MB86R0x_CCNT_BASE; | |
| 25 | - | |
| 26 | - /* We select mode 0 for group 2 and mode 1 for group 4 */ | |
| 27 | - writel(0x00000010, &ccnt->cmux_md); | |
| 28 | - | |
| 29 | - gd->flags = 0; | |
| 30 | - gd->bd->bi_boot_params = PHYS_SDRAM + PHYS_SDRAM_SIZE - 0x10000; | |
| 31 | - | |
| 32 | - icache_enable(); | |
| 33 | - dcache_enable(); | |
| 34 | - | |
| 35 | - return 0; | |
| 36 | -} | |
| 37 | - | |
| 38 | -static void setup_display_power(uint32_t pwr_bit, char *pwm_opts, | |
| 39 | - unsigned long pwm_base) | |
| 40 | -{ | |
| 41 | - struct mb86r0x_gpio *gpio = (struct mb86r0x_gpio *) | |
| 42 | - MB86R0x_GPIO_BASE; | |
| 43 | - struct mb86r0x_pwm *pwm = (struct mb86r0x_pwm *) pwm_base; | |
| 44 | - const char *e; | |
| 45 | - | |
| 46 | - writel(readl(&gpio->gpdr2) | pwr_bit, &gpio->gpdr2); | |
| 47 | - | |
| 48 | - e = getenv(pwm_opts); | |
| 49 | - if (e != NULL) { | |
| 50 | - const char *s; | |
| 51 | - uint32_t freq, init; | |
| 52 | - | |
| 53 | - freq = 0; | |
| 54 | - init = 0; | |
| 55 | - | |
| 56 | - s = strchr(e, 'f'); | |
| 57 | - if (s != NULL) | |
| 58 | - freq = simple_strtol(s + 2, NULL, 0); | |
| 59 | - | |
| 60 | - s = strchr(e, 'i'); | |
| 61 | - if (s != NULL) | |
| 62 | - init = simple_strtol(s + 2, NULL, 0); | |
| 63 | - | |
| 64 | - if (freq > 0) { | |
| 65 | - writel(CONFIG_MB86R0x_IOCLK / 1000 / freq, | |
| 66 | - &pwm->bcr); | |
| 67 | - writel(1002, &pwm->tpr); | |
| 68 | - writel(1, &pwm->pr); | |
| 69 | - writel(init * 10 + 1, &pwm->dr); | |
| 70 | - writel(1, &pwm->cr); | |
| 71 | - writel(1, &pwm->sr); | |
| 72 | - } | |
| 73 | - } | |
| 74 | -} | |
| 75 | - | |
| 76 | -int board_late_init(void) | |
| 77 | -{ | |
| 78 | - struct mb86r0x_gpio *gpio = (struct mb86r0x_gpio *) | |
| 79 | - MB86R0x_GPIO_BASE; | |
| 80 | - uint32_t in_word; | |
| 81 | - | |
| 82 | -#ifdef CONFIG_VIDEO_MB86R0xGDC | |
| 83 | - /* Check if we have valid display settings and turn on power if so */ | |
| 84 | - /* Display 0 */ | |
| 85 | - if (getenv("gs_dsp_0_param") || getenv("videomode")) | |
| 86 | - setup_display_power((1 << 3), "gs_dsp_0_pwm", | |
| 87 | - MB86R0x_PWM0_BASE); | |
| 88 | - | |
| 89 | - /* The corresponding GPIO is always an output */ | |
| 90 | - writel(readl(&gpio->gpddr2) | (1 << 3), &gpio->gpddr2); | |
| 91 | - | |
| 92 | - /* Display 1 */ | |
| 93 | - if (getenv("gs_dsp_1_param") || getenv("videomode1")) | |
| 94 | - setup_display_power((1 << 4), "gs_dsp_1_pwm", | |
| 95 | - MB86R0x_PWM1_BASE); | |
| 96 | - | |
| 97 | - /* The corresponding GPIO is always an output */ | |
| 98 | - writel(readl(&gpio->gpddr2) | (1 << 4), &gpio->gpddr2); | |
| 99 | -#endif /* CONFIG_VIDEO_MB86R0xGDC */ | |
| 100 | - | |
| 101 | - /* 5V enable */ | |
| 102 | - writel(readl(&gpio->gpdr1) & ~(1 << 5), &gpio->gpdr1); | |
| 103 | - writel(readl(&gpio->gpddr1) | (1 << 5), &gpio->gpddr1); | |
| 104 | - | |
| 105 | - /* We have special boot options if told by GPIOs */ | |
| 106 | - in_word = readl(&gpio->gpdr1); | |
| 107 | - | |
| 108 | - if ((in_word & 0xC0) == 0xC0) { | |
| 109 | - setenv("stdin", "serial"); | |
| 110 | - setenv("stdout", "serial"); | |
| 111 | - setenv("stderr", "serial"); | |
| 112 | - setenv("preboot", "run gs_slow_boot"); | |
| 113 | - } else if ((in_word & 0xC0) != 0) { | |
| 114 | - setenv("stdout", "vga"); | |
| 115 | - setenv("preboot", "run gs_slow_boot"); | |
| 116 | - } else { | |
| 117 | - setenv("stdin", "serial"); | |
| 118 | - setenv("stdout", "serial"); | |
| 119 | - setenv("stderr", "serial"); | |
| 120 | - if (getenv("gs_devel")) { | |
| 121 | - setenv("preboot", "run gs_slow_boot"); | |
| 122 | - } else { | |
| 123 | - setenv("preboot", "run gs_fast_boot"); | |
| 124 | - } | |
| 125 | - } | |
| 126 | - | |
| 127 | - return 0; | |
| 128 | -} | |
| 129 | - | |
| 130 | -int misc_init_r(void) | |
| 131 | -{ | |
| 132 | - return 0; | |
| 133 | -} | |
| 134 | - | |
| 135 | -/* | |
| 136 | - * DRAM configuration | |
| 137 | - */ | |
| 138 | -int dram_init(void) | |
| 139 | -{ | |
| 140 | - /* dram_init must store complete ramsize in gd->ram_size */ | |
| 141 | - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, | |
| 142 | - PHYS_SDRAM_SIZE); | |
| 143 | - | |
| 144 | - return 0; | |
| 145 | -} | |
| 146 | - | |
| 147 | -void dram_init_banksize(void) | |
| 148 | -{ | |
| 149 | - gd->bd->bi_dram[0].start = PHYS_SDRAM; | |
| 150 | - gd->bd->bi_dram[0].size = gd->ram_size; | |
| 151 | -} | |
| 152 | - | |
| 153 | -int board_eth_init(bd_t *bis) | |
| 154 | -{ | |
| 155 | - int rc = 0; | |
| 156 | -#ifdef CONFIG_SMC911X | |
| 157 | - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); | |
| 158 | -#endif | |
| 159 | - return rc; | |
| 160 | -} |
board/syteco/jadecpu/lowlevel_init.S
| 1 | -/* | |
| 2 | - * Board specific setup info | |
| 3 | - * | |
| 4 | - * (C) Copyright 2007, mycable GmbH | |
| 5 | - * Carsten Schneider <cs@mycable.de>, Alexander Bigga <ab@mycable.de> | |
| 6 | - * | |
| 7 | - * (C) Copyright 2003, ARM Ltd. | |
| 8 | - * Philippe Robin, <philippe.robin@arm.com> | |
| 9 | - * | |
| 10 | - * SPDX-License-Identifier: GPL-2.0+ | |
| 11 | - */ | |
| 12 | - | |
| 13 | -#include <config.h> | |
| 14 | -#include <version.h> | |
| 15 | -#include <asm/macro.h> | |
| 16 | -#include <asm/arch/mb86r0x.h> | |
| 17 | -#include <generated/asm-offsets.h> | |
| 18 | - | |
| 19 | -/* Set up the platform, once the cpu has been initialized */ | |
| 20 | -.globl lowlevel_init | |
| 21 | -lowlevel_init: | |
| 22 | -/* | |
| 23 | - * Initialize Clock Reset Generator (CRG) | |
| 24 | - */ | |
| 25 | - | |
| 26 | - ldr r0, =MB86R0x_CRG_BASE | |
| 27 | - | |
| 28 | - /* Not change the initial value that is set by external pin.*/ | |
| 29 | -WAIT_PLL: | |
| 30 | - ldr r2, [r0, #CRG_CRPR] /* Wait for PLLREADY */ | |
| 31 | - tst r2, #MB86R0x_CRG_CRPR_PLLRDY | |
| 32 | - beq WAIT_PLL | |
| 33 | - | |
| 34 | - /* Set clock gate control */ | |
| 35 | - ldr r1, =CONFIG_SYS_CRG_CRHA_INIT | |
| 36 | - str r1, [r0, #CRG_CRHA] | |
| 37 | - ldr r1, =CONFIG_SYS_CRG_CRPA_INIT | |
| 38 | - str r1, [r0, #CRG_CRPA] | |
| 39 | - ldr r1, =CONFIG_SYS_CRG_CRPB_INIT | |
| 40 | - str r1, [r0, #CRG_CRPB] | |
| 41 | - ldr r1, =CONFIG_SYS_CRG_CRHB_INIT | |
| 42 | - str r1, [r0, #CRG_CRHB] | |
| 43 | - ldr r1, =CONFIG_SYS_CRG_CRAM_INIT | |
| 44 | - str r1, [r0, #CRG_CRAM] | |
| 45 | - | |
| 46 | -/* | |
| 47 | - * Initialize External Bus Interface | |
| 48 | - */ | |
| 49 | - ldr r0, =MB86R0x_MEMC_BASE | |
| 50 | - | |
| 51 | - ldr r1, =CONFIG_SYS_MEMC_MCFMODE0_INIT | |
| 52 | - str r1, [r0, #MEMC_MCFMODE0] | |
| 53 | - ldr r1, =CONFIG_SYS_MEMC_MCFMODE2_INIT | |
| 54 | - str r1, [r0, #MEMC_MCFMODE2] | |
| 55 | - ldr r1, =CONFIG_SYS_MEMC_MCFMODE4_INIT | |
| 56 | - str r1, [r0, #MEMC_MCFMODE4] | |
| 57 | - | |
| 58 | - ldr r1, =CONFIG_SYS_MEMC_MCFTIM0_INIT | |
| 59 | - str r1, [r0, #MEMC_MCFTIM0] | |
| 60 | - ldr r1, =CONFIG_SYS_MEMC_MCFTIM2_INIT | |
| 61 | - str r1, [r0, #MEMC_MCFTIM2] | |
| 62 | - ldr r1, =CONFIG_SYS_MEMC_MCFTIM4_INIT | |
| 63 | - str r1, [r0, #MEMC_MCFTIM4] | |
| 64 | - | |
| 65 | - ldr r1, =CONFIG_SYS_MEMC_MCFAREA0_INIT | |
| 66 | - str r1, [r0, #MEMC_MCFAREA0] | |
| 67 | - ldr r1, =CONFIG_SYS_MEMC_MCFAREA2_INIT | |
| 68 | - str r1, [r0, #MEMC_MCFAREA2] | |
| 69 | - ldr r1, =CONFIG_SYS_MEMC_MCFAREA4_INIT | |
| 70 | - str r1, [r0, #MEMC_MCFAREA4] | |
| 71 | - | |
| 72 | -/* | |
| 73 | - * Initialize DDR2 Controller | |
| 74 | - */ | |
| 75 | - | |
| 76 | - /* Wait for PLL LOCK up time or more */ | |
| 77 | - wait_timer 20 | |
| 78 | - | |
| 79 | - /* | |
| 80 | - * (2) Initialize DDRIF | |
| 81 | - */ | |
| 82 | - ldr r0, =MB86R0x_DDR2_BASE | |
| 83 | - ldr r1, =CONFIG_SYS_DDR2_DRIMS_INIT | |
| 84 | - strh r1, [r0, #DDR2_DRIMS] | |
| 85 | - | |
| 86 | - /* | |
| 87 | - * (3) Wait for 20MCKPs(120nsec) or more | |
| 88 | - */ | |
| 89 | - wait_timer 20 | |
| 90 | - | |
| 91 | - /* | |
| 92 | - * (4) IRESET/IUSRRST release | |
| 93 | - */ | |
| 94 | - ldr r0, =MB86R0x_CCNT_BASE | |
| 95 | - ldr r1, =CONFIG_SYS_CCNT_CDCRC_INIT_1 | |
| 96 | - str r1, [r0, #CCNT_CDCRC] | |
| 97 | - | |
| 98 | - /* | |
| 99 | - * (5) Wait for 20MCKPs(120nsec) or more | |
| 100 | - */ | |
| 101 | - wait_timer 20 | |
| 102 | - | |
| 103 | - /* | |
| 104 | - * (6) IDLLRST release | |
| 105 | - */ | |
| 106 | - ldr r0, =MB86R0x_CCNT_BASE | |
| 107 | - ldr r1, =CONFIG_SYS_CCNT_CDCRC_INIT_2 | |
| 108 | - str r1, [r0, #CCNT_CDCRC] | |
| 109 | - | |
| 110 | - /* | |
| 111 | - * (7+8) Wait for 200us(=200000ns) or more (DDR2 Spec) | |
| 112 | - */ | |
| 113 | - wait_timer 33536 | |
| 114 | - | |
| 115 | - /* | |
| 116 | - * (9) MCKE ON | |
| 117 | - */ | |
| 118 | - ldr r0, =MB86R0x_DDR2_BASE | |
| 119 | - ldr r1, =CONFIG_SYS_DDR2_DRIC1_INIT | |
| 120 | - strh r1, [r0, #DDR2_DRIC1] | |
| 121 | - ldr r1, =CONFIG_SYS_DDR2_DRIC2_INIT | |
| 122 | - strh r1, [r0, #DDR2_DRIC2] | |
| 123 | - ldr r1, =CONFIG_SYS_DDR2_DRCA_INIT | |
| 124 | - strh r1, [r0, #DDR2_DRCA] | |
| 125 | - ldr r1, =MB86R0x_DDR2_DRCI_INIT | |
| 126 | - strh r1, [r0, #DDR2_DRIC] | |
| 127 | - | |
| 128 | - /* | |
| 129 | - * (10) Initialize SDRAM | |
| 130 | - */ | |
| 131 | - | |
| 132 | - ldr r1, =MB86R0x_DDR2_DRCI_CMD | |
| 133 | - strh r1, [r0, #DDR2_DRIC] | |
| 134 | - | |
| 135 | - wait_timer 67 /* 400ns wait */ | |
| 136 | - | |
| 137 | - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_1 | |
| 138 | - strh r1, [r0, #DDR2_DRIC1] | |
| 139 | - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_1 | |
| 140 | - strh r1, [r0, #DDR2_DRIC2] | |
| 141 | - ldr r1, =MB86R0x_DDR2_DRCI_CMD | |
| 142 | - strh r1, [r0, #DDR2_DRIC] | |
| 143 | - | |
| 144 | - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_2 | |
| 145 | - strh r1, [r0, #DDR2_DRIC1] | |
| 146 | - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_2 | |
| 147 | - strh r1, [r0, #DDR2_DRIC2] | |
| 148 | - ldr r1, =MB86R0x_DDR2_DRCI_CMD | |
| 149 | - strh r1, [r0, #DDR2_DRIC] | |
| 150 | - | |
| 151 | - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_3 | |
| 152 | - strh r1, [r0, #DDR2_DRIC1] | |
| 153 | - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_3 | |
| 154 | - strh r1, [r0, #DDR2_DRIC2] | |
| 155 | - ldr r1, =MB86R0x_DDR2_DRCI_CMD | |
| 156 | - strh r1, [r0, #DDR2_DRIC] | |
| 157 | - | |
| 158 | - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_4 | |
| 159 | - strh r1, [r0, #DDR2_DRIC1] | |
| 160 | - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_4 | |
| 161 | - strh r1, [r0, #DDR2_DRIC2] | |
| 162 | - ldr r1, =MB86R0x_DDR2_DRCI_CMD | |
| 163 | - strh r1, [r0, #DDR2_DRIC] | |
| 164 | - | |
| 165 | - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_5 | |
| 166 | - strh r1, [r0, #DDR2_DRIC1] | |
| 167 | - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_5 | |
| 168 | - strh r1, [r0, #DDR2_DRIC2] | |
| 169 | - ldr r1, =MB86R0x_DDR2_DRCI_CMD | |
| 170 | - strh r1, [r0, #DDR2_DRIC] | |
| 171 | - | |
| 172 | - wait_timer 200 | |
| 173 | - | |
| 174 | - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_6 | |
| 175 | - strh r1, [r0, #DDR2_DRIC1] | |
| 176 | - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_6 | |
| 177 | - strh r1, [r0, #DDR2_DRIC2] | |
| 178 | - ldr r1, =MB86R0x_DDR2_DRCI_CMD | |
| 179 | - strh r1, [r0, #DDR2_DRIC] | |
| 180 | - | |
| 181 | - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_7 | |
| 182 | - strh r1, [r0, #DDR2_DRIC1] | |
| 183 | - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_7 | |
| 184 | - strh r1, [r0, #DDR2_DRIC2] | |
| 185 | - ldr r1, =MB86R0x_DDR2_DRCI_CMD | |
| 186 | - strh r1, [r0, #DDR2_DRIC] | |
| 187 | - | |
| 188 | - wait_timer 18 /* 105ns wait */ | |
| 189 | - | |
| 190 | - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_8 | |
| 191 | - strh r1, [r0, #DDR2_DRIC1] | |
| 192 | - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_8 | |
| 193 | - strh r1, [r0, #DDR2_DRIC2] | |
| 194 | - ldr r1, =MB86R0x_DDR2_DRCI_CMD | |
| 195 | - strh r1, [r0, #DDR2_DRIC] | |
| 196 | - | |
| 197 | - wait_timer 200 /* MRS to OCD: 200clock */ | |
| 198 | - | |
| 199 | - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_9 | |
| 200 | - strh r1, [r0, #DDR2_DRIC1] | |
| 201 | - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_9 | |
| 202 | - strh r1, [r0, #DDR2_DRIC2] | |
| 203 | - ldr r1, =MB86R0x_DDR2_DRCI_CMD | |
| 204 | - strh r1, [r0, #DDR2_DRIC] | |
| 205 | - | |
| 206 | - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC1_10 | |
| 207 | - strh r1, [r0, #DDR2_DRIC1] | |
| 208 | - ldr r1, =CONFIG_SYS_DDR2_INIT_DRIC2_10 | |
| 209 | - strh r1, [r0, #DDR2_DRIC2] | |
| 210 | - ldr r1, =MB86R0x_DDR2_DRCI_CMD | |
| 211 | - strh r1, [r0, #DDR2_DRIC] | |
| 212 | - | |
| 213 | - ldr r1, =CONFIG_SYS_DDR2_DRCM_INIT | |
| 214 | - strh r1, [r0, #DDR2_DRCM] | |
| 215 | - | |
| 216 | - ldr r1, =CONFIG_SYS_DDR2_DRCST1_INIT | |
| 217 | - strh r1, [r0, #DDR2_DRCST1] | |
| 218 | - | |
| 219 | - ldr r1, =CONFIG_SYS_DDR2_DRCST2_INIT | |
| 220 | - strh r1, [r0, #DDR2_DRCST2] | |
| 221 | - | |
| 222 | - ldr r1, =CONFIG_SYS_DDR2_DRCR_INIT | |
| 223 | - strh r1, [r0, #DDR2_DRCR] | |
| 224 | - | |
| 225 | - ldr r1, =CONFIG_SYS_DDR2_DRCF_INIT | |
| 226 | - strh r1, [r0, #DDR2_DRCF] | |
| 227 | - | |
| 228 | - ldr r1, =CONFIG_SYS_DDR2_DRASR_INIT | |
| 229 | - strh r1, [r0, #DDR2_DRASR] | |
| 230 | - | |
| 231 | - /* | |
| 232 | - * (11) ODT setting | |
| 233 | - */ | |
| 234 | - ldr r1, =CONFIG_SYS_DDR2_DROBS_INIT | |
| 235 | - strh r1, [r0, #DDR2_DROBS] | |
| 236 | - ldr r1, =CONFIG_SYS_DDR2_DROABA_INIT | |
| 237 | - strh r1, [r0, #DDR2_DROABA] | |
| 238 | - ldr r1, =CONFIG_SYS_DDR2_DRIBSODT1_INIT | |
| 239 | - strh r1, [r0, #DDR2_DRIBSODT1] | |
| 240 | - | |
| 241 | - /* | |
| 242 | - * (12) Shift to ODTCONT ON (SDRAM side) and DDR2 usual operation mode | |
| 243 | - */ | |
| 244 | - ldr r1, =CONFIG_SYS_DDR2_DROS_INIT | |
| 245 | - strh r1, [r0, #DDR2_DROS] | |
| 246 | - ldr r1, =MB86R0x_DDR2_DRCI_NORMAL | |
| 247 | - strh r1, [r0, #DDR2_DRIC] | |
| 248 | - | |
| 249 | - mov pc, lr |
configs/jadecpu_defconfig
doc/README.scrapyard
| ... | ... | @@ -12,23 +12,24 @@ |
| 12 | 12 | |
| 13 | 13 | Board Arch CPU Commit Removed Last known maintainer/contact |
| 14 | 14 | ================================================================================================= |
| 15 | -icecube_5200 powerpc mpc5xxx - - Wolfgang Denk <wd@denx.de> | |
| 16 | -Lite5200 powerpc mpc5xxx - - | |
| 17 | -cpci5200 powerpc mpc5xxx - - Reinhard Arlt <reinhard.arlt@esd-electronics.com> | |
| 18 | -mecp5200 powerpc mpc5xxx - - Reinhard Arlt <reinhard.arlt@esd-electronics.com> | |
| 19 | -pf5200 powerpc mpc5xxx - - Reinhard Arlt <reinhard.arlt@esd-electronics.com> | |
| 20 | -PM520 powerpc mpc5xxx - - Josef Wagner <Wagner@Microsys.de> | |
| 21 | -Total5200 powerpc mpc5xxx - - | |
| 22 | -CATcenter powerpc ppc4xx - - | |
| 23 | -PPChameleonEVB powerpc ppc4xx - - Andrea "llandre" Marson <andrea.marson@dave-tech.it> | |
| 24 | -P2020DS powerpc mpc85xx - - | |
| 25 | -P2020COME powerpc mpc85xx - - Ira W. Snyder <iws@ovro.caltech.edu> | |
| 26 | -P2020RDB powerpc mpc85xx - - Poonam Aggrwal <poonam.aggrwal@freescale.com> | |
| 27 | -P2010RDB powerpc mpc85xx - - | |
| 28 | -P1020RDB powerpc mpc85xx - - | |
| 29 | -P1011RDB powerpc mpc85xx - - | |
| 30 | -MPC8360EMDS powerpc mpc83xx - - Dave Liu <daveliu@freescale.com> | |
| 31 | -MPC8360ERDK powerpc mpc83xx - - Anton Vorontsov <avorontsov@ru.mvista.com> | |
| 15 | +jadecpu arm arm926ejs - - Matthias Weisser <weisserm@arcor.de> | |
| 16 | +icecube_5200 powerpc mpc5xxx 37b608a5 2015-01-23 Wolfgang Denk <wd@denx.de> | |
| 17 | +Lite5200 powerpc mpc5xxx 37b608a5 2015-01-23 | |
| 18 | +cpci5200 powerpc mpc5xxx 37b608a5 2015-01-23 Reinhard Arlt <reinhard.arlt@esd-electronics.com> | |
| 19 | +mecp5200 powerpc mpc5xxx 37b608a5 2015-01-23 Reinhard Arlt <reinhard.arlt@esd-electronics.com> | |
| 20 | +pf5200 powerpc mpc5xxx 37b608a5 2015-01-23 Reinhard Arlt <reinhard.arlt@esd-electronics.com> | |
| 21 | +PM520 powerpc mpc5xxx a258e732 2015-01-23 Josef Wagner <Wagner@Microsys.de> | |
| 22 | +Total5200 powerpc mpc5xxx ad734f7d 2015-01-23 | |
| 23 | +CATcenter powerpc ppc4xx 5344cc1a 2015-01-23 | |
| 24 | +PPChameleonEVB powerpc ppc4xx 5344cc1a 2015-01-23 Andrea "llandre" Marson <andrea.marson@dave-tech.it> | |
| 25 | +P2020DS powerpc mpc85xx 168dcc6c 2015-01-23 | |
| 26 | +P2020COME powerpc mpc85xx 89123536 2015-01-23 Ira W. Snyder <iws@ovro.caltech.edu> | |
| 27 | +P2020RDB powerpc mpc85xx 743d4815 2015-01-23 Poonam Aggrwal <poonam.aggrwal@freescale.com> | |
| 28 | +P2010RDB powerpc mpc85xx 743d4815 2015-01-23 | |
| 29 | +P1020RDB powerpc mpc85xx 743d4815 2015-01-23 | |
| 30 | +P1011RDB powerpc mpc85xx 743d4815 2015-01-23 | |
| 31 | +MPC8360EMDS powerpc mpc83xx 8d1e3cb1 2015-01-23 Dave Liu <daveliu@freescale.com> | |
| 32 | +MPC8360ERDK powerpc mpc83xx 8d1e3cb1 2015-01-23 Anton Vorontsov <avorontsov@ru.mvista.com> | |
| 32 | 33 | P3G4 powerpc 74xx_7xx d928664f 2015-01-16 Wolfgang Denk <wd@denx.de> |
| 33 | 34 | ZUMA powerpc 74xx_7xx d928664f 2015-01-16 Nye Liu <nyet@zumanetworks.com> |
| 34 | 35 | ppmc7xx powerpc 74xx_7xx d928664f 2015-01-16 |
drivers/video/Makefile
| ... | ... | @@ -32,7 +32,6 @@ |
| 32 | 32 | obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o |
| 33 | 33 | obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o |
| 34 | 34 | obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o |
| 35 | -obj-$(CONFIG_VIDEO_MB86R0xGDC) += mb86r0xgdc.o videomodes.o | |
| 36 | 35 | obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o |
| 37 | 36 | obj-$(CONFIG_VIDEO_IPUV3) += mxc_ipuv3_fb.o ipu_common.o ipu_disp.o |
| 38 | 37 | obj-$(CONFIG_VIDEO_MXS) += mxsfb.o videomodes.o |
drivers/video/mb86r0xgdc.c
| 1 | -/* | |
| 2 | - * (C) Copyright 2010 | |
| 3 | - * Matthias Weisser <weisserm@arcor.de> | |
| 4 | - * | |
| 5 | - * SPDX-License-Identifier: GPL-2.0+ | |
| 6 | - */ | |
| 7 | - | |
| 8 | -/* | |
| 9 | - * mb86r0xgdc.c - Graphic interface for Fujitsu MB86R0x integrated graphic | |
| 10 | - * controller. | |
| 11 | - */ | |
| 12 | - | |
| 13 | -#include <common.h> | |
| 14 | - | |
| 15 | -#include <malloc.h> | |
| 16 | -#include <asm/io.h> | |
| 17 | -#include <asm/arch/hardware.h> | |
| 18 | -#include <video_fb.h> | |
| 19 | -#include "videomodes.h" | |
| 20 | - | |
| 21 | -/* | |
| 22 | - * 4MB (at the end of system RAM) | |
| 23 | - */ | |
| 24 | -#define VIDEO_MEM_SIZE 0x400000 | |
| 25 | - | |
| 26 | -#define FB_SYNC_CLK_INV (1<<16) /* pixel clock inverted */ | |
| 27 | - | |
| 28 | -/* | |
| 29 | - * Graphic Device | |
| 30 | - */ | |
| 31 | -static GraphicDevice mb86r0x; | |
| 32 | - | |
| 33 | -static void dsp_init(struct mb86r0x_gdc_dsp *dsp, char *modestr, | |
| 34 | - u32 *videomem) | |
| 35 | -{ | |
| 36 | - struct ctfb_res_modes var_mode; | |
| 37 | - u32 dcm1, dcm2, dcm3; | |
| 38 | - u16 htp, hdp, hdb, hsp, vtr, vsp, vdp; | |
| 39 | - u8 hsw, vsw; | |
| 40 | - u32 l2m, l2em, l2oa0, l2da0, l2oa1, l2da1; | |
| 41 | - u16 l2dx, l2dy, l2wx, l2wy, l2ww, l2wh; | |
| 42 | - unsigned long div; | |
| 43 | - int bpp; | |
| 44 | - | |
| 45 | - bpp = video_get_params(&var_mode, modestr); | |
| 46 | - | |
| 47 | - if (bpp == 0) { | |
| 48 | - var_mode.xres = 640; | |
| 49 | - var_mode.yres = 480; | |
| 50 | - var_mode.pixclock = 39721; /* 25MHz */ | |
| 51 | - var_mode.left_margin = 48; | |
| 52 | - var_mode.right_margin = 16; | |
| 53 | - var_mode.upper_margin = 33; | |
| 54 | - var_mode.lower_margin = 10; | |
| 55 | - var_mode.hsync_len = 96; | |
| 56 | - var_mode.vsync_len = 2; | |
| 57 | - var_mode.sync = 0; | |
| 58 | - var_mode.vmode = 0; | |
| 59 | - bpp = 15; | |
| 60 | - } | |
| 61 | - | |
| 62 | - /* Fill memory with white */ | |
| 63 | - memset(videomem, 0xFF, var_mode.xres * var_mode.yres * 2); | |
| 64 | - | |
| 65 | - mb86r0x.winSizeX = var_mode.xres; | |
| 66 | - mb86r0x.winSizeY = var_mode.yres; | |
| 67 | - | |
| 68 | - /* LCD base clock is ~ 660MHZ. We do calculations in kHz */ | |
| 69 | - div = 660000 / (1000000000L / var_mode.pixclock); | |
| 70 | - if (div > 64) | |
| 71 | - div = 64; | |
| 72 | - if (0 == div) | |
| 73 | - div = 1; | |
| 74 | - | |
| 75 | - dcm1 = (div - 1) << 8; | |
| 76 | - dcm2 = 0x00000000; | |
| 77 | - if (var_mode.sync & FB_SYNC_CLK_INV) | |
| 78 | - dcm3 = 0x00000100; | |
| 79 | - else | |
| 80 | - dcm3 = 0x00000000; | |
| 81 | - | |
| 82 | - htp = var_mode.left_margin + var_mode.xres + | |
| 83 | - var_mode.hsync_len + var_mode.right_margin; | |
| 84 | - hdp = var_mode.xres; | |
| 85 | - hdb = var_mode.xres; | |
| 86 | - hsp = var_mode.xres + var_mode.right_margin; | |
| 87 | - hsw = var_mode.hsync_len; | |
| 88 | - | |
| 89 | - vsw = var_mode.vsync_len; | |
| 90 | - vtr = var_mode.upper_margin + var_mode.yres + | |
| 91 | - var_mode.vsync_len + var_mode.lower_margin; | |
| 92 | - vsp = var_mode.yres + var_mode.lower_margin; | |
| 93 | - vdp = var_mode.yres; | |
| 94 | - | |
| 95 | - l2m = ((var_mode.yres - 1) << (0)) | | |
| 96 | - (((var_mode.xres * 2) / 64) << (16)) | | |
| 97 | - ((1) << (31)); | |
| 98 | - | |
| 99 | - l2em = (1 << 0) | (1 << 1); | |
| 100 | - | |
| 101 | - l2oa0 = mb86r0x.frameAdrs; | |
| 102 | - l2da0 = mb86r0x.frameAdrs; | |
| 103 | - l2oa1 = mb86r0x.frameAdrs; | |
| 104 | - l2da1 = mb86r0x.frameAdrs; | |
| 105 | - l2dx = 0; | |
| 106 | - l2dy = 0; | |
| 107 | - l2wx = 0; | |
| 108 | - l2wy = 0; | |
| 109 | - l2ww = var_mode.xres; | |
| 110 | - l2wh = var_mode.yres - 1; | |
| 111 | - | |
| 112 | - writel(dcm1, &dsp->dcm1); | |
| 113 | - writel(dcm2, &dsp->dcm2); | |
| 114 | - writel(dcm3, &dsp->dcm3); | |
| 115 | - | |
| 116 | - writew(htp, &dsp->htp); | |
| 117 | - writew(hdp, &dsp->hdp); | |
| 118 | - writew(hdb, &dsp->hdb); | |
| 119 | - writew(hsp, &dsp->hsp); | |
| 120 | - writeb(hsw, &dsp->hsw); | |
| 121 | - | |
| 122 | - writeb(vsw, &dsp->vsw); | |
| 123 | - writew(vtr, &dsp->vtr); | |
| 124 | - writew(vsp, &dsp->vsp); | |
| 125 | - writew(vdp, &dsp->vdp); | |
| 126 | - | |
| 127 | - writel(l2m, &dsp->l2m); | |
| 128 | - writel(l2em, &dsp->l2em); | |
| 129 | - writel(l2oa0, &dsp->l2oa0); | |
| 130 | - writel(l2da0, &dsp->l2da0); | |
| 131 | - writel(l2oa1, &dsp->l2oa1); | |
| 132 | - writel(l2da1, &dsp->l2da1); | |
| 133 | - writew(l2dx, &dsp->l2dx); | |
| 134 | - writew(l2dy, &dsp->l2dy); | |
| 135 | - writew(l2wx, &dsp->l2wx); | |
| 136 | - writew(l2wy, &dsp->l2wy); | |
| 137 | - writew(l2ww, &dsp->l2ww); | |
| 138 | - writew(l2wh, &dsp->l2wh); | |
| 139 | - | |
| 140 | - writel(dcm1 | (1 << 18) | (1 << 31), &dsp->dcm1); | |
| 141 | -} | |
| 142 | - | |
| 143 | -void *video_hw_init(void) | |
| 144 | -{ | |
| 145 | - struct mb86r0x_gdc *gdc = (struct mb86r0x_gdc *) MB86R0x_GDC_BASE; | |
| 146 | - GraphicDevice *pGD = &mb86r0x; | |
| 147 | - char *s; | |
| 148 | - u32 *vid; | |
| 149 | - | |
| 150 | - memset(pGD, 0, sizeof(GraphicDevice)); | |
| 151 | - | |
| 152 | - pGD->gdfIndex = GDF_15BIT_555RGB; | |
| 153 | - pGD->gdfBytesPP = 2; | |
| 154 | - pGD->memSize = VIDEO_MEM_SIZE; | |
| 155 | - pGD->frameAdrs = PHYS_SDRAM + PHYS_SDRAM_SIZE - VIDEO_MEM_SIZE; | |
| 156 | - | |
| 157 | - vid = (u32 *)pGD->frameAdrs; | |
| 158 | - | |
| 159 | - s = getenv("videomode"); | |
| 160 | - if (s != NULL) | |
| 161 | - dsp_init(&gdc->dsp0, s, vid); | |
| 162 | - | |
| 163 | - s = getenv("videomode1"); | |
| 164 | - if (s != NULL) | |
| 165 | - dsp_init(&gdc->dsp1, s, vid); | |
| 166 | - | |
| 167 | - return pGD; | |
| 168 | -} |
include/configs/jadecpu.h
| 1 | -/* | |
| 2 | - * (C) Copyright 2010 | |
| 3 | - * Matthias Weisser <weisserm@arcor.de> | |
| 4 | - * | |
| 5 | - * Configuation settings for the jadecpu board | |
| 6 | - * | |
| 7 | - * SPDX-License-Identifier: GPL-2.0+ | |
| 8 | - */ | |
| 9 | - | |
| 10 | -#ifndef __CONFIG_H | |
| 11 | -#define __CONFIG_H | |
| 12 | - | |
| 13 | -#define CONFIG_MB86R0x | |
| 14 | -#define CONFIG_MB86R0x_IOCLK get_bus_freq(0) | |
| 15 | -#define CONFIG_SYS_TEXT_BASE 0x10000000 | |
| 16 | - | |
| 17 | - | |
| 18 | -#define CONFIG_USE_ARCH_MEMCPY | |
| 19 | -#define CONFIG_USE_ARCH_MEMSET | |
| 20 | - | |
| 21 | -#define MACH_TYPE_JADECPU 2636 | |
| 22 | - | |
| 23 | -#define CONFIG_MACH_TYPE MACH_TYPE_JADECPU | |
| 24 | - | |
| 25 | -/* | |
| 26 | - * Environment settings | |
| 27 | - */ | |
| 28 | -#define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 29 | - "gs_fast_boot=setenv bootdelay 5\0" \ | |
| 30 | - "gs_slow_boot=setenv bootdelay 10\0" \ | |
| 31 | - "bootcmd=dcache off; mw.l 0x40000000 0 1024; usb start;" \ | |
| 32 | - "fatls usb 0; fatload usb 0 0x40000000 jadecpu-init.bin;" \ | |
| 33 | - "bootelf 0x40000000\0" \ | |
| 34 | - "" | |
| 35 | - | |
| 36 | -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ | |
| 37 | -#define CONFIG_SETUP_MEMORY_TAGS 1 | |
| 38 | -#define CONFIG_INITRD_TAG 1 | |
| 39 | -#define CONFIG_BOARD_LATE_INIT | |
| 40 | - | |
| 41 | -/* | |
| 42 | - * Compressions | |
| 43 | - */ | |
| 44 | -#define CONFIG_LZO | |
| 45 | - | |
| 46 | -/* | |
| 47 | - * Hardware drivers | |
| 48 | - */ | |
| 49 | - | |
| 50 | -/* | |
| 51 | - * Serial | |
| 52 | - */ | |
| 53 | -#define CONFIG_SYS_NS16550 | |
| 54 | -#define CONFIG_SYS_NS16550_SERIAL | |
| 55 | -#define CONFIG_SYS_NS16550_REG_SIZE (-4) | |
| 56 | -#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
| 57 | -#define CONFIG_SYS_NS16550_COM1 0xfffe1000 /* UART 0 */ | |
| 58 | -#define CONFIG_SYS_NS16550_COM2 0xfff50000 /* UART 2 */ | |
| 59 | -#define CONFIG_SYS_NS16550_COM3 0xfff51000 /* UART 3 */ | |
| 60 | -#define CONFIG_SYS_NS16550_COM4 0xfff43000 /* UART 4 */ | |
| 61 | - | |
| 62 | -#define CONFIG_CONS_INDEX 4 | |
| 63 | - | |
| 64 | -/* | |
| 65 | - * Ethernet | |
| 66 | - */ | |
| 67 | -#define CONFIG_SMC911X | |
| 68 | -#define CONFIG_SMC911X_BASE 0x02000000 | |
| 69 | -#define CONFIG_SMC911X_16_BIT | |
| 70 | - | |
| 71 | -/* | |
| 72 | - * Video | |
| 73 | - */ | |
| 74 | -#define CONFIG_VIDEO | |
| 75 | -#define CONFIG_VIDEO_MB86R0xGDC | |
| 76 | -#define CONFIG_SYS_WHITE_ON_BLACK | |
| 77 | -#define CONFIG_CFB_CONSOLE | |
| 78 | -#define CONFIG_SYS_CONSOLE_IS_IN_ENV | |
| 79 | -#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE | |
| 80 | -#define CONFIG_VIDEO_LOGO | |
| 81 | -#define CONFIG_SPLASH_SCREEN | |
| 82 | -#define CONFIG_SPLASH_SCREEN_ALIGN | |
| 83 | -#define CONFIG_VIDEO_BMP_LOGO | |
| 84 | -#define CONFIG_VIDEO_BMP_GZIP | |
| 85 | -#define CONFIG_VIDEO_BMP_RLE8 | |
| 86 | -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (800*480 + 256*4 + 10*1024) | |
| 87 | -#define VIDEO_FB_16BPP_WORD_SWAP | |
| 88 | -#define VIDEO_KBD_INIT_FCT 0 | |
| 89 | -#define VIDEO_TSTC_FCT serial_stub_tstc | |
| 90 | -#define VIDEO_GETC_FCT serial_stub_getc | |
| 91 | - | |
| 92 | -/* | |
| 93 | - * BOOTP options | |
| 94 | - */ | |
| 95 | -#define CONFIG_BOOTP_BOOTFILESIZE 1 | |
| 96 | -#define CONFIG_BOOTP_BOOTPATH 1 | |
| 97 | -#define CONFIG_BOOTP_GATEWAY 1 | |
| 98 | -#define CONFIG_BOOTP_HOSTNAME 1 | |
| 99 | - | |
| 100 | -/* | |
| 101 | - * Command line configuration. | |
| 102 | - */ | |
| 103 | -#include <config_cmd_default.h> | |
| 104 | -#undef CONFIG_CMD_BDI | |
| 105 | -#undef CONFIG_CMD_FPGA | |
| 106 | -#undef CONFIG_CMD_IMLS | |
| 107 | -#undef CONFIG_CMD_LOADS | |
| 108 | -#undef CONFIG_CMD_SOURCE | |
| 109 | -#undef CONFIG_CMD_NFS | |
| 110 | -#undef CONFIG_CMD_XIMG | |
| 111 | - | |
| 112 | -#define CONFIG_CMD_BMP | |
| 113 | -#define CONFIG_CMD_DHCP | |
| 114 | -#define CONFIG_CMD_ELF | |
| 115 | -#define CONFIG_CMD_FAT | |
| 116 | -#define CONFIG_CMD_PING | |
| 117 | -#define CONFIG_CMD_USB | |
| 118 | -#define CONFIG_CMD_CACHE | |
| 119 | - | |
| 120 | -#define CONFIG_SYS_HUSH_PARSER | |
| 121 | - | |
| 122 | -/* USB */ | |
| 123 | -#define CONFIG_USB_OHCI_NEW | |
| 124 | -#define CONFIG_SYS_USB_OHCI_REGS_BASE 0xFFF81000 | |
| 125 | -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mb86r0x" | |
| 126 | -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 | |
| 127 | -#define CONFIG_USB_STORAGE | |
| 128 | -#define CONFIG_DOS_PARTITION | |
| 129 | - | |
| 130 | -/* SDRAM */ | |
| 131 | -#define CONFIG_NR_DRAM_BANKS 1 | |
| 132 | -#define PHYS_SDRAM 0x40000000 /* Start address of DDRRAM */ | |
| 133 | -#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */ | |
| 134 | - | |
| 135 | -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM | |
| 136 | -#define CONFIG_SYS_INIT_SP_ADDR 0x01008000 | |
| 137 | - | |
| 138 | -/* | |
| 139 | - * FLASH and environment organization | |
| 140 | - */ | |
| 141 | -#define CONFIG_SYS_FLASH_BASE 0x10000000 | |
| 142 | -#define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
| 143 | -#define CONFIG_SYS_MAX_FLASH_SECT 256 | |
| 144 | -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
| 145 | - | |
| 146 | -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000) | |
| 147 | -#define CONFIG_ENV_IS_IN_FLASH 1 | |
| 148 | -#define CONFIG_ENV_SECT_SIZE (128 * 1024) | |
| 149 | -#define CONFIG_ENV_SIZE (128 * 1024) | |
| 150 | - | |
| 151 | -/* | |
| 152 | - * CFI FLASH driver setup | |
| 153 | - */ | |
| 154 | -#define CONFIG_SYS_FLASH_CFI 1 | |
| 155 | -#define CONFIG_FLASH_CFI_DRIVER 1 | |
| 156 | -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* ~10x faster */ | |
| 157 | - | |
| 158 | -#define CONFIG_SYS_LOAD_ADDR 0x40000000 /* load address */ | |
| 159 | - | |
| 160 | -#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM + (512*1024)) | |
| 161 | -#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM + PHYS_SDRAM_SIZE) | |
| 162 | - | |
| 163 | -#define CONFIG_BAUDRATE 115200 | |
| 164 | - | |
| 165 | -#define CONFIG_SYS_PROMPT "jade> " | |
| 166 | -#define CONFIG_SYS_CBSIZE 256 | |
| 167 | -#define CONFIG_SYS_MAXARGS 16 | |
| 168 | -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
| 169 | - sizeof(CONFIG_SYS_PROMPT) + 16) | |
| 170 | -#define CONFIG_SYS_LONGHELP 1 | |
| 171 | -#define CONFIG_CMDLINE_EDITING 1 | |
| 172 | - | |
| 173 | -#define CONFIG_PREBOOT "" | |
| 174 | - | |
| 175 | -#define CONFIG_BOOTDELAY 5 | |
| 176 | -#define CONFIG_AUTOBOOT_KEYED | |
| 177 | -#define CONFIG_AUTOBOOT_PROMPT "boot in %d s\n", bootdelay | |
| 178 | -#define CONFIG_AUTOBOOT_DELAY_STR "delaygs" | |
| 179 | -#define CONFIG_AUTOBOOT_STOP_STR "stopgs" | |
| 180 | - | |
| 181 | -/* | |
| 182 | - * Size of malloc() pool | |
| 183 | - */ | |
| 184 | -#define CONFIG_SYS_MALLOC_LEN (10 << 20) | |
| 185 | -#define CONFIG_SYS_MEM_TOP_HIDE (4 << 20) | |
| 186 | - | |
| 187 | -/* | |
| 188 | - * Clock reset generator init | |
| 189 | - */ | |
| 190 | -#define CONFIG_SYS_CRG_CRHA_INIT 0xffff | |
| 191 | -#define CONFIG_SYS_CRG_CRPA_INIT 0xffff | |
| 192 | -#define CONFIG_SYS_CRG_CRPB_INIT 0xfffe | |
| 193 | -#define CONFIG_SYS_CRG_CRHB_INIT 0xffff | |
| 194 | -#define CONFIG_SYS_CRG_CRAM_INIT 0xffef | |
| 195 | - | |
| 196 | -/* | |
| 197 | - * Memory controller settings | |
| 198 | - */ | |
| 199 | -#define CONFIG_SYS_MEMC_MCFMODE0_INIT 0x00000001 /* 16bit */ | |
| 200 | -#define CONFIG_SYS_MEMC_MCFMODE2_INIT 0x00000001 /* 16bit */ | |
| 201 | -#define CONFIG_SYS_MEMC_MCFMODE4_INIT 0x00000021 /* 16bit, Page*/ | |
| 202 | -#define CONFIG_SYS_MEMC_MCFTIM0_INIT 0x16191008 | |
| 203 | -#define CONFIG_SYS_MEMC_MCFTIM2_INIT 0x03061008 | |
| 204 | -#define CONFIG_SYS_MEMC_MCFTIM4_INIT 0x03061804 | |
| 205 | -#define CONFIG_SYS_MEMC_MCFAREA0_INIT 0x000000c0 /* 0x0c000000 1MB */ | |
| 206 | -#define CONFIG_SYS_MEMC_MCFAREA2_INIT 0x00000020 /* 0x02000000 1MB */ | |
| 207 | -#define CONFIG_SYS_MEMC_MCFAREA4_INIT 0x001f0000 /* 0x10000000 32 MB */ | |
| 208 | - | |
| 209 | -/* | |
| 210 | - * DDR2 controller init settings | |
| 211 | - */ | |
| 212 | -#define CONFIG_SYS_DDR2_DRIMS_INIT 0x5555 | |
| 213 | -#define CONFIG_SYS_CCNT_CDCRC_INIT_1 0x00000002 | |
| 214 | -#define CONFIG_SYS_CCNT_CDCRC_INIT_2 0x00000003 | |
| 215 | -#define CONFIG_SYS_DDR2_DRIC1_INIT 0x003f | |
| 216 | -#define CONFIG_SYS_DDR2_DRIC2_INIT 0x0000 | |
| 217 | -#define CONFIG_SYS_DDR2_DRCA_INIT 0xc124 /* 512Mbit DDR2SDRAM x 2 */ | |
| 218 | -#define CONFIG_SYS_DDR2_DRCM_INIT 0x0032 | |
| 219 | -#define CONFIG_SYS_DDR2_DRCST1_INIT 0x3418 | |
| 220 | -#define CONFIG_SYS_DDR2_DRCST2_INIT 0x6e32 | |
| 221 | -#define CONFIG_SYS_DDR2_DRCR_INIT 0x0141 | |
| 222 | -#define CONFIG_SYS_DDR2_DRCF_INIT 0x0002 | |
| 223 | -#define CONFIG_SYS_DDR2_DRASR_INIT 0x0001 | |
| 224 | -#define CONFIG_SYS_DDR2_DROBS_INIT 0x0001 | |
| 225 | -#define CONFIG_SYS_DDR2_DROABA_INIT 0x0103 | |
| 226 | -#define CONFIG_SYS_DDR2_DRIBSODT1_INIT 0x003F | |
| 227 | -#define CONFIG_SYS_DDR2_DROS_INIT 0x0001 | |
| 228 | - | |
| 229 | -/* | |
| 230 | - * DRAM init sequence | |
| 231 | - */ | |
| 232 | - | |
| 233 | -/* PALL Command */ | |
| 234 | -#define CONFIG_SYS_DDR2_INIT_DRIC1_1 0x0017 | |
| 235 | -#define CONFIG_SYS_DDR2_INIT_DRIC2_1 0x0400 | |
| 236 | - | |
| 237 | -/* EMR(2) command */ | |
| 238 | -#define CONFIG_SYS_DDR2_INIT_DRIC1_2 0x0006 | |
| 239 | -#define CONFIG_SYS_DDR2_INIT_DRIC2_2 0x0000 | |
| 240 | - | |
| 241 | -/* EMR(3) command */ | |
| 242 | -#define CONFIG_SYS_DDR2_INIT_DRIC1_3 0x0007 | |
| 243 | -#define CONFIG_SYS_DDR2_INIT_DRIC2_3 0x0000 | |
| 244 | - | |
| 245 | -/* EMR(1) command */ | |
| 246 | -#define CONFIG_SYS_DDR2_INIT_DRIC1_4 0x0005 | |
| 247 | -#define CONFIG_SYS_DDR2_INIT_DRIC2_4 0x0000 | |
| 248 | - | |
| 249 | -/* MRS command */ | |
| 250 | -#define CONFIG_SYS_DDR2_INIT_DRIC1_5 0x0004 | |
| 251 | -#define CONFIG_SYS_DDR2_INIT_DRIC2_5 0x0532 | |
| 252 | - | |
| 253 | -/* PALL command */ | |
| 254 | -#define CONFIG_SYS_DDR2_INIT_DRIC1_6 0x0017 | |
| 255 | -#define CONFIG_SYS_DDR2_INIT_DRIC2_6 0x0400 | |
| 256 | - | |
| 257 | -/* REF command 1 */ | |
| 258 | -#define CONFIG_SYS_DDR2_INIT_DRIC1_7 0x000f | |
| 259 | -#define CONFIG_SYS_DDR2_INIT_DRIC2_7 0x0000 | |
| 260 | - | |
| 261 | -/* MRS command */ | |
| 262 | -#define CONFIG_SYS_DDR2_INIT_DRIC1_8 0x0004 | |
| 263 | -#define CONFIG_SYS_DDR2_INIT_DRIC2_8 0x0432 | |
| 264 | - | |
| 265 | -/* EMR(1) command */ | |
| 266 | -#define CONFIG_SYS_DDR2_INIT_DRIC1_9 0x0005 | |
| 267 | -#define CONFIG_SYS_DDR2_INIT_DRIC2_9 0x0380 | |
| 268 | - | |
| 269 | -/* EMR(1) command */ | |
| 270 | -#define CONFIG_SYS_DDR2_INIT_DRIC1_10 0x0005 | |
| 271 | -#define CONFIG_SYS_DDR2_INIT_DRIC2_10 0x0002 | |
| 272 | - | |
| 273 | -#endif /* __CONFIG_H */ |
include/serial.h
| ... | ... | @@ -29,7 +29,7 @@ |
| 29 | 29 | #if defined(CONFIG_405GP) || \ |
| 30 | 30 | defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ |
| 31 | 31 | defined(CONFIG_405EX) || defined(CONFIG_440) || \ |
| 32 | - defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) || \ | |
| 32 | + defined(CONFIG_MPC5xxx) || \ | |
| 33 | 33 | defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) || \ |
| 34 | 34 | defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) || \ |
| 35 | 35 | defined(CONFIG_TEGRA) || defined(CONFIG_SYS_COREBOOT) || \ |