Eric Lee / smarc-uboot

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Commit 423e84bc728b4c73bfbdefacb011be59a83797e0

Authored by Peng Fan
Committed by Stefano Babic
1 parent 995e9fef8f
Exists in smarc_8mq_lf_v2020.04 and in 17 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

imx: cpu: move speed/temp to common cpu 

The i.MX7 cpu speed/temp code could be reused on i.MX8M,
so move them to common cpu code.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>

Showing 2 changed files with 73 additions and 71 deletions Side-by-side Diff

arch/arm/mach-imx/cpu.c
Diff comments   View file @ 423e84b
... ... @@ -333,6 +333,79 @@
333 333 }
334 334 #endif
335 335  
  336 +#if defined(CONFIG_MX7)
  337 +/*
  338 + * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
  339 + * defines a 2-bit SPEED_GRADING
  340 + */
  341 +#define OCOTP_TESTER3_SPEED_SHIFT 8
  342 +#define OCOTP_TESTER3_SPEED_800MHZ 0
  343 +#define OCOTP_TESTER3_SPEED_500MHZ 1
  344 +#define OCOTP_TESTER3_SPEED_1GHZ 2
  345 +#define OCOTP_TESTER3_SPEED_1P2GHZ 3
  346 +
  347 +u32 get_cpu_speed_grade_hz(void)
  348 +{
  349 + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  350 + struct fuse_bank *bank = &ocotp->bank[1];
  351 + struct fuse_bank1_regs *fuse =
  352 + (struct fuse_bank1_regs *)bank->fuse_regs;
  353 + uint32_t val;
  354 +
  355 + val = readl(&fuse->tester3);
  356 + val >>= OCOTP_TESTER3_SPEED_SHIFT;
  357 + val &= 0x3;
  358 +
  359 + switch(val) {
  360 + case OCOTP_TESTER3_SPEED_800MHZ:
  361 + return 800000000;
  362 + case OCOTP_TESTER3_SPEED_500MHZ:
  363 + return 500000000;
  364 + case OCOTP_TESTER3_SPEED_1GHZ:
  365 + return 1000000000;
  366 + case OCOTP_TESTER3_SPEED_1P2GHZ:
  367 + return 1200000000;
  368 + }
  369 + return 0;
  370 +}
  371 +
  372 +/*
  373 + * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
  374 + * defines a 2-bit SPEED_GRADING
  375 + */
  376 +#define OCOTP_TESTER3_TEMP_SHIFT 6
  377 +
  378 +u32 get_cpu_temp_grade(int *minc, int *maxc)
  379 +{
  380 + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
  381 + struct fuse_bank *bank = &ocotp->bank[1];
  382 + struct fuse_bank1_regs *fuse =
  383 + (struct fuse_bank1_regs *)bank->fuse_regs;
  384 + uint32_t val;
  385 +
  386 + val = readl(&fuse->tester3);
  387 + val >>= OCOTP_TESTER3_TEMP_SHIFT;
  388 + val &= 0x3;
  389 +
  390 + if (minc && maxc) {
  391 + if (val == TEMP_AUTOMOTIVE) {
  392 + *minc = -40;
  393 + *maxc = 125;
  394 + } else if (val == TEMP_INDUSTRIAL) {
  395 + *minc = -40;
  396 + *maxc = 105;
  397 + } else if (val == TEMP_EXTCOMMERCIAL) {
  398 + *minc = -20;
  399 + *maxc = 105;
  400 + } else {
  401 + *minc = 0;
  402 + *maxc = 95;
  403 + }
  404 + }
  405 + return val;
  406 +}
  407 +#endif
  408 +
336 409 #ifdef CONFIG_NXP_BOARD_REVISION
337 410 int nxp_board_rev(void)
338 411 {
arch/arm/mach-imx/mx7/soc.c
Diff comments   View file @ 423e84b
... ... @@ -97,77 +97,6 @@
97 97 };
98 98 #endif
99 99  
100   -/*
101   - * OCOTP_TESTER3[9:8] (see Fusemap Description Table offset 0x440)
102   - * defines a 2-bit SPEED_GRADING
103   - */
104   -#define OCOTP_TESTER3_SPEED_SHIFT 8
105   -#define OCOTP_TESTER3_SPEED_800MHZ 0
106   -#define OCOTP_TESTER3_SPEED_500MHZ 1
107   -#define OCOTP_TESTER3_SPEED_1GHZ 2
108   -#define OCOTP_TESTER3_SPEED_1P2GHZ 3
109   -
110   -u32 get_cpu_speed_grade_hz(void)
111   -{
112   - struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
113   - struct fuse_bank *bank = &ocotp->bank[1];
114   - struct fuse_bank1_regs *fuse =
115   - (struct fuse_bank1_regs *)bank->fuse_regs;
116   - uint32_t val;
117   -
118   - val = readl(&fuse->tester3);
119   - val >>= OCOTP_TESTER3_SPEED_SHIFT;
120   - val &= 0x3;
121   -
122   - switch(val) {
123   - case OCOTP_TESTER3_SPEED_800MHZ:
124   - return 800000000;
125   - case OCOTP_TESTER3_SPEED_500MHZ:
126   - return 500000000;
127   - case OCOTP_TESTER3_SPEED_1GHZ:
128   - return 1000000000;
129   - case OCOTP_TESTER3_SPEED_1P2GHZ:
130   - return 1200000000;
131   - }
132   - return 0;
133   -}
134   -
135   -/*
136   - * OCOTP_TESTER3[7:6] (see Fusemap Description Table offset 0x440)
137   - * defines a 2-bit SPEED_GRADING
138   - */
139   -#define OCOTP_TESTER3_TEMP_SHIFT 6
140   -
141   -u32 get_cpu_temp_grade(int *minc, int *maxc)
142   -{
143   - struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
144   - struct fuse_bank *bank = &ocotp->bank[1];
145   - struct fuse_bank1_regs *fuse =
146   - (struct fuse_bank1_regs *)bank->fuse_regs;
147   - uint32_t val;
148   -
149   - val = readl(&fuse->tester3);
150   - val >>= OCOTP_TESTER3_TEMP_SHIFT;
151   - val &= 0x3;
152   -
153   - if (minc && maxc) {
154   - if (val == TEMP_AUTOMOTIVE) {
155   - *minc = -40;
156   - *maxc = 125;
157   - } else if (val == TEMP_INDUSTRIAL) {
158   - *minc = -40;
159   - *maxc = 105;
160   - } else if (val == TEMP_EXTCOMMERCIAL) {
161   - *minc = -20;
162   - *maxc = 105;
163   - } else {
164   - *minc = 0;
165   - *maxc = 95;
166   - }
167   - }
168   - return val;
169   -}
170   -
171 100 static bool is_mx7d(void)
172 101 {
173 102 struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;