rockchip: pinctrl: rk322x: Move the iomux definitions into pinctrl-driver

Clean the iomux definitions at grf_rk322x.h, and move them into pinctrl-driver for resolving the compiling error of redefinition. After that, define the uart2 iomux at rk322x-board file. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

rockchip: pinctrl: rk322x: Move the iomux definitions into pinctrl-driver
Clean the iomux definitions at grf_rk322x.h, and move them into pinctrl-driver for resolving the compiling error of redefinition. After that, define the uart2 iomux at rk322x-board file. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
David Wu · Philipp Tomsich
1 parent c132f38d24
Showing 4 changed files with 492 additions and 456 deletions Side-by-side Diff
arch/arm/include/asm/arch-rockchip/grf_rk322x.h
arch/arm/mach-rockchip/rk322x-board-spl.c
arch/arm/mach-rockchip/rk322x-board.c
drivers/pinctrl/rockchip/pinctrl_rk322x.c
@@ -88,461 +88,6 @@
 	unsigned int busdmac_con[4];
 };
  
-/* GRF_GPIO0A_IOMUX */
-enum {
-	GPIO0A7_SHIFT		= 14,
-	GPIO0A7_MASK		= 3 << GPIO0A7_SHIFT,
-	GPIO0A7_GPIO		= 0,
-	GPIO0A7_I2C3_SDA,
-	GPIO0A7_HDMI_DDCSDA,
-
-	GPIO0A6_SHIFT		= 12,
-	GPIO0A6_MASK		= 3 << GPIO0A6_SHIFT,
-	GPIO0A6_GPIO		= 0,
-	GPIO0A6_I2C3_SCL,
-	GPIO0A6_HDMI_DDCSCL,
-
-	GPIO0A3_SHIFT		= 6,
-	GPIO0A3_MASK		= 3 << GPIO0A3_SHIFT,
-	GPIO0A3_GPIO		= 0,
-	GPIO0A3_I2C1_SDA,
-	GPIO0A3_SDIO_CMD,
-
-	GPIO0A2_SHIFT		= 4,
-	GPIO0A2_MASK		= 3 << GPIO0A2_SHIFT,
-	GPIO0A2_GPIO		= 0,
-	GPIO0A2_I2C1_SCL,
-
-	GPIO0A1_SHIFT		= 2,
-	GPIO0A1_MASK		= 3 << GPIO0A1_SHIFT,
-	GPIO0A1_GPIO		= 0,
-	GPIO0A1_I2C0_SDA,
-
-	GPIO0A0_SHIFT		= 0,
-	GPIO0A0_MASK		= 3 << GPIO0A0_SHIFT,
-	GPIO0A0_GPIO		= 0,
-	GPIO0A0_I2C0_SCL,
-};
-
-/* GRF_GPIO0B_IOMUX */
-enum {
-	GPIO0B7_SHIFT		= 14,
-	GPIO0B7_MASK		= 3 << GPIO0B7_SHIFT,
-	GPIO0B7_GPIO		= 0,
-	GPIO0B7_HDMI_HDP,
-
-	GPIO0B6_SHIFT		= 12,
-	GPIO0B6_MASK		= 3 << GPIO0B6_SHIFT,
-	GPIO0B6_GPIO		= 0,
-	GPIO0B6_I2S_SDI,
-	GPIO0B6_SPI_CSN0,
-
-	GPIO0B5_SHIFT		= 10,
-	GPIO0B5_MASK		= 3 << GPIO0B5_SHIFT,
-	GPIO0B5_GPIO		= 0,
-	GPIO0B5_I2S_SDO,
-	GPIO0B5_SPI_RXD,
-
-	GPIO0B3_SHIFT		= 6,
-	GPIO0B3_MASK		= 3 << GPIO0B3_SHIFT,
-	GPIO0B3_GPIO		= 0,
-	GPIO0B3_I2S1_LRCKRX,
-	GPIO0B3_SPI_TXD,
-
-	GPIO0B1_SHIFT		= 2,
-	GPIO0B1_MASK		= 3 << GPIO0B1_SHIFT,
-	GPIO0B1_GPIO		= 0,
-	GPIO0B1_I2S_SCLK,
-	GPIO0B1_SPI_CLK,
-
-	GPIO0B0_SHIFT		= 0,
-	GPIO0B0_MASK		= 3,
-	GPIO0B0_GPIO		= 0,
-	GPIO0B0_I2S_MCLK,
-};
-
-/* GRF_GPIO0C_IOMUX */
-enum {
-	GPIO0C4_SHIFT		= 8,
-	GPIO0C4_MASK		= 3 << GPIO0C4_SHIFT,
-	GPIO0C4_GPIO		= 0,
-	GPIO0C4_HDMI_CECSDA,
-
-	GPIO0C1_SHIFT		= 2,
-	GPIO0C1_MASK		= 3 << GPIO0C1_SHIFT,
-	GPIO0C1_GPIO		= 0,
-	GPIO0C1_UART0_RSTN,
-	GPIO0C1_CLK_OUT1,
-};
-
-/* GRF_GPIO0D_IOMUX */
-enum {
-	GPIO0D6_SHIFT		= 12,
-	GPIO0D6_MASK		= 3 << GPIO0D6_SHIFT,
-	GPIO0D6_GPIO		= 0,
-	GPIO0D6_SDIO_PWREN,
-	GPIO0D6_PWM11,
-
-
-	GPIO0D4_SHIFT		= 8,
-	GPIO0D4_MASK		= 3 << GPIO0D4_SHIFT,
-	GPIO0D4_GPIO		= 0,
-	GPIO0D4_PWM2,
-
-	GPIO0D3_SHIFT		= 6,
-	GPIO0D3_MASK		= 3 << GPIO0D3_SHIFT,
-	GPIO0D3_GPIO		= 0,
-	GPIO0D3_PWM1,
-
-	GPIO0D2_SHIFT		= 4,
-	GPIO0D2_MASK		= 3 << GPIO0D2_SHIFT,
-	GPIO0D2_GPIO		= 0,
-	GPIO0D2_PWM0,
-};
-
-/* GRF_GPIO1A_IOMUX */
-enum {
-	GPIO1A7_SHIFT		= 14,
-	GPIO1A7_MASK		= 1,
-	GPIO1A7_GPIO		= 0,
-	GPIO1A7_SDMMC_WRPRT,
-};
-
-/* GRF_GPIO1B_IOMUX */
-enum {
-	GPIO1B7_SHIFT		= 14,
-	GPIO1B7_MASK		= 3 << GPIO1B7_SHIFT,
-	GPIO1B7_GPIO		= 0,
-	GPIO1B7_SDMMC_CMD,
-
-	GPIO1B6_SHIFT		= 12,
-	GPIO1B6_MASK		= 3 << GPIO1B6_SHIFT,
-	GPIO1B6_GPIO		= 0,
-	GPIO1B6_SDMMC_PWREN,
-
-	GPIO1B4_SHIFT		= 8,
-	GPIO1B4_MASK		= 3 << GPIO1B4_SHIFT,
-	GPIO1B4_GPIO		= 0,
-	GPIO1B4_SPI_CSN1,
-	GPIO1B4_PWM12,
-
-	GPIO1B3_SHIFT		= 6,
-	GPIO1B3_MASK		= 3 << GPIO1B3_SHIFT,
-	GPIO1B3_GPIO		= 0,
-	GPIO1B3_UART1_RSTN,
-	GPIO1B3_PWM13,
-
-	GPIO1B2_SHIFT		= 4,
-	GPIO1B2_MASK		= 3 << GPIO1B2_SHIFT,
-	GPIO1B2_GPIO		= 0,
-	GPIO1B2_UART1_SIN,
-	GPIO1B2_UART21_SIN,
-
-	GPIO1B1_SHIFT		= 2,
-	GPIO1B1_MASK		= 3 << GPIO1B1_SHIFT,
-	GPIO1B1_GPIO		= 0,
-	GPIO1B1_UART1_SOUT,
-	GPIO1B1_UART21_SOUT,
-};
-
-/* GRF_GPIO1C_IOMUX */
-enum {
-	GPIO1C7_SHIFT		= 14,
-	GPIO1C7_MASK		= 3 << GPIO1C7_SHIFT,
-	GPIO1C7_GPIO		= 0,
-	GPIO1C7_NAND_CS3,
-	GPIO1C7_EMMC_RSTNOUT,
-
-	GPIO1C6_SHIFT		= 12,
-	GPIO1C6_MASK		= 3 << GPIO1C6_SHIFT,
-	GPIO1C6_GPIO		= 0,
-	GPIO1C6_NAND_CS2,
-	GPIO1C6_EMMC_CMD,
-
-
-	GPIO1C5_SHIFT		= 10,
-	GPIO1C5_MASK		= 3 << GPIO1C5_SHIFT,
-	GPIO1C5_GPIO		= 0,
-	GPIO1C5_SDMMC_D3,
-	GPIO1C5_JTAG_TMS,
-
-	GPIO1C4_SHIFT		= 8,
-	GPIO1C4_MASK		= 3 << GPIO1C4_SHIFT,
-	GPIO1C4_GPIO		= 0,
-	GPIO1C4_SDMMC_D2,
-	GPIO1C4_JTAG_TCK,
-
-	GPIO1C3_SHIFT		= 6,
-	GPIO1C3_MASK		= 3 << GPIO1C3_SHIFT,
-	GPIO1C3_GPIO		= 0,
-	GPIO1C3_SDMMC_D1,
-	GPIO1C3_UART2_SIN,
-
-	GPIO1C2_SHIFT		= 4,
-	GPIO1C2_MASK		= 3 << GPIO1C2_SHIFT ,
-	GPIO1C2_GPIO		= 0,
-	GPIO1C2_SDMMC_D0,
-	GPIO1C2_UART2_SOUT,
-
-	GPIO1C1_SHIFT		= 2,
-	GPIO1C1_MASK		= 3 << GPIO1C1_SHIFT,
-	GPIO1C1_GPIO		= 0,
-	GPIO1C1_SDMMC_DETN,
-
-	GPIO1C0_SHIFT		= 0,
-	GPIO1C0_MASK		= 3 << GPIO1C0_SHIFT,
-	GPIO1C0_GPIO		= 0,
-	GPIO1C0_SDMMC_CLKOUT,
-};
-
-/* GRF_GPIO1D_IOMUX */
-enum {
-	GPIO1D7_SHIFT		= 14,
-	GPIO1D7_MASK		= 3 << GPIO1D7_SHIFT,
-	GPIO1D7_GPIO		= 0,
-	GPIO1D7_NAND_D7,
-	GPIO1D7_EMMC_D7,
-
-	GPIO1D6_SHIFT		= 12,
-	GPIO1D6_MASK		= 3 << GPIO1D6_SHIFT,
-	GPIO1D6_GPIO		= 0,
-	GPIO1D6_NAND_D6,
-	GPIO1D6_EMMC_D6,
-
-	GPIO1D5_SHIFT		= 10,
-	GPIO1D5_MASK		= 3 << GPIO1D5_SHIFT,
-	GPIO1D5_GPIO		= 0,
-	GPIO1D5_NAND_D5,
-	GPIO1D5_EMMC_D5,
-
-	GPIO1D4_SHIFT		= 8,
-	GPIO1D4_MASK		= 3 << GPIO1D4_SHIFT,
-	GPIO1D4_GPIO		= 0,
-	GPIO1D4_NAND_D4,
-	GPIO1D4_EMMC_D4,
-
-	GPIO1D3_SHIFT		= 6,
-	GPIO1D3_MASK		= 3 << GPIO1D3_SHIFT,
-	GPIO1D3_GPIO		= 0,
-	GPIO1D3_NAND_D3,
-	GPIO1D3_EMMC_D3,
-
-	GPIO1D2_SHIFT		= 4,
-	GPIO1D2_MASK		= 3 << GPIO1D2_SHIFT,
-	GPIO1D2_GPIO		= 0,
-	GPIO1D2_NAND_D2,
-	GPIO1D2_EMMC_D2,
-
-	GPIO1D1_SHIFT		= 2,
-	GPIO1D1_MASK		= 3 << GPIO1D1_SHIFT,
-	GPIO1D1_GPIO		= 0,
-	GPIO1D1_NAND_D1,
-	GPIO1D1_EMMC_D1,
-
-	GPIO1D0_SHIFT		= 0,
-	GPIO1D0_MASK		= 3 << GPIO1D0_SHIFT,
-	GPIO1D0_GPIO		= 0,
-	GPIO1D0_NAND_D0,
-	GPIO1D0_EMMC_D0,
-};
-
-/* GRF_GPIO2A_IOMUX */
-enum {
-	GPIO2A7_SHIFT		= 14,
-	GPIO2A7_MASK		= 3 << GPIO2A7_SHIFT,
-	GPIO2A7_GPIO		= 0,
-	GPIO2A7_NAND_DQS,
-	GPIO2A7_EMMC_CLKOUT,
-
-	GPIO2A5_SHIFT		= 10,
-	GPIO2A5_MASK		= 3 << GPIO2A5_SHIFT,
-	GPIO2A5_GPIO		= 0,
-	GPIO2A5_NAND_WP,
-	GPIO2A5_EMMC_PWREN,
-
-	GPIO2A4_SHIFT		= 8,
-	GPIO2A4_MASK		= 3 << GPIO2A4_SHIFT,
-	GPIO2A4_GPIO		= 0,
-	GPIO2A4_NAND_RDY,
-	GPIO2A4_EMMC_CMD,
-
-	GPIO2A3_SHIFT		= 6,
-	GPIO2A3_MASK		= 3 << GPIO2A3_SHIFT,
-	GPIO2A3_GPIO		= 0,
-	GPIO2A3_NAND_RDN,
-	GPIO2A4_SPI1_CSN1,
-
-	GPIO2A2_SHIFT		= 4,
-	GPIO2A2_MASK		= 3 << GPIO2A2_SHIFT,
-	GPIO2A2_GPIO		= 0,
-	GPIO2A2_NAND_WRN,
-	GPIO2A4_SPI1_CSN0,
-
-	GPIO2A1_SHIFT		= 2,
-	GPIO2A1_MASK		= 3 << GPIO2A1_SHIFT,
-	GPIO2A1_GPIO		= 0,
-	GPIO2A1_NAND_CLE,
-	GPIO2A1_SPI1_TXD,
-
-	GPIO2A0_SHIFT		= 0,
-	GPIO2A0_MASK		= 3 << GPIO2A0_SHIFT,
-	GPIO2A0_GPIO		= 0,
-	GPIO2A0_NAND_ALE,
-	GPIO2A0_SPI1_RXD,
-};
-
-/* GRF_GPIO2B_IOMUX */
-enum {
-	GPIO2B7_SHIFT		= 14,
-	GPIO2B7_MASK		= 3 << GPIO2B7_SHIFT,
-	GPIO2B7_GPIO		= 0,
-	GPIO2B7_GMAC_RXER,
-
-	GPIO2B6_SHIFT		= 12,
-	GPIO2B6_MASK		= 3 << GPIO2B6_SHIFT,
-	GPIO2B6_GPIO		= 0,
-	GPIO2B6_GMAC_CLK,
-	GPIO2B6_MAC_LINK,
-
-	GPIO2B5_SHIFT		= 10,
-	GPIO2B5_MASK		= 3 << GPIO2B5_SHIFT,
-	GPIO2B5_GPIO		= 0,
-	GPIO2B5_GMAC_TXEN,
-
-	GPIO2B4_SHIFT		= 8,
-	GPIO2B4_MASK		= 3 << GPIO2B4_SHIFT,
-	GPIO2B4_GPIO		= 0,
-	GPIO2B4_GMAC_MDIO,
-
-	GPIO2B3_SHIFT		= 6,
-	GPIO2B3_MASK		= 3 << GPIO2B3_SHIFT,
-	GPIO2B3_GPIO		= 0,
-	GPIO2B3_GMAC_RXCLK,
-
-	GPIO2B2_SHIFT		= 4,
-	GPIO2B2_MASK		= 3 << GPIO2B2_SHIFT,
-	GPIO2B2_GPIO		= 0,
-	GPIO2B2_GMAC_CRS,
-
-	GPIO2B1_SHIFT		= 2,
-	GPIO2B1_MASK		= 3 << GPIO2B1_SHIFT,
-	GPIO2B1_GPIO		= 0,
-	GPIO2B1_GMAC_TXCLK,
-
-
-	GPIO2B0_SHIFT		= 0,
-	GPIO2B0_MASK		= 3 << GPIO2B0_SHIFT,
-	GPIO2B0_GPIO		= 0,
-	GPIO2B0_GMAC_RXDV,
-	GPIO2B0_MAC_SPEED_IOUT,
-};
-
-/* GRF_GPIO2C_IOMUX */
-enum {
-	GPIO2C7_SHIFT		= 14,
-	GPIO2C7_MASK		= 3 << GPIO2C7_SHIFT,
-	GPIO2C7_GPIO		= 0,
-	GPIO2C7_GMAC_TXD3,
-
-	GPIO2C6_SHIFT		= 12,
-	GPIO2C6_MASK		= 3 << GPIO2C6_SHIFT,
-	GPIO2C6_GPIO		= 0,
-	GPIO2C6_GMAC_TXD2,
-
-	GPIO2C5_SHIFT		= 10,
-	GPIO2C5_MASK		= 3 << GPIO2C5_SHIFT,
-	GPIO2C5_GPIO		= 0,
-	GPIO2C5_I2C2_SCL,
-	GPIO2C5_GMAC_RXD2,
-
-	GPIO2C4_SHIFT		= 8,
-	GPIO2C4_MASK		= 3 << GPIO2C4_SHIFT,
-	GPIO2C4_GPIO		= 0,
-	GPIO2C4_I2C2_SDA,
-	GPIO2C4_GMAC_RXD3,
-
-	GPIO2C3_SHIFT		= 6,
-	GPIO2C3_MASK		= 3 << GPIO2C3_SHIFT,
-	GPIO2C3_GPIO		= 0,
-	GPIO2C3_GMAC_TXD0,
-
-	GPIO2C2_SHIFT		= 4,
-	GPIO2C2_MASK		= 3 << GPIO2C2_SHIFT,
-	GPIO2C2_GPIO		= 0,
-	GPIO2C2_GMAC_TXD1,
-
-	GPIO2C1_SHIFT		= 2,
-	GPIO2C1_MASK		= 3 << GPIO2C1_SHIFT,
-	GPIO2C1_GPIO		= 0,
-	GPIO2C1_GMAC_RXD0,
-
-	GPIO2C0_SHIFT		= 0,
-	GPIO2C0_MASK		= 3 << GPIO2C0_SHIFT,
-	GPIO2C0_GPIO		= 0,
-	GPIO2C0_GMAC_RXD1,
-};
-
-/* GRF_GPIO2D_IOMUX */
-enum {
-	GPIO2D1_SHIFT		= 2,
-	GPIO2D1_MASK		= 3 << GPIO2D1_SHIFT,
-	GPIO2D1_GPIO		= 0,
-	GPIO2D1_GMAC_MDC,
-
-	GPIO2D0_SHIFT		= 0,
-	GPIO2D0_MASK		= 3,
-	GPIO2D0_GPIO		= 0,
-	GPIO2D0_GMAC_COL,
-};
-
-/* GRF_GPIO3C_IOMUX */
-enum {
-	GPIO3C6_SHIFT		= 12,
-	GPIO3C6_MASK		= 3 << GPIO3C6_SHIFT,
-	GPIO3C6_GPIO		= 0,
-	GPIO3C6_DRV_VBUS1,
-
-	GPIO3C5_SHIFT		= 10,
-	GPIO3C5_MASK		= 3 << GPIO3C5_SHIFT,
-	GPIO3C5_GPIO		= 0,
-	GPIO3C5_PWM10,
-
-	GPIO3C1_SHIFT		= 2,
-	GPIO3C1_MASK		= 3 << GPIO3C1_SHIFT,
-	GPIO3C1_GPIO		= 0,
-	GPIO3C1_DRV_VBUS,
-};
-
-/* GRF_GPIO3D_IOMUX */
-enum {
-	GPIO3D2_SHIFT	= 4,
-	GPIO3D2_MASK	= 3 << GPIO3D2_SHIFT,
-	GPIO3D2_GPIO	= 0,
-	GPIO3D2_PWM3,
-};
-
-/* GRF_CON_IOMUX */
-enum {
-	CON_IOMUX_GMAC_SHIFT		= 15,
-	CON_IOMUX_GMAC_MASK	= 1 << CON_IOMUX_GMAC_SHIFT,
-	CON_IOMUX_UART1SEL_SHIFT	= 11,
-	CON_IOMUX_UART1SEL_MASK	= 1 << CON_IOMUX_UART1SEL_SHIFT,
-	CON_IOMUX_UART2SEL_SHIFT	= 8,
-	CON_IOMUX_UART2SEL_MASK	= 1 << CON_IOMUX_UART2SEL_SHIFT,
-	CON_IOMUX_UART2SEL_2	= 0,
-	CON_IOMUX_UART2SEL_21,
-	CON_IOMUX_EMMCSEL_SHIFT	= 7,
-	CON_IOMUX_EMMCSEL_MASK	= 1 << CON_IOMUX_EMMCSEL_SHIFT,
-	CON_IOMUX_PWM3SEL_SHIFT	= 3,
-	CON_IOMUX_PWM3SEL_MASK	= 1 << CON_IOMUX_PWM3SEL_SHIFT,
-	CON_IOMUX_PWM2SEL_SHIFT	= 2,
-	CON_IOMUX_PWM2SEL_MASK	= 1 << CON_IOMUX_PWM2SEL_SHIFT,
-	CON_IOMUX_PWM1SEL_SHIFT	= 1,
-	CON_IOMUX_PWM1SEL_MASK	= 1 << CON_IOMUX_PWM1SEL_SHIFT,
-	CON_IOMUX_PWM0SEL_SHIFT	= 0,
-	CON_IOMUX_PWM0SEL_MASK	= 1 << CON_IOMUX_PWM0SEL_SHIFT,
-};
-
 /* GRF_MACPHY_CON0 */
 enum {
 	MACPHY_CFG_ENABLE_SHIFT = 0,
@@ -30,7 +30,27 @@
  
 void board_debug_uart_init(void)
 {
-static struct rk322x_grf * const grf = (void *)GRF_BASE;
+	static struct rk322x_grf * const grf = (void *)GRF_BASE;
+	enum {
+		GPIO1B2_SHIFT		= 4,
+		GPIO1B2_MASK		= 3 << GPIO1B2_SHIFT,
+		GPIO1B2_GPIO            = 0,
+		GPIO1B2_UART1_SIN,
+		GPIO1B2_UART21_SIN,
+
+		GPIO1B1_SHIFT		= 2,
+		GPIO1B1_MASK		= 3 << GPIO1B1_SHIFT,
+		GPIO1B1_GPIO            = 0,
+		GPIO1B1_UART1_SOUT,
+		GPIO1B1_UART21_SOUT,
+	};
+	enum {
+		CON_IOMUX_UART2SEL_SHIFT= 8,
+		CON_IOMUX_UART2SEL_MASK	= 1 << CON_IOMUX_UART2SEL_SHIFT,
+		CON_IOMUX_UART2SEL_2	= 0,
+		CON_IOMUX_UART2SEL_21,
+	};
+
 	/* Enable early UART2 channel 1 on the RK322x */
 	rk_clrsetreg(&grf->gpio1b_iomux,
 		     GPIO1B1_MASK | GPIO1B2_MASK,
@@ -34,6 +34,24 @@
 	/* Enable early UART2 channel 1 on the RK322x */
 #define GRF_BASE	0x11000000
 	struct rk322x_grf * const grf = (void *)GRF_BASE;
+	enum {
+		GPIO1B2_SHIFT		= 4,
+		GPIO1B2_MASK		= 3 << GPIO1B2_SHIFT,
+		GPIO1B2_GPIO		= 0,
+		GPIO1B2_UART21_SIN,
+
+		GPIO1B1_SHIFT		= 2,
+		GPIO1B1_MASK		= 3 << GPIO1B1_SHIFT,
+		GPIO1B1_GPIO            = 0,
+		GPIO1B1_UART1_SOUT,
+		GPIO1B1_UART21_SOUT,
+	};
+	enum {
+		CON_IOMUX_UART2SEL_SHIFT= 8,
+		CON_IOMUX_UART2SEL_MASK	= 1 << CON_IOMUX_UART2SEL_SHIFT,
+		CON_IOMUX_UART2SEL_2	= 0,
+		CON_IOMUX_UART2SEL_21,
+	};
  
 	rk_clrsetreg(&grf->gpio1b_iomux,
 		     GPIO1B1_MASK | GPIO1B2_MASK,
@@ -17,6 +17,459 @@
  
 DECLARE_GLOBAL_DATA_PTR;
  
+/* GRF_GPIO0A_IOMUX */
+enum {
+	GPIO0A7_SHIFT		= 14,
+	GPIO0A7_MASK		= 3 << GPIO0A7_SHIFT,
+	GPIO0A7_GPIO		= 0,
+	GPIO0A7_I2C3_SDA,
+	GPIO0A7_HDMI_DDCSDA,
+
+	GPIO0A6_SHIFT		= 12,
+	GPIO0A6_MASK		= 3 << GPIO0A6_SHIFT,
+	GPIO0A6_GPIO		= 0,
+	GPIO0A6_I2C3_SCL,
+	GPIO0A6_HDMI_DDCSCL,
+
+	GPIO0A3_SHIFT		= 6,
+	GPIO0A3_MASK		= 3 << GPIO0A3_SHIFT,
+	GPIO0A3_GPIO		= 0,
+	GPIO0A3_I2C1_SDA,
+	GPIO0A3_SDIO_CMD,
+
+	GPIO0A2_SHIFT		= 4,
+	GPIO0A2_MASK		= 3 << GPIO0A2_SHIFT,
+	GPIO0A2_GPIO		= 0,
+	GPIO0A2_I2C1_SCL,
+
+	GPIO0A1_SHIFT		= 2,
+	GPIO0A1_MASK		= 3 << GPIO0A1_SHIFT,
+	GPIO0A1_GPIO		= 0,
+	GPIO0A1_I2C0_SDA,
+
+	GPIO0A0_SHIFT		= 0,
+	GPIO0A0_MASK		= 3 << GPIO0A0_SHIFT,
+	GPIO0A0_GPIO		= 0,
+	GPIO0A0_I2C0_SCL,
+};
+
+/* GRF_GPIO0B_IOMUX */
+enum {
+	GPIO0B7_SHIFT		= 14,
+	GPIO0B7_MASK		= 3 << GPIO0B7_SHIFT,
+	GPIO0B7_GPIO		= 0,
+	GPIO0B7_HDMI_HDP,
+
+	GPIO0B6_SHIFT		= 12,
+	GPIO0B6_MASK		= 3 << GPIO0B6_SHIFT,
+	GPIO0B6_GPIO		= 0,
+	GPIO0B6_I2S_SDI,
+	GPIO0B6_SPI_CSN0,
+
+	GPIO0B5_SHIFT		= 10,
+	GPIO0B5_MASK		= 3 << GPIO0B5_SHIFT,
+	GPIO0B5_GPIO		= 0,
+	GPIO0B5_I2S_SDO,
+	GPIO0B5_SPI_RXD,
+
+	GPIO0B3_SHIFT		= 6,
+	GPIO0B3_MASK		= 3 << GPIO0B3_SHIFT,
+	GPIO0B3_GPIO		= 0,
+	GPIO0B3_I2S1_LRCKRX,
+	GPIO0B3_SPI_TXD,
+
+	GPIO0B1_SHIFT		= 2,
+	GPIO0B1_MASK		= 3 << GPIO0B1_SHIFT,
+	GPIO0B1_GPIO		= 0,
+	GPIO0B1_I2S_SCLK,
+	GPIO0B1_SPI_CLK,
+
+	GPIO0B0_SHIFT		= 0,
+	GPIO0B0_MASK		= 3,
+	GPIO0B0_GPIO		= 0,
+	GPIO0B0_I2S_MCLK,
+};
+
+/* GRF_GPIO0C_IOMUX */
+enum {
+	GPIO0C4_SHIFT		= 8,
+	GPIO0C4_MASK		= 3 << GPIO0C4_SHIFT,
+	GPIO0C4_GPIO		= 0,
+	GPIO0C4_HDMI_CECSDA,
+
+	GPIO0C1_SHIFT		= 2,
+	GPIO0C1_MASK		= 3 << GPIO0C1_SHIFT,
+	GPIO0C1_GPIO		= 0,
+	GPIO0C1_UART0_RSTN,
+	GPIO0C1_CLK_OUT1,
+};
+
+/* GRF_GPIO0D_IOMUX */
+enum {
+	GPIO0D6_SHIFT		= 12,
+	GPIO0D6_MASK		= 3 << GPIO0D6_SHIFT,
+	GPIO0D6_GPIO		= 0,
+	GPIO0D6_SDIO_PWREN,
+	GPIO0D6_PWM11,
+
+	GPIO0D4_SHIFT		= 8,
+	GPIO0D4_MASK		= 3 << GPIO0D4_SHIFT,
+	GPIO0D4_GPIO		= 0,
+	GPIO0D4_PWM2,
+
+	GPIO0D3_SHIFT		= 6,
+	GPIO0D3_MASK		= 3 << GPIO0D3_SHIFT,
+	GPIO0D3_GPIO		= 0,
+	GPIO0D3_PWM1,
+
+	GPIO0D2_SHIFT		= 4,
+	GPIO0D2_MASK		= 3 << GPIO0D2_SHIFT,
+	GPIO0D2_GPIO		= 0,
+	GPIO0D2_PWM0,
+};
+
+/* GRF_GPIO1A_IOMUX */
+enum {
+	GPIO1A7_SHIFT		= 14,
+	GPIO1A7_MASK		= 1,
+	GPIO1A7_GPIO		= 0,
+	GPIO1A7_SDMMC_WRPRT,
+};
+
+/* GRF_GPIO1B_IOMUX */
+enum {
+	GPIO1B7_SHIFT		= 14,
+	GPIO1B7_MASK		= 3 << GPIO1B7_SHIFT,
+	GPIO1B7_GPIO		= 0,
+	GPIO1B7_SDMMC_CMD,
+
+	GPIO1B6_SHIFT		= 12,
+	GPIO1B6_MASK		= 3 << GPIO1B6_SHIFT,
+	GPIO1B6_GPIO		= 0,
+	GPIO1B6_SDMMC_PWREN,
+
+	GPIO1B4_SHIFT		= 8,
+	GPIO1B4_MASK		= 3 << GPIO1B4_SHIFT,
+	GPIO1B4_GPIO		= 0,
+	GPIO1B4_SPI_CSN1,
+	GPIO1B4_PWM12,
+
+	GPIO1B3_SHIFT		= 6,
+	GPIO1B3_MASK		= 3 << GPIO1B3_SHIFT,
+	GPIO1B3_GPIO		= 0,
+	GPIO1B3_UART1_RSTN,
+	GPIO1B3_PWM13,
+
+	GPIO1B2_SHIFT		= 4,
+	GPIO1B2_MASK		= 3 << GPIO1B2_SHIFT,
+	GPIO1B2_GPIO		= 0,
+	GPIO1B2_UART1_SIN,
+	GPIO1B2_UART21_SIN,
+
+	GPIO1B1_SHIFT		= 2,
+	GPIO1B1_MASK		= 3 << GPIO1B1_SHIFT,
+	GPIO1B1_GPIO		= 0,
+	GPIO1B1_UART1_SOUT,
+	GPIO1B1_UART21_SOUT,
+};
+
+/* GRF_GPIO1C_IOMUX */
+enum {
+	GPIO1C7_SHIFT		= 14,
+	GPIO1C7_MASK		= 3 << GPIO1C7_SHIFT,
+	GPIO1C7_GPIO		= 0,
+	GPIO1C7_NAND_CS3,
+	GPIO1C7_EMMC_RSTNOUT,
+
+	GPIO1C6_SHIFT		= 12,
+	GPIO1C6_MASK		= 3 << GPIO1C6_SHIFT,
+	GPIO1C6_GPIO		= 0,
+	GPIO1C6_NAND_CS2,
+	GPIO1C6_EMMC_CMD,
+
+	GPIO1C5_SHIFT		= 10,
+	GPIO1C5_MASK		= 3 << GPIO1C5_SHIFT,
+	GPIO1C5_GPIO		= 0,
+	GPIO1C5_SDMMC_D3,
+	GPIO1C5_JTAG_TMS,
+
+	GPIO1C4_SHIFT		= 8,
+	GPIO1C4_MASK		= 3 << GPIO1C4_SHIFT,
+	GPIO1C4_GPIO		= 0,
+	GPIO1C4_SDMMC_D2,
+	GPIO1C4_JTAG_TCK,
+
+	GPIO1C3_SHIFT		= 6,
+	GPIO1C3_MASK		= 3 << GPIO1C3_SHIFT,
+	GPIO1C3_GPIO		= 0,
+	GPIO1C3_SDMMC_D1,
+	GPIO1C3_UART2_SIN,
+
+	GPIO1C2_SHIFT		= 4,
+	GPIO1C2_MASK		= 3 << GPIO1C2_SHIFT,
+	GPIO1C2_GPIO		= 0,
+	GPIO1C2_SDMMC_D0,
+	GPIO1C2_UART2_SOUT,
+
+	GPIO1C1_SHIFT		= 2,
+	GPIO1C1_MASK		= 3 << GPIO1C1_SHIFT,
+	GPIO1C1_GPIO		= 0,
+	GPIO1C1_SDMMC_DETN,
+
+	GPIO1C0_SHIFT		= 0,
+	GPIO1C0_MASK		= 3 << GPIO1C0_SHIFT,
+	GPIO1C0_GPIO		= 0,
+	GPIO1C0_SDMMC_CLKOUT,
+};
+
+/* GRF_GPIO1D_IOMUX */
+enum {
+	GPIO1D7_SHIFT		= 14,
+	GPIO1D7_MASK		= 3 << GPIO1D7_SHIFT,
+	GPIO1D7_GPIO		= 0,
+	GPIO1D7_NAND_D7,
+	GPIO1D7_EMMC_D7,
+
+	GPIO1D6_SHIFT		= 12,
+	GPIO1D6_MASK		= 3 << GPIO1D6_SHIFT,
+	GPIO1D6_GPIO		= 0,
+	GPIO1D6_NAND_D6,
+	GPIO1D6_EMMC_D6,
+
+	GPIO1D5_SHIFT		= 10,
+	GPIO1D5_MASK		= 3 << GPIO1D5_SHIFT,
+	GPIO1D5_GPIO		= 0,
+	GPIO1D5_NAND_D5,
+	GPIO1D5_EMMC_D5,
+
+	GPIO1D4_SHIFT		= 8,
+	GPIO1D4_MASK		= 3 << GPIO1D4_SHIFT,
+	GPIO1D4_GPIO		= 0,
+	GPIO1D4_NAND_D4,
+	GPIO1D4_EMMC_D4,
+
+	GPIO1D3_SHIFT		= 6,
+	GPIO1D3_MASK		= 3 << GPIO1D3_SHIFT,
+	GPIO1D3_GPIO		= 0,
+	GPIO1D3_NAND_D3,
+	GPIO1D3_EMMC_D3,
+
+	GPIO1D2_SHIFT		= 4,
+	GPIO1D2_MASK		= 3 << GPIO1D2_SHIFT,
+	GPIO1D2_GPIO		= 0,
+	GPIO1D2_NAND_D2,
+	GPIO1D2_EMMC_D2,
+
+	GPIO1D1_SHIFT		= 2,
+	GPIO1D1_MASK		= 3 << GPIO1D1_SHIFT,
+	GPIO1D1_GPIO		= 0,
+	GPIO1D1_NAND_D1,
+	GPIO1D1_EMMC_D1,
+
+	GPIO1D0_SHIFT		= 0,
+	GPIO1D0_MASK		= 3 << GPIO1D0_SHIFT,
+	GPIO1D0_GPIO		= 0,
+	GPIO1D0_NAND_D0,
+	GPIO1D0_EMMC_D0,
+};
+
+/* GRF_GPIO2A_IOMUX */
+enum {
+	GPIO2A7_SHIFT		= 14,
+	GPIO2A7_MASK		= 3 << GPIO2A7_SHIFT,
+	GPIO2A7_GPIO		= 0,
+	GPIO2A7_NAND_DQS,
+	GPIO2A7_EMMC_CLKOUT,
+
+	GPIO2A5_SHIFT		= 10,
+	GPIO2A5_MASK		= 3 << GPIO2A5_SHIFT,
+	GPIO2A5_GPIO		= 0,
+	GPIO2A5_NAND_WP,
+	GPIO2A5_EMMC_PWREN,
+
+	GPIO2A4_SHIFT		= 8,
+	GPIO2A4_MASK		= 3 << GPIO2A4_SHIFT,
+	GPIO2A4_GPIO		= 0,
+	GPIO2A4_NAND_RDY,
+	GPIO2A4_EMMC_CMD,
+
+	GPIO2A3_SHIFT		= 6,
+	GPIO2A3_MASK		= 3 << GPIO2A3_SHIFT,
+	GPIO2A3_GPIO		= 0,
+	GPIO2A3_NAND_RDN,
+	GPIO2A4_SPI1_CSN1,
+
+	GPIO2A2_SHIFT		= 4,
+	GPIO2A2_MASK		= 3 << GPIO2A2_SHIFT,
+	GPIO2A2_GPIO		= 0,
+	GPIO2A2_NAND_WRN,
+	GPIO2A4_SPI1_CSN0,
+
+	GPIO2A1_SHIFT		= 2,
+	GPIO2A1_MASK		= 3 << GPIO2A1_SHIFT,
+	GPIO2A1_GPIO		= 0,
+	GPIO2A1_NAND_CLE,
+	GPIO2A1_SPI1_TXD,
+
+	GPIO2A0_SHIFT		= 0,
+	GPIO2A0_MASK		= 3 << GPIO2A0_SHIFT,
+	GPIO2A0_GPIO		= 0,
+	GPIO2A0_NAND_ALE,
+	GPIO2A0_SPI1_RXD,
+};
+
+/* GRF_GPIO2B_IOMUX */
+enum {
+	GPIO2B7_SHIFT		= 14,
+	GPIO2B7_MASK		= 3 << GPIO2B7_SHIFT,
+	GPIO2B7_GPIO		= 0,
+	GPIO2B7_GMAC_RXER,
+
+	GPIO2B6_SHIFT		= 12,
+	GPIO2B6_MASK		= 3 << GPIO2B6_SHIFT,
+	GPIO2B6_GPIO		= 0,
+	GPIO2B6_GMAC_CLK,
+	GPIO2B6_MAC_LINK,
+
+	GPIO2B5_SHIFT		= 10,
+	GPIO2B5_MASK		= 3 << GPIO2B5_SHIFT,
+	GPIO2B5_GPIO		= 0,
+	GPIO2B5_GMAC_TXEN,
+
+	GPIO2B4_SHIFT		= 8,
+	GPIO2B4_MASK		= 3 << GPIO2B4_SHIFT,
+	GPIO2B4_GPIO		= 0,
+	GPIO2B4_GMAC_MDIO,
+
+	GPIO2B3_SHIFT		= 6,
+	GPIO2B3_MASK		= 3 << GPIO2B3_SHIFT,
+	GPIO2B3_GPIO		= 0,
+	GPIO2B3_GMAC_RXCLK,
+
+	GPIO2B2_SHIFT		= 4,
+	GPIO2B2_MASK		= 3 << GPIO2B2_SHIFT,
+	GPIO2B2_GPIO		= 0,
+	GPIO2B2_GMAC_CRS,
+
+	GPIO2B1_SHIFT		= 2,
+	GPIO2B1_MASK		= 3 << GPIO2B1_SHIFT,
+	GPIO2B1_GPIO		= 0,
+	GPIO2B1_GMAC_TXCLK,
+
+	GPIO2B0_SHIFT		= 0,
+	GPIO2B0_MASK		= 3 << GPIO2B0_SHIFT,
+	GPIO2B0_GPIO		= 0,
+	GPIO2B0_GMAC_RXDV,
+	GPIO2B0_MAC_SPEED_IOUT,
+};
+
+/* GRF_GPIO2C_IOMUX */
+enum {
+	GPIO2C7_SHIFT		= 14,
+	GPIO2C7_MASK		= 3 << GPIO2C7_SHIFT,
+	GPIO2C7_GPIO		= 0,
+	GPIO2C7_GMAC_TXD3,
+
+	GPIO2C6_SHIFT		= 12,
+	GPIO2C6_MASK		= 3 << GPIO2C6_SHIFT,
+	GPIO2C6_GPIO		= 0,
+	GPIO2C6_GMAC_TXD2,
+
+	GPIO2C5_SHIFT		= 10,
+	GPIO2C5_MASK		= 3 << GPIO2C5_SHIFT,
+	GPIO2C5_GPIO		= 0,
+	GPIO2C5_I2C2_SCL,
+	GPIO2C5_GMAC_RXD2,
+
+	GPIO2C4_SHIFT		= 8,
+	GPIO2C4_MASK		= 3 << GPIO2C4_SHIFT,
+	GPIO2C4_GPIO		= 0,
+	GPIO2C4_I2C2_SDA,
+	GPIO2C4_GMAC_RXD3,
+
+	GPIO2C3_SHIFT		= 6,
+	GPIO2C3_MASK		= 3 << GPIO2C3_SHIFT,
+	GPIO2C3_GPIO		= 0,
+	GPIO2C3_GMAC_TXD0,
+
+	GPIO2C2_SHIFT		= 4,
+	GPIO2C2_MASK		= 3 << GPIO2C2_SHIFT,
+	GPIO2C2_GPIO		= 0,
+	GPIO2C2_GMAC_TXD1,
+
+	GPIO2C1_SHIFT		= 2,
+	GPIO2C1_MASK		= 3 << GPIO2C1_SHIFT,
+	GPIO2C1_GPIO		= 0,
+	GPIO2C1_GMAC_RXD0,
+
+	GPIO2C0_SHIFT		= 0,
+	GPIO2C0_MASK		= 3 << GPIO2C0_SHIFT,
+	GPIO2C0_GPIO		= 0,
+	GPIO2C0_GMAC_RXD1,
+};
+
+/* GRF_GPIO2D_IOMUX */
+enum {
+	GPIO2D1_SHIFT		= 2,
+	GPIO2D1_MASK		= 3 << GPIO2D1_SHIFT,
+	GPIO2D1_GPIO		= 0,
+	GPIO2D1_GMAC_MDC,
+
+	GPIO2D0_SHIFT		= 0,
+	GPIO2D0_MASK		= 3,
+	GPIO2D0_GPIO		= 0,
+	GPIO2D0_GMAC_COL,
+};
+
+/* GRF_GPIO3C_IOMUX */
+enum {
+	GPIO3C6_SHIFT		= 12,
+	GPIO3C6_MASK		= 3 << GPIO3C6_SHIFT,
+	GPIO3C6_GPIO		= 0,
+	GPIO3C6_DRV_VBUS1,
+
+	GPIO3C5_SHIFT		= 10,
+	GPIO3C5_MASK		= 3 << GPIO3C5_SHIFT,
+	GPIO3C5_GPIO		= 0,
+	GPIO3C5_PWM10,
+
+	GPIO3C1_SHIFT		= 2,
+	GPIO3C1_MASK		= 3 << GPIO3C1_SHIFT,
+	GPIO3C1_GPIO		= 0,
+	GPIO3C1_DRV_VBUS,
+};
+
+/* GRF_GPIO3D_IOMUX */
+enum {
+	GPIO3D2_SHIFT	= 4,
+	GPIO3D2_MASK	= 3 << GPIO3D2_SHIFT,
+	GPIO3D2_GPIO	= 0,
+	GPIO3D2_PWM3,
+};
+
+/* GRF_CON_IOMUX */
+enum {
+	CON_IOMUX_GMACSEL_SHIFT	= 15,
+	CON_IOMUX_GMACSEL_MASK	= 1 << CON_IOMUX_GMACSEL_SHIFT,
+	CON_IOMUX_GMACSEL_1	= 1,
+	CON_IOMUX_UART1SEL_SHIFT	= 11,
+	CON_IOMUX_UART1SEL_MASK	= 1 << CON_IOMUX_UART1SEL_SHIFT,
+	CON_IOMUX_UART2SEL_SHIFT	= 8,
+	CON_IOMUX_UART2SEL_MASK	= 1 << CON_IOMUX_UART2SEL_SHIFT,
+	CON_IOMUX_UART2SEL_2	= 0,
+	CON_IOMUX_UART2SEL_21,
+	CON_IOMUX_EMMCSEL_SHIFT	= 7,
+	CON_IOMUX_EMMCSEL_MASK	= 1 << CON_IOMUX_EMMCSEL_SHIFT,
+	CON_IOMUX_PWM3SEL_SHIFT	= 3,
+	CON_IOMUX_PWM3SEL_MASK	= 1 << CON_IOMUX_PWM3SEL_SHIFT,
+	CON_IOMUX_PWM2SEL_SHIFT	= 2,
+	CON_IOMUX_PWM2SEL_MASK	= 1 << CON_IOMUX_PWM2SEL_SHIFT,
+	CON_IOMUX_PWM1SEL_SHIFT	= 1,
+	CON_IOMUX_PWM1SEL_MASK	= 1 << CON_IOMUX_PWM1SEL_SHIFT,
+	CON_IOMUX_PWM0SEL_SHIFT	= 0,
+	CON_IOMUX_PWM0SEL_MASK	= 1 << CON_IOMUX_PWM0SEL_SHIFT,
+};
+
 struct rk322x_pinctrl_priv {
 	struct rk322x_grf *grf;
 };
...	...	@@ -88,461 +88,6 @@
88	88	unsigned int busdmac_con[4];
89	89	};
90	90
91		-/* GRF_GPIO0A_IOMUX */
92		-enum {
93		- GPIO0A7_SHIFT = 14,
94		- GPIO0A7_MASK = 3 << GPIO0A7_SHIFT,
95		- GPIO0A7_GPIO = 0,
96		- GPIO0A7_I2C3_SDA,
97		- GPIO0A7_HDMI_DDCSDA,
98		-
99		- GPIO0A6_SHIFT = 12,
100		- GPIO0A6_MASK = 3 << GPIO0A6_SHIFT,
101		- GPIO0A6_GPIO = 0,
102		- GPIO0A6_I2C3_SCL,
103		- GPIO0A6_HDMI_DDCSCL,
104		-
105		- GPIO0A3_SHIFT = 6,
106		- GPIO0A3_MASK = 3 << GPIO0A3_SHIFT,
107		- GPIO0A3_GPIO = 0,
108		- GPIO0A3_I2C1_SDA,
109		- GPIO0A3_SDIO_CMD,
110		-
111		- GPIO0A2_SHIFT = 4,
112		- GPIO0A2_MASK = 3 << GPIO0A2_SHIFT,
113		- GPIO0A2_GPIO = 0,
114		- GPIO0A2_I2C1_SCL,
115		-
116		- GPIO0A1_SHIFT = 2,
117		- GPIO0A1_MASK = 3 << GPIO0A1_SHIFT,
118		- GPIO0A1_GPIO = 0,
119		- GPIO0A1_I2C0_SDA,
120		-
121		- GPIO0A0_SHIFT = 0,
122		- GPIO0A0_MASK = 3 << GPIO0A0_SHIFT,
123		- GPIO0A0_GPIO = 0,
124		- GPIO0A0_I2C0_SCL,
125		-};
126		-
127		-/* GRF_GPIO0B_IOMUX */
128		-enum {
129		- GPIO0B7_SHIFT = 14,
130		- GPIO0B7_MASK = 3 << GPIO0B7_SHIFT,
131		- GPIO0B7_GPIO = 0,
132		- GPIO0B7_HDMI_HDP,
133		-
134		- GPIO0B6_SHIFT = 12,
135		- GPIO0B6_MASK = 3 << GPIO0B6_SHIFT,
136		- GPIO0B6_GPIO = 0,
137		- GPIO0B6_I2S_SDI,
138		- GPIO0B6_SPI_CSN0,
139		-
140		- GPIO0B5_SHIFT = 10,
141		- GPIO0B5_MASK = 3 << GPIO0B5_SHIFT,
142		- GPIO0B5_GPIO = 0,
143		- GPIO0B5_I2S_SDO,
144		- GPIO0B5_SPI_RXD,
145		-
146		- GPIO0B3_SHIFT = 6,
147		- GPIO0B3_MASK = 3 << GPIO0B3_SHIFT,
148		- GPIO0B3_GPIO = 0,
149		- GPIO0B3_I2S1_LRCKRX,
150		- GPIO0B3_SPI_TXD,
151		-
152		- GPIO0B1_SHIFT = 2,
153		- GPIO0B1_MASK = 3 << GPIO0B1_SHIFT,
154		- GPIO0B1_GPIO = 0,
155		- GPIO0B1_I2S_SCLK,
156		- GPIO0B1_SPI_CLK,
157		-
158		- GPIO0B0_SHIFT = 0,
159		- GPIO0B0_MASK = 3,
160		- GPIO0B0_GPIO = 0,
161		- GPIO0B0_I2S_MCLK,
162		-};
163		-
164		-/* GRF_GPIO0C_IOMUX */
165		-enum {
166		- GPIO0C4_SHIFT = 8,
167		- GPIO0C4_MASK = 3 << GPIO0C4_SHIFT,
168		- GPIO0C4_GPIO = 0,
169		- GPIO0C4_HDMI_CECSDA,
170		-
171		- GPIO0C1_SHIFT = 2,
172		- GPIO0C1_MASK = 3 << GPIO0C1_SHIFT,
173		- GPIO0C1_GPIO = 0,
174		- GPIO0C1_UART0_RSTN,
175		- GPIO0C1_CLK_OUT1,
176		-};
177		-
178		-/* GRF_GPIO0D_IOMUX */
179		-enum {
180		- GPIO0D6_SHIFT = 12,
181		- GPIO0D6_MASK = 3 << GPIO0D6_SHIFT,
182		- GPIO0D6_GPIO = 0,
183		- GPIO0D6_SDIO_PWREN,
184		- GPIO0D6_PWM11,
185		-
186		-
187		- GPIO0D4_SHIFT = 8,
188		- GPIO0D4_MASK = 3 << GPIO0D4_SHIFT,
189		- GPIO0D4_GPIO = 0,
190		- GPIO0D4_PWM2,
191		-
192		- GPIO0D3_SHIFT = 6,
193		- GPIO0D3_MASK = 3 << GPIO0D3_SHIFT,
194		- GPIO0D3_GPIO = 0,
195		- GPIO0D3_PWM1,
196		-
197		- GPIO0D2_SHIFT = 4,
198		- GPIO0D2_MASK = 3 << GPIO0D2_SHIFT,
199		- GPIO0D2_GPIO = 0,
200		- GPIO0D2_PWM0,
201		-};
202		-
203		-/* GRF_GPIO1A_IOMUX */
204		-enum {
205		- GPIO1A7_SHIFT = 14,
206		- GPIO1A7_MASK = 1,
207		- GPIO1A7_GPIO = 0,
208		- GPIO1A7_SDMMC_WRPRT,
209		-};
210		-
211		-/* GRF_GPIO1B_IOMUX */
212		-enum {
213		- GPIO1B7_SHIFT = 14,
214		- GPIO1B7_MASK = 3 << GPIO1B7_SHIFT,
215		- GPIO1B7_GPIO = 0,
216		- GPIO1B7_SDMMC_CMD,
217		-
218		- GPIO1B6_SHIFT = 12,
219		- GPIO1B6_MASK = 3 << GPIO1B6_SHIFT,
220		- GPIO1B6_GPIO = 0,
221		- GPIO1B6_SDMMC_PWREN,
222		-
223		- GPIO1B4_SHIFT = 8,
224		- GPIO1B4_MASK = 3 << GPIO1B4_SHIFT,
225		- GPIO1B4_GPIO = 0,
226		- GPIO1B4_SPI_CSN1,
227		- GPIO1B4_PWM12,
228		-
229		- GPIO1B3_SHIFT = 6,
230		- GPIO1B3_MASK = 3 << GPIO1B3_SHIFT,
231		- GPIO1B3_GPIO = 0,
232		- GPIO1B3_UART1_RSTN,
233		- GPIO1B3_PWM13,
234		-
235		- GPIO1B2_SHIFT = 4,
236		- GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
237		- GPIO1B2_GPIO = 0,
238		- GPIO1B2_UART1_SIN,
239		- GPIO1B2_UART21_SIN,
240		-
241		- GPIO1B1_SHIFT = 2,
242		- GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
243		- GPIO1B1_GPIO = 0,
244		- GPIO1B1_UART1_SOUT,
245		- GPIO1B1_UART21_SOUT,
246		-};
247		-
248		-/* GRF_GPIO1C_IOMUX */
249		-enum {
250		- GPIO1C7_SHIFT = 14,
251		- GPIO1C7_MASK = 3 << GPIO1C7_SHIFT,
252		- GPIO1C7_GPIO = 0,
253		- GPIO1C7_NAND_CS3,
254		- GPIO1C7_EMMC_RSTNOUT,
255		-
256		- GPIO1C6_SHIFT = 12,
257		- GPIO1C6_MASK = 3 << GPIO1C6_SHIFT,
258		- GPIO1C6_GPIO = 0,
259		- GPIO1C6_NAND_CS2,
260		- GPIO1C6_EMMC_CMD,
261		-
262		-
263		- GPIO1C5_SHIFT = 10,
264		- GPIO1C5_MASK = 3 << GPIO1C5_SHIFT,
265		- GPIO1C5_GPIO = 0,
266		- GPIO1C5_SDMMC_D3,
267		- GPIO1C5_JTAG_TMS,
268		-
269		- GPIO1C4_SHIFT = 8,
270		- GPIO1C4_MASK = 3 << GPIO1C4_SHIFT,
271		- GPIO1C4_GPIO = 0,
272		- GPIO1C4_SDMMC_D2,
273		- GPIO1C4_JTAG_TCK,
274		-
275		- GPIO1C3_SHIFT = 6,
276		- GPIO1C3_MASK = 3 << GPIO1C3_SHIFT,
277		- GPIO1C3_GPIO = 0,
278		- GPIO1C3_SDMMC_D1,
279		- GPIO1C3_UART2_SIN,
280		-
281		- GPIO1C2_SHIFT = 4,
282		- GPIO1C2_MASK = 3 << GPIO1C2_SHIFT ,
283		- GPIO1C2_GPIO = 0,
284		- GPIO1C2_SDMMC_D0,
285		- GPIO1C2_UART2_SOUT,
286		-
287		- GPIO1C1_SHIFT = 2,
288		- GPIO1C1_MASK = 3 << GPIO1C1_SHIFT,
289		- GPIO1C1_GPIO = 0,
290		- GPIO1C1_SDMMC_DETN,
291		-
292		- GPIO1C0_SHIFT = 0,
293		- GPIO1C0_MASK = 3 << GPIO1C0_SHIFT,
294		- GPIO1C0_GPIO = 0,
295		- GPIO1C0_SDMMC_CLKOUT,
296		-};
297		-
298		-/* GRF_GPIO1D_IOMUX */
299		-enum {
300		- GPIO1D7_SHIFT = 14,
301		- GPIO1D7_MASK = 3 << GPIO1D7_SHIFT,
302		- GPIO1D7_GPIO = 0,
303		- GPIO1D7_NAND_D7,
304		- GPIO1D7_EMMC_D7,
305		-
306		- GPIO1D6_SHIFT = 12,
307		- GPIO1D6_MASK = 3 << GPIO1D6_SHIFT,
308		- GPIO1D6_GPIO = 0,
309		- GPIO1D6_NAND_D6,
310		- GPIO1D6_EMMC_D6,
311		-
312		- GPIO1D5_SHIFT = 10,
313		- GPIO1D5_MASK = 3 << GPIO1D5_SHIFT,
314		- GPIO1D5_GPIO = 0,
315		- GPIO1D5_NAND_D5,
316		- GPIO1D5_EMMC_D5,
317		-
318		- GPIO1D4_SHIFT = 8,
319		- GPIO1D4_MASK = 3 << GPIO1D4_SHIFT,
320		- GPIO1D4_GPIO = 0,
321		- GPIO1D4_NAND_D4,
322		- GPIO1D4_EMMC_D4,
323		-
324		- GPIO1D3_SHIFT = 6,
325		- GPIO1D3_MASK = 3 << GPIO1D3_SHIFT,
326		- GPIO1D3_GPIO = 0,
327		- GPIO1D3_NAND_D3,
328		- GPIO1D3_EMMC_D3,
329		-
330		- GPIO1D2_SHIFT = 4,
331		- GPIO1D2_MASK = 3 << GPIO1D2_SHIFT,
332		- GPIO1D2_GPIO = 0,
333		- GPIO1D2_NAND_D2,
334		- GPIO1D2_EMMC_D2,
335		-
336		- GPIO1D1_SHIFT = 2,
337		- GPIO1D1_MASK = 3 << GPIO1D1_SHIFT,
338		- GPIO1D1_GPIO = 0,
339		- GPIO1D1_NAND_D1,
340		- GPIO1D1_EMMC_D1,
341		-
342		- GPIO1D0_SHIFT = 0,
343		- GPIO1D0_MASK = 3 << GPIO1D0_SHIFT,
344		- GPIO1D0_GPIO = 0,
345		- GPIO1D0_NAND_D0,
346		- GPIO1D0_EMMC_D0,
347		-};
348		-
349		-/* GRF_GPIO2A_IOMUX */
350		-enum {
351		- GPIO2A7_SHIFT = 14,
352		- GPIO2A7_MASK = 3 << GPIO2A7_SHIFT,
353		- GPIO2A7_GPIO = 0,
354		- GPIO2A7_NAND_DQS,
355		- GPIO2A7_EMMC_CLKOUT,
356		-
357		- GPIO2A5_SHIFT = 10,
358		- GPIO2A5_MASK = 3 << GPIO2A5_SHIFT,
359		- GPIO2A5_GPIO = 0,
360		- GPIO2A5_NAND_WP,
361		- GPIO2A5_EMMC_PWREN,
362		-
363		- GPIO2A4_SHIFT = 8,
364		- GPIO2A4_MASK = 3 << GPIO2A4_SHIFT,
365		- GPIO2A4_GPIO = 0,
366		- GPIO2A4_NAND_RDY,
367		- GPIO2A4_EMMC_CMD,
368		-
369		- GPIO2A3_SHIFT = 6,
370		- GPIO2A3_MASK = 3 << GPIO2A3_SHIFT,
371		- GPIO2A3_GPIO = 0,
372		- GPIO2A3_NAND_RDN,
373		- GPIO2A4_SPI1_CSN1,
374		-
375		- GPIO2A2_SHIFT = 4,
376		- GPIO2A2_MASK = 3 << GPIO2A2_SHIFT,
377		- GPIO2A2_GPIO = 0,
378		- GPIO2A2_NAND_WRN,
379		- GPIO2A4_SPI1_CSN0,
380		-
381		- GPIO2A1_SHIFT = 2,
382		- GPIO2A1_MASK = 3 << GPIO2A1_SHIFT,
383		- GPIO2A1_GPIO = 0,
384		- GPIO2A1_NAND_CLE,
385		- GPIO2A1_SPI1_TXD,
386		-
387		- GPIO2A0_SHIFT = 0,
388		- GPIO2A0_MASK = 3 << GPIO2A0_SHIFT,
389		- GPIO2A0_GPIO = 0,
390		- GPIO2A0_NAND_ALE,
391		- GPIO2A0_SPI1_RXD,
392		-};
393		-
394		-/* GRF_GPIO2B_IOMUX */
395		-enum {
396		- GPIO2B7_SHIFT = 14,
397		- GPIO2B7_MASK = 3 << GPIO2B7_SHIFT,
398		- GPIO2B7_GPIO = 0,
399		- GPIO2B7_GMAC_RXER,
400		-
401		- GPIO2B6_SHIFT = 12,
402		- GPIO2B6_MASK = 3 << GPIO2B6_SHIFT,
403		- GPIO2B6_GPIO = 0,
404		- GPIO2B6_GMAC_CLK,
405		- GPIO2B6_MAC_LINK,
406		-
407		- GPIO2B5_SHIFT = 10,
408		- GPIO2B5_MASK = 3 << GPIO2B5_SHIFT,
409		- GPIO2B5_GPIO = 0,
410		- GPIO2B5_GMAC_TXEN,
411		-
412		- GPIO2B4_SHIFT = 8,
413		- GPIO2B4_MASK = 3 << GPIO2B4_SHIFT,
414		- GPIO2B4_GPIO = 0,
415		- GPIO2B4_GMAC_MDIO,
416		-
417		- GPIO2B3_SHIFT = 6,
418		- GPIO2B3_MASK = 3 << GPIO2B3_SHIFT,
419		- GPIO2B3_GPIO = 0,
420		- GPIO2B3_GMAC_RXCLK,
421		-
422		- GPIO2B2_SHIFT = 4,
423		- GPIO2B2_MASK = 3 << GPIO2B2_SHIFT,
424		- GPIO2B2_GPIO = 0,
425		- GPIO2B2_GMAC_CRS,
426		-
427		- GPIO2B1_SHIFT = 2,
428		- GPIO2B1_MASK = 3 << GPIO2B1_SHIFT,
429		- GPIO2B1_GPIO = 0,
430		- GPIO2B1_GMAC_TXCLK,
431		-
432		-
433		- GPIO2B0_SHIFT = 0,
434		- GPIO2B0_MASK = 3 << GPIO2B0_SHIFT,
435		- GPIO2B0_GPIO = 0,
436		- GPIO2B0_GMAC_RXDV,
437		- GPIO2B0_MAC_SPEED_IOUT,
438		-};
439		-
440		-/* GRF_GPIO2C_IOMUX */
441		-enum {
442		- GPIO2C7_SHIFT = 14,
443		- GPIO2C7_MASK = 3 << GPIO2C7_SHIFT,
444		- GPIO2C7_GPIO = 0,
445		- GPIO2C7_GMAC_TXD3,
446		-
447		- GPIO2C6_SHIFT = 12,
448		- GPIO2C6_MASK = 3 << GPIO2C6_SHIFT,
449		- GPIO2C6_GPIO = 0,
450		- GPIO2C6_GMAC_TXD2,
451		-
452		- GPIO2C5_SHIFT = 10,
453		- GPIO2C5_MASK = 3 << GPIO2C5_SHIFT,
454		- GPIO2C5_GPIO = 0,
455		- GPIO2C5_I2C2_SCL,
456		- GPIO2C5_GMAC_RXD2,
457		-
458		- GPIO2C4_SHIFT = 8,
459		- GPIO2C4_MASK = 3 << GPIO2C4_SHIFT,
460		- GPIO2C4_GPIO = 0,
461		- GPIO2C4_I2C2_SDA,
462		- GPIO2C4_GMAC_RXD3,
463		-
464		- GPIO2C3_SHIFT = 6,
465		- GPIO2C3_MASK = 3 << GPIO2C3_SHIFT,
466		- GPIO2C3_GPIO = 0,
467		- GPIO2C3_GMAC_TXD0,
468		-
469		- GPIO2C2_SHIFT = 4,
470		- GPIO2C2_MASK = 3 << GPIO2C2_SHIFT,
471		- GPIO2C2_GPIO = 0,
472		- GPIO2C2_GMAC_TXD1,
473		-
474		- GPIO2C1_SHIFT = 2,
475		- GPIO2C1_MASK = 3 << GPIO2C1_SHIFT,
476		- GPIO2C1_GPIO = 0,
477		- GPIO2C1_GMAC_RXD0,
478		-
479		- GPIO2C0_SHIFT = 0,
480		- GPIO2C0_MASK = 3 << GPIO2C0_SHIFT,
481		- GPIO2C0_GPIO = 0,
482		- GPIO2C0_GMAC_RXD1,
483		-};
484		-
485		-/* GRF_GPIO2D_IOMUX */
486		-enum {
487		- GPIO2D1_SHIFT = 2,
488		- GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
489		- GPIO2D1_GPIO = 0,
490		- GPIO2D1_GMAC_MDC,
491		-
492		- GPIO2D0_SHIFT = 0,
493		- GPIO2D0_MASK = 3,
494		- GPIO2D0_GPIO = 0,
495		- GPIO2D0_GMAC_COL,
496		-};
497		-
498		-/* GRF_GPIO3C_IOMUX */
499		-enum {
500		- GPIO3C6_SHIFT = 12,
501		- GPIO3C6_MASK = 3 << GPIO3C6_SHIFT,
502		- GPIO3C6_GPIO = 0,
503		- GPIO3C6_DRV_VBUS1,
504		-
505		- GPIO3C5_SHIFT = 10,
506		- GPIO3C5_MASK = 3 << GPIO3C5_SHIFT,
507		- GPIO3C5_GPIO = 0,
508		- GPIO3C5_PWM10,
509		-
510		- GPIO3C1_SHIFT = 2,
511		- GPIO3C1_MASK = 3 << GPIO3C1_SHIFT,
512		- GPIO3C1_GPIO = 0,
513		- GPIO3C1_DRV_VBUS,
514		-};
515		-
516		-/* GRF_GPIO3D_IOMUX */
517		-enum {
518		- GPIO3D2_SHIFT = 4,
519		- GPIO3D2_MASK = 3 << GPIO3D2_SHIFT,
520		- GPIO3D2_GPIO = 0,
521		- GPIO3D2_PWM3,
522		-};
523		-
524		-/* GRF_CON_IOMUX */
525		-enum {
526		- CON_IOMUX_GMAC_SHIFT = 15,
527		- CON_IOMUX_GMAC_MASK = 1 << CON_IOMUX_GMAC_SHIFT,
528		- CON_IOMUX_UART1SEL_SHIFT = 11,
529		- CON_IOMUX_UART1SEL_MASK = 1 << CON_IOMUX_UART1SEL_SHIFT,
530		- CON_IOMUX_UART2SEL_SHIFT = 8,
531		- CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
532		- CON_IOMUX_UART2SEL_2 = 0,
533		- CON_IOMUX_UART2SEL_21,
534		- CON_IOMUX_EMMCSEL_SHIFT = 7,
535		- CON_IOMUX_EMMCSEL_MASK = 1 << CON_IOMUX_EMMCSEL_SHIFT,
536		- CON_IOMUX_PWM3SEL_SHIFT = 3,
537		- CON_IOMUX_PWM3SEL_MASK = 1 << CON_IOMUX_PWM3SEL_SHIFT,
538		- CON_IOMUX_PWM2SEL_SHIFT = 2,
539		- CON_IOMUX_PWM2SEL_MASK = 1 << CON_IOMUX_PWM2SEL_SHIFT,
540		- CON_IOMUX_PWM1SEL_SHIFT = 1,
541		- CON_IOMUX_PWM1SEL_MASK = 1 << CON_IOMUX_PWM1SEL_SHIFT,
542		- CON_IOMUX_PWM0SEL_SHIFT = 0,
543		- CON_IOMUX_PWM0SEL_MASK = 1 << CON_IOMUX_PWM0SEL_SHIFT,
544		-};
545		-
546	91	/* GRF_MACPHY_CON0 */
547	92	enum {
548	93	MACPHY_CFG_ENABLE_SHIFT = 0,
...	...	@@ -30,7 +30,27 @@
30	30
31	31	void board_debug_uart_init(void)
32	32	{
33		-static struct rk322x_grf * const grf = (void *)GRF_BASE;
	33	+ static struct rk322x_grf * const grf = (void *)GRF_BASE;
	34	+ enum {
	35	+ GPIO1B2_SHIFT = 4,
	36	+ GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
	37	+ GPIO1B2_GPIO = 0,
	38	+ GPIO1B2_UART1_SIN,
	39	+ GPIO1B2_UART21_SIN,
	40	+
	41	+ GPIO1B1_SHIFT = 2,
	42	+ GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
	43	+ GPIO1B1_GPIO = 0,
	44	+ GPIO1B1_UART1_SOUT,
	45	+ GPIO1B1_UART21_SOUT,
	46	+ };
	47	+ enum {
	48	+ CON_IOMUX_UART2SEL_SHIFT= 8,
	49	+ CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
	50	+ CON_IOMUX_UART2SEL_2 = 0,
	51	+ CON_IOMUX_UART2SEL_21,
	52	+ };
	53	+
34	54	/* Enable early UART2 channel 1 on the RK322x */
35	55	rk_clrsetreg(&grf->gpio1b_iomux,
36	56	GPIO1B1_MASK \| GPIO1B2_MASK,
...	...	@@ -34,6 +34,24 @@
34	34	/* Enable early UART2 channel 1 on the RK322x */
35	35	#define GRF_BASE 0x11000000
36	36	struct rk322x_grf * const grf = (void *)GRF_BASE;
	37	+ enum {
	38	+ GPIO1B2_SHIFT = 4,
	39	+ GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
	40	+ GPIO1B2_GPIO = 0,
	41	+ GPIO1B2_UART21_SIN,
	42	+
	43	+ GPIO1B1_SHIFT = 2,
	44	+ GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
	45	+ GPIO1B1_GPIO = 0,
	46	+ GPIO1B1_UART1_SOUT,
	47	+ GPIO1B1_UART21_SOUT,
	48	+ };
	49	+ enum {
	50	+ CON_IOMUX_UART2SEL_SHIFT= 8,
	51	+ CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
	52	+ CON_IOMUX_UART2SEL_2 = 0,
	53	+ CON_IOMUX_UART2SEL_21,
	54	+ };
37	55
38	56	rk_clrsetreg(&grf->gpio1b_iomux,
39	57	GPIO1B1_MASK \| GPIO1B2_MASK,
...	...	@@ -17,6 +17,459 @@
17	17
18	18	DECLARE_GLOBAL_DATA_PTR;
19	19
	20	+/* GRF_GPIO0A_IOMUX */
	21	+enum {
	22	+ GPIO0A7_SHIFT = 14,
	23	+ GPIO0A7_MASK = 3 << GPIO0A7_SHIFT,
	24	+ GPIO0A7_GPIO = 0,
	25	+ GPIO0A7_I2C3_SDA,
	26	+ GPIO0A7_HDMI_DDCSDA,
	27	+
	28	+ GPIO0A6_SHIFT = 12,
	29	+ GPIO0A6_MASK = 3 << GPIO0A6_SHIFT,
	30	+ GPIO0A6_GPIO = 0,
	31	+ GPIO0A6_I2C3_SCL,
	32	+ GPIO0A6_HDMI_DDCSCL,
	33	+
	34	+ GPIO0A3_SHIFT = 6,
	35	+ GPIO0A3_MASK = 3 << GPIO0A3_SHIFT,
	36	+ GPIO0A3_GPIO = 0,
	37	+ GPIO0A3_I2C1_SDA,
	38	+ GPIO0A3_SDIO_CMD,
	39	+
	40	+ GPIO0A2_SHIFT = 4,
	41	+ GPIO0A2_MASK = 3 << GPIO0A2_SHIFT,
	42	+ GPIO0A2_GPIO = 0,
	43	+ GPIO0A2_I2C1_SCL,
	44	+
	45	+ GPIO0A1_SHIFT = 2,
	46	+ GPIO0A1_MASK = 3 << GPIO0A1_SHIFT,
	47	+ GPIO0A1_GPIO = 0,
	48	+ GPIO0A1_I2C0_SDA,
	49	+
	50	+ GPIO0A0_SHIFT = 0,
	51	+ GPIO0A0_MASK = 3 << GPIO0A0_SHIFT,
	52	+ GPIO0A0_GPIO = 0,
	53	+ GPIO0A0_I2C0_SCL,
	54	+};
	55	+
	56	+/* GRF_GPIO0B_IOMUX */
	57	+enum {
	58	+ GPIO0B7_SHIFT = 14,
	59	+ GPIO0B7_MASK = 3 << GPIO0B7_SHIFT,
	60	+ GPIO0B7_GPIO = 0,
	61	+ GPIO0B7_HDMI_HDP,
	62	+
	63	+ GPIO0B6_SHIFT = 12,
	64	+ GPIO0B6_MASK = 3 << GPIO0B6_SHIFT,
	65	+ GPIO0B6_GPIO = 0,
	66	+ GPIO0B6_I2S_SDI,
	67	+ GPIO0B6_SPI_CSN0,
	68	+
	69	+ GPIO0B5_SHIFT = 10,
	70	+ GPIO0B5_MASK = 3 << GPIO0B5_SHIFT,
	71	+ GPIO0B5_GPIO = 0,
	72	+ GPIO0B5_I2S_SDO,
	73	+ GPIO0B5_SPI_RXD,
	74	+
	75	+ GPIO0B3_SHIFT = 6,
	76	+ GPIO0B3_MASK = 3 << GPIO0B3_SHIFT,
	77	+ GPIO0B3_GPIO = 0,
	78	+ GPIO0B3_I2S1_LRCKRX,
	79	+ GPIO0B3_SPI_TXD,
	80	+
	81	+ GPIO0B1_SHIFT = 2,
	82	+ GPIO0B1_MASK = 3 << GPIO0B1_SHIFT,
	83	+ GPIO0B1_GPIO = 0,
	84	+ GPIO0B1_I2S_SCLK,
	85	+ GPIO0B1_SPI_CLK,
	86	+
	87	+ GPIO0B0_SHIFT = 0,
	88	+ GPIO0B0_MASK = 3,
	89	+ GPIO0B0_GPIO = 0,
	90	+ GPIO0B0_I2S_MCLK,
	91	+};
	92	+
	93	+/* GRF_GPIO0C_IOMUX */
	94	+enum {
	95	+ GPIO0C4_SHIFT = 8,
	96	+ GPIO0C4_MASK = 3 << GPIO0C4_SHIFT,
	97	+ GPIO0C4_GPIO = 0,
	98	+ GPIO0C4_HDMI_CECSDA,
	99	+
	100	+ GPIO0C1_SHIFT = 2,
	101	+ GPIO0C1_MASK = 3 << GPIO0C1_SHIFT,
	102	+ GPIO0C1_GPIO = 0,
	103	+ GPIO0C1_UART0_RSTN,
	104	+ GPIO0C1_CLK_OUT1,
	105	+};
	106	+
	107	+/* GRF_GPIO0D_IOMUX */
	108	+enum {
	109	+ GPIO0D6_SHIFT = 12,
	110	+ GPIO0D6_MASK = 3 << GPIO0D6_SHIFT,
	111	+ GPIO0D6_GPIO = 0,
	112	+ GPIO0D6_SDIO_PWREN,
	113	+ GPIO0D6_PWM11,
	114	+
	115	+ GPIO0D4_SHIFT = 8,
	116	+ GPIO0D4_MASK = 3 << GPIO0D4_SHIFT,
	117	+ GPIO0D4_GPIO = 0,
	118	+ GPIO0D4_PWM2,
	119	+
	120	+ GPIO0D3_SHIFT = 6,
	121	+ GPIO0D3_MASK = 3 << GPIO0D3_SHIFT,
	122	+ GPIO0D3_GPIO = 0,
	123	+ GPIO0D3_PWM1,
	124	+
	125	+ GPIO0D2_SHIFT = 4,
	126	+ GPIO0D2_MASK = 3 << GPIO0D2_SHIFT,
	127	+ GPIO0D2_GPIO = 0,
	128	+ GPIO0D2_PWM0,
	129	+};
	130	+
	131	+/* GRF_GPIO1A_IOMUX */
	132	+enum {
	133	+ GPIO1A7_SHIFT = 14,
	134	+ GPIO1A7_MASK = 1,
	135	+ GPIO1A7_GPIO = 0,
	136	+ GPIO1A7_SDMMC_WRPRT,
	137	+};
	138	+
	139	+/* GRF_GPIO1B_IOMUX */
	140	+enum {
	141	+ GPIO1B7_SHIFT = 14,
	142	+ GPIO1B7_MASK = 3 << GPIO1B7_SHIFT,
	143	+ GPIO1B7_GPIO = 0,
	144	+ GPIO1B7_SDMMC_CMD,
	145	+
	146	+ GPIO1B6_SHIFT = 12,
	147	+ GPIO1B6_MASK = 3 << GPIO1B6_SHIFT,
	148	+ GPIO1B6_GPIO = 0,
	149	+ GPIO1B6_SDMMC_PWREN,
	150	+
	151	+ GPIO1B4_SHIFT = 8,
	152	+ GPIO1B4_MASK = 3 << GPIO1B4_SHIFT,
	153	+ GPIO1B4_GPIO = 0,
	154	+ GPIO1B4_SPI_CSN1,
	155	+ GPIO1B4_PWM12,
	156	+
	157	+ GPIO1B3_SHIFT = 6,
	158	+ GPIO1B3_MASK = 3 << GPIO1B3_SHIFT,
	159	+ GPIO1B3_GPIO = 0,
	160	+ GPIO1B3_UART1_RSTN,
	161	+ GPIO1B3_PWM13,
	162	+
	163	+ GPIO1B2_SHIFT = 4,
	164	+ GPIO1B2_MASK = 3 << GPIO1B2_SHIFT,
	165	+ GPIO1B2_GPIO = 0,
	166	+ GPIO1B2_UART1_SIN,
	167	+ GPIO1B2_UART21_SIN,
	168	+
	169	+ GPIO1B1_SHIFT = 2,
	170	+ GPIO1B1_MASK = 3 << GPIO1B1_SHIFT,
	171	+ GPIO1B1_GPIO = 0,
	172	+ GPIO1B1_UART1_SOUT,
	173	+ GPIO1B1_UART21_SOUT,
	174	+};
	175	+
	176	+/* GRF_GPIO1C_IOMUX */
	177	+enum {
	178	+ GPIO1C7_SHIFT = 14,
	179	+ GPIO1C7_MASK = 3 << GPIO1C7_SHIFT,
	180	+ GPIO1C7_GPIO = 0,
	181	+ GPIO1C7_NAND_CS3,
	182	+ GPIO1C7_EMMC_RSTNOUT,
	183	+
	184	+ GPIO1C6_SHIFT = 12,
	185	+ GPIO1C6_MASK = 3 << GPIO1C6_SHIFT,
	186	+ GPIO1C6_GPIO = 0,
	187	+ GPIO1C6_NAND_CS2,
	188	+ GPIO1C6_EMMC_CMD,
	189	+
	190	+ GPIO1C5_SHIFT = 10,
	191	+ GPIO1C5_MASK = 3 << GPIO1C5_SHIFT,
	192	+ GPIO1C5_GPIO = 0,
	193	+ GPIO1C5_SDMMC_D3,
	194	+ GPIO1C5_JTAG_TMS,
	195	+
	196	+ GPIO1C4_SHIFT = 8,
	197	+ GPIO1C4_MASK = 3 << GPIO1C4_SHIFT,
	198	+ GPIO1C4_GPIO = 0,
	199	+ GPIO1C4_SDMMC_D2,
	200	+ GPIO1C4_JTAG_TCK,
	201	+
	202	+ GPIO1C3_SHIFT = 6,
	203	+ GPIO1C3_MASK = 3 << GPIO1C3_SHIFT,
	204	+ GPIO1C3_GPIO = 0,
	205	+ GPIO1C3_SDMMC_D1,
	206	+ GPIO1C3_UART2_SIN,
	207	+
	208	+ GPIO1C2_SHIFT = 4,
	209	+ GPIO1C2_MASK = 3 << GPIO1C2_SHIFT,
	210	+ GPIO1C2_GPIO = 0,
	211	+ GPIO1C2_SDMMC_D0,
	212	+ GPIO1C2_UART2_SOUT,
	213	+
	214	+ GPIO1C1_SHIFT = 2,
	215	+ GPIO1C1_MASK = 3 << GPIO1C1_SHIFT,
	216	+ GPIO1C1_GPIO = 0,
	217	+ GPIO1C1_SDMMC_DETN,
	218	+
	219	+ GPIO1C0_SHIFT = 0,
	220	+ GPIO1C0_MASK = 3 << GPIO1C0_SHIFT,
	221	+ GPIO1C0_GPIO = 0,
	222	+ GPIO1C0_SDMMC_CLKOUT,
	223	+};
	224	+
	225	+/* GRF_GPIO1D_IOMUX */
	226	+enum {
	227	+ GPIO1D7_SHIFT = 14,
	228	+ GPIO1D7_MASK = 3 << GPIO1D7_SHIFT,
	229	+ GPIO1D7_GPIO = 0,
	230	+ GPIO1D7_NAND_D7,
	231	+ GPIO1D7_EMMC_D7,
	232	+
	233	+ GPIO1D6_SHIFT = 12,
	234	+ GPIO1D6_MASK = 3 << GPIO1D6_SHIFT,
	235	+ GPIO1D6_GPIO = 0,
	236	+ GPIO1D6_NAND_D6,
	237	+ GPIO1D6_EMMC_D6,
	238	+
	239	+ GPIO1D5_SHIFT = 10,
	240	+ GPIO1D5_MASK = 3 << GPIO1D5_SHIFT,
	241	+ GPIO1D5_GPIO = 0,
	242	+ GPIO1D5_NAND_D5,
	243	+ GPIO1D5_EMMC_D5,
	244	+
	245	+ GPIO1D4_SHIFT = 8,
	246	+ GPIO1D4_MASK = 3 << GPIO1D4_SHIFT,
	247	+ GPIO1D4_GPIO = 0,
	248	+ GPIO1D4_NAND_D4,
	249	+ GPIO1D4_EMMC_D4,
	250	+
	251	+ GPIO1D3_SHIFT = 6,
	252	+ GPIO1D3_MASK = 3 << GPIO1D3_SHIFT,
	253	+ GPIO1D3_GPIO = 0,
	254	+ GPIO1D3_NAND_D3,
	255	+ GPIO1D3_EMMC_D3,
	256	+
	257	+ GPIO1D2_SHIFT = 4,
	258	+ GPIO1D2_MASK = 3 << GPIO1D2_SHIFT,
	259	+ GPIO1D2_GPIO = 0,
	260	+ GPIO1D2_NAND_D2,
	261	+ GPIO1D2_EMMC_D2,
	262	+
	263	+ GPIO1D1_SHIFT = 2,
	264	+ GPIO1D1_MASK = 3 << GPIO1D1_SHIFT,
	265	+ GPIO1D1_GPIO = 0,
	266	+ GPIO1D1_NAND_D1,
	267	+ GPIO1D1_EMMC_D1,
	268	+
	269	+ GPIO1D0_SHIFT = 0,
	270	+ GPIO1D0_MASK = 3 << GPIO1D0_SHIFT,
	271	+ GPIO1D0_GPIO = 0,
	272	+ GPIO1D0_NAND_D0,
	273	+ GPIO1D0_EMMC_D0,
	274	+};
	275	+
	276	+/* GRF_GPIO2A_IOMUX */
	277	+enum {
	278	+ GPIO2A7_SHIFT = 14,
	279	+ GPIO2A7_MASK = 3 << GPIO2A7_SHIFT,
	280	+ GPIO2A7_GPIO = 0,
	281	+ GPIO2A7_NAND_DQS,
	282	+ GPIO2A7_EMMC_CLKOUT,
	283	+
	284	+ GPIO2A5_SHIFT = 10,
	285	+ GPIO2A5_MASK = 3 << GPIO2A5_SHIFT,
	286	+ GPIO2A5_GPIO = 0,
	287	+ GPIO2A5_NAND_WP,
	288	+ GPIO2A5_EMMC_PWREN,
	289	+
	290	+ GPIO2A4_SHIFT = 8,
	291	+ GPIO2A4_MASK = 3 << GPIO2A4_SHIFT,
	292	+ GPIO2A4_GPIO = 0,
	293	+ GPIO2A4_NAND_RDY,
	294	+ GPIO2A4_EMMC_CMD,
	295	+
	296	+ GPIO2A3_SHIFT = 6,
	297	+ GPIO2A3_MASK = 3 << GPIO2A3_SHIFT,
	298	+ GPIO2A3_GPIO = 0,
	299	+ GPIO2A3_NAND_RDN,
	300	+ GPIO2A4_SPI1_CSN1,
	301	+
	302	+ GPIO2A2_SHIFT = 4,
	303	+ GPIO2A2_MASK = 3 << GPIO2A2_SHIFT,
	304	+ GPIO2A2_GPIO = 0,
	305	+ GPIO2A2_NAND_WRN,
	306	+ GPIO2A4_SPI1_CSN0,
	307	+
	308	+ GPIO2A1_SHIFT = 2,
	309	+ GPIO2A1_MASK = 3 << GPIO2A1_SHIFT,
	310	+ GPIO2A1_GPIO = 0,
	311	+ GPIO2A1_NAND_CLE,
	312	+ GPIO2A1_SPI1_TXD,
	313	+
	314	+ GPIO2A0_SHIFT = 0,
	315	+ GPIO2A0_MASK = 3 << GPIO2A0_SHIFT,
	316	+ GPIO2A0_GPIO = 0,
	317	+ GPIO2A0_NAND_ALE,
	318	+ GPIO2A0_SPI1_RXD,
	319	+};
	320	+
	321	+/* GRF_GPIO2B_IOMUX */
	322	+enum {
	323	+ GPIO2B7_SHIFT = 14,
	324	+ GPIO2B7_MASK = 3 << GPIO2B7_SHIFT,
	325	+ GPIO2B7_GPIO = 0,
	326	+ GPIO2B7_GMAC_RXER,
	327	+
	328	+ GPIO2B6_SHIFT = 12,
	329	+ GPIO2B6_MASK = 3 << GPIO2B6_SHIFT,
	330	+ GPIO2B6_GPIO = 0,
	331	+ GPIO2B6_GMAC_CLK,
	332	+ GPIO2B6_MAC_LINK,
	333	+
	334	+ GPIO2B5_SHIFT = 10,
	335	+ GPIO2B5_MASK = 3 << GPIO2B5_SHIFT,
	336	+ GPIO2B5_GPIO = 0,
	337	+ GPIO2B5_GMAC_TXEN,
	338	+
	339	+ GPIO2B4_SHIFT = 8,
	340	+ GPIO2B4_MASK = 3 << GPIO2B4_SHIFT,
	341	+ GPIO2B4_GPIO = 0,
	342	+ GPIO2B4_GMAC_MDIO,
	343	+
	344	+ GPIO2B3_SHIFT = 6,
	345	+ GPIO2B3_MASK = 3 << GPIO2B3_SHIFT,
	346	+ GPIO2B3_GPIO = 0,
	347	+ GPIO2B3_GMAC_RXCLK,
	348	+
	349	+ GPIO2B2_SHIFT = 4,
	350	+ GPIO2B2_MASK = 3 << GPIO2B2_SHIFT,
	351	+ GPIO2B2_GPIO = 0,
	352	+ GPIO2B2_GMAC_CRS,
	353	+
	354	+ GPIO2B1_SHIFT = 2,
	355	+ GPIO2B1_MASK = 3 << GPIO2B1_SHIFT,
	356	+ GPIO2B1_GPIO = 0,
	357	+ GPIO2B1_GMAC_TXCLK,
	358	+
	359	+ GPIO2B0_SHIFT = 0,
	360	+ GPIO2B0_MASK = 3 << GPIO2B0_SHIFT,
	361	+ GPIO2B0_GPIO = 0,
	362	+ GPIO2B0_GMAC_RXDV,
	363	+ GPIO2B0_MAC_SPEED_IOUT,
	364	+};
	365	+
	366	+/* GRF_GPIO2C_IOMUX */
	367	+enum {
	368	+ GPIO2C7_SHIFT = 14,
	369	+ GPIO2C7_MASK = 3 << GPIO2C7_SHIFT,
	370	+ GPIO2C7_GPIO = 0,
	371	+ GPIO2C7_GMAC_TXD3,
	372	+
	373	+ GPIO2C6_SHIFT = 12,
	374	+ GPIO2C6_MASK = 3 << GPIO2C6_SHIFT,
	375	+ GPIO2C6_GPIO = 0,
	376	+ GPIO2C6_GMAC_TXD2,
	377	+
	378	+ GPIO2C5_SHIFT = 10,
	379	+ GPIO2C5_MASK = 3 << GPIO2C5_SHIFT,
	380	+ GPIO2C5_GPIO = 0,
	381	+ GPIO2C5_I2C2_SCL,
	382	+ GPIO2C5_GMAC_RXD2,
	383	+
	384	+ GPIO2C4_SHIFT = 8,
	385	+ GPIO2C4_MASK = 3 << GPIO2C4_SHIFT,
	386	+ GPIO2C4_GPIO = 0,
	387	+ GPIO2C4_I2C2_SDA,
	388	+ GPIO2C4_GMAC_RXD3,
	389	+
	390	+ GPIO2C3_SHIFT = 6,
	391	+ GPIO2C3_MASK = 3 << GPIO2C3_SHIFT,
	392	+ GPIO2C3_GPIO = 0,
	393	+ GPIO2C3_GMAC_TXD0,
	394	+
	395	+ GPIO2C2_SHIFT = 4,
	396	+ GPIO2C2_MASK = 3 << GPIO2C2_SHIFT,
	397	+ GPIO2C2_GPIO = 0,
	398	+ GPIO2C2_GMAC_TXD1,
	399	+
	400	+ GPIO2C1_SHIFT = 2,
	401	+ GPIO2C1_MASK = 3 << GPIO2C1_SHIFT,
	402	+ GPIO2C1_GPIO = 0,
	403	+ GPIO2C1_GMAC_RXD0,
	404	+
	405	+ GPIO2C0_SHIFT = 0,
	406	+ GPIO2C0_MASK = 3 << GPIO2C0_SHIFT,
	407	+ GPIO2C0_GPIO = 0,
	408	+ GPIO2C0_GMAC_RXD1,
	409	+};
	410	+
	411	+/* GRF_GPIO2D_IOMUX */
	412	+enum {
	413	+ GPIO2D1_SHIFT = 2,
	414	+ GPIO2D1_MASK = 3 << GPIO2D1_SHIFT,
	415	+ GPIO2D1_GPIO = 0,
	416	+ GPIO2D1_GMAC_MDC,
	417	+
	418	+ GPIO2D0_SHIFT = 0,
	419	+ GPIO2D0_MASK = 3,
	420	+ GPIO2D0_GPIO = 0,
	421	+ GPIO2D0_GMAC_COL,
	422	+};
	423	+
	424	+/* GRF_GPIO3C_IOMUX */
	425	+enum {
	426	+ GPIO3C6_SHIFT = 12,
	427	+ GPIO3C6_MASK = 3 << GPIO3C6_SHIFT,
	428	+ GPIO3C6_GPIO = 0,
	429	+ GPIO3C6_DRV_VBUS1,
	430	+
	431	+ GPIO3C5_SHIFT = 10,
	432	+ GPIO3C5_MASK = 3 << GPIO3C5_SHIFT,
	433	+ GPIO3C5_GPIO = 0,
	434	+ GPIO3C5_PWM10,
	435	+
	436	+ GPIO3C1_SHIFT = 2,
	437	+ GPIO3C1_MASK = 3 << GPIO3C1_SHIFT,
	438	+ GPIO3C1_GPIO = 0,
	439	+ GPIO3C1_DRV_VBUS,
	440	+};
	441	+
	442	+/* GRF_GPIO3D_IOMUX */
	443	+enum {
	444	+ GPIO3D2_SHIFT = 4,
	445	+ GPIO3D2_MASK = 3 << GPIO3D2_SHIFT,
	446	+ GPIO3D2_GPIO = 0,
	447	+ GPIO3D2_PWM3,
	448	+};
	449	+
	450	+/* GRF_CON_IOMUX */
	451	+enum {
	452	+ CON_IOMUX_GMACSEL_SHIFT = 15,
	453	+ CON_IOMUX_GMACSEL_MASK = 1 << CON_IOMUX_GMACSEL_SHIFT,
	454	+ CON_IOMUX_GMACSEL_1 = 1,
	455	+ CON_IOMUX_UART1SEL_SHIFT = 11,
	456	+ CON_IOMUX_UART1SEL_MASK = 1 << CON_IOMUX_UART1SEL_SHIFT,
	457	+ CON_IOMUX_UART2SEL_SHIFT = 8,
	458	+ CON_IOMUX_UART2SEL_MASK = 1 << CON_IOMUX_UART2SEL_SHIFT,
	459	+ CON_IOMUX_UART2SEL_2 = 0,
	460	+ CON_IOMUX_UART2SEL_21,
	461	+ CON_IOMUX_EMMCSEL_SHIFT = 7,
	462	+ CON_IOMUX_EMMCSEL_MASK = 1 << CON_IOMUX_EMMCSEL_SHIFT,
	463	+ CON_IOMUX_PWM3SEL_SHIFT = 3,
	464	+ CON_IOMUX_PWM3SEL_MASK = 1 << CON_IOMUX_PWM3SEL_SHIFT,
	465	+ CON_IOMUX_PWM2SEL_SHIFT = 2,
	466	+ CON_IOMUX_PWM2SEL_MASK = 1 << CON_IOMUX_PWM2SEL_SHIFT,
	467	+ CON_IOMUX_PWM1SEL_SHIFT = 1,
	468	+ CON_IOMUX_PWM1SEL_MASK = 1 << CON_IOMUX_PWM1SEL_SHIFT,
	469	+ CON_IOMUX_PWM0SEL_SHIFT = 0,
	470	+ CON_IOMUX_PWM0SEL_MASK = 1 << CON_IOMUX_PWM0SEL_SHIFT,
	471	+};
	472	+
20	473	struct rk322x_pinctrl_priv {
21	474	struct rk322x_grf *grf;
22	475	};