ARMv8: fix bug for flush data cache by set/way

When flush the d$ with set/way instruction, it need calculate the way's offset = log2(Associativity); but in current uboot's code, it use below formula to calculate the offset: log2(Associativity * 2 - 1), so finally it cannot flush data cache properly. Signed-off-by: Leo Yan <leoy@marvell.com>

ARMv8: fix bug for flush data cache by set/way
When flush the d$ with set/way instruction, it need calculate the way's offset = log2(Associativity); but in current uboot's code, it use below formula to calculate the offset: log2(Associativity * 2 - 1), so finally it cannot flush data cache properly. Signed-off-by: Leo Yan <leoy@marvell.com>
Leo Yan · Albert ARIBAUD
1 parent 88590148fa
Showing 1 changed file with 1 additions and 3 deletions Side-by-side Diff
arch/arm/cpu/armv8/cache.S
@@ -31,9 +31,7 @@
 	add	x2, x2, #4		/* x2 <- log2(cache line size) */
 	mov	x3, #0x3ff
 	and	x3, x3, x6, lsr #3	/* x3 <- max number of #ways */
-	add	w4, w3, w3
-	sub	w4, w4, 1		/* round up log2(#ways + 1) */
-	clz	w5, w4			/* bit position of #ways */
+	clz	w5, w3			/* bit position of #ways */
 	mov	x4, #0x7fff
 	and	x4, x4, x6, lsr #13	/* x4 <- max number of #sets */
 	/* x12 <- cache level << 1 */
...	...	@@ -31,9 +31,7 @@
31	31	add x2, x2, #4 /* x2 <- log2(cache line size) */
32	32	mov x3, #0x3ff
33	33	and x3, x3, x6, lsr #3 /* x3 <- max number of #ways */
34		- add w4, w3, w3
35		- sub w4, w4, 1 /* round up log2(#ways + 1) */
36		- clz w5, w4 /* bit position of #ways */
	34	+ clz w5, w3 /* bit position of #ways */
37	35	mov x4, #0x7fff
38	36	and x4, x4, x6, lsr #13 /* x4 <- max number of #sets */
39	37	/* x12 <- cache level << 1 */