board: arm:: Add support for Broadcom BCM23550

Add support for the Broadcom BCM23550 board. Signed-off-by: Steve Rae <srae@broadcom.com>

board: arm:: Add support for Broadcom BCM23550
Add support for the Broadcom BCM23550 board. Signed-off-by: Steve Rae <srae@broadcom.com>
Steve Rae · Tom Rini
1 parent 1e031249a5
Showing 20 changed files with 2283 additions and 0 deletions Side-by-side Diff
arch/arm/Kconfig
arch/arm/cpu/armv7/Makefile
arch/arm/cpu/armv7/bcm235xx/Makefile
arch/arm/cpu/armv7/bcm235xx/clk-bcm235xx.c
arch/arm/cpu/armv7/bcm235xx/clk-bsc.c
arch/arm/cpu/armv7/bcm235xx/clk-core.c
arch/arm/cpu/armv7/bcm235xx/clk-core.h
arch/arm/cpu/armv7/bcm235xx/clk-eth.c
arch/arm/cpu/armv7/bcm235xx/clk-sdio.c
arch/arm/cpu/armv7/bcm235xx/clk-usb-otg.c
arch/arm/cpu/armv7/kona-common/Makefile
arch/arm/cpu/armv7/kona-common/reset.S
arch/arm/include/asm/arch-bcm235xx/gpio.h
arch/arm/include/asm/arch-bcm235xx/sysmap.h
board/broadcom/bcm23550_w1d/Kconfig
board/broadcom/bcm23550_w1d/MAINTAINERS
board/broadcom/bcm23550_w1d/Makefile
board/broadcom/bcm23550_w1d/bcm23550_w1d.c
configs/bcm23550_w1d_defconfig
include/configs/bcm23550_w1d.h
@@ -441,6 +441,10 @@
 	select CPU_V7
 	select SUPPORT_SPL
  
+config TARGET_BCM23550_W1D
+	bool "Support bcm23550_w1d"
+	select CPU_V7
+
 config TARGET_BCM28155_AP
 	bool "Support bcm28155_ap"
 	select CPU_V7
@@ -898,6 +902,7 @@
 source "board/armltd/vexpress/Kconfig"
 source "board/armltd/vexpress64/Kconfig"
 source "board/bluegiga/apx4devkit/Kconfig"
+source "board/broadcom/bcm23550_w1d/Kconfig"
 source "board/broadcom/bcm28155_ap/Kconfig"
 source "board/broadcom/bcmcygnus/Kconfig"
 source "board/broadcom/bcmnsp/Kconfig"
@@ -38,6 +38,7 @@
 endif
  
 obj-$(if $(filter am33xx,$(SOC)),y) += am33xx/
+obj-$(if $(filter bcm235xx,$(SOC)),y) += bcm235xx/
 obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/
 obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/
 obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/
+#
+# Copyright 2013 Broadcom Corporation.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= clk-core.o
+obj-y	+= clk-bcm235xx.o
+obj-y	+= clk-sdio.o
+obj-y	+= clk-bsc.o
+obj-$(CONFIG_BCM_SF2_ETH) += clk-eth.o
+obj-y	+= clk-usb-otg.o
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ *
+ * bcm235xx-specific clock tables
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sysmap.h>
+#include <asm/kona-common/clk.h>
+#include "clk-core.h"
+
+#define CLOCK_1K		1000
+#define CLOCK_1M		(CLOCK_1K * 1000)
+
+/* declare a reference clock */
+#define DECLARE_REF_CLK(clk_name, clk_parent, clk_rate, clk_div) \
+static struct refclk clk_name = { \
+	.clk	=	{ \
+		.name	=	#clk_name, \
+		.parent =	clk_parent, \
+		.rate	=	clk_rate, \
+		.div	=	clk_div, \
+		.ops	=	&ref_clk_ops, \
+	}, \
+}
+
+/*
+ * Reference clocks
+ */
+
+/* Declare a list of reference clocks */
+DECLARE_REF_CLK(ref_crystal,	0,		26  * CLOCK_1M,	1);
+DECLARE_REF_CLK(var_96m,	0,		96  * CLOCK_1M,	1);
+DECLARE_REF_CLK(ref_96m,	0,		96  * CLOCK_1M,	1);
+DECLARE_REF_CLK(ref_312m,	0,		312 * CLOCK_1M,	0);
+DECLARE_REF_CLK(ref_104m,	&ref_312m.clk,	104 * CLOCK_1M,	3);
+DECLARE_REF_CLK(ref_52m,	&ref_104m.clk,	52  * CLOCK_1M,	2);
+DECLARE_REF_CLK(ref_13m,	&ref_52m.clk,	13  * CLOCK_1M,	4);
+DECLARE_REF_CLK(var_312m,	0,		312 * CLOCK_1M,	0);
+DECLARE_REF_CLK(var_104m,	&var_312m.clk,	104 * CLOCK_1M,	3);
+DECLARE_REF_CLK(var_52m,	&var_104m.clk,	52  * CLOCK_1M,	2);
+DECLARE_REF_CLK(var_13m,	&var_52m.clk,	13  * CLOCK_1M,	4);
+
+struct refclk_lkup {
+	struct refclk *procclk;
+	const char *name;
+};
+
+/* Lookup table for string to clk tranlation */
+#define MKSTR(x) {&x, #x}
+static struct refclk_lkup refclk_str_tbl[] = {
+	MKSTR(ref_crystal), MKSTR(var_96m), MKSTR(ref_96m),
+	MKSTR(ref_312m), MKSTR(ref_104m), MKSTR(ref_52m),
+	MKSTR(ref_13m), MKSTR(var_312m), MKSTR(var_104m),
+	MKSTR(var_52m), MKSTR(var_13m),
+};
+
+int refclk_entries = sizeof(refclk_str_tbl)/sizeof(refclk_str_tbl[0]);
+
+/* convert ref clock string to clock structure pointer */
+struct refclk *refclk_str_to_clk(const char *name)
+{
+	int i;
+	struct refclk_lkup *tblp = refclk_str_tbl;
+	for (i = 0; i < refclk_entries; i++, tblp++) {
+		if (!(strcmp(name, tblp->name)))
+			return tblp->procclk;
+	}
+	return NULL;
+}
+
+/* frequency tables indexed by freq_id */
+unsigned long master_axi_freq_tbl[8] = {
+	26 * CLOCK_1M,
+	52 * CLOCK_1M,
+	104 * CLOCK_1M,
+	156 * CLOCK_1M,
+	156 * CLOCK_1M,
+	208 * CLOCK_1M,
+	312 * CLOCK_1M,
+	312 * CLOCK_1M
+};
+
+unsigned long master_ahb_freq_tbl[8] = {
+	26 * CLOCK_1M,
+	52 * CLOCK_1M,
+	52 * CLOCK_1M,
+	52 * CLOCK_1M,
+	78 * CLOCK_1M,
+	104 * CLOCK_1M,
+	104 * CLOCK_1M,
+	156 * CLOCK_1M
+};
+
+unsigned long slave_axi_freq_tbl[8] = {
+	26 * CLOCK_1M,
+	52 * CLOCK_1M,
+	78 * CLOCK_1M,
+	104 * CLOCK_1M,
+	156 * CLOCK_1M,
+	156 * CLOCK_1M
+};
+
+unsigned long slave_apb_freq_tbl[8] = {
+	26 * CLOCK_1M,
+	26 * CLOCK_1M,
+	39 * CLOCK_1M,
+	52 * CLOCK_1M,
+	52 * CLOCK_1M,
+	78 * CLOCK_1M
+};
+
+unsigned long esub_freq_tbl[8] = {
+	78 * CLOCK_1M,
+	156 * CLOCK_1M,
+	156 * CLOCK_1M,
+	156 * CLOCK_1M,
+	208 * CLOCK_1M,
+	208 * CLOCK_1M,
+	208 * CLOCK_1M
+};
+
+static struct bus_clk_data bsc1_apb_data = {
+	.gate = HW_SW_GATE_AUTO(0x0458, 16, 0, 1),
+};
+
+static struct bus_clk_data bsc2_apb_data = {
+	.gate = HW_SW_GATE_AUTO(0x045c, 16, 0, 1),
+};
+
+static struct bus_clk_data bsc3_apb_data = {
+	.gate = HW_SW_GATE_AUTO(0x0484, 16, 0, 1),
+};
+
+/* * Master CCU clocks */
+static struct peri_clk_data sdio1_data = {
+	.gate		= HW_SW_GATE(0x0358, 18, 2, 3),
+	.clocks		= CLOCKS("ref_crystal",
+				 "var_52m",
+				 "ref_52m",
+				 "var_96m",
+				 "ref_96m"),
+	.sel		= SELECTOR(0x0a28, 0, 3),
+	.div		= DIVIDER(0x0a28, 4, 14),
+	.trig		= TRIGGER(0x0afc, 9),
+};
+
+static struct peri_clk_data sdio2_data = {
+	.gate		= HW_SW_GATE(0x035c, 18, 2, 3),
+	.clocks		= CLOCKS("ref_crystal",
+				 "var_52m",
+				 "ref_52m",
+				 "var_96m",
+				 "ref_96m"),
+	.sel		= SELECTOR(0x0a2c, 0, 3),
+	.div		= DIVIDER(0x0a2c, 4, 14),
+	.trig		= TRIGGER(0x0afc, 10),
+};
+
+static struct peri_clk_data sdio3_data = {
+	.gate		= HW_SW_GATE(0x0364, 18, 2, 3),
+	.clocks		= CLOCKS("ref_crystal",
+				 "var_52m",
+				 "ref_52m",
+				 "var_96m",
+				 "ref_96m"),
+	.sel		= SELECTOR(0x0a34, 0, 3),
+	.div		= DIVIDER(0x0a34, 4, 14),
+	.trig		= TRIGGER(0x0afc, 12),
+};
+
+static struct peri_clk_data sdio4_data = {
+	.gate		= HW_SW_GATE(0x0360, 18, 2, 3),
+	.clocks		= CLOCKS("ref_crystal",
+				 "var_52m",
+				 "ref_52m",
+				 "var_96m",
+				 "ref_96m"),
+	.sel		= SELECTOR(0x0a30, 0, 3),
+	.div		= DIVIDER(0x0a30, 4, 14),
+	.trig		= TRIGGER(0x0afc, 11),
+};
+
+static struct peri_clk_data sdio1_sleep_data = {
+	.clocks		= CLOCKS("ref_32k"),
+	.gate		= SW_ONLY_GATE(0x0358, 20, 4),
+};
+
+static struct peri_clk_data sdio2_sleep_data = {
+	.clocks		= CLOCKS("ref_32k"),
+	.gate		= SW_ONLY_GATE(0x035c, 20, 4),
+};
+
+static struct peri_clk_data sdio3_sleep_data = {
+	.clocks		= CLOCKS("ref_32k"),
+	.gate		= SW_ONLY_GATE(0x0364, 20, 4),
+};
+
+static struct peri_clk_data sdio4_sleep_data = {
+	.clocks		= CLOCKS("ref_32k"),
+	.gate		= SW_ONLY_GATE(0x0360, 20, 4),
+};
+
+static struct bus_clk_data usb_otg_ahb_data = {
+	.gate		= HW_SW_GATE_AUTO(0x0348, 16, 0, 1),
+};
+
+static struct bus_clk_data sdio1_ahb_data = {
+	.gate		= HW_SW_GATE_AUTO(0x0358, 16, 0, 1),
+};
+
+static struct bus_clk_data sdio2_ahb_data = {
+	.gate		= HW_SW_GATE_AUTO(0x035c, 16, 0, 1),
+};
+
+static struct bus_clk_data sdio3_ahb_data = {
+	.gate		= HW_SW_GATE_AUTO(0x0364, 16, 0, 1),
+};
+
+static struct bus_clk_data sdio4_ahb_data = {
+	.gate		= HW_SW_GATE_AUTO(0x0360, 16, 0, 1),
+};
+
+/* * Slave CCU clocks */
+static struct peri_clk_data bsc1_data = {
+	.gate		= HW_SW_GATE(0x0458, 18, 2, 3),
+	.clocks		= CLOCKS("ref_crystal",
+				 "var_104m",
+				 "ref_104m",
+				 "var_13m",
+				 "ref_13m"),
+	.sel		= SELECTOR(0x0a64, 0, 3),
+	.trig		= TRIGGER(0x0afc, 23),
+};
+
+static struct peri_clk_data bsc2_data = {
+	.gate		= HW_SW_GATE(0x045c, 18, 2, 3),
+	.clocks		= CLOCKS("ref_crystal",
+				 "var_104m",
+				 "ref_104m",
+				 "var_13m",
+				 "ref_13m"),
+	.sel		= SELECTOR(0x0a68, 0, 3),
+	.trig		= TRIGGER(0x0afc, 24),
+};
+
+static struct peri_clk_data bsc3_data = {
+	.gate		= HW_SW_GATE(0x0484, 18, 2, 3),
+	.clocks		= CLOCKS("ref_crystal",
+				 "var_104m",
+				 "ref_104m",
+				 "var_13m",
+				 "ref_13m"),
+	.sel		= SELECTOR(0x0a84, 0, 3),
+	.trig		= TRIGGER(0x0b00, 2),
+};
+
+/*
+ * CCU clocks
+ */
+
+static struct ccu_clock kpm_ccu_clk = {
+	.clk = {
+		.name = "kpm_ccu_clk",
+		.ops = &ccu_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.num_policy_masks = 1,
+	.policy_freq_offset = 0x00000008,
+	.freq_bit_shift = 8,
+	.policy_ctl_offset = 0x0000000c,
+	.policy0_mask_offset = 0x00000010,
+	.policy1_mask_offset = 0x00000014,
+	.policy2_mask_offset = 0x00000018,
+	.policy3_mask_offset = 0x0000001c,
+	.lvm_en_offset = 0x00000034,
+	.freq_id = 2,
+	.freq_tbl = master_axi_freq_tbl,
+};
+
+static struct ccu_clock kps_ccu_clk = {
+	.clk = {
+		.name = "kps_ccu_clk",
+		.ops = &ccu_clk_ops,
+		.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+	},
+	.num_policy_masks = 2,
+	.policy_freq_offset = 0x00000008,
+	.freq_bit_shift = 8,
+	.policy_ctl_offset = 0x0000000c,
+	.policy0_mask_offset = 0x00000010,
+	.policy1_mask_offset = 0x00000014,
+	.policy2_mask_offset = 0x00000018,
+	.policy3_mask_offset = 0x0000001c,
+	.policy0_mask2_offset = 0x00000048,
+	.policy1_mask2_offset = 0x0000004c,
+	.policy2_mask2_offset = 0x00000050,
+	.policy3_mask2_offset = 0x00000054,
+	.lvm_en_offset = 0x00000034,
+	.freq_id = 2,
+	.freq_tbl = slave_axi_freq_tbl,
+};
+
+#ifdef CONFIG_BCM_SF2_ETH
+static struct ccu_clock esub_ccu_clk = {
+	.clk = {
+		.name = "esub_ccu_clk",
+		.ops = &ccu_clk_ops,
+		.ccu_clk_mgr_base = ESUB_CLK_BASE_ADDR,
+	},
+	.num_policy_masks = 1,
+	.policy_freq_offset = 0x00000008,
+	.freq_bit_shift = 8,
+	.policy_ctl_offset = 0x0000000c,
+	.policy0_mask_offset = 0x00000010,
+	.policy1_mask_offset = 0x00000014,
+	.policy2_mask_offset = 0x00000018,
+	.policy3_mask_offset = 0x0000001c,
+	.lvm_en_offset = 0x00000034,
+	.freq_id = 2,
+	.freq_tbl = esub_freq_tbl,
+};
+#endif
+
+/*
+ * Bus clocks
+ */
+
+/* KPM bus clocks */
+static struct bus_clock usb_otg_ahb_clk = {
+	.clk = {
+		.name = "usb_otg_ahb_clk",
+		.parent = &kpm_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.freq_tbl = master_ahb_freq_tbl,
+	.data = &usb_otg_ahb_data,
+};
+
+static struct bus_clock sdio1_ahb_clk = {
+	.clk = {
+		.name = "sdio1_ahb_clk",
+		.parent = &kpm_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.freq_tbl = master_ahb_freq_tbl,
+	.data = &sdio1_ahb_data,
+};
+
+static struct bus_clock sdio2_ahb_clk = {
+	.clk = {
+		.name = "sdio2_ahb_clk",
+		.parent = &kpm_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.freq_tbl = master_ahb_freq_tbl,
+	.data = &sdio2_ahb_data,
+};
+
+static struct bus_clock sdio3_ahb_clk = {
+	.clk = {
+		.name = "sdio3_ahb_clk",
+		.parent = &kpm_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.freq_tbl = master_ahb_freq_tbl,
+	.data = &sdio3_ahb_data,
+};
+
+static struct bus_clock sdio4_ahb_clk = {
+	.clk = {
+		.name = "sdio4_ahb_clk",
+		.parent = &kpm_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.freq_tbl = master_ahb_freq_tbl,
+	.data = &sdio4_ahb_data,
+};
+
+static struct bus_clock bsc1_apb_clk = {
+	.clk = {
+		.name = "bsc1_apb_clk",
+		.parent = &kps_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+	},
+	.freq_tbl = slave_apb_freq_tbl,
+	.data = &bsc1_apb_data,
+};
+
+static struct bus_clock bsc2_apb_clk = {
+	.clk = {
+		.name = "bsc2_apb_clk",
+		.parent = &kps_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+		},
+	.freq_tbl = slave_apb_freq_tbl,
+	.data = &bsc2_apb_data,
+};
+
+static struct bus_clock bsc3_apb_clk = {
+	.clk = {
+		.name = "bsc3_apb_clk",
+		.parent = &kps_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+		},
+	.freq_tbl = slave_apb_freq_tbl,
+	.data = &bsc3_apb_data,
+};
+
+/* KPM peripheral */
+static struct peri_clock sdio1_clk = {
+	.clk = {
+		.name = "sdio1_clk",
+		.parent = &ref_52m.clk,
+		.ops = &peri_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.data = &sdio1_data,
+};
+
+static struct peri_clock sdio2_clk = {
+	.clk = {
+		.name = "sdio2_clk",
+		.parent = &ref_52m.clk,
+		.ops = &peri_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.data = &sdio2_data,
+};
+
+static struct peri_clock sdio3_clk = {
+	.clk = {
+		.name = "sdio3_clk",
+		.parent = &ref_52m.clk,
+		.ops = &peri_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.data = &sdio3_data,
+};
+
+static struct peri_clock sdio4_clk = {
+	.clk = {
+		.name = "sdio4_clk",
+		.parent = &ref_52m.clk,
+		.ops = &peri_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.data = &sdio4_data,
+};
+
+static struct peri_clock sdio1_sleep_clk = {
+	.clk = {
+		.name = "sdio1_sleep_clk",
+		.parent = &kpm_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.data = &sdio1_sleep_data,
+};
+
+static struct peri_clock sdio2_sleep_clk = {
+	.clk = {
+		.name = "sdio2_sleep_clk",
+		.parent = &kpm_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.data = &sdio2_sleep_data,
+};
+
+static struct peri_clock sdio3_sleep_clk = {
+	.clk = {
+		.name = "sdio3_sleep_clk",
+		.parent = &kpm_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.data = &sdio3_sleep_data,
+};
+
+static struct peri_clock sdio4_sleep_clk = {
+	.clk = {
+		.name = "sdio4_sleep_clk",
+		.parent = &kpm_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.data = &sdio4_sleep_data,
+};
+
+/* KPS peripheral clock */
+static struct peri_clock bsc1_clk = {
+	.clk = {
+		.name = "bsc1_clk",
+		.parent = &ref_13m.clk,
+		.rate = 13 * CLOCK_1M,
+		.div = 1,
+		.ops = &peri_clk_ops,
+		.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+	},
+	.data = &bsc1_data,
+};
+
+static struct peri_clock bsc2_clk = {
+	.clk = {
+		.name = "bsc2_clk",
+		.parent = &ref_13m.clk,
+		.rate = 13 * CLOCK_1M,
+		.div = 1,
+		.ops = &peri_clk_ops,
+		.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+	},
+	.data = &bsc2_data,
+};
+
+static struct peri_clock bsc3_clk = {
+	.clk = {
+		.name = "bsc3_clk",
+		.parent = &ref_13m.clk,
+		.rate = 13 * CLOCK_1M,
+		.div = 1,
+		.ops = &peri_clk_ops,
+		.ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
+	},
+	.data = &bsc3_data,
+};
+
+/* public table for registering clocks */
+struct clk_lookup arch_clk_tbl[] = {
+	/* Peripheral clocks */
+	CLK_LK(sdio1),
+	CLK_LK(sdio2),
+	CLK_LK(sdio3),
+	CLK_LK(sdio4),
+	CLK_LK(sdio1_sleep),
+	CLK_LK(sdio2_sleep),
+	CLK_LK(sdio3_sleep),
+	CLK_LK(sdio4_sleep),
+	CLK_LK(bsc1),
+	CLK_LK(bsc2),
+	CLK_LK(bsc3),
+	/* Bus clocks */
+	CLK_LK(usb_otg_ahb),
+	CLK_LK(sdio1_ahb),
+	CLK_LK(sdio2_ahb),
+	CLK_LK(sdio3_ahb),
+	CLK_LK(sdio4_ahb),
+	CLK_LK(bsc1_apb),
+	CLK_LK(bsc2_apb),
+	CLK_LK(bsc3_apb),
+#ifdef CONFIG_BCM_SF2_ETH
+	CLK_LK(esub_ccu),
+#endif
+};
+
+/* public array size */
+unsigned int arch_clk_tbl_array_size = ARRAY_SIZE(arch_clk_tbl);
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sysmap.h>
+#include <asm/kona-common/clk.h>
+#include "clk-core.h"
+
+/* Enable appropriate clocks for a BSC/I2C port */
+int clk_bsc_enable(void *base)
+{
+	int ret;
+	char *bscstr, *apbstr;
+
+	switch ((u32) base) {
+	case PMU_BSC_BASE_ADDR:
+		/* PMU clock is always enabled */
+		return 0;
+	case BSC1_BASE_ADDR:
+		bscstr = "bsc1_clk";
+		apbstr = "bsc1_apb_clk";
+		break;
+	case BSC2_BASE_ADDR:
+		bscstr = "bsc2_clk";
+		apbstr = "bsc2_apb_clk";
+		break;
+	case BSC3_BASE_ADDR:
+		bscstr = "bsc3_clk";
+		apbstr = "bsc3_apb_clk";
+		break;
+	default:
+		printf("%s: base 0x%p not found\n", __func__, base);
+		return -EINVAL;
+	}
+
+	/* Note that the bus clock must be enabled first */
+
+	ret = clk_get_and_enable(apbstr);
+	if (ret)
+		return ret;
+
+	ret = clk_get_and_enable(bscstr);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+/*
+ *
+ * bcm235xx architecture clock framework
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <bitfield.h>
+#include <asm/arch/sysmap.h>
+#include <asm/kona-common/clk.h>
+#include "clk-core.h"
+
+#define CLK_WR_ACCESS_PASSWORD	0x00a5a501
+#define WR_ACCESS_OFFSET	0	/* common to all clock blocks */
+#define POLICY_CTL_GO		1	/* Load and refresh policy masks */
+#define POLICY_CTL_GO_ATL	4	/* Active Load */
+
+/* Helper function */
+int clk_get_and_enable(char *clkstr)
+{
+	int ret = 0;
+	struct clk *c;
+
+	debug("%s: %s\n", __func__, clkstr);
+
+	c = clk_get(clkstr);
+	if (c) {
+		ret = clk_enable(c);
+		if (ret)
+			return ret;
+	} else {
+		printf("%s: Couldn't find %s\n", __func__, clkstr);
+		return -EINVAL;
+	}
+	return ret;
+}
+
+/*
+ * Poll a register in a CCU's address space, returning when the
+ * specified bit in that register's value is set (or clear). Delay
+ * a microsecond after each read of the register. Returns true if
+ * successful, or false if we gave up trying.
+ *
+ * Caller must ensure the CCU lock is held.
+ */
+#define CLK_GATE_DELAY_USEC 2000
+static inline int wait_bit(void *base, u32 offset, u32 bit, bool want)
+{
+	unsigned int tries;
+	u32 bit_mask = 1 << bit;
+
+	for (tries = 0; tries < CLK_GATE_DELAY_USEC; tries++) {
+		u32 val;
+		bool bit_val;
+
+		val = readl(base + offset);
+		bit_val = (val & bit_mask) ? 1 : 0;
+		if (bit_val == want)
+			return 0;	/* success */
+		udelay(1);
+	}
+
+	debug("%s: timeout on addr 0x%p, waiting for bit %d to go to %d\n",
+	      __func__, base + offset, bit, want);
+
+	return -ETIMEDOUT;
+}
+
+/* Enable a peripheral clock */
+static int peri_clk_enable(struct clk *c, int enable)
+{
+	int ret = 0;
+	u32 reg;
+	struct peri_clock *peri_clk = to_peri_clk(c);
+	struct peri_clk_data *cd = peri_clk->data;
+	struct bcm_clk_gate *gate = &cd->gate;
+	void *base = (void *)c->ccu_clk_mgr_base;
+
+
+	debug("%s: %s\n", __func__, c->name);
+
+	clk_get_rate(c);	/* Make sure rate and sel are filled in */
+
+	/* enable access */
+	writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
+
+	if (enable) {
+		debug("%s %s set rate %lu div %lu sel %d parent %lu\n",
+		      __func__, c->name, c->rate, c->div, c->sel,
+		      c->parent->rate);
+
+		/*
+		 * clkgate - only software controllable gates are
+		 * supported by u-boot which includes all clocks
+		 * that matter. This avoids bringing in a lot of extra
+		 * complexity as done in the kernel framework.
+		 */
+		if (gate_exists(gate)) {
+			reg = readl(base + cd->gate.offset);
+			reg |= (1 << cd->gate.en_bit);
+			writel(reg, base + cd->gate.offset);
+		}
+
+		/* div and pll select */
+		if (divider_exists(&cd->div)) {
+			reg = readl(base + cd->div.offset);
+			bitfield_replace(reg, cd->div.shift, cd->div.width,
+					 c->div - 1);
+			writel(reg, base + cd->div.offset);
+		}
+
+		/* frequency selector */
+		if (selector_exists(&cd->sel)) {
+			reg = readl(base + cd->sel.offset);
+			bitfield_replace(reg, cd->sel.shift, cd->sel.width,
+					 c->sel);
+			writel(reg, base + cd->sel.offset);
+		}
+
+		/* trigger */
+		if (trigger_exists(&cd->trig)) {
+			writel((1 << cd->trig.bit), base + cd->trig.offset);
+
+			/* wait for trigger status bit to go to 0 */
+			ret = wait_bit(base, cd->trig.offset, cd->trig.bit, 0);
+			if (ret)
+				return ret;
+		}
+
+		/* wait for running (status_bit = 1) */
+		ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 1);
+		if (ret)
+			return ret;
+	} else {
+		debug("%s disable clock %s\n", __func__, c->name);
+
+		/* clkgate */
+		reg = readl(base + cd->gate.offset);
+		reg &= ~(1 << cd->gate.en_bit);
+		writel(reg, base + cd->gate.offset);
+
+		/* wait for stop (status_bit = 0) */
+		ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit, 0);
+	}
+
+	/* disable access */
+	writel(0, base + WR_ACCESS_OFFSET);
+
+	return ret;
+}
+
+/* Set the rate of a peripheral clock */
+static int peri_clk_set_rate(struct clk *c, unsigned long rate)
+{
+	int ret = 0;
+	int i;
+	unsigned long diff;
+	unsigned long new_rate = 0, div = 1;
+	struct peri_clock *peri_clk = to_peri_clk(c);
+	struct peri_clk_data *cd = peri_clk->data;
+	const char **clock;
+
+	debug("%s: %s\n", __func__, c->name);
+	diff = rate;
+
+	i = 0;
+	for (clock = cd->clocks; *clock; clock++, i++) {
+		struct refclk *ref = refclk_str_to_clk(*clock);
+		if (!ref) {
+			printf("%s: Lookup of %s failed\n", __func__, *clock);
+			return -EINVAL;
+		}
+
+		/* round to the new rate */
+		div = ref->clk.rate / rate;
+		if (div == 0)
+			div = 1;
+
+		new_rate = ref->clk.rate / div;
+
+		/* get the min diff */
+		if (abs(new_rate - rate) < diff) {
+			diff = abs(new_rate - rate);
+			c->sel = i;
+			c->parent = &ref->clk;
+			c->rate = new_rate;
+			c->div = div;
+		}
+	}
+
+	debug("%s %s set rate %lu div %lu sel %d parent %lu\n", __func__,
+	      c->name, c->rate, c->div, c->sel, c->parent->rate);
+	return ret;
+}
+
+/* Get the rate of a peripheral clock */
+static unsigned long peri_clk_get_rate(struct clk *c)
+{
+	struct peri_clock *peri_clk = to_peri_clk(c);
+	struct peri_clk_data *cd = peri_clk->data;
+	void *base = (void *)c->ccu_clk_mgr_base;
+	int div = 1;
+	const char **clock;
+	struct refclk *ref;
+	u32 reg;
+
+	debug("%s: %s\n", __func__, c->name);
+	if (selector_exists(&cd->sel)) {
+		reg = readl(base + cd->sel.offset);
+		c->sel = bitfield_extract(reg, cd->sel.shift, cd->sel.width);
+	} else {
+		/*
+		 * For peri clocks that don't have a selector, the single
+		 * reference clock will always exist at index 0.
+		 */
+		c->sel = 0;
+	}
+
+	if (divider_exists(&cd->div)) {
+		reg = readl(base + cd->div.offset);
+		div = bitfield_extract(reg, cd->div.shift, cd->div.width);
+		div += 1;
+	}
+
+	clock = cd->clocks;
+	ref = refclk_str_to_clk(clock[c->sel]);
+	if (!ref) {
+		printf("%s: Can't lookup %s\n", __func__, clock[c->sel]);
+		return 0;
+	}
+
+	c->parent = &ref->clk;
+	c->div = div;
+	c->rate = c->parent->rate / c->div;
+	debug("%s parent rate %lu div %d sel %d rate %lu\n", __func__,
+	      c->parent->rate, div, c->sel, c->rate);
+
+	return c->rate;
+}
+
+/* Peripheral clock operations */
+struct clk_ops peri_clk_ops = {
+	.enable = peri_clk_enable,
+	.set_rate = peri_clk_set_rate,
+	.get_rate = peri_clk_get_rate,
+};
+
+/* Enable a CCU clock */
+static int ccu_clk_enable(struct clk *c, int enable)
+{
+	struct ccu_clock *ccu_clk = to_ccu_clk(c);
+	void *base = (void *)c->ccu_clk_mgr_base;
+	int ret = 0;
+	u32 reg;
+
+	debug("%s: %s\n", __func__, c->name);
+	if (!enable)
+		return -EINVAL;	/* CCU clock cannot shutdown */
+
+	/* enable access */
+	writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
+
+	/* config enable for policy engine */
+	writel(1, base + ccu_clk->lvm_en_offset);
+
+	/* wait for bit to go to 0 */
+	ret = wait_bit(base, ccu_clk->lvm_en_offset, 0, 0);
+	if (ret)
+		return ret;
+
+	/* freq ID */
+	if (!ccu_clk->freq_bit_shift)
+		ccu_clk->freq_bit_shift = 8;
+
+	/* Set frequency id for each of the 4 policies */
+	reg = ccu_clk->freq_id |
+	    (ccu_clk->freq_id << (ccu_clk->freq_bit_shift)) |
+	    (ccu_clk->freq_id << (ccu_clk->freq_bit_shift * 2)) |
+	    (ccu_clk->freq_id << (ccu_clk->freq_bit_shift * 3));
+	writel(reg, base + ccu_clk->policy_freq_offset);
+
+	/* enable all clock mask */
+	writel(0x7fffffff, base + ccu_clk->policy0_mask_offset);
+	writel(0x7fffffff, base + ccu_clk->policy1_mask_offset);
+	writel(0x7fffffff, base + ccu_clk->policy2_mask_offset);
+	writel(0x7fffffff, base + ccu_clk->policy3_mask_offset);
+
+	if (ccu_clk->num_policy_masks == 2) {
+		writel(0x7fffffff, base + ccu_clk->policy0_mask2_offset);
+		writel(0x7fffffff, base + ccu_clk->policy1_mask2_offset);
+		writel(0x7fffffff, base + ccu_clk->policy2_mask2_offset);
+		writel(0x7fffffff, base + ccu_clk->policy3_mask2_offset);
+	}
+
+	/* start policy engine */
+	reg = readl(base + ccu_clk->policy_ctl_offset);
+	reg |= (POLICY_CTL_GO + POLICY_CTL_GO_ATL);
+	writel(reg, base + ccu_clk->policy_ctl_offset);
+
+	/* wait till started */
+	ret = wait_bit(base, ccu_clk->policy_ctl_offset, 0, 0);
+	if (ret)
+		return ret;
+
+	/* disable access */
+	writel(0, base + WR_ACCESS_OFFSET);
+
+	return ret;
+}
+
+/* Get the CCU clock rate */
+static unsigned long ccu_clk_get_rate(struct clk *c)
+{
+	struct ccu_clock *ccu_clk = to_ccu_clk(c);
+	debug("%s: %s\n", __func__, c->name);
+	c->rate = ccu_clk->freq_tbl[ccu_clk->freq_id];
+	return c->rate;
+}
+
+/* CCU clock operations */
+struct clk_ops ccu_clk_ops = {
+	.enable = ccu_clk_enable,
+	.get_rate = ccu_clk_get_rate,
+};
+
+/* Enable a bus clock */
+static int bus_clk_enable(struct clk *c, int enable)
+{
+	struct bus_clock *bus_clk = to_bus_clk(c);
+	struct bus_clk_data *cd = bus_clk->data;
+	void *base = (void *)c->ccu_clk_mgr_base;
+	int ret = 0;
+	u32 reg;
+
+	debug("%s: %s\n", __func__, c->name);
+	/* enable access */
+	writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET);
+
+	/* enable gating */
+	reg = readl(base + cd->gate.offset);
+	if (!!(reg & (1 << cd->gate.status_bit)) == !!enable)
+		debug("%s already %s\n", c->name,
+		      enable ? "enabled" : "disabled");
+	else {
+		int want = (enable) ? 1 : 0;
+		reg |= (1 << cd->gate.hw_sw_sel_bit);
+
+		if (enable)
+			reg |= (1 << cd->gate.en_bit);
+		else
+			reg &= ~(1 << cd->gate.en_bit);
+
+		writel(reg, base + cd->gate.offset);
+		ret = wait_bit(base, cd->gate.offset, cd->gate.status_bit,
+			       want);
+		if (ret)
+			return ret;
+	}
+
+	/* disable access */
+	writel(0, base + WR_ACCESS_OFFSET);
+
+	return ret;
+}
+
+/* Get the rate of a bus clock */
+static unsigned long bus_clk_get_rate(struct clk *c)
+{
+	struct bus_clock *bus_clk = to_bus_clk(c);
+	struct ccu_clock *ccu_clk;
+
+	debug("%s: %s\n", __func__, c->name);
+	ccu_clk = to_ccu_clk(c->parent);
+
+	c->rate = bus_clk->freq_tbl[ccu_clk->freq_id];
+	c->div = ccu_clk->freq_tbl[ccu_clk->freq_id] / c->rate;
+	return c->rate;
+}
+
+/* Bus clock operations */
+struct clk_ops bus_clk_ops = {
+	.enable = bus_clk_enable,
+	.get_rate = bus_clk_get_rate,
+};
+
+/* Enable a reference clock */
+static int ref_clk_enable(struct clk *c, int enable)
+{
+	debug("%s: %s\n", __func__, c->name);
+	return 0;
+}
+
+/* Reference clock operations */
+struct clk_ops ref_clk_ops = {
+	.enable = ref_clk_enable,
+};
+
+/*
+ * clk.h implementation follows
+ */
+
+/* Initialize the clock framework */
+int clk_init(void)
+{
+	debug("%s:\n", __func__);
+	return 0;
+}
+
+/* Get a clock handle, give a name string */
+struct clk *clk_get(const char *con_id)
+{
+	int i;
+	struct clk_lookup *clk_tblp;
+
+	debug("%s: %s\n", __func__, con_id);
+
+	clk_tblp = arch_clk_tbl;
+	for (i = 0; i < arch_clk_tbl_array_size; i++, clk_tblp++) {
+		if (clk_tblp->con_id) {
+			if (!con_id || strcmp(clk_tblp->con_id, con_id))
+				continue;
+			return clk_tblp->clk;
+		}
+	}
+	return NULL;
+}
+
+/* Enable a clock */
+int clk_enable(struct clk *c)
+{
+	int ret = 0;
+
+	debug("%s: %s\n", __func__, c->name);
+	if (!c->ops || !c->ops->enable)
+		return -1;
+
+	/* enable parent clock first */
+	if (c->parent)
+		ret = clk_enable(c->parent);
+
+	if (ret)
+		return ret;
+
+	if (!c->use_cnt) {
+		c->use_cnt++;
+		ret = c->ops->enable(c, 1);
+	}
+
+	return ret;
+}
+
+/* Disable a clock */
+void clk_disable(struct clk *c)
+{
+	debug("%s: %s\n", __func__, c->name);
+	if (!c->ops || !c->ops->enable)
+		return;
+
+	if (c->use_cnt) {
+		c->use_cnt--;
+		c->ops->enable(c, 0);
+	}
+
+	/* disable parent */
+	if (c->parent)
+		clk_disable(c->parent);
+}
+
+/* Get the clock rate */
+unsigned long clk_get_rate(struct clk *c)
+{
+	unsigned long rate;
+
+	debug("%s: %s\n", __func__, c->name);
+	if (!c || !c->ops || !c->ops->get_rate)
+		return 0;
+
+	rate = c->ops->get_rate(c);
+	debug("%s: rate = %ld\n", __func__, rate);
+	return rate;
+}
+
+/* Set the clock rate */
+int clk_set_rate(struct clk *c, unsigned long rate)
+{
+	int ret;
+
+	debug("%s: %s rate=%ld\n", __func__, c->name, rate);
+	if (!c || !c->ops || !c->ops->set_rate)
+		return -EINVAL;
+
+	if (c->use_cnt)
+		return -EINVAL;
+
+	ret = c->ops->set_rate(c, rate);
+
+	return ret;
+}
+
+/* Not required for this arch */
+/*
+long clk_round_rate(struct clk *clk, unsigned long rate);
+int clk_set_parent(struct clk *clk, struct clk *parent);
+struct clk *clk_get_parent(struct clk *clk);
+*/
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <linux/stddef.h>
+
+#ifdef CONFIG_CLK_DEBUG
+#undef writel
+#undef readl
+static inline void writel(u32 val, void *addr)
+{
+	printf("Write [0x%p] = 0x%08x\n", addr, val);
+	*(u32 *)addr = val;
+}
+
+static inline u32 readl(void *addr)
+{
+	u32 val = *(u32 *)addr;
+	printf("Read  [0x%p] = 0x%08x\n", addr, val);
+	return val;
+}
+#endif
+
+struct clk;
+
+struct clk_lookup {
+	const char *dev_id;
+	const char *con_id;
+	struct clk *clk;
+};
+
+extern struct clk_lookup arch_clk_tbl[];
+extern unsigned int arch_clk_tbl_array_size;
+
+/**
+ * struct clk_ops - standard clock operations
+ * @enable: enable/disable clock, see clk_enable() and clk_disable()
+ * @set_rate: set the clock rate, see clk_set_rate().
+ * @get_rate: get the clock rate, see clk_get_rate().
+ * @round_rate: round a given clock rate, see clk_round_rate().
+ * @set_parent: set the clock's parent, see clk_set_parent().
+ *
+ * Group the common clock implementations together so that we
+ * don't have to keep setting the same fiels again. We leave
+ * enable in struct clk.
+ *
+ */
+struct clk_ops {
+	int (*enable)(struct clk *c, int enable);
+	int (*set_rate)(struct clk *c, unsigned long rate);
+	unsigned long (*get_rate)(struct clk *c);
+	unsigned long (*round_rate)(struct clk *c, unsigned long rate);
+	int (*set_parent)(struct clk *c, struct clk *parent);
+};
+
+struct clk {
+	struct clk *parent;
+	const char *name;
+	int use_cnt;
+	unsigned long rate;	/* in HZ */
+
+	/* programmable divider. 0 means fixed ratio to parent clock */
+	unsigned long div;
+
+	struct clk_src *src;
+	struct clk_ops *ops;
+
+	unsigned long ccu_clk_mgr_base;
+	int sel;
+};
+
+struct refclk *refclk_str_to_clk(const char *name);
+
+/* The common clock framework uses u8 to represent a parent index */
+#define PARENT_COUNT_MAX	((u32)U8_MAX)
+
+#define BAD_CLK_INDEX		U8_MAX	/* Can't ever be valid */
+#define BAD_CLK_NAME		((const char *)-1)
+
+#define BAD_SCALED_DIV_VALUE	U64_MAX
+
+/*
+ * Utility macros for object flag management. If possible, flags
+ * should be defined such that 0 is the desired default value.
+ */
+#define FLAG(type, flag)		BCM_CLK_ ## type ## _FLAGS_ ## flag
+#define FLAG_SET(obj, type, flag)	((obj)->flags |= FLAG(type, flag))
+#define FLAG_CLEAR(obj, type, flag)	((obj)->flags &= ~(FLAG(type, flag)))
+#define FLAG_FLIP(obj, type, flag)	((obj)->flags ^= FLAG(type, flag))
+#define FLAG_TEST(obj, type, flag)	(!!((obj)->flags & FLAG(type, flag)))
+
+/* Clock field state tests */
+
+#define gate_exists(gate)		FLAG_TEST(gate, GATE, EXISTS)
+#define gate_is_enabled(gate)		FLAG_TEST(gate, GATE, ENABLED)
+#define gate_is_hw_controllable(gate)	FLAG_TEST(gate, GATE, HW)
+#define gate_is_sw_controllable(gate)	FLAG_TEST(gate, GATE, SW)
+#define gate_is_sw_managed(gate)	FLAG_TEST(gate, GATE, SW_MANAGED)
+#define gate_is_no_disable(gate)	FLAG_TEST(gate, GATE, NO_DISABLE)
+
+#define gate_flip_enabled(gate)		FLAG_FLIP(gate, GATE, ENABLED)
+
+#define divider_exists(div)		FLAG_TEST(div, DIV, EXISTS)
+#define divider_is_fixed(div)		FLAG_TEST(div, DIV, FIXED)
+#define divider_has_fraction(div)	(!divider_is_fixed(div) && \
+						(div)->frac_width > 0)
+
+#define selector_exists(sel)		((sel)->width != 0)
+#define trigger_exists(trig)		FLAG_TEST(trig, TRIG, EXISTS)
+
+/* Clock type, used to tell common block what it's part of */
+enum bcm_clk_type {
+	bcm_clk_none,		/* undefined clock type */
+	bcm_clk_bus,
+	bcm_clk_core,
+	bcm_clk_peri
+};
+
+/*
+ * Gating control and status is managed by a 32-bit gate register.
+ *
+ * There are several types of gating available:
+ * - (no gate)
+ *     A clock with no gate is assumed to be always enabled.
+ * - hardware-only gating (auto-gating)
+ *     Enabling or disabling clocks with this type of gate is
+ *     managed automatically by the hardware. Such clocks can be
+ *     considered by the software to be enabled. The current status
+ *     of auto-gated clocks can be read from the gate status bit.
+ * - software-only gating
+ *     Auto-gating is not available for this type of clock.
+ *     Instead, software manages whether it's enabled by setting or
+ *     clearing the enable bit. The current gate status of a gate
+ *     under software control can be read from the gate status bit.
+ *     To ensure a change to the gating status is complete, the
+ *     status bit can be polled to verify that the gate has entered
+ *     the desired state.
+ * - selectable hardware or software gating
+ *     Gating for this type of clock can be configured to be either
+ *     under software or hardware control. Which type is in use is
+ *     determined by the hw_sw_sel bit of the gate register.
+ */
+struct bcm_clk_gate {
+	u32 offset;		/* gate register offset */
+	u32 status_bit;		/* 0: gate is disabled; 0: gatge is enabled */
+	u32 en_bit;		/* 0: disable; 1: enable */
+	u32 hw_sw_sel_bit;	/* 0: hardware gating; 1: software gating */
+	u32 flags;		/* BCM_CLK_GATE_FLAGS_* below */
+};
+
+/*
+ * Gate flags:
+ *   HW         means this gate can be auto-gated
+ *   SW         means the state of this gate can be software controlled
+ *   NO_DISABLE means this gate is (only) enabled if under software control
+ *   SW_MANAGED means the status of this gate is under software control
+ *   ENABLED    means this software-managed gate is *supposed* to be enabled
+ */
+#define BCM_CLK_GATE_FLAGS_EXISTS	((u32)1 << 0)	/* Gate is valid */
+#define BCM_CLK_GATE_FLAGS_HW		((u32)1 << 1)	/* Can auto-gate */
+#define BCM_CLK_GATE_FLAGS_SW		((u32)1 << 2)	/* Software control */
+#define BCM_CLK_GATE_FLAGS_NO_DISABLE	((u32)1 << 3)	/* HW or enabled */
+#define BCM_CLK_GATE_FLAGS_SW_MANAGED	((u32)1 << 4)	/* SW now in control */
+#define BCM_CLK_GATE_FLAGS_ENABLED	((u32)1 << 5)	/* If SW_MANAGED */
+
+/*
+ * Gate initialization macros.
+ *
+ * Any gate initially under software control will be enabled.
+ */
+
+/* A hardware/software gate initially under software control */
+#define HW_SW_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit)	\
+	{								\
+		.offset = (_offset),					\
+		.status_bit = (_status_bit),				\
+		.en_bit = (_en_bit),					\
+		.hw_sw_sel_bit = (_hw_sw_sel_bit),			\
+		.flags = FLAG(GATE, HW)|FLAG(GATE, SW)|			\
+			FLAG(GATE, SW_MANAGED)|FLAG(GATE, ENABLED)|	\
+			FLAG(GATE, EXISTS),				\
+	}
+
+/* A hardware/software gate initially under hardware control */
+#define HW_SW_GATE_AUTO(_offset, _status_bit, _en_bit, _hw_sw_sel_bit)	\
+	{								\
+		.offset = (_offset),					\
+		.status_bit = (_status_bit),				\
+		.en_bit = (_en_bit),					\
+		.hw_sw_sel_bit = (_hw_sw_sel_bit),			\
+		.flags = FLAG(GATE, HW)|FLAG(GATE, SW)|			\
+			FLAG(GATE, EXISTS),				\
+	}
+
+/* A hardware-or-enabled gate (enabled if not under hardware control) */
+#define HW_ENABLE_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit)	\
+	{								\
+		.offset = (_offset),					\
+		.status_bit = (_status_bit),				\
+		.en_bit = (_en_bit),					\
+		.hw_sw_sel_bit = (_hw_sw_sel_bit),			\
+		.flags = FLAG(GATE, HW)|FLAG(GATE, SW)|			\
+			FLAG(GATE, NO_DISABLE)|FLAG(GATE, EXISTS),	\
+	}
+
+/* A software-only gate */
+#define SW_ONLY_GATE(_offset, _status_bit, _en_bit)			\
+	{								\
+		.offset = (_offset),					\
+		.status_bit = (_status_bit),				\
+		.en_bit = (_en_bit),					\
+		.flags = FLAG(GATE, SW)|FLAG(GATE, SW_MANAGED)|		\
+			FLAG(GATE, ENABLED)|FLAG(GATE, EXISTS),		\
+	}
+
+/* A hardware-only gate */
+#define HW_ONLY_GATE(_offset, _status_bit)				\
+	{								\
+		.offset = (_offset),					\
+		.status_bit = (_status_bit),				\
+		.flags = FLAG(GATE, HW)|FLAG(GATE, EXISTS),		\
+	}
+
+/*
+ * Each clock can have zero, one, or two dividers which change the
+ * output rate of the clock. Each divider can be either fixed or
+ * variable. If there are two dividers, they are the "pre-divider"
+ * and the "regular" or "downstream" divider. If there is only one,
+ * there is no pre-divider.
+ *
+ * A fixed divider is any non-zero (positive) value, and it
+ * indicates how the input rate is affected by the divider.
+ *
+ * The value of a variable divider is maintained in a sub-field of a
+ * 32-bit divider register. The position of the field in the
+ * register is defined by its offset and width. The value recorded
+ * in this field is always 1 less than the value it represents.
+ *
+ * In addition, a variable divider can indicate that some subset
+ * of its bits represent a "fractional" part of the divider. Such
+ * bits comprise the low-order portion of the divider field, and can
+ * be viewed as representing the portion of the divider that lies to
+ * the right of the decimal point. Most variable dividers have zero
+ * fractional bits. Variable dividers with non-zero fraction width
+ * still record a value 1 less than the value they represent; the
+ * added 1 does *not* affect the low-order bit in this case, it
+ * affects the bits above the fractional part only. (Often in this
+ * code a divider field value is distinguished from the value it
+ * represents by referring to the latter as a "divisor".)
+ *
+ * In order to avoid dealing with fractions, divider arithmetic is
+ * performed using "scaled" values. A scaled value is one that's
+ * been left-shifted by the fractional width of a divider. Dividing
+ * a scaled value by a scaled divisor produces the desired quotient
+ * without loss of precision and without any other special handling
+ * for fractions.
+ *
+ * The recorded value of a variable divider can be modified. To
+ * modify either divider (or both), a clock must be enabled (i.e.,
+ * using its gate). In addition, a trigger register (described
+ * below) must be used to commit the change, and polled to verify
+ * the change is complete.
+ */
+struct bcm_clk_div {
+	union {
+		struct {	/* variable divider */
+			u32 offset;	/* divider register offset */
+			u32 shift;	/* field shift */
+			u32 width;	/* field width */
+			u32 frac_width;	/* field fraction width */
+
+			u64 scaled_div;	/* scaled divider value */
+		};
+		u32 fixed;	/* non-zero fixed divider value */
+	};
+	u32 flags;		/* BCM_CLK_DIV_FLAGS_* below */
+};
+
+/*
+ * Divider flags:
+ *   EXISTS means this divider exists
+ *   FIXED means it is a fixed-rate divider
+ */
+#define BCM_CLK_DIV_FLAGS_EXISTS	((u32)1 << 0)	/* Divider is valid */
+#define BCM_CLK_DIV_FLAGS_FIXED		((u32)1 << 1)	/* Fixed-value */
+
+/* Divider initialization macros */
+
+/* A fixed (non-zero) divider */
+#define FIXED_DIVIDER(_value)						\
+	{								\
+		.fixed = (_value),					\
+		.flags = FLAG(DIV, EXISTS)|FLAG(DIV, FIXED),		\
+	}
+
+/* A divider with an integral divisor */
+#define DIVIDER(_offset, _shift, _width)				\
+	{								\
+		.offset = (_offset),					\
+		.shift = (_shift),					\
+		.width = (_width),					\
+		.scaled_div = BAD_SCALED_DIV_VALUE,			\
+		.flags = FLAG(DIV, EXISTS),				\
+	}
+
+/* A divider whose divisor has an integer and fractional part */
+#define FRAC_DIVIDER(_offset, _shift, _width, _frac_width)		\
+	{								\
+		.offset = (_offset),					\
+		.shift = (_shift),					\
+		.width = (_width),					\
+		.frac_width = (_frac_width),				\
+		.scaled_div = BAD_SCALED_DIV_VALUE,			\
+		.flags = FLAG(DIV, EXISTS),				\
+	}
+
+/*
+ * Clocks may have multiple "parent" clocks. If there is more than
+ * one, a selector must be specified to define which of the parent
+ * clocks is currently in use. The selected clock is indicated in a
+ * sub-field of a 32-bit selector register. The range of
+ * representable selector values typically exceeds the number of
+ * available parent clocks. Occasionally the reset value of a
+ * selector field is explicitly set to a (specific) value that does
+ * not correspond to a defined input clock.
+ *
+ * We register all known parent clocks with the common clock code
+ * using a packed array (i.e., no empty slots) of (parent) clock
+ * names, and refer to them later using indexes into that array.
+ * We maintain an array of selector values indexed by common clock
+ * index values in order to map between these common clock indexes
+ * and the selector values used by the hardware.
+ *
+ * Like dividers, a selector can be modified, but to do so a clock
+ * must be enabled, and a trigger must be used to commit the change.
+ */
+struct bcm_clk_sel {
+	u32 offset;		/* selector register offset */
+	u32 shift;		/* field shift */
+	u32 width;		/* field width */
+
+	u32 parent_count;	/* number of entries in parent_sel[] */
+	u32 *parent_sel;	/* array of parent selector values */
+	u8 clk_index;		/* current selected index in parent_sel[] */
+};
+
+/* Selector initialization macro */
+#define SELECTOR(_offset, _shift, _width)				\
+	{								\
+		.offset = (_offset),					\
+		.shift = (_shift),					\
+		.width = (_width),					\
+		.clk_index = BAD_CLK_INDEX,				\
+	}
+
+/*
+ * Making changes to a variable divider or a selector for a clock
+ * requires the use of a trigger. A trigger is defined by a single
+ * bit within a register. To signal a change, a 1 is written into
+ * that bit. To determine when the change has been completed, that
+ * trigger bit is polled; the read value will be 1 while the change
+ * is in progress, and 0 when it is complete.
+ *
+ * Occasionally a clock will have more than one trigger. In this
+ * case, the "pre-trigger" will be used when changing a clock's
+ * selector and/or its pre-divider.
+ */
+struct bcm_clk_trig {
+	u32 offset;		/* trigger register offset */
+	u32 bit;		/* trigger bit */
+	u32 flags;		/* BCM_CLK_TRIG_FLAGS_* below */
+};
+
+/*
+ * Trigger flags:
+ *   EXISTS means this trigger exists
+ */
+#define BCM_CLK_TRIG_FLAGS_EXISTS	((u32)1 << 0)	/* Trigger is valid */
+
+/* Trigger initialization macro */
+#define TRIGGER(_offset, _bit)						\
+	{								\
+		.offset = (_offset),					\
+		.bit = (_bit),						\
+		.flags = FLAG(TRIG, EXISTS),				\
+	}
+
+struct bus_clk_data {
+	struct bcm_clk_gate gate;
+};
+
+struct core_clk_data {
+	struct bcm_clk_gate gate;
+};
+
+struct peri_clk_data {
+	struct bcm_clk_gate gate;
+	struct bcm_clk_trig pre_trig;
+	struct bcm_clk_div pre_div;
+	struct bcm_clk_trig trig;
+	struct bcm_clk_div div;
+	struct bcm_clk_sel sel;
+	const char *clocks[];	/* must be last; use CLOCKS() to declare */
+};
+#define CLOCKS(...)	{ __VA_ARGS__, NULL, }
+#define NO_CLOCKS	{ NULL, }	/* Must use of no parent clocks */
+
+struct refclk {
+	struct clk clk;
+};
+
+struct peri_clock {
+	struct clk clk;
+	struct peri_clk_data *data;
+};
+
+struct ccu_clock {
+	struct clk clk;
+
+	int num_policy_masks;
+	unsigned long policy_freq_offset;
+	int freq_bit_shift;	/* 8 for most CCUs */
+	unsigned long policy_ctl_offset;
+	unsigned long policy0_mask_offset;
+	unsigned long policy1_mask_offset;
+	unsigned long policy2_mask_offset;
+	unsigned long policy3_mask_offset;
+	unsigned long policy0_mask2_offset;
+	unsigned long policy1_mask2_offset;
+	unsigned long policy2_mask2_offset;
+	unsigned long policy3_mask2_offset;
+	unsigned long lvm_en_offset;
+
+	int freq_id;
+	unsigned long *freq_tbl;
+};
+
+struct bus_clock {
+	struct clk clk;
+	struct bus_clk_data *data;
+	unsigned long *freq_tbl;
+};
+
+struct ref_clock {
+	struct clk clk;
+};
+
+static inline int is_same_clock(struct clk *a, struct clk *b)
+{
+	return a == b;
+}
+
+#define to_clk(p) (&((p)->clk))
+#define name_to_clk(name) (&((name##_clk).clk))
+/* declare a struct clk_lookup */
+#define CLK_LK(name) \
+{.con_id = __stringify(name##_clk), .clk = name_to_clk(name),}
+
+static inline struct refclk *to_refclk(struct clk *clock)
+{
+	return container_of(clock, struct refclk, clk);
+}
+
+static inline struct peri_clock *to_peri_clk(struct clk *clock)
+{
+	return container_of(clock, struct peri_clock, clk);
+}
+
+static inline struct ccu_clock *to_ccu_clk(struct clk *clock)
+{
+	return container_of(clock, struct ccu_clock, clk);
+}
+
+static inline struct bus_clock *to_bus_clk(struct clk *clock)
+{
+	return container_of(clock, struct bus_clock, clk);
+}
+
+static inline struct ref_clock *to_ref_clk(struct clk *clock)
+{
+	return container_of(clock, struct ref_clock, clk);
+}
+
+extern struct clk_ops peri_clk_ops;
+extern struct clk_ops ccu_clk_ops;
+extern struct clk_ops bus_clk_ops;
+extern struct clk_ops ref_clk_ops;
+
+int clk_get_and_enable(char *clkstr);
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sysmap.h>
+#include <asm/kona-common/clk.h>
+#include "clk-core.h"
+
+#define WR_ACCESS_ADDR			ESUB_CLK_BASE_ADDR
+#define WR_ACCESS_PASSWORD				0xA5A500
+
+#define PLLE_POST_RESETB_ADDR		(ESUB_CLK_BASE_ADDR + 0x00000C00)
+
+#define PLLE_RESETB_ADDR		(ESUB_CLK_BASE_ADDR + 0x00000C58)
+#define PLLE_RESETB_I_PLL_RESETB_PLLE_MASK		0x00010000
+#define PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK	0x00000001
+
+#define PLL_LOCK_ADDR			(ESUB_CLK_BASE_ADDR + 0x00000C38)
+#define PLL_LOCK_PLL_LOCK_PLLE_MASK			0x00000001
+
+#define ESW_SYS_DIV_ADDR		(ESUB_CLK_BASE_ADDR + 0x00000A04)
+#define ESW_SYS_DIV_PLL_SELECT_MASK			0x00000300
+#define ESW_SYS_DIV_DIV_MASK				0x0000001C
+#define ESW_SYS_DIV_PLL_VAR_208M_CLK_SELECT		0x00000100
+#define ESW_SYS_DIV_DIV_SELECT				0x4
+#define ESW_SYS_DIV_TRIGGER_MASK			0x00000001
+
+#define ESUB_AXI_DIV_DEBUG_ADDR		(ESUB_CLK_BASE_ADDR + 0x00000E04)
+#define ESUB_AXI_DIV_DEBUG_PLL_SELECT_MASK		0x0000001C
+#define ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK	0x00000040
+#define ESUB_AXI_DIV_DEBUG_PLL_VAR_208M_CLK_SELECT	0x0
+#define ESUB_AXI_DIV_DEBUG_TRIGGER_MASK			0x00000001
+
+#define PLL_MAX_RETRY	100
+
+/* Enable appropriate clocks for Ethernet */
+int clk_eth_enable(void)
+{
+	int rc = -1;
+	int retry_count = 0;
+	rc = clk_get_and_enable("esub_ccu_clk");
+
+	/* Enable Access to CCU registers */
+	writel((1 | WR_ACCESS_PASSWORD), WR_ACCESS_ADDR);
+
+	writel(readl(PLLE_POST_RESETB_ADDR) &
+	       ~PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK,
+	       PLLE_POST_RESETB_ADDR);
+
+	/* Take PLL out of reset and put into normal mode */
+	writel(readl(PLLE_RESETB_ADDR) | PLLE_RESETB_I_PLL_RESETB_PLLE_MASK,
+	       PLLE_RESETB_ADDR);
+
+	/* Wait for PLL lock */
+	rc = -1;
+	while (retry_count < PLL_MAX_RETRY) {
+		udelay(100);
+		if (readl(PLL_LOCK_ADDR) & PLL_LOCK_PLL_LOCK_PLLE_MASK) {
+			rc = 0;
+			break;
+		}
+		retry_count++;
+	}
+
+	if (rc == -1) {
+		printf("%s: ETH-PLL lock timeout, Ethernet is not enabled!\n",
+		       __func__);
+		return -1;
+	}
+
+	writel(readl(PLLE_POST_RESETB_ADDR) |
+	       PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK,
+	       PLLE_POST_RESETB_ADDR);
+
+	/* Switch esw_sys_clk to use 104MHz(208MHz/2) clock */
+	writel((readl(ESW_SYS_DIV_ADDR) &
+		~(ESW_SYS_DIV_PLL_SELECT_MASK | ESW_SYS_DIV_DIV_MASK)) |
+	       ESW_SYS_DIV_PLL_VAR_208M_CLK_SELECT | ESW_SYS_DIV_DIV_SELECT,
+	       ESW_SYS_DIV_ADDR);
+
+	writel(readl(ESW_SYS_DIV_ADDR) | ESW_SYS_DIV_TRIGGER_MASK,
+	       ESW_SYS_DIV_ADDR);
+
+	/* Wait for trigger complete */
+	rc = -1;
+	retry_count = 0;
+	while (retry_count < PLL_MAX_RETRY) {
+		udelay(100);
+		if (!(readl(ESW_SYS_DIV_ADDR) & ESW_SYS_DIV_TRIGGER_MASK)) {
+			rc = 0;
+			break;
+		}
+		retry_count++;
+	}
+
+	if (rc == -1) {
+		printf("%s: SYS CLK Trigger timeout, Ethernet is not enabled!\n",
+		       __func__);
+		return -1;
+	}
+
+	/* switch Esub AXI clock to 208MHz */
+	writel((readl(ESUB_AXI_DIV_DEBUG_ADDR) &
+		~(ESUB_AXI_DIV_DEBUG_PLL_SELECT_MASK |
+		  ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK |
+		  ESUB_AXI_DIV_DEBUG_TRIGGER_MASK)) |
+	       ESUB_AXI_DIV_DEBUG_PLL_VAR_208M_CLK_SELECT |
+	       ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK,
+	       ESUB_AXI_DIV_DEBUG_ADDR);
+
+	writel(readl(ESUB_AXI_DIV_DEBUG_ADDR) |
+	       ESUB_AXI_DIV_DEBUG_TRIGGER_MASK,
+	       ESUB_AXI_DIV_DEBUG_ADDR);
+
+	/* Wait for trigger complete */
+	rc = -1;
+	retry_count = 0;
+	while (retry_count < PLL_MAX_RETRY) {
+		udelay(100);
+		if (!(readl(ESUB_AXI_DIV_DEBUG_ADDR) &
+		      ESUB_AXI_DIV_DEBUG_TRIGGER_MASK)) {
+			rc = 0;
+			break;
+		}
+		retry_count++;
+	}
+
+	if (rc == -1) {
+		printf("%s: AXI CLK Trigger timeout, Ethernet is not enabled!\n",
+		       __func__);
+		return -1;
+	}
+
+	/* Disable Access to CCU registers */
+	writel(WR_ACCESS_PASSWORD, WR_ACCESS_ADDR);
+
+	return rc;
+}
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/sysmap.h>
+#include <asm/kona-common/clk.h>
+#include "clk-core.h"
+
+/* Enable appropriate clocks for an SDIO port */
+int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep)
+{
+	int ret;
+	struct clk *c;
+
+	char *clkstr;
+	char *slpstr;
+	char *ahbstr;
+
+	switch ((u32) base) {
+	case CONFIG_SYS_SDIO_BASE0:
+		clkstr = CONFIG_SYS_SDIO0 "_clk";
+		ahbstr = CONFIG_SYS_SDIO0 "_ahb_clk";
+		slpstr = CONFIG_SYS_SDIO0 "_sleep_clk";
+		break;
+	case CONFIG_SYS_SDIO_BASE1:
+		clkstr = CONFIG_SYS_SDIO1 "_clk";
+		ahbstr = CONFIG_SYS_SDIO1 "_ahb_clk";
+		slpstr = CONFIG_SYS_SDIO1 "_sleep_clk";
+		break;
+	case CONFIG_SYS_SDIO_BASE2:
+		clkstr = CONFIG_SYS_SDIO2 "_clk";
+		ahbstr = CONFIG_SYS_SDIO2 "_ahb_clk";
+		slpstr = CONFIG_SYS_SDIO2 "_sleep_clk";
+		break;
+	case CONFIG_SYS_SDIO_BASE3:
+		clkstr = CONFIG_SYS_SDIO3 "_clk";
+		ahbstr = CONFIG_SYS_SDIO3 "_ahb_clk";
+		slpstr = CONFIG_SYS_SDIO3 "_sleep_clk";
+		break;
+	default:
+		printf("%s: base 0x%p not found\n", __func__, base);
+		return -EINVAL;
+	}
+
+	ret = clk_get_and_enable(ahbstr);
+	if (ret)
+		return ret;
+
+	ret = clk_get_and_enable(slpstr);
+	if (ret)
+		return ret;
+
+	c = clk_get(clkstr);
+	if (c) {
+		ret = clk_set_rate(c, rate);
+		if (ret)
+			return ret;
+
+		ret = clk_enable(c);
+		if (ret)
+			return ret;
+	} else {
+		printf("%s: Couldn't find %s\n", __func__, clkstr);
+		return -EINVAL;
+	}
+	*actual_ratep = rate;
+	return 0;
+}
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/arch/sysmap.h>
+#include "clk-core.h"
+
+/* Enable appropriate clocks for the USB OTG port */
+int clk_usb_otg_enable(void *base)
+{
+	char *ahbstr;
+
+	switch ((u32) base) {
+	case HSOTG_BASE_ADDR:
+		ahbstr = "usb_otg_ahb_clk";
+		break;
+	default:
+		printf("%s: base 0x%p not found\n", __func__, base);
+		return -EINVAL;
+	}
+
+	return clk_get_and_enable(ahbstr);
+}
@@ -7,4 +7,5 @@
 obj-y	+= s_init.o
 obj-y	+= hwinit-common.o
 obj-y	+= clk-stubs.o
+obj-${CONFIG_KONA_RESET_S} += reset.o
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+.globl reset_cpu
+reset_cpu:
+	ldr	r1, =0x35001f00
+	ldr	r2, [r1]
+	ldr	r4, =0x80000000
+	and	r4, r2, r4
+	ldr	r3, =0xA5A500
+	orr	r4, r4, r3
+	orr	r4, r4, #0x1
+
+	str	r4, [r1]
+
+	ldr	r1, =0x35001f04
+	ldr	r2, [r1]
+	ldr	r4, =0x80000000
+	and	r4, r2, r4
+	str	r4, [r1]
+
+_loop_forever:
+	b	_loop_forever
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ARCH_BCM235XX_GPIO_H
+#define __ARCH_BCM235XX_GPIO_H
+
+/*
+ * Empty file - cmd_gpio.c requires this. The implementation
+ * is in drivers/gpio/kona_gpio.c instead of inlined here.
+ */
+
+#endif
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __ARCH_BCM235XX_SYSMAP_H
+
+#define BSC1_BASE_ADDR		0x3e016000
+#define BSC2_BASE_ADDR		0x3e017000
+#define BSC3_BASE_ADDR		0x3e018000
+#define GPIO2_BASE_ADDR		0x35003000
+#define HSOTG_BASE_ADDR		0x3f120000
+#define HSOTG_CTRL_BASE_ADDR	0x3f130000
+#define KONA_MST_CLK_BASE_ADDR	0x3f001000
+#define KONA_SLV_CLK_BASE_ADDR	0x3e011000
+#define PMU_BSC_BASE_ADDR	0x3500d000
+#define SDIO1_BASE_ADDR		0x3f180000
+#define SDIO2_BASE_ADDR		0x3f190000
+#define SDIO3_BASE_ADDR		0x3f1a0000
+#define SDIO4_BASE_ADDR		0x3f1b0000
+#define TIMER_BASE_ADDR		0x3e00d000
+
+#define HSOTG_DCTL_OFFSET					0x00000804
+#define    HSOTG_DCTL_SFTDISCON_MASK				0x00000002
+
+#define HSOTG_CTRL_PHY_P1CTL_OFFSET				0x00000008
+#define    HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK			0x00000002
+#define    HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK		0x00000001
+
+#endif
+if TARGET_BCM23550_W1D
+
+config SYS_BOARD
+	default "bcm23550_w1d"
+
+config SYS_VENDOR
+	default "broadcom"
+
+config SYS_SOC
+	default "bcm235xx"
+
+config SYS_CONFIG_NAME
+	default "bcm23550_w1d"
+
+endif
+BCM23550_W1D BOARD
+M:	Steve Rae <srae@broadcom.com>
+S:	Maintained
+F:	board/broadcom/bcm23550_w1d/
+F:	include/configs/bcm23550_w1d.h
+F:	configs/bcm23550_w1d_defconfig
+#
+# Copyright 2013 Broadcom Corporation.
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y	+= bcm23550_w1d.o
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/mach-types.h>
+#include <mmc.h>
+#include <asm/kona-common/kona_sdhci.h>
+#include <asm/kona-common/clk.h>
+#include <asm/arch/sysmap.h>
+
+#include <usb.h>
+#include <usb/dwc2_udc.h>
+#include <g_dnl.h>
+
+#define SECWATCHDOG_SDOGCR_OFFSET	0x00000000
+#define SECWATCHDOG_SDOGCR_EN_SHIFT	27
+#define SECWATCHDOG_SDOGCR_SRSTEN_SHIFT	26
+#define SECWATCHDOG_SDOGCR_CLKS_SHIFT	20
+#define SECWATCHDOG_SDOGCR_LD_SHIFT	0
+
+#ifndef CONFIG_USB_SERIALNO
+#define CONFIG_USB_SERIALNO "1234567890"
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * board_init - early hardware init
+ */
+int board_init(void)
+{
+	printf("Relocation Offset is: %08lx\n", gd->reloc_off);
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	clk_init();
+
+	return 0;
+}
+
+/*
+ * misc_init_r - miscellaneous platform dependent initializations
+ */
+int misc_init_r(void)
+{
+	return 0;
+}
+
+/*
+ * dram_init - sets uboots idea of sdram size
+ */
+int dram_init(void)
+{
+	gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
+				    CONFIG_SYS_SDRAM_SIZE);
+	return 0;
+}
+
+/* This is called after dram_init() so use get_ram_size result */
+void dram_init_banksize(void)
+{
+	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_dram[0].size = gd->ram_size;
+}
+
+#ifdef CONFIG_KONA_SDHCI
+/*
+ * mmc_init - Initializes mmc
+ */
+int board_mmc_init(bd_t *bis)
+{
+	int ret = 0;
+
+	/* Register eMMC - SDIO2 */
+	ret = kona_sdhci_init(1, 400000, 0);
+	if (ret)
+		return ret;
+
+	/* Register SD Card - SDIO4 kona_mmc_init assumes 0 based index */
+	ret = kona_sdhci_init(3, 400000, 0);
+	return ret;
+}
+#endif
+
+#ifdef CONFIG_USB_GADGET
+static struct dwc2_plat_otg_data bcm_otg_data = {
+	.regs_otg	= HSOTG_BASE_ADDR
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	debug("%s: performing dwc2_udc_probe\n", __func__);
+	return dwc2_udc_probe(&bcm_otg_data);
+}
+
+int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
+{
+	debug("%s\n", __func__);
+	if (!getenv("serial#"))
+		g_dnl_set_serialnumber(CONFIG_USB_SERIALNO);
+	return 0;
+}
+
+int g_dnl_get_board_bcd_device_number(int gcnum)
+{
+	debug("%s\n", __func__);
+	return 1;
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+	debug("%s\n", __func__);
+	return 0;
+}
+#endif
+CONFIG_ARM=y
+CONFIG_TARGET_BCM23550_W1D=y
+CONFIG_HUSH_PARSER=y
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+# CONFIG_CMD_NFS is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_FAT=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DWC2_OTG=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Broadcom Corporation"
+CONFIG_G_DNL_VENDOR_NUM=0x18d1
+CONFIG_G_DNL_PRODUCT_NUM=0x0d02
+CONFIG_OF_LIBFDT=y
+/*
+ * Copyright 2013 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __BCM23550_W1D_H
+#define __BCM23550_W1D_H
+
+#include <linux/sizes.h>
+#include <asm/arch/sysmap.h>
+
+/* CPU, chip, mach, etc */
+#define CONFIG_KONA
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_KONA_RESET_S
+
+/*
+ * Memory configuration
+ */
+#define CONFIG_SYS_TEXT_BASE		0x9f000000
+
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CONFIG_SYS_SDRAM_SIZE		0x20000000
+#define CONFIG_NR_DRAM_BANKS		1
+
+#define CONFIG_SYS_MALLOC_LEN		SZ_4M	/* see armv7/start.S. */
+#define CONFIG_STACKSIZE		SZ_256K
+
+/* GPIO Driver */
+#define CONFIG_KONA_GPIO
+
+/* MMC/SD Driver */
+#define CONFIG_SDHCI
+#define CONFIG_MMC_SDMA
+#define CONFIG_KONA_SDHCI
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+
+#define CONFIG_SYS_SDIO_BASE0 SDIO1_BASE_ADDR
+#define CONFIG_SYS_SDIO_BASE1 SDIO2_BASE_ADDR
+#define CONFIG_SYS_SDIO_BASE2 SDIO3_BASE_ADDR
+#define CONFIG_SYS_SDIO_BASE3 SDIO4_BASE_ADDR
+#define CONFIG_SYS_SDIO0_MAX_CLK 48000000
+#define CONFIG_SYS_SDIO1_MAX_CLK 48000000
+#define CONFIG_SYS_SDIO2_MAX_CLK 48000000
+#define CONFIG_SYS_SDIO3_MAX_CLK 48000000
+#define CONFIG_SYS_SDIO0 "sdio1"
+#define CONFIG_SYS_SDIO1 "sdio2"
+#define CONFIG_SYS_SDIO2 "sdio3"
+#define CONFIG_SYS_SDIO3 "sdio4"
+
+/* I2C Driver */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_KONA
+#define CONFIG_SYS_SPD_BUS_NUM	3	/* Start with PMU bus */
+#define CONFIG_SYS_MAX_I2C_BUS	4
+#define CONFIG_SYS_I2C_BASE0	BSC1_BASE_ADDR
+#define CONFIG_SYS_I2C_BASE1	BSC2_BASE_ADDR
+#define CONFIG_SYS_I2C_BASE2	BSC3_BASE_ADDR
+#define CONFIG_SYS_I2C_BASE3	PMU_BSC_BASE_ADDR
+
+/* Timer Driver */
+#define CONFIG_SYS_TIMER_RATE		32000
+#define CONFIG_SYS_TIMER_COUNTER	(TIMER_BASE_ADDR + 4) /* STCLO offset */
+
+/* Init functions */
+#define CONFIG_MISC_INIT_R	/* board's misc_init_r function */
+
+/* Some commands use this as the default load address */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE
+
+/* No mtest functions as recommended */
+
+/*
+ * This is the initial SP which is used only briefly for relocating the u-boot
+ * image to the top of SDRAM. After relocation u-boot moves the stack to the
+ * proper place.
+ */
+#define CONFIG_SYS_INIT_SP_ADDR		CONFIG_SYS_TEXT_BASE
+
+/* Serial Info */
+#define CONFIG_SYS_NS16550_SERIAL
+/* Post pad 3 bytes after each reg addr */
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		13000000
+#define CONFIG_CONS_INDEX		1
+#define CONFIG_SYS_NS16550_COM1		0x3e000000
+
+#define CONFIG_BAUDRATE			115200
+
+/* must fit into GPT:u-boot-env partition */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV		0
+#define CONFIG_ENV_OFFSET		(0x00011a00 * 512)
+#define CONFIG_ENV_SIZE			(8 * 512)
+
+#define CONFIG_SYS_NO_FLASH	/* Not using NAND/NOR unmanaged flash */
+
+/* console configuration */
+#define CONFIG_SYS_CBSIZE		1024	/* Console buffer size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+			sizeof(CONFIG_SYS_PROMPT) + 16)	/* Printbuffer size */
+#define CONFIG_SYS_MAXARGS		64
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+
+/*
+ * One partition type must be defined for part.c
+ * This is necessary for the fatls command to work on an SD card
+ * for example.
+ */
+#define CONFIG_DOS_PARTITION
+#define CONFIG_EFI_PARTITION
+
+/* version string, parser, etc */
+#define CONFIG_VERSION_VARIABLE
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
+
+#define CONFIG_CRC32_VERIFY
+#define CONFIG_MX_CYCLIC
+
+/* Initial upstream - boot to cmd prompt only */
+#define CONFIG_BOOTCOMMAND		""
+
+/* Commands */
+#define CONFIG_FAT_WRITE
+
+/* Fastboot and USB OTG */
+#define CONFIG_USB_FUNCTION_FASTBOOT
+#define CONFIG_CMD_FASTBOOT
+#define CONFIG_FASTBOOT_FLASH
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV	0
+#define CONFIG_SYS_CACHELINE_SIZE	64
+#define CONFIG_FASTBOOT_BUF_SIZE	0x1d000000
+#define CONFIG_FASTBOOT_BUF_ADDR	CONFIG_SYS_SDRAM_BASE
+#undef CONFIG_USB_GADGET_VBUS_DRAW
+#define CONFIG_USB_GADGET_VBUS_DRAW	0
+#define CONFIG_USB_GADGET_DWC2_PHY_8_BIT
+#define CONFIG_USB_GADGET_BCM_UDC_OTG_PHY
+#define CONFIG_USBID_ADDR		0x34052c46
+
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_SYS_L2CACHE_OFF
+
+#endif /* __BCM23550_W1D_H */
...	...	@@ -441,6 +441,10 @@
441	441	select CPU_V7
442	442	select SUPPORT_SPL
443	443
	444	+config TARGET_BCM23550_W1D
	445	+ bool "Support bcm23550_w1d"
	446	+ select CPU_V7
	447	+
444	448	config TARGET_BCM28155_AP
445	449	bool "Support bcm28155_ap"
446	450	select CPU_V7
...	...	@@ -898,6 +902,7 @@
898	902	source "board/armltd/vexpress/Kconfig"
899	903	source "board/armltd/vexpress64/Kconfig"
900	904	source "board/bluegiga/apx4devkit/Kconfig"
	905	+source "board/broadcom/bcm23550_w1d/Kconfig"
901	906	source "board/broadcom/bcm28155_ap/Kconfig"
902	907	source "board/broadcom/bcmcygnus/Kconfig"
903	908	source "board/broadcom/bcmnsp/Kconfig"
...	...	@@ -38,6 +38,7 @@
38	38	endif
39	39
40	40	obj-$(if $(filter am33xx,$(SOC)),y) += am33xx/
	41	+obj-$(if $(filter bcm235xx,$(SOC)),y) += bcm235xx/
41	42	obj-$(if $(filter bcm281xx,$(SOC)),y) += bcm281xx/
42	43	obj-$(if $(filter bcmcygnus,$(SOC)),y) += bcmcygnus/
43	44	obj-$(if $(filter bcmnsp,$(SOC)),y) += bcmnsp/
	1	+#
	2	+# Copyright 2013 Broadcom Corporation.
	3	+#
	4	+# SPDX-License-Identifier: GPL-2.0+
	5	+#
	6	+
	7	+obj-y += clk-core.o
	8	+obj-y += clk-bcm235xx.o
	9	+obj-y += clk-sdio.o
	10	+obj-y += clk-bsc.o
	11	+obj-$(CONFIG_BCM_SF2_ETH) += clk-eth.o
	12	+obj-y += clk-usb-otg.o
	1	+/*
	2	+ * Copyright 2013 Broadcom Corporation.
	3	+ *
	4	+ * SPDX-License-Identifier: GPL-2.0+
	5	+ */
	6	+
	7	+/*
	8	+ *
	9	+ * bcm235xx-specific clock tables
	10	+ *
	11	+ */
	12	+
	13	+#include <common.h>
	14	+#include <asm/io.h>
	15	+#include <asm/errno.h>
	16	+#include <asm/arch/sysmap.h>
	17	+#include <asm/kona-common/clk.h>
	18	+#include "clk-core.h"
	19	+
	20	+#define CLOCK_1K 1000
	21	+#define CLOCK_1M (CLOCK_1K * 1000)
	22	+
	23	+/* declare a reference clock */
	24	+#define DECLARE_REF_CLK(clk_name, clk_parent, clk_rate, clk_div) \
	25	+static struct refclk clk_name = { \
	26	+ .clk = { \
	27	+ .name = #clk_name, \
	28	+ .parent = clk_parent, \
	29	+ .rate = clk_rate, \
	30	+ .div = clk_div, \
	31	+ .ops = &ref_clk_ops, \
	32	+ }, \
	33	+}
	34	+
	35	+/*
	36	+ * Reference clocks
	37	+ */
	38	+
	39	+/* Declare a list of reference clocks */
	40	+DECLARE_REF_CLK(ref_crystal, 0, 26 * CLOCK_1M, 1);
	41	+DECLARE_REF_CLK(var_96m, 0, 96 * CLOCK_1M, 1);
	42	+DECLARE_REF_CLK(ref_96m, 0, 96 * CLOCK_1M, 1);
	43	+DECLARE_REF_CLK(ref_312m, 0, 312 * CLOCK_1M, 0);
	44	+DECLARE_REF_CLK(ref_104m, &ref_312m.clk, 104 * CLOCK_1M, 3);
	45	+DECLARE_REF_CLK(ref_52m, &ref_104m.clk, 52 * CLOCK_1M, 2);
	46	+DECLARE_REF_CLK(ref_13m, &ref_52m.clk, 13 * CLOCK_1M, 4);
	47	+DECLARE_REF_CLK(var_312m, 0, 312 * CLOCK_1M, 0);
	48	+DECLARE_REF_CLK(var_104m, &var_312m.clk, 104 * CLOCK_1M, 3);
	49	+DECLARE_REF_CLK(var_52m, &var_104m.clk, 52 * CLOCK_1M, 2);
	50	+DECLARE_REF_CLK(var_13m, &var_52m.clk, 13 * CLOCK_1M, 4);
	51	+
	52	+struct refclk_lkup {
	53	+ struct refclk *procclk;
	54	+ const char *name;
	55	+};
	56	+
	57	+/* Lookup table for string to clk tranlation */
	58	+#define MKSTR(x) {&x, #x}
	59	+static struct refclk_lkup refclk_str_tbl[] = {
	60	+ MKSTR(ref_crystal), MKSTR(var_96m), MKSTR(ref_96m),
	61	+ MKSTR(ref_312m), MKSTR(ref_104m), MKSTR(ref_52m),
	62	+ MKSTR(ref_13m), MKSTR(var_312m), MKSTR(var_104m),
	63	+ MKSTR(var_52m), MKSTR(var_13m),
	64	+};
	65	+
	66	+int refclk_entries = sizeof(refclk_str_tbl)/sizeof(refclk_str_tbl[0]);
	67	+
	68	+/* convert ref clock string to clock structure pointer */
	69	+struct refclk refclk_str_to_clk(const char name)
	70	+{
	71	+ int i;
	72	+ struct refclk_lkup *tblp = refclk_str_tbl;
	73	+ for (i = 0; i < refclk_entries; i++, tblp++) {
	74	+ if (!(strcmp(name, tblp->name)))
	75	+ return tblp->procclk;
	76	+ }
	77	+ return NULL;
	78	+}
	79	+
	80	+/* frequency tables indexed by freq_id */
	81	+unsigned long master_axi_freq_tbl[8] = {
	82	+ 26 * CLOCK_1M,
	83	+ 52 * CLOCK_1M,
	84	+ 104 * CLOCK_1M,
	85	+ 156 * CLOCK_1M,
	86	+ 156 * CLOCK_1M,
	87	+ 208 * CLOCK_1M,
	88	+ 312 * CLOCK_1M,
	89	+ 312 * CLOCK_1M
	90	+};
	91	+
	92	+unsigned long master_ahb_freq_tbl[8] = {
	93	+ 26 * CLOCK_1M,
	94	+ 52 * CLOCK_1M,
	95	+ 52 * CLOCK_1M,
	96	+ 52 * CLOCK_1M,
	97	+ 78 * CLOCK_1M,
	98	+ 104 * CLOCK_1M,
	99	+ 104 * CLOCK_1M,
	100	+ 156 * CLOCK_1M
	101	+};
	102	+
	103	+unsigned long slave_axi_freq_tbl[8] = {
	104	+ 26 * CLOCK_1M,
	105	+ 52 * CLOCK_1M,
	106	+ 78 * CLOCK_1M,
	107	+ 104 * CLOCK_1M,
	108	+ 156 * CLOCK_1M,
	109	+ 156 * CLOCK_1M
	110	+};
	111	+
	112	+unsigned long slave_apb_freq_tbl[8] = {
	113	+ 26 * CLOCK_1M,
	114	+ 26 * CLOCK_1M,
	115	+ 39 * CLOCK_1M,
	116	+ 52 * CLOCK_1M,
	117	+ 52 * CLOCK_1M,
	118	+ 78 * CLOCK_1M
	119	+};
	120	+
	121	+unsigned long esub_freq_tbl[8] = {
	122	+ 78 * CLOCK_1M,
	123	+ 156 * CLOCK_1M,
	124	+ 156 * CLOCK_1M,
	125	+ 156 * CLOCK_1M,
	126	+ 208 * CLOCK_1M,
	127	+ 208 * CLOCK_1M,
	128	+ 208 * CLOCK_1M
	129	+};
	130	+
	131	+static struct bus_clk_data bsc1_apb_data = {
	132	+ .gate = HW_SW_GATE_AUTO(0x0458, 16, 0, 1),
	133	+};
	134	+
	135	+static struct bus_clk_data bsc2_apb_data = {
	136	+ .gate = HW_SW_GATE_AUTO(0x045c, 16, 0, 1),
	137	+};
	138	+
	139	+static struct bus_clk_data bsc3_apb_data = {
	140	+ .gate = HW_SW_GATE_AUTO(0x0484, 16, 0, 1),
	141	+};
	142	+
	143	+/* * Master CCU clocks */
	144	+static struct peri_clk_data sdio1_data = {
	145	+ .gate = HW_SW_GATE(0x0358, 18, 2, 3),
	146	+ .clocks = CLOCKS("ref_crystal",
	147	+ "var_52m",
	148	+ "ref_52m",
	149	+ "var_96m",
	150	+ "ref_96m"),
	151	+ .sel = SELECTOR(0x0a28, 0, 3),
	152	+ .div = DIVIDER(0x0a28, 4, 14),
	153	+ .trig = TRIGGER(0x0afc, 9),
	154	+};
	155	+
	156	+static struct peri_clk_data sdio2_data = {
	157	+ .gate = HW_SW_GATE(0x035c, 18, 2, 3),
	158	+ .clocks = CLOCKS("ref_crystal",
	159	+ "var_52m",
	160	+ "ref_52m",
	161	+ "var_96m",
	162	+ "ref_96m"),
	163	+ .sel = SELECTOR(0x0a2c, 0, 3),
	164	+ .div = DIVIDER(0x0a2c, 4, 14),
	165	+ .trig = TRIGGER(0x0afc, 10),
	166	+};
	167	+
	168	+static struct peri_clk_data sdio3_data = {
	169	+ .gate = HW_SW_GATE(0x0364, 18, 2, 3),
	170	+ .clocks = CLOCKS("ref_crystal",
	171	+ "var_52m",
	172	+ "ref_52m",
	173	+ "var_96m",
	174	+ "ref_96m"),
	175	+ .sel = SELECTOR(0x0a34, 0, 3),
	176	+ .div = DIVIDER(0x0a34, 4, 14),
	177	+ .trig = TRIGGER(0x0afc, 12),
	178	+};
	179	+
	180	+static struct peri_clk_data sdio4_data = {
	181	+ .gate = HW_SW_GATE(0x0360, 18, 2, 3),
	182	+ .clocks = CLOCKS("ref_crystal",
	183	+ "var_52m",
	184	+ "ref_52m",
	185	+ "var_96m",
	186	+ "ref_96m"),
	187	+ .sel = SELECTOR(0x0a30, 0, 3),
	188	+ .div = DIVIDER(0x0a30, 4, 14),
	189	+ .trig = TRIGGER(0x0afc, 11),
	190	+};
	191	+
	192	+static struct peri_clk_data sdio1_sleep_data = {
	193	+ .clocks = CLOCKS("ref_32k"),
	194	+ .gate = SW_ONLY_GATE(0x0358, 20, 4),
	195	+};
	196	+
	197	+static struct peri_clk_data sdio2_sleep_data = {
	198	+ .clocks = CLOCKS("ref_32k"),
	199	+ .gate = SW_ONLY_GATE(0x035c, 20, 4),
	200	+};
	201	+
	202	+static struct peri_clk_data sdio3_sleep_data = {
	203	+ .clocks = CLOCKS("ref_32k"),
	204	+ .gate = SW_ONLY_GATE(0x0364, 20, 4),
	205	+};
	206	+
	207	+static struct peri_clk_data sdio4_sleep_data = {
	208	+ .clocks = CLOCKS("ref_32k"),
	209	+ .gate = SW_ONLY_GATE(0x0360, 20, 4),
	210	+};
	211	+
	212	+static struct bus_clk_data usb_otg_ahb_data = {
	213	+ .gate = HW_SW_GATE_AUTO(0x0348, 16, 0, 1),
	214	+};
	215	+
	216	+static struct bus_clk_data sdio1_ahb_data = {
	217	+ .gate = HW_SW_GATE_AUTO(0x0358, 16, 0, 1),
	218	+};
	219	+
	220	+static struct bus_clk_data sdio2_ahb_data = {
	221	+ .gate = HW_SW_GATE_AUTO(0x035c, 16, 0, 1),
	222	+};
	223	+
	224	+static struct bus_clk_data sdio3_ahb_data = {
	225	+ .gate = HW_SW_GATE_AUTO(0x0364, 16, 0, 1),
	226	+};
	227	+
	228	+static struct bus_clk_data sdio4_ahb_data = {
	229	+ .gate = HW_SW_GATE_AUTO(0x0360, 16, 0, 1),
	230	+};
	231	+
	232	+/* * Slave CCU clocks */
	233	+static struct peri_clk_data bsc1_data = {
	234	+ .gate = HW_SW_GATE(0x0458, 18, 2, 3),
	235	+ .clocks = CLOCKS("ref_crystal",
	236	+ "var_104m",
	237	+ "ref_104m",
	238	+ "var_13m",
	239	+ "ref_13m"),
	240	+ .sel = SELECTOR(0x0a64, 0, 3),
	241	+ .trig = TRIGGER(0x0afc, 23),
	242	+};
	243	+
	244	+static struct peri_clk_data bsc2_data = {
	245	+ .gate = HW_SW_GATE(0x045c, 18, 2, 3),
	246	+ .clocks = CLOCKS("ref_crystal",
	247	+ "var_104m",
	248	+ "ref_104m",
	249	+ "var_13m",
	250	+ "ref_13m"),
	251	+ .sel = SELECTOR(0x0a68, 0, 3),
	252	+ .trig = TRIGGER(0x0afc, 24),
	253	+};
	254	+
	255	+static struct peri_clk_data bsc3_data = {
	256	+ .gate = HW_SW_GATE(0x0484, 18, 2, 3),
	257	+ .clocks = CLOCKS("ref_crystal",
	258	+ "var_104m",
	259	+ "ref_104m",
	260	+ "var_13m",
	261	+ "ref_13m"),
	262	+ .sel = SELECTOR(0x0a84, 0, 3),
	263	+ .trig = TRIGGER(0x0b00, 2),
	264	+};
	265	+
	266	+/*
	267	+ * CCU clocks
	268	+ */
	269	+
	270	+static struct ccu_clock kpm_ccu_clk = {
	271	+ .clk = {
	272	+ .name = "kpm_ccu_clk",
	273	+ .ops = &ccu_clk_ops,
	274	+ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
	275	+ },
	276	+ .num_policy_masks = 1,
	277	+ .policy_freq_offset = 0x00000008,
	278	+ .freq_bit_shift = 8,
	279	+ .policy_ctl_offset = 0x0000000c,
	280	+ .policy0_mask_offset = 0x00000010,
	281	+ .policy1_mask_offset = 0x00000014,
	282	+ .policy2_mask_offset = 0x00000018,
	283	+ .policy3_mask_offset = 0x0000001c,
	284	+ .lvm_en_offset = 0x00000034,
	285	+ .freq_id = 2,
	286	+ .freq_tbl = master_axi_freq_tbl,
	287	+};
	288	+
	289	+static struct ccu_clock kps_ccu_clk = {
	290	+ .clk = {
	291	+ .name = "kps_ccu_clk",
	292	+ .ops = &ccu_clk_ops,
	293	+ .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
	294	+ },
	295	+ .num_policy_masks = 2,
	296	+ .policy_freq_offset = 0x00000008,
	297	+ .freq_bit_shift = 8,
	298	+ .policy_ctl_offset = 0x0000000c,
	299	+ .policy0_mask_offset = 0x00000010,
	300	+ .policy1_mask_offset = 0x00000014,
	301	+ .policy2_mask_offset = 0x00000018,
	302	+ .policy3_mask_offset = 0x0000001c,
	303	+ .policy0_mask2_offset = 0x00000048,
	304	+ .policy1_mask2_offset = 0x0000004c,
	305	+ .policy2_mask2_offset = 0x00000050,
	306	+ .policy3_mask2_offset = 0x00000054,
	307	+ .lvm_en_offset = 0x00000034,
	308	+ .freq_id = 2,
	309	+ .freq_tbl = slave_axi_freq_tbl,
	310	+};
	311	+
	312	+#ifdef CONFIG_BCM_SF2_ETH
	313	+static struct ccu_clock esub_ccu_clk = {
	314	+ .clk = {
	315	+ .name = "esub_ccu_clk",
	316	+ .ops = &ccu_clk_ops,
	317	+ .ccu_clk_mgr_base = ESUB_CLK_BASE_ADDR,
	318	+ },
	319	+ .num_policy_masks = 1,
	320	+ .policy_freq_offset = 0x00000008,
	321	+ .freq_bit_shift = 8,
	322	+ .policy_ctl_offset = 0x0000000c,
	323	+ .policy0_mask_offset = 0x00000010,
	324	+ .policy1_mask_offset = 0x00000014,
	325	+ .policy2_mask_offset = 0x00000018,
	326	+ .policy3_mask_offset = 0x0000001c,
	327	+ .lvm_en_offset = 0x00000034,
	328	+ .freq_id = 2,
	329	+ .freq_tbl = esub_freq_tbl,
	330	+};
	331	+#endif
	332	+
	333	+/*
	334	+ * Bus clocks
	335	+ */
	336	+
	337	+/* KPM bus clocks */
	338	+static struct bus_clock usb_otg_ahb_clk = {
	339	+ .clk = {
	340	+ .name = "usb_otg_ahb_clk",
	341	+ .parent = &kpm_ccu_clk.clk,
	342	+ .ops = &bus_clk_ops,
	343	+ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
	344	+ },
	345	+ .freq_tbl = master_ahb_freq_tbl,
	346	+ .data = &usb_otg_ahb_data,
	347	+};
	348	+
	349	+static struct bus_clock sdio1_ahb_clk = {
	350	+ .clk = {
	351	+ .name = "sdio1_ahb_clk",
	352	+ .parent = &kpm_ccu_clk.clk,
	353	+ .ops = &bus_clk_ops,
	354	+ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
	355	+ },
	356	+ .freq_tbl = master_ahb_freq_tbl,
	357	+ .data = &sdio1_ahb_data,
	358	+};
	359	+
	360	+static struct bus_clock sdio2_ahb_clk = {
	361	+ .clk = {
	362	+ .name = "sdio2_ahb_clk",
	363	+ .parent = &kpm_ccu_clk.clk,
	364	+ .ops = &bus_clk_ops,
	365	+ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
	366	+ },
	367	+ .freq_tbl = master_ahb_freq_tbl,
	368	+ .data = &sdio2_ahb_data,
	369	+};
	370	+
	371	+static struct bus_clock sdio3_ahb_clk = {
	372	+ .clk = {
	373	+ .name = "sdio3_ahb_clk",
	374	+ .parent = &kpm_ccu_clk.clk,
	375	+ .ops = &bus_clk_ops,
	376	+ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
	377	+ },
	378	+ .freq_tbl = master_ahb_freq_tbl,
	379	+ .data = &sdio3_ahb_data,
	380	+};
	381	+
	382	+static struct bus_clock sdio4_ahb_clk = {
	383	+ .clk = {
	384	+ .name = "sdio4_ahb_clk",
	385	+ .parent = &kpm_ccu_clk.clk,
	386	+ .ops = &bus_clk_ops,
	387	+ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
	388	+ },
	389	+ .freq_tbl = master_ahb_freq_tbl,
	390	+ .data = &sdio4_ahb_data,
	391	+};
	392	+
	393	+static struct bus_clock bsc1_apb_clk = {
	394	+ .clk = {
	395	+ .name = "bsc1_apb_clk",
	396	+ .parent = &kps_ccu_clk.clk,
	397	+ .ops = &bus_clk_ops,
	398	+ .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
	399	+ },
	400	+ .freq_tbl = slave_apb_freq_tbl,
	401	+ .data = &bsc1_apb_data,
	402	+};
	403	+
	404	+static struct bus_clock bsc2_apb_clk = {
	405	+ .clk = {
	406	+ .name = "bsc2_apb_clk",
	407	+ .parent = &kps_ccu_clk.clk,
	408	+ .ops = &bus_clk_ops,
	409	+ .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
	410	+ },
	411	+ .freq_tbl = slave_apb_freq_tbl,
	412	+ .data = &bsc2_apb_data,
	413	+};
	414	+
	415	+static struct bus_clock bsc3_apb_clk = {
	416	+ .clk = {
	417	+ .name = "bsc3_apb_clk",
	418	+ .parent = &kps_ccu_clk.clk,
	419	+ .ops = &bus_clk_ops,
	420	+ .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
	421	+ },
	422	+ .freq_tbl = slave_apb_freq_tbl,
	423	+ .data = &bsc3_apb_data,
	424	+};
	425	+
	426	+/* KPM peripheral */
	427	+static struct peri_clock sdio1_clk = {
	428	+ .clk = {
	429	+ .name = "sdio1_clk",
	430	+ .parent = &ref_52m.clk,
	431	+ .ops = &peri_clk_ops,
	432	+ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
	433	+ },
	434	+ .data = &sdio1_data,
	435	+};
	436	+
	437	+static struct peri_clock sdio2_clk = {
	438	+ .clk = {
	439	+ .name = "sdio2_clk",
	440	+ .parent = &ref_52m.clk,
	441	+ .ops = &peri_clk_ops,
	442	+ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
	443	+ },
	444	+ .data = &sdio2_data,
	445	+};
	446	+
	447	+static struct peri_clock sdio3_clk = {
	448	+ .clk = {
	449	+ .name = "sdio3_clk",
	450	+ .parent = &ref_52m.clk,
	451	+ .ops = &peri_clk_ops,
	452	+ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
	453	+ },
	454	+ .data = &sdio3_data,
	455	+};
	456	+
	457	+static struct peri_clock sdio4_clk = {
	458	+ .clk = {
	459	+ .name = "sdio4_clk",
	460	+ .parent = &ref_52m.clk,
	461	+ .ops = &peri_clk_ops,
	462	+ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
	463	+ },
	464	+ .data = &sdio4_data,
	465	+};
	466	+
	467	+static struct peri_clock sdio1_sleep_clk = {
	468	+ .clk = {
	469	+ .name = "sdio1_sleep_clk",
	470	+ .parent = &kpm_ccu_clk.clk,
	471	+ .ops = &bus_clk_ops,
	472	+ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
	473	+ },
	474	+ .data = &sdio1_sleep_data,
	475	+};
	476	+
	477	+static struct peri_clock sdio2_sleep_clk = {
	478	+ .clk = {
	479	+ .name = "sdio2_sleep_clk",
	480	+ .parent = &kpm_ccu_clk.clk,
	481	+ .ops = &bus_clk_ops,
	482	+ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
	483	+ },
	484	+ .data = &sdio2_sleep_data,
	485	+};
	486	+
	487	+static struct peri_clock sdio3_sleep_clk = {
	488	+ .clk = {
	489	+ .name = "sdio3_sleep_clk",
	490	+ .parent = &kpm_ccu_clk.clk,
	491	+ .ops = &bus_clk_ops,
	492	+ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
	493	+ },
	494	+ .data = &sdio3_sleep_data,
	495	+};
	496	+
	497	+static struct peri_clock sdio4_sleep_clk = {
	498	+ .clk = {
	499	+ .name = "sdio4_sleep_clk",
	500	+ .parent = &kpm_ccu_clk.clk,
	501	+ .ops = &bus_clk_ops,
	502	+ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
	503	+ },
	504	+ .data = &sdio4_sleep_data,
	505	+};
	506	+
	507	+/* KPS peripheral clock */
	508	+static struct peri_clock bsc1_clk = {
	509	+ .clk = {
	510	+ .name = "bsc1_clk",
	511	+ .parent = &ref_13m.clk,
	512	+ .rate = 13 * CLOCK_1M,
	513	+ .div = 1,
	514	+ .ops = &peri_clk_ops,
	515	+ .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
	516	+ },
	517	+ .data = &bsc1_data,
	518	+};
	519	+
	520	+static struct peri_clock bsc2_clk = {
	521	+ .clk = {
	522	+ .name = "bsc2_clk",
	523	+ .parent = &ref_13m.clk,
	524	+ .rate = 13 * CLOCK_1M,
	525	+ .div = 1,
	526	+ .ops = &peri_clk_ops,
	527	+ .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
	528	+ },
	529	+ .data = &bsc2_data,
	530	+};
	531	+
	532	+static struct peri_clock bsc3_clk = {
	533	+ .clk = {
	534	+ .name = "bsc3_clk",
	535	+ .parent = &ref_13m.clk,
	536	+ .rate = 13 * CLOCK_1M,
	537	+ .div = 1,
	538	+ .ops = &peri_clk_ops,
	539	+ .ccu_clk_mgr_base = KONA_SLV_CLK_BASE_ADDR,
	540	+ },
	541	+ .data = &bsc3_data,
	542	+};
	543	+
	544	+/* public table for registering clocks */
	545	+struct clk_lookup arch_clk_tbl[] = {
	546	+ /* Peripheral clocks */
	547	+ CLK_LK(sdio1),
	548	+ CLK_LK(sdio2),
	549	+ CLK_LK(sdio3),
	550	+ CLK_LK(sdio4),
	551	+ CLK_LK(sdio1_sleep),
	552	+ CLK_LK(sdio2_sleep),
	553	+ CLK_LK(sdio3_sleep),
	554	+ CLK_LK(sdio4_sleep),
	555	+ CLK_LK(bsc1),
	556	+ CLK_LK(bsc2),
	557	+ CLK_LK(bsc3),
	558	+ /* Bus clocks */
	559	+ CLK_LK(usb_otg_ahb),
	560	+ CLK_LK(sdio1_ahb),
	561	+ CLK_LK(sdio2_ahb),
	562	+ CLK_LK(sdio3_ahb),
	563	+ CLK_LK(sdio4_ahb),
	564	+ CLK_LK(bsc1_apb),
	565	+ CLK_LK(bsc2_apb),
	566	+ CLK_LK(bsc3_apb),
	567	+#ifdef CONFIG_BCM_SF2_ETH
	568	+ CLK_LK(esub_ccu),
	569	+#endif
	570	+};
	571	+
	572	+/* public array size */
	573	+unsigned int arch_clk_tbl_array_size = ARRAY_SIZE(arch_clk_tbl);
	1	+/*
	2	+ * Copyright 2014 Broadcom Corporation.
	3	+ *
	4	+ * SPDX-License-Identifier: GPL-2.0+
	5	+ */
	6	+
	7	+#include <common.h>
	8	+#include <asm/io.h>
	9	+#include <asm/errno.h>
	10	+#include <asm/arch/sysmap.h>
	11	+#include <asm/kona-common/clk.h>
	12	+#include "clk-core.h"
	13	+
	14	+#define WR_ACCESS_ADDR ESUB_CLK_BASE_ADDR
	15	+#define WR_ACCESS_PASSWORD 0xA5A500
	16	+
	17	+#define PLLE_POST_RESETB_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C00)
	18	+
	19	+#define PLLE_RESETB_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C58)
	20	+#define PLLE_RESETB_I_PLL_RESETB_PLLE_MASK 0x00010000
	21	+#define PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK 0x00000001
	22	+
	23	+#define PLL_LOCK_ADDR (ESUB_CLK_BASE_ADDR + 0x00000C38)
	24	+#define PLL_LOCK_PLL_LOCK_PLLE_MASK 0x00000001
	25	+
	26	+#define ESW_SYS_DIV_ADDR (ESUB_CLK_BASE_ADDR + 0x00000A04)
	27	+#define ESW_SYS_DIV_PLL_SELECT_MASK 0x00000300
	28	+#define ESW_SYS_DIV_DIV_MASK 0x0000001C
	29	+#define ESW_SYS_DIV_PLL_VAR_208M_CLK_SELECT 0x00000100
	30	+#define ESW_SYS_DIV_DIV_SELECT 0x4
	31	+#define ESW_SYS_DIV_TRIGGER_MASK 0x00000001
	32	+
	33	+#define ESUB_AXI_DIV_DEBUG_ADDR (ESUB_CLK_BASE_ADDR + 0x00000E04)
	34	+#define ESUB_AXI_DIV_DEBUG_PLL_SELECT_MASK 0x0000001C
	35	+#define ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK 0x00000040
	36	+#define ESUB_AXI_DIV_DEBUG_PLL_VAR_208M_CLK_SELECT 0x0
	37	+#define ESUB_AXI_DIV_DEBUG_TRIGGER_MASK 0x00000001
	38	+
	39	+#define PLL_MAX_RETRY 100
	40	+
	41	+/* Enable appropriate clocks for Ethernet */
	42	+int clk_eth_enable(void)
	43	+{
	44	+ int rc = -1;
	45	+ int retry_count = 0;
	46	+ rc = clk_get_and_enable("esub_ccu_clk");
	47	+
	48	+ /* Enable Access to CCU registers */
	49	+ writel((1 \| WR_ACCESS_PASSWORD), WR_ACCESS_ADDR);
	50	+
	51	+ writel(readl(PLLE_POST_RESETB_ADDR) &
	52	+ ~PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK,
	53	+ PLLE_POST_RESETB_ADDR);
	54	+
	55	+ /* Take PLL out of reset and put into normal mode */
	56	+ writel(readl(PLLE_RESETB_ADDR) \| PLLE_RESETB_I_PLL_RESETB_PLLE_MASK,
	57	+ PLLE_RESETB_ADDR);
	58	+
	59	+ /* Wait for PLL lock */
	60	+ rc = -1;
	61	+ while (retry_count < PLL_MAX_RETRY) {
	62	+ udelay(100);
	63	+ if (readl(PLL_LOCK_ADDR) & PLL_LOCK_PLL_LOCK_PLLE_MASK) {
	64	+ rc = 0;
	65	+ break;
	66	+ }
	67	+ retry_count++;
	68	+ }
	69	+
	70	+ if (rc == -1) {
	71	+ printf("%s: ETH-PLL lock timeout, Ethernet is not enabled!\n",
	72	+ __func__);
	73	+ return -1;
	74	+ }
	75	+
	76	+ writel(readl(PLLE_POST_RESETB_ADDR) \|
	77	+ PLLE_POST_RESETB_I_POST_RESETB_PLLE_MASK,
	78	+ PLLE_POST_RESETB_ADDR);
	79	+
	80	+ /* Switch esw_sys_clk to use 104MHz(208MHz/2) clock */
	81	+ writel((readl(ESW_SYS_DIV_ADDR) &
	82	+ ~(ESW_SYS_DIV_PLL_SELECT_MASK \| ESW_SYS_DIV_DIV_MASK)) \|
	83	+ ESW_SYS_DIV_PLL_VAR_208M_CLK_SELECT \| ESW_SYS_DIV_DIV_SELECT,
	84	+ ESW_SYS_DIV_ADDR);
	85	+
	86	+ writel(readl(ESW_SYS_DIV_ADDR) \| ESW_SYS_DIV_TRIGGER_MASK,
	87	+ ESW_SYS_DIV_ADDR);
	88	+
	89	+ /* Wait for trigger complete */
	90	+ rc = -1;
	91	+ retry_count = 0;
	92	+ while (retry_count < PLL_MAX_RETRY) {
	93	+ udelay(100);
	94	+ if (!(readl(ESW_SYS_DIV_ADDR) & ESW_SYS_DIV_TRIGGER_MASK)) {
	95	+ rc = 0;
	96	+ break;
	97	+ }
	98	+ retry_count++;
	99	+ }
	100	+
	101	+ if (rc == -1) {
	102	+ printf("%s: SYS CLK Trigger timeout, Ethernet is not enabled!\n",
	103	+ __func__);
	104	+ return -1;
	105	+ }
	106	+
	107	+ /* switch Esub AXI clock to 208MHz */
	108	+ writel((readl(ESUB_AXI_DIV_DEBUG_ADDR) &
	109	+ ~(ESUB_AXI_DIV_DEBUG_PLL_SELECT_MASK \|
	110	+ ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK \|
	111	+ ESUB_AXI_DIV_DEBUG_TRIGGER_MASK)) \|
	112	+ ESUB_AXI_DIV_DEBUG_PLL_VAR_208M_CLK_SELECT \|
	113	+ ESUB_AXI_DIV_DEBUG_PLL_SELECT_OVERRIDE_MASK,
	114	+ ESUB_AXI_DIV_DEBUG_ADDR);
	115	+
	116	+ writel(readl(ESUB_AXI_DIV_DEBUG_ADDR) \|
	117	+ ESUB_AXI_DIV_DEBUG_TRIGGER_MASK,
	118	+ ESUB_AXI_DIV_DEBUG_ADDR);
	119	+
	120	+ /* Wait for trigger complete */
	121	+ rc = -1;
	122	+ retry_count = 0;
	123	+ while (retry_count < PLL_MAX_RETRY) {
	124	+ udelay(100);
	125	+ if (!(readl(ESUB_AXI_DIV_DEBUG_ADDR) &
	126	+ ESUB_AXI_DIV_DEBUG_TRIGGER_MASK)) {
	127	+ rc = 0;
	128	+ break;
	129	+ }
	130	+ retry_count++;
	131	+ }
	132	+
	133	+ if (rc == -1) {
	134	+ printf("%s: AXI CLK Trigger timeout, Ethernet is not enabled!\n",
	135	+ __func__);
	136	+ return -1;
	137	+ }
	138	+
	139	+ /* Disable Access to CCU registers */
	140	+ writel(WR_ACCESS_PASSWORD, WR_ACCESS_ADDR);
	141	+
	142	+ return rc;
	143	+}
...	...	@@ -7,4 +7,5 @@
7	7	obj-y += s_init.o
8	8	obj-y += hwinit-common.o
9	9	obj-y += clk-stubs.o
	10	+obj-${CONFIG_KONA_RESET_S} += reset.o
	1	+if TARGET_BCM23550_W1D
	2	+
	3	+config SYS_BOARD
	4	+ default "bcm23550_w1d"
	5	+
	6	+config SYS_VENDOR
	7	+ default "broadcom"
	8	+
	9	+config SYS_SOC
	10	+ default "bcm235xx"
	11	+
	12	+config SYS_CONFIG_NAME
	13	+ default "bcm23550_w1d"
	14	+
	15	+endif
	1	+BCM23550_W1D BOARD
	2	+M: Steve Rae <srae@broadcom.com>
	3	+S: Maintained
	4	+F: board/broadcom/bcm23550_w1d/
	5	+F: include/configs/bcm23550_w1d.h
	6	+F: configs/bcm23550_w1d_defconfig
	1	+#
	2	+# Copyright 2013 Broadcom Corporation.
	3	+#
	4	+# SPDX-License-Identifier: GPL-2.0+
	5	+#
	6	+
	7	+obj-y += bcm23550_w1d.o
	1	+CONFIG_ARM=y
	2	+CONFIG_TARGET_BCM23550_W1D=y
	3	+CONFIG_HUSH_PARSER=y
	4	+CONFIG_CMD_BOOTZ=y
	5	+# CONFIG_CMD_IMLS is not set
	6	+CONFIG_CMD_ASKENV=y
	7	+# CONFIG_CMD_FLASH is not set
	8	+CONFIG_CMD_MMC=y
	9	+CONFIG_CMD_I2C=y
	10	+CONFIG_CMD_GPIO=y
	11	+# CONFIG_CMD_SETEXPR is not set
	12	+# CONFIG_CMD_NET is not set
	13	+# CONFIG_CMD_NFS is not set
	14	+CONFIG_CMD_CACHE=y
	15	+CONFIG_CMD_FAT=y
	16	+CONFIG_SYS_NS16550=y
	17	+CONFIG_USB=y
	18	+CONFIG_USB_GADGET=y
	19	+CONFIG_USB_GADGET_DWC2_OTG=y
	20	+CONFIG_USB_GADGET_DOWNLOAD=y
	21	+CONFIG_G_DNL_MANUFACTURER="Broadcom Corporation"
	22	+CONFIG_G_DNL_VENDOR_NUM=0x18d1
	23	+CONFIG_G_DNL_PRODUCT_NUM=0x0d02
	24	+CONFIG_OF_LIBFDT=y