MIPS: add support for Broadcom MIPS BCM6368 SoC family

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>

MIPS: add support for Broadcom MIPS BCM6368 SoC family
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
Álvaro Fernández Rojas · Daniel Schwierzeck
1 parent 8c8ef2e825
Showing 5 changed files with 263 additions and 0 deletions Side-by-side Diff
arch/mips/dts/brcm,bcm6368.dtsi
arch/mips/mach-bmips/Kconfig
include/configs/bmips_bcm6368.h
include/dt-bindings/clock/bcm6368-clock.h
include/dt-bindings/reset/bcm6368-reset.h
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <dt-bindings/clock/bcm6368-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/reset/bcm6368-reset.h>
+#include "skeleton.dtsi"
+
+/ {
+	compatible = "brcm,bcm6368";
+
+	aliases {
+		spi0 = &spi;
+	};
+
+	cpus {
+		reg = <0x10000000 0x4>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		u-boot,dm-pre-reloc;
+
+		cpu@0 {
+			compatible = "brcm,bcm6368-cpu", "mips,mips4Kc";
+			device_type = "cpu";
+			reg = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		cpu@1 {
+			compatible = "brcm,bcm6368-cpu", "mips,mips4Kc";
+			device_type = "cpu";
+			reg = <1>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	clocks {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		u-boot,dm-pre-reloc;
+
+		periph_osc: periph-osc {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <50000000>;
+			u-boot,dm-pre-reloc;
+		};
+
+		periph_clk: periph-clk {
+			compatible = "brcm,bcm6345-clk";
+			reg = <0x10000004 0x4>;
+			#clock-cells = <1>;
+		};
+	};
+
+	pflash: nor@18000000 {
+		compatible = "cfi-flash";
+		reg = <0x18000000 0x2000000>;
+		bank-width = <2>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		status = "disabled";
+	};
+
+	ubus {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		u-boot,dm-pre-reloc;
+
+		pll_cntl: syscon@10000008 {
+			compatible = "syscon";
+			reg = <0x10000008 0x4>;
+		};
+
+		syscon-reboot {
+			compatible = "syscon-reboot";
+			regmap = <&pll_cntl>;
+			offset = <0x0>;
+			mask = <0x1>;
+		};
+
+		periph_rst: reset-controller@10000010 {
+			compatible = "brcm,bcm6345-reset";
+			reg = <0x10000010 0x4>;
+			#reset-cells = <1>;
+		};
+
+		wdt: watchdog@1000005c {
+			compatible = "brcm,bcm6345-wdt";
+			reg = <0x1000005c 0xc>;
+			clocks = <&periph_osc>;
+		};
+
+		wdt-reboot {
+			compatible = "wdt-reboot";
+			wdt = <&wdt>;
+		};
+
+		gpio1: gpio-controller@10000080 {
+			compatible = "brcm,bcm6345-gpio";
+			reg = <0x10000080 0x4>, <0x10000088 0x4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <6>;
+
+			status = "disabled";
+		};
+
+		gpio0: gpio-controller@10000084 {
+			compatible = "brcm,bcm6345-gpio";
+			reg = <0x10000084 0x4>, <0x1000008c 0x4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			status = "disabled";
+		};
+
+		leds: led-controller@100000d0 {
+			compatible = "brcm,bcm6358-leds";
+			reg = <0x100000d0 0x8>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			status = "disabled";
+		};
+
+		uart0: serial@10000100 {
+			compatible = "brcm,bcm6345-uart";
+			reg = <0x10000100 0x18>;
+			clocks = <&periph_osc>;
+
+			status = "disabled";
+		};
+
+		uart1: serial@10000120 {
+			compatible = "brcm,bcm6345-uart";
+			reg = <0x10000120 0x18>;
+			clocks = <&periph_osc>;
+
+			status = "disabled";
+		};
+
+		spi: spi@10000800 {
+			compatible = "brcm,bcm6358-spi";
+			reg = <0x10000800 0x70c>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&periph_clk BCM6368_CLK_SPI>;
+			resets = <&periph_rst BCM6368_RST_SPI>;
+			spi-max-frequency = <20000000>;
+			num-cs = <6>;
+
+			status = "disabled";
+		};
+
+		memory-controller@10001200 {
+			compatible = "brcm,bcm6358-mc";
+			reg = <0x10001200 0x4c>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+};
@@ -10,6 +10,7 @@
 	default "bcm6338" if SOC_BMIPS_BCM6338
 	default "bcm6348" if SOC_BMIPS_BCM6348
 	default "bcm6358" if SOC_BMIPS_BCM6358
+	default "bcm6368" if SOC_BMIPS_BCM6368
 	default "bcm63268" if SOC_BMIPS_BCM63268
  
 choice
@@ -69,6 +70,17 @@
 	select SYSRESET_SYSCON
 	help
 	  This supports BMIPS BCM6358 family including BCM6358 and BCM6359.
+
+config SOC_BMIPS_BCM6368
+	bool "BMIPS BCM6368 family"
+	select SUPPORTS_BIG_ENDIAN
+	select SUPPORTS_CPU_MIPS32_R1
+	select MIPS_TUNE_4KC
+	select MIPS_L1_CACHE_SHIFT_4
+	select SWAP_IO_SPACE
+	select SYSRESET_SYSCON
+	help
+	  This supports BMIPS BCM6368 family including BCM6368 and BCM6369.
  
 config SOC_BMIPS_BCM63268
 	bool "BMIPS BCM63268 family"
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_BMIPS_BCM6368_H
+#define __CONFIG_BMIPS_BCM6368_H
+
+/* CPU */
+#define CONFIG_SYS_MIPS_TIMER_FREQ	200000000
+
+/* RAM */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+
+/* U-Boot */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE + 0x100000
+
+#if defined(CONFIG_BMIPS_BOOT_RAM)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_INIT_SP_OFFSET	0x2000
+#endif
+
+#define CONFIG_SYS_FLASH_BASE			0xb8000000
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT	1
+
+#endif /* __CONFIG_BMIPS_BCM6368_H */
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BCM6368_H
+#define __DT_BINDINGS_CLOCK_BCM6368_H
+
+#define BCM6368_CLK_VDSL_QPROC		2
+#define BCM6368_CLK_VDSL_AFE		3
+#define BCM6368_CLK_VDSL_BONDING	4
+#define BCM6368_CLK_VDSL		5
+#define BCM6368_CLK_PHYMIPS		6
+#define BCM6368_CLK_SWPKT_USB		7
+#define BCM6368_CLK_SWPKT_SAR		8
+#define BCM6368_CLK_SPI			9
+#define BCM6368_CLK_USBD		10
+#define BCM6368_CLK_SAR			11
+#define BCM6368_CLK_ROBOSW		12
+#define BCM6368_CLK_UTOPIA		13
+#define BCM6368_CLK_PCM			14
+#define BCM6368_CLK_USBH		15
+#define BCM6368_CLK_GLESS		16
+#define BCM6368_CLK_NAND		17
+#define BCM6368_CLK_IPSEC		18
+#define BCM6368_CLK_USBH_IDDQ		19
+
+#endif /* __DT_BINDINGS_CLOCK_BCM6368_H */
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_RESET_BCM6368_H
+#define __DT_BINDINGS_RESET_BCM6368_H
+
+#define BCM6368_RST_SPI		0
+#define BCM6368_RST_MPI		3
+#define BCM6368_RST_IPSEC	4
+#define BCM6368_RST_EPHY	6
+#define BCM6368_RST_SAR		7
+#define BCM6368_RST_SWITCH	10
+#define BCM6368_RST_USBD	11
+#define BCM6368_RST_USBH	12
+#define BCM6368_RST_PCM		13
+
+#endif /* __DT_BINDINGS_RESET_BCM6368_H */
	1	+/*
	2	+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
	3	+ *
	4	+ * SPDX-License-Identifier: GPL-2.0+
	5	+ */
	6	+
	7	+#include <dt-bindings/clock/bcm6368-clock.h>
	8	+#include <dt-bindings/gpio/gpio.h>
	9	+#include <dt-bindings/reset/bcm6368-reset.h>
	10	+#include "skeleton.dtsi"
	11	+
	12	+/ {
	13	+ compatible = "brcm,bcm6368";
	14	+
	15	+ aliases {
	16	+ spi0 = &spi;
	17	+ };
	18	+
	19	+ cpus {
	20	+ reg = <0x10000000 0x4>;
	21	+ #address-cells = <1>;
	22	+ #size-cells = <0>;
	23	+ u-boot,dm-pre-reloc;
	24	+
	25	+ cpu@0 {
	26	+ compatible = "brcm,bcm6368-cpu", "mips,mips4Kc";
	27	+ device_type = "cpu";
	28	+ reg = <0>;
	29	+ u-boot,dm-pre-reloc;
	30	+ };
	31	+
	32	+ cpu@1 {
	33	+ compatible = "brcm,bcm6368-cpu", "mips,mips4Kc";
	34	+ device_type = "cpu";
	35	+ reg = <1>;
	36	+ u-boot,dm-pre-reloc;
	37	+ };
	38	+ };
	39	+
	40	+ clocks {
	41	+ compatible = "simple-bus";
	42	+ #address-cells = <1>;
	43	+ #size-cells = <1>;
	44	+ u-boot,dm-pre-reloc;
	45	+
	46	+ periph_osc: periph-osc {
	47	+ compatible = "fixed-clock";
	48	+ #clock-cells = <0>;
	49	+ clock-frequency = <50000000>;
	50	+ u-boot,dm-pre-reloc;
	51	+ };
	52	+
	53	+ periph_clk: periph-clk {
	54	+ compatible = "brcm,bcm6345-clk";
	55	+ reg = <0x10000004 0x4>;
	56	+ #clock-cells = <1>;
	57	+ };
	58	+ };
	59	+
	60	+ pflash: nor@18000000 {
	61	+ compatible = "cfi-flash";
	62	+ reg = <0x18000000 0x2000000>;
	63	+ bank-width = <2>;
	64	+ #address-cells = <1>;
	65	+ #size-cells = <1>;
	66	+
	67	+ status = "disabled";
	68	+ };
	69	+
	70	+ ubus {
	71	+ compatible = "simple-bus";
	72	+ #address-cells = <1>;
	73	+ #size-cells = <1>;
	74	+ u-boot,dm-pre-reloc;
	75	+
	76	+ pll_cntl: syscon@10000008 {
	77	+ compatible = "syscon";
	78	+ reg = <0x10000008 0x4>;
	79	+ };
	80	+
	81	+ syscon-reboot {
	82	+ compatible = "syscon-reboot";
	83	+ regmap = <&pll_cntl>;
	84	+ offset = <0x0>;
	85	+ mask = <0x1>;
	86	+ };
	87	+
	88	+ periph_rst: reset-controller@10000010 {
	89	+ compatible = "brcm,bcm6345-reset";
	90	+ reg = <0x10000010 0x4>;
	91	+ #reset-cells = <1>;
	92	+ };
	93	+
	94	+ wdt: watchdog@1000005c {
	95	+ compatible = "brcm,bcm6345-wdt";
	96	+ reg = <0x1000005c 0xc>;
	97	+ clocks = <&periph_osc>;
	98	+ };
	99	+
	100	+ wdt-reboot {
	101	+ compatible = "wdt-reboot";
	102	+ wdt = <&wdt>;
	103	+ };
	104	+
	105	+ gpio1: gpio-controller@10000080 {
	106	+ compatible = "brcm,bcm6345-gpio";
	107	+ reg = <0x10000080 0x4>, <0x10000088 0x4>;
	108	+ gpio-controller;
	109	+ #gpio-cells = <2>;
	110	+ ngpios = <6>;
	111	+
	112	+ status = "disabled";
	113	+ };
	114	+
	115	+ gpio0: gpio-controller@10000084 {
	116	+ compatible = "brcm,bcm6345-gpio";
	117	+ reg = <0x10000084 0x4>, <0x1000008c 0x4>;
	118	+ gpio-controller;
	119	+ #gpio-cells = <2>;
	120	+
	121	+ status = "disabled";
	122	+ };
	123	+
	124	+ leds: led-controller@100000d0 {
	125	+ compatible = "brcm,bcm6358-leds";
	126	+ reg = <0x100000d0 0x8>;
	127	+ #address-cells = <1>;
	128	+ #size-cells = <0>;
	129	+
	130	+ status = "disabled";
	131	+ };
	132	+
	133	+ uart0: serial@10000100 {
	134	+ compatible = "brcm,bcm6345-uart";
	135	+ reg = <0x10000100 0x18>;
	136	+ clocks = <&periph_osc>;
	137	+
	138	+ status = "disabled";
	139	+ };
	140	+
	141	+ uart1: serial@10000120 {
	142	+ compatible = "brcm,bcm6345-uart";
	143	+ reg = <0x10000120 0x18>;
	144	+ clocks = <&periph_osc>;
	145	+
	146	+ status = "disabled";
	147	+ };
	148	+
	149	+ spi: spi@10000800 {
	150	+ compatible = "brcm,bcm6358-spi";
	151	+ reg = <0x10000800 0x70c>;
	152	+ #address-cells = <1>;
	153	+ #size-cells = <0>;
	154	+ clocks = <&periph_clk BCM6368_CLK_SPI>;
	155	+ resets = <&periph_rst BCM6368_RST_SPI>;
	156	+ spi-max-frequency = <20000000>;
	157	+ num-cs = <6>;
	158	+
	159	+ status = "disabled";
	160	+ };
	161	+
	162	+ memory-controller@10001200 {
	163	+ compatible = "brcm,bcm6358-mc";
	164	+ reg = <0x10001200 0x4c>;
	165	+ u-boot,dm-pre-reloc;
	166	+ };
	167	+ };
	168	+};
...	...	@@ -10,6 +10,7 @@
10	10	default "bcm6338" if SOC_BMIPS_BCM6338
11	11	default "bcm6348" if SOC_BMIPS_BCM6348
12	12	default "bcm6358" if SOC_BMIPS_BCM6358
	13	+ default "bcm6368" if SOC_BMIPS_BCM6368
13	14	default "bcm63268" if SOC_BMIPS_BCM63268
14	15
15	16	choice
...	...	@@ -69,6 +70,17 @@
69	70	select SYSRESET_SYSCON
70	71	help
71	72	This supports BMIPS BCM6358 family including BCM6358 and BCM6359.
	73	+
	74	+config SOC_BMIPS_BCM6368
	75	+ bool "BMIPS BCM6368 family"
	76	+ select SUPPORTS_BIG_ENDIAN
	77	+ select SUPPORTS_CPU_MIPS32_R1
	78	+ select MIPS_TUNE_4KC
	79	+ select MIPS_L1_CACHE_SHIFT_4
	80	+ select SWAP_IO_SPACE
	81	+ select SYSRESET_SYSCON
	82	+ help
	83	+ This supports BMIPS BCM6368 family including BCM6368 and BCM6369.
72	84
73	85	config SOC_BMIPS_BCM63268
74	86	bool "BMIPS BCM63268 family"
	1	+/*
	2	+ * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
	3	+ *
	4	+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
	5	+ *
	6	+ * SPDX-License-Identifier: GPL-2.0+
	7	+ */
	8	+
	9	+#ifndef __DT_BINDINGS_CLOCK_BCM6368_H
	10	+#define __DT_BINDINGS_CLOCK_BCM6368_H
	11	+
	12	+#define BCM6368_CLK_VDSL_QPROC 2
	13	+#define BCM6368_CLK_VDSL_AFE 3
	14	+#define BCM6368_CLK_VDSL_BONDING 4
	15	+#define BCM6368_CLK_VDSL 5
	16	+#define BCM6368_CLK_PHYMIPS 6
	17	+#define BCM6368_CLK_SWPKT_USB 7
	18	+#define BCM6368_CLK_SWPKT_SAR 8
	19	+#define BCM6368_CLK_SPI 9
	20	+#define BCM6368_CLK_USBD 10
	21	+#define BCM6368_CLK_SAR 11
	22	+#define BCM6368_CLK_ROBOSW 12
	23	+#define BCM6368_CLK_UTOPIA 13
	24	+#define BCM6368_CLK_PCM 14
	25	+#define BCM6368_CLK_USBH 15
	26	+#define BCM6368_CLK_GLESS 16
	27	+#define BCM6368_CLK_NAND 17
	28	+#define BCM6368_CLK_IPSEC 18
	29	+#define BCM6368_CLK_USBH_IDDQ 19
	30	+
	31	+#endif /* __DT_BINDINGS_CLOCK_BCM6368_H */