Commit 43d9616cffb4a130e1620e3e33fc9bc1bcabe399
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* Patch by Robert Schwebel, 21 Jan 2003:
- Add support for Innokom board - Don't complain if "install" fails - README cleanup (remove duplicated lines) - Update PXA header files * Add documentation for existing POST code (doc/README.POST) * Patch by Laudney Ren, 15 Jan 2003: Fix handling of redundand environment in "tools/envcrc.c" * Patch by Detlev Zundel, 28 Feb 2003: Add bedbug support for 824x systems * Add support for 16 MB flash configuration of TRAB board * Patch by Erwin Rol, 27 Feb 2003: Add support for RTEMS * Add image information to README * Fix dual PCMCIA slot support (when running with just one slot populated) * Add VFD type detection to trab board * extend drivers/cs8900.c driver to synchronize ethaddr environment variable with value in the EEPROM
Showing 26 changed files with 3495 additions and 391 deletions Side-by-side Diff
- CHANGELOG
- CREDITS
- MAINTAINERS
- MAKEALL
- Makefile
- README
- board/innokom/Makefile
- board/innokom/config.mk
- board/innokom/flash.c
- board/innokom/innokom.c
- board/innokom/memsetup.S
- board/innokom/u-boot.lds
- board/r360mpi/flash.c
- common/env_flash.c
- cpu/mpc824x/Makefile
- cpu/mpc824x/start.S
- cpu/mpc824x/traps.c
- cpu/xscale/Makefile
- cpu/xscale/i2c.c
- doc/README.POST
- include/asm-arm/arch-pxa/pxa-regs.h
- include/asm-arm/arch-xscale/pxa-regs.h
- include/asm-arm/proc-armv/ptrace.h
- include/configs/innokom.h
- include/configs/trab.h
- tools/envcrc.c
CHANGELOG
1 | 1 | ====================================================================== |
2 | -Changes since U-Boot 0.2.1: | |
2 | +Changes since U-Boot 0.2.2: | |
3 | 3 | ====================================================================== |
4 | 4 | |
5 | +* Patch by Robert Schwebel, 21 Jan 2003: | |
6 | + - Add support for Innokom board | |
7 | + - Don't complain if "install" fails | |
8 | + - README cleanup (remove duplicated lines) | |
9 | + - Update PXA header files | |
10 | + | |
11 | +* Add documentation for existing POST code (doc/README.POST) | |
12 | + | |
13 | +* Patch by Laudney Ren, 15 Jan 2003: | |
14 | + Fix handling of redundand environment in "tools/envcrc.c" | |
15 | + | |
16 | +* Patch by Detlev Zundel, 28 Feb 2003: | |
17 | + Add bedbug support for 824x systems | |
18 | + | |
19 | +* Add support for 16 MB flash configuration of TRAB board | |
20 | + | |
21 | +* Patch by Erwin Rol, 27 Feb 2003: | |
22 | + Add support for RTEMS | |
23 | + | |
24 | +* Add image information to README | |
25 | + | |
5 | 26 | * Patch by Stefan Roese, 18 Feb 2003: |
6 | 27 | CPCIISER4 configuration updated. |
7 | 28 | |
8 | 29 | |
... | ... | @@ -14,8 +35,20 @@ |
14 | 35 | PCI spec 2.2 defines, that a pci target has 2^25 pci clocks after |
15 | 36 | RST# to respond to configuration cycles (33MHz -> 1s). |
16 | 37 | |
38 | +* Fix dual PCMCIA slot support (when running with just one | |
39 | + slot populated) | |
40 | + | |
41 | +* Add VFD type detection to trab board | |
42 | + | |
43 | +* extend drivers/cs8900.c driver to synchronize ethaddr environment | |
44 | + variable with value in the EEPROM | |
45 | + | |
17 | 46 | * Patch by Stefan Roese, 10 Feb 2003: |
18 | 47 | Add support for 4MB and 128MB onboard SDRAM (cpu/ppc4xx/sdram.c) |
48 | + | |
49 | +====================================================================== | |
50 | +Changes for U-Boot 0.2.2: | |
51 | +====================================================================== | |
19 | 52 | |
20 | 53 | * Add dual ethernet support on PM826 |
21 | 54 |
CREDITS
MAINTAINERS
... | ... | @@ -246,6 +246,7 @@ |
246 | 246 | Robert Schwebel <r.schwebel@pengutronix.de> |
247 | 247 | |
248 | 248 | csb226 xscale |
249 | + innokom xscale | |
249 | 250 | |
250 | 251 | Alex Zรผpke <azu@sysgo.de> |
251 | 252 | |
... | ... | @@ -262,6 +263,17 @@ |
262 | 263 | Daniel Engstrรถm <daniel@omicron.se> |
263 | 264 | |
264 | 265 | sc520_cdp x86 |
266 | + | |
267 | +######################################################################### | |
268 | +# MIPS Systems: # | |
269 | +# # | |
270 | +# Maintainer Name, Email Address # | |
271 | +# Board CPU # | |
272 | +######################################################################### | |
273 | + | |
274 | +Wolfgang Denk <wd@denx.de> | |
275 | + | |
276 | + incaip MIPS32 4Kc | |
265 | 277 | |
266 | 278 | ######################################################################### |
267 | 279 | # End of MAINTAINERS list # |
MAKEALL
... | ... | @@ -101,7 +101,7 @@ |
101 | 101 | ## Xscale Systems |
102 | 102 | ######################################################################### |
103 | 103 | |
104 | -LIST_xscale="lubbock cradle csb226" | |
104 | +LIST_xscale="lubbock cradle csb226 innokom" | |
105 | 105 | |
106 | 106 | |
107 | 107 | LIST_arm="${LIST_SA} ${LIST_ARM7} ${LIST_ARM9} ${LIST_xscale}" |
Makefile
... | ... | @@ -77,8 +77,11 @@ |
77 | 77 | ifeq ($(ARCH),i386) |
78 | 78 | #CROSS_COMPILE = i386-elf- |
79 | 79 | endif |
80 | +ifeq ($(ARCH),mips) | |
81 | +CROSS_COMPILE = mips_4KC- | |
80 | 82 | endif |
81 | 83 | endif |
84 | +endif | |
82 | 85 | |
83 | 86 | export CROSS_COMPILE |
84 | 87 | |
... | ... | @@ -129,8 +132,8 @@ |
129 | 132 | all: u-boot.srec u-boot.bin System.map |
130 | 133 | |
131 | 134 | install: all |
132 | - cp u-boot.bin /tftpboot/u-boot.bin | |
133 | - cp u-boot.bin /net/sam/tftpboot/u-boot.bin | |
135 | + -cp u-boot.bin /tftpboot/u-boot.bin | |
136 | + -cp u-boot.bin /net/denx/tftpboot/u-boot.bin | |
134 | 137 | |
135 | 138 | u-boot.srec: u-boot |
136 | 139 | $(OBJCOPY) ${OBJCFLAGS} -O srec $< $@ |
137 | 140 | |
... | ... | @@ -611,14 +614,22 @@ |
611 | 614 | ## ARM920T Systems |
612 | 615 | ######################################################################### |
613 | 616 | |
617 | +xtract_trab = $(subst _big_flash,,$(subst _config,,$1)) | |
618 | + | |
614 | 619 | smdk2400_config : unconfig |
615 | 620 | @./mkconfig $(@:_config=) arm arm920t smdk2400 |
616 | 621 | |
617 | 622 | smdk2410_config : unconfig |
618 | 623 | @./mkconfig $(@:_config=) arm arm920t smdk2410 |
619 | 624 | |
620 | -trab_config : unconfig | |
621 | - @./mkconfig $(@:_config=) arm arm920t trab | |
625 | +trab_config \ | |
626 | +trab_big_flash_config: unconfig | |
627 | + @ >include/config.h | |
628 | + @[ -z "$(findstring _big_flash,$@)" ] || \ | |
629 | + { echo "#define CONFIG_BIG_FLASH" >>include/config.h ; \ | |
630 | + echo "... with big flash support" ; \ | |
631 | + } | |
632 | + @./mkconfig -a $(call xtract_trab,$@) arm arm920t trab | |
622 | 633 | |
623 | 634 | ######################################################################### |
624 | 635 | ## ARM720T Systems |
625 | 636 | |
626 | 637 | |
... | ... | @@ -631,18 +642,21 @@ |
631 | 642 | @./mkconfig $(@:_config=) arm arm720t ep7312 |
632 | 643 | |
633 | 644 | ######################################################################### |
634 | -## Xscale Systems | |
645 | +## XScale Systems | |
635 | 646 | ######################################################################### |
636 | 647 | |
637 | -lubbock_config : unconfig | |
638 | - @./mkconfig $(@:_config=) arm xscale lubbock | |
639 | - | |
640 | 648 | cradle_config : unconfig |
641 | 649 | @./mkconfig $(@:_config=) arm xscale cradle |
642 | 650 | |
643 | 651 | csb226_config : unconfig |
644 | 652 | @./mkconfig $(@:_config=) arm xscale csb226 |
645 | 653 | |
654 | +innokom_config : unconfig | |
655 | + @./mkconfig $(@:_config=) arm xscale innokom | |
656 | + | |
657 | +lubbock_config : unconfig | |
658 | + @./mkconfig $(@:_config=) arm xscale lubbock | |
659 | + | |
646 | 660 | #======================================================================== |
647 | 661 | # i386 |
648 | 662 | #======================================================================== |
649 | 663 | |
650 | 664 | |
... | ... | @@ -652,8 +666,18 @@ |
652 | 666 | sc520_cdp_config : unconfig |
653 | 667 | @./mkconfig $(@:_config=) i386 i386 sc520_cdp |
654 | 668 | |
669 | +#======================================================================== | |
670 | +# MIPS | |
671 | +#======================================================================== | |
655 | 672 | ######################################################################### |
673 | +## MIPS32 4Kc | |
674 | +######################################################################### | |
656 | 675 | |
676 | +incaip_config : unconfig | |
677 | + @./mkconfig $(@:_config=) mips mips incaip | |
678 | + | |
679 | + | |
680 | + | |
657 | 681 | clean: |
658 | 682 | find . -type f \ |
659 | 683 | \( -name 'core' -o -name '*.bak' -o -name '*~' \ |
... | ... | @@ -674,6 +698,7 @@ |
674 | 698 | rm -fr *.*~ |
675 | 699 | rm -f u-boot u-boot.bin u-boot.elf u-boot.srec u-boot.map System.map |
676 | 700 | rm -f tools/crc32.c tools/environment.c tools/env/crc32.c |
701 | + rm -f cpu/mpc824x/bedbug_603e.c | |
677 | 702 | rm -f include/asm/arch include/asm |
678 | 703 | |
679 | 704 | mrproper \ |
README
... | ... | @@ -395,10 +395,10 @@ |
395 | 395 | default environment. |
396 | 396 | |
397 | 397 | - Console Interface: |
398 | - Depending on board, define exactly one serial port | |
399 | - (like CONFIG_8xx_CONS_SMC1, CONFIG_8xx_CONS_SMC2, | |
400 | - CONFIG_8xx_CONS_SCC1, ...), or switch off the serial | |
401 | - console by defining CONFIG_8xx_CONS_NONE | |
398 | + Depending on board, define exactly one serial port | |
399 | + (like CONFIG_8xx_CONS_SMC1, CONFIG_8xx_CONS_SMC2, | |
400 | + CONFIG_8xx_CONS_SCC1, ...), or switch off the serial | |
401 | + console by defining CONFIG_8xx_CONS_NONE | |
402 | 402 | |
403 | 403 | Note: if CONFIG_8xx_CONS_NONE is defined, the serial |
404 | 404 | port routines must be defined elsewhere |
... | ... | @@ -443,9 +443,9 @@ |
443 | 443 | addional board info beside |
444 | 444 | the logo |
445 | 445 | |
446 | - When CONFIG_CFB_CONSOLE is defined, video console is | |
447 | - default i/o. Serial console can be forced with | |
448 | - environment 'console=serial'. | |
446 | + When CONFIG_CFB_CONSOLE is defined, video console is | |
447 | + default i/o. Serial console can be forced with | |
448 | + environment 'console=serial'. | |
449 | 449 | |
450 | 450 | - Console Baudrate: |
451 | 451 | CONFIG_BAUDRATE - in bps |
452 | 452 | |
... | ... | @@ -489,15 +489,15 @@ |
489 | 489 | within "Boot Delay" after reset. |
490 | 490 | |
491 | 491 | CONFIG_BOOTARGS |
492 | - This can be used to pass arguments to the bootm | |
493 | - command. The value of CONFIG_BOOTARGS goes into the | |
494 | - environment value "bootargs". | |
492 | + This can be used to pass arguments to the bootm | |
493 | + command. The value of CONFIG_BOOTARGS goes into the | |
494 | + environment value "bootargs". | |
495 | 495 | |
496 | 496 | CONFIG_RAMBOOT and CONFIG_NFSBOOT |
497 | - The value of these goes into the environment as | |
498 | - "ramboot" and "nfsboot" respectively, and can be used | |
499 | - as a convenience, when switching between booting from | |
500 | - ram and nfs. | |
497 | + The value of these goes into the environment as | |
498 | + "ramboot" and "nfsboot" respectively, and can be used | |
499 | + as a convenience, when switching between booting from | |
500 | + ram and nfs. | |
501 | 501 | |
502 | 502 | - Pre-Boot Commands: |
503 | 503 | CONFIG_PREBOOT |
... | ... | @@ -596,13 +596,13 @@ |
596 | 596 | |
597 | 597 | |
598 | 598 | Note: Don't enable the "icache" and "dcache" commands |
599 | - (configuration option CFG_CMD_CACHE) unless you know | |
600 | - what you (and your U-Boot users) are doing. Data | |
601 | - cache cannot be enabled on systems like the 8xx or | |
602 | - 8260 (where accesses to the IMMR region must be | |
603 | - uncached), and it cannot be disabled on all other | |
604 | - systems where we (mis-) use the data cache to hold an | |
605 | - initial stack and some data. | |
599 | + (configuration option CFG_CMD_CACHE) unless you know | |
600 | + what you (and your U-Boot users) are doing. Data | |
601 | + cache cannot be enabled on systems like the 8xx or | |
602 | + 8260 (where accesses to the IMMR region must be | |
603 | + uncached), and it cannot be disabled on all other | |
604 | + systems where we (mis-) use the data cache to hold an | |
605 | + initial stack and some data. | |
606 | 606 | |
607 | 607 | |
608 | 608 | XXX - this list needs to get updated! |
... | ... | @@ -628,10 +628,10 @@ |
628 | 628 | |
629 | 629 | - Timestamp Support: |
630 | 630 | |
631 | - When CONFIG_TIMESTAMP is selected, the timestamp | |
632 | - (date and time) of an image is printed by image | |
633 | - commands like bootm or iminfo. This option is | |
634 | - automatically enabled when you select CFG_CMD_DATE . | |
631 | + When CONFIG_TIMESTAMP is selected, the timestamp | |
632 | + (date and time) of an image is printed by image | |
633 | + commands like bootm or iminfo. This option is | |
634 | + automatically enabled when you select CFG_CMD_DATE . | |
635 | 635 | |
636 | 636 | - Partition Support: |
637 | 637 | CONFIG_MAC_PARTITION and/or CONFIG_DOS_PARTITION |
638 | 638 | |
... | ... | @@ -720,14 +720,14 @@ |
720 | 720 | standard LiLo mode numbers. |
721 | 721 | Following modes are supported (* is default): |
722 | 722 | |
723 | - 800x600 1024x768 1280x1024 | |
724 | - 256 (8bit) 303* 305 307 | |
725 | - 65536 (16bit) 314 317 31a | |
726 | - 16,7 Mill (24bit) 315 318 31b | |
723 | + 800x600 1024x768 1280x1024 | |
724 | + 256 (8bit) 303* 305 307 | |
725 | + 65536 (16bit) 314 317 31a | |
726 | + 16,7 Mill (24bit) 315 318 31b | |
727 | 727 | (i.e. setenv videomode 317; saveenv; reset;) |
728 | 728 | |
729 | 729 | CONFIG_VIDEO_SED13806 |
730 | - Enable Epson SED13806 driver. This driver supports 8bpp | |
730 | + Enable Epson SED13806 driver. This driver supports 8bpp | |
731 | 731 | and 16bpp modes defined by CONFIG_VIDEO_SED13806_8BPP |
732 | 732 | or CONFIG_VIDEO_SED13806_16BPP |
733 | 733 | |
... | ... | @@ -839,8 +839,8 @@ |
839 | 839 | either CONFIG_HARD_I2C or CONFIG_SOFT_I2C must be defined |
840 | 840 | to include the appropriate I2C driver. |
841 | 841 | |
842 | - See also: common/cmd_i2c.c for a description of the | |
843 | - command line interface. | |
842 | + See also: common/cmd_i2c.c for a description of the | |
843 | + command line interface. | |
844 | 844 | |
845 | 845 | |
846 | 846 | CONFIG_HARD_I2C |
847 | 847 | |
... | ... | @@ -855,14 +855,14 @@ |
855 | 855 | |
856 | 856 | I2C_INIT |
857 | 857 | |
858 | - (Optional). Any commands necessary to enable I2C | |
859 | - controller or configure ports. | |
858 | + (Optional). Any commands necessary to enable I2C | |
859 | + controller or configure ports. | |
860 | 860 | |
861 | 861 | I2C_PORT |
862 | 862 | |
863 | - (Only for MPC8260 CPU). The I/O port to use (the code | |
864 | - assumes both bits are on the same port). Valid values | |
865 | - are 0..3 for ports A..D. | |
863 | + (Only for MPC8260 CPU). The I/O port to use (the code | |
864 | + assumes both bits are on the same port). Valid values | |
865 | + are 0..3 for ports A..D. | |
866 | 866 | |
867 | 867 | I2C_ACTIVE |
868 | 868 | |
869 | 869 | |
870 | 870 | |
871 | 871 | |
872 | 872 | |
873 | 873 | |
874 | 874 | |
... | ... | @@ -910,40 +910,40 @@ |
910 | 910 | |
911 | 911 | CONFIG_SOFT_SPI |
912 | 912 | |
913 | - Enables a software (bit-bang) SPI driver rather than | |
914 | - using hardware support. This is a general purpose | |
915 | - driver that only requires three general I/O port pins | |
916 | - (two outputs, one input) to function. If this is | |
917 | - defined, the board configuration must define several | |
918 | - SPI configuration items (port pins to use, etc). For | |
919 | - an example, see include/configs/sacsng.h. | |
913 | + Enables a software (bit-bang) SPI driver rather than | |
914 | + using hardware support. This is a general purpose | |
915 | + driver that only requires three general I/O port pins | |
916 | + (two outputs, one input) to function. If this is | |
917 | + defined, the board configuration must define several | |
918 | + SPI configuration items (port pins to use, etc). For | |
919 | + an example, see include/configs/sacsng.h. | |
920 | 920 | |
921 | 921 | - FPGA Support: CONFIG_FPGA_COUNT |
922 | 922 | |
923 | - Specify the number of FPGA devices to support. | |
923 | + Specify the number of FPGA devices to support. | |
924 | 924 | |
925 | - CONFIG_FPGA | |
925 | + CONFIG_FPGA | |
926 | 926 | |
927 | - Used to specify the types of FPGA devices. For | |
927 | + Used to specify the types of FPGA devices. For | |
928 | 928 | example, |
929 | 929 | #define CONFIG_FPGA CFG_XILINX_VIRTEX2 |
930 | 930 | |
931 | 931 | CFG_FPGA_PROG_FEEDBACK |
932 | 932 | |
933 | - Enable printing of hash marks during FPGA | |
933 | + Enable printing of hash marks during FPGA | |
934 | 934 | configuration. |
935 | 935 | |
936 | 936 | CFG_FPGA_CHECK_BUSY |
937 | 937 | |
938 | - Enable checks on FPGA configuration interface busy | |
939 | - status by the configuration function. This option | |
940 | - will require a board or device specific function to | |
941 | - be written. | |
938 | + Enable checks on FPGA configuration interface busy | |
939 | + status by the configuration function. This option | |
940 | + will require a board or device specific function to | |
941 | + be written. | |
942 | 942 | |
943 | 943 | CONFIG_FPGA_DELAY |
944 | 944 | |
945 | - If defined, a function that provides delays in the | |
946 | - FPGA configuration driver. | |
945 | + If defined, a function that provides delays in the | |
946 | + FPGA configuration driver. | |
947 | 947 | |
948 | 948 | CFG_FPGA_CHECK_CTRLC |
949 | 949 | |
950 | 950 | |
951 | 951 | |
952 | 952 | |
... | ... | @@ -951,25 +951,25 @@ |
951 | 951 | |
952 | 952 | CFG_FPGA_CHECK_ERROR |
953 | 953 | |
954 | - Check for configuration errors during FPGA bitfile | |
955 | - loading. For example, abort during Virtex II | |
956 | - configuration if the INIT_B line goes low (which | |
957 | - indicated a CRC error). | |
954 | + Check for configuration errors during FPGA bitfile | |
955 | + loading. For example, abort during Virtex II | |
956 | + configuration if the INIT_B line goes low (which | |
957 | + indicated a CRC error). | |
958 | 958 | |
959 | 959 | CFG_FPGA_WAIT_INIT |
960 | 960 | |
961 | - Maximum time to wait for the INIT_B line to deassert | |
962 | - after PROB_B has been deasserted during a Virtex II | |
963 | - FPGA configuration sequence. The default time is 500 mS. | |
961 | + Maximum time to wait for the INIT_B line to deassert | |
962 | + after PROB_B has been deasserted during a Virtex II | |
963 | + FPGA configuration sequence. The default time is 500 mS. | |
964 | 964 | |
965 | 965 | CFG_FPGA_WAIT_BUSY |
966 | 966 | |
967 | - Maximum time to wait for BUSY to deassert during | |
968 | - Virtex II FPGA configuration. The default is 5 mS. | |
967 | + Maximum time to wait for BUSY to deassert during | |
968 | + Virtex II FPGA configuration. The default is 5 mS. | |
969 | 969 | |
970 | 970 | CFG_FPGA_WAIT_CONFIG |
971 | 971 | |
972 | - Time to wait after FPGA configuration. The default is | |
972 | + Time to wait after FPGA configuration. The default is | |
973 | 973 | 200 mS. |
974 | 974 | |
975 | 975 | - FPGA Support: CONFIG_FPGA_COUNT |
... | ... | @@ -987,10 +987,10 @@ |
987 | 987 | |
988 | 988 | CFG_FPGA_CHECK_BUSY |
989 | 989 | |
990 | - Enable checks on FPGA configuration interface busy | |
991 | - status by the configuration function. This option | |
992 | - will require a board or device specific function to | |
993 | - be written. | |
990 | + Enable checks on FPGA configuration interface busy | |
991 | + status by the configuration function. This option | |
992 | + will require a board or device specific function to | |
993 | + be written. | |
994 | 994 | |
995 | 995 | CONFIG_FPGA_DELAY |
996 | 996 | |
997 | 997 | |
998 | 998 | |
999 | 999 | |
1000 | 1000 | |
1001 | 1001 | |
... | ... | @@ -1002,44 +1002,44 @@ |
1002 | 1002 | |
1003 | 1003 | CFG_FPGA_CHECK_ERROR |
1004 | 1004 | |
1005 | - Check for configuration errors during FPGA bitfile | |
1006 | - loading. For example, abort during Virtex II | |
1007 | - configuration if the INIT_B line goes low (which | |
1008 | - indicated a CRC error). | |
1005 | + Check for configuration errors during FPGA bitfile | |
1006 | + loading. For example, abort during Virtex II | |
1007 | + configuration if the INIT_B line goes low (which | |
1008 | + indicated a CRC error). | |
1009 | 1009 | |
1010 | 1010 | CFG_FPGA_WAIT_INIT |
1011 | 1011 | |
1012 | - Maximum time to wait for the INIT_B line to deassert | |
1013 | - after PROB_B has been deasserted during a Virtex II | |
1014 | - FPGA configuration sequence. The default time is 500 | |
1015 | - mS. | |
1012 | + Maximum time to wait for the INIT_B line to deassert | |
1013 | + after PROB_B has been deasserted during a Virtex II | |
1014 | + FPGA configuration sequence. The default time is 500 | |
1015 | + mS. | |
1016 | 1016 | |
1017 | 1017 | CFG_FPGA_WAIT_BUSY |
1018 | 1018 | |
1019 | - Maximum time to wait for BUSY to deassert during | |
1020 | - Virtex II FPGA configuration. The default is 5 mS. | |
1019 | + Maximum time to wait for BUSY to deassert during | |
1020 | + Virtex II FPGA configuration. The default is 5 mS. | |
1021 | 1021 | |
1022 | 1022 | CFG_FPGA_WAIT_CONFIG |
1023 | 1023 | |
1024 | - Time to wait after FPGA configuration. The default is | |
1025 | - 200 mS. | |
1024 | + Time to wait after FPGA configuration. The default is | |
1025 | + 200 mS. | |
1026 | 1026 | |
1027 | 1027 | - Configuration Management: |
1028 | 1028 | CONFIG_IDENT_STRING |
1029 | 1029 | |
1030 | - If defined, this string will be added to the U-Boot | |
1031 | - version information (U_BOOT_VERSION) | |
1030 | + If defined, this string will be added to the U-Boot | |
1031 | + version information (U_BOOT_VERSION) | |
1032 | 1032 | |
1033 | 1033 | - Vendor Parameter Protection: |
1034 | 1034 | |
1035 | - U-Boot considers the values of the environment | |
1036 | - variables "serial#" (Board Serial Number) and | |
1037 | - "ethaddr" (Ethernet Address) to bb parameters that | |
1038 | - are set once by the board vendor / manufacturer, and | |
1039 | - protects these variables from casual modification by | |
1040 | - the user. Once set, these variables are read-only, | |
1041 | - and write or delete attempts are rejected. You can | |
1042 | - change this behviour: | |
1035 | + U-Boot considers the values of the environment | |
1036 | + variables "serial#" (Board Serial Number) and | |
1037 | + "ethaddr" (Ethernet Address) to bb parameters that | |
1038 | + are set once by the board vendor / manufacturer, and | |
1039 | + protects these variables from casual modification by | |
1040 | + the user. Once set, these variables are read-only, | |
1041 | + and write or delete attempts are rejected. You can | |
1042 | + change this behviour: | |
1043 | 1043 | |
1044 | 1044 | If CONFIG_ENV_OVERWRITE is #defined in your config |
1045 | 1045 | file, the write protection for vendor parameters is |
... | ... | @@ -1099,10 +1099,10 @@ |
1099 | 1099 | |
1100 | 1100 | CONFIG_NET_RETRY_COUNT |
1101 | 1101 | |
1102 | - This variable defines the number of retries for | |
1103 | - network operations like ARP, RARP, TFTP, or BOOTP | |
1104 | - before giving up the operation. If not defined, a | |
1105 | - default value of 5 is used. | |
1102 | + This variable defines the number of retries for | |
1103 | + network operations like ARP, RARP, TFTP, or BOOTP | |
1104 | + before giving up the operation. If not defined, a | |
1105 | + default value of 5 is used. | |
1106 | 1106 | |
1107 | 1107 | - Command Interpreter: |
1108 | 1108 | CFG_HUSH_PARSER |
1109 | 1109 | |
... | ... | @@ -1125,18 +1125,18 @@ |
1125 | 1125 | |
1126 | 1126 | Note: |
1127 | 1127 | |
1128 | - In the current implementation, the local variables | |
1129 | - space and global environment variables space are | |
1130 | - separated. Local variables are those you define by | |
1131 | - simply typing like `name=value'. To access a local | |
1132 | - variable later on, you have write `$name' or | |
1133 | - `${name}'; variable directly by typing say `$name' at | |
1134 | - the command prompt. | |
1128 | + In the current implementation, the local variables | |
1129 | + space and global environment variables space are | |
1130 | + separated. Local variables are those you define by | |
1131 | + simply typing like `name=value'. To access a local | |
1132 | + variable later on, you have write `$name' or | |
1133 | + `${name}'; variable directly by typing say `$name' at | |
1134 | + the command prompt. | |
1135 | 1135 | |
1136 | - Global environment variables are those you use | |
1137 | - setenv/printenv to work with. To run a command stored | |
1138 | - in such a variable, you need to use the run command, | |
1139 | - and you must not use the '$' sign to access them. | |
1136 | + Global environment variables are those you use | |
1137 | + setenv/printenv to work with. To run a command stored | |
1138 | + in such a variable, you need to use the run command, | |
1139 | + and you must not use the '$' sign to access them. | |
1140 | 1140 | |
1141 | 1141 | To store commands and special characters in a |
1142 | 1142 | variable, please use double quotation marks |
1143 | 1143 | |
1144 | 1144 | |
1145 | 1145 | |
1146 | 1146 | |
... | ... | @@ -1147,38 +1147,38 @@ |
1147 | 1147 | - Default Environment |
1148 | 1148 | CONFIG_EXTRA_ENV_SETTINGS |
1149 | 1149 | |
1150 | - Define this to contain any number of null terminated | |
1151 | - strings (variable = value pairs) that will be part of | |
1152 | - the default enviroment compiled into the boot image. | |
1150 | + Define this to contain any number of null terminated | |
1151 | + strings (variable = value pairs) that will be part of | |
1152 | + the default enviroment compiled into the boot image. | |
1153 | 1153 | |
1154 | - For example, place something like this in your | |
1155 | - board's config file: | |
1154 | + For example, place something like this in your | |
1155 | + board's config file: | |
1156 | 1156 | |
1157 | 1157 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
1158 | 1158 | "myvar1=value1\0" \ |
1159 | 1159 | "myvar2=value2\0" |
1160 | 1160 | |
1161 | - Warning: This method is based on knowledge about the | |
1162 | - internal format how the environment is stored by the | |
1163 | - U-Boot code. This is NOT an official, exported | |
1164 | - interface! Although it is unlikely that this format | |
1165 | - will change soon, but there is no guarantee either. | |
1161 | + Warning: This method is based on knowledge about the | |
1162 | + internal format how the environment is stored by the | |
1163 | + U-Boot code. This is NOT an official, exported | |
1164 | + interface! Although it is unlikely that this format | |
1165 | + will change soon, but there is no guarantee either. | |
1166 | 1166 | You better know what you are doing here. |
1167 | 1167 | |
1168 | - Note: overly (ab)use of the default environment is | |
1169 | - discouraged. Make sure to check other ways to preset | |
1170 | - the environment like the autoscript function or the | |
1171 | - boot command first. | |
1168 | + Note: overly (ab)use of the default environment is | |
1169 | + discouraged. Make sure to check other ways to preset | |
1170 | + the environment like the autoscript function or the | |
1171 | + boot command first. | |
1172 | 1172 | |
1173 | 1173 | - Show boot progress |
1174 | 1174 | CONFIG_SHOW_BOOT_PROGRESS |
1175 | 1175 | |
1176 | - Defining this option allows to add some board- | |
1177 | - specific code (calling a user-provided function | |
1178 | - "show_boot_progress(int)") that enables you to show | |
1179 | - the system's boot progress on some display (for | |
1180 | - example, some LED's) on your board. At the moment, | |
1181 | - the following checkpoints are implemented: | |
1176 | + Defining this option allows to add some board- | |
1177 | + specific code (calling a user-provided function | |
1178 | + "show_boot_progress(int)") that enables you to show | |
1179 | + the system's boot progress on some display (for | |
1180 | + example, some LED's) on your board. At the moment, | |
1181 | + the following checkpoints are implemented: | |
1182 | 1182 | |
1183 | 1183 | Arg Where When |
1184 | 1184 | 1 common/cmd_bootm.c before attempting to boot an image |
1185 | 1185 | |
1186 | 1186 | |
... | ... | @@ -1241,23 +1241,23 @@ |
1241 | 1241 | - Modem debug support: |
1242 | 1242 | CONFIG_MODEM_SUPPORT_DEBUG |
1243 | 1243 | |
1244 | - Enables debugging stuff (char screen[1024], dbg()) | |
1245 | - for modem support. Useful only with BDI2000. | |
1244 | + Enables debugging stuff (char screen[1024], dbg()) | |
1245 | + for modem support. Useful only with BDI2000. | |
1246 | 1246 | |
1247 | 1247 | - General: |
1248 | 1248 | |
1249 | - In the target system modem support is enabled when a | |
1250 | - specific key (key combination) is pressed during | |
1251 | - power-on. Otherwise U-Boot will boot normally | |
1252 | - (autoboot). The key_pressed() fuction is called from | |
1253 | - board_init(). Currently key_pressed() is a dummy | |
1254 | - function, returning 1 and thus enabling modem | |
1255 | - initialization. | |
1249 | + In the target system modem support is enabled when a | |
1250 | + specific key (key combination) is pressed during | |
1251 | + power-on. Otherwise U-Boot will boot normally | |
1252 | + (autoboot). The key_pressed() fuction is called from | |
1253 | + board_init(). Currently key_pressed() is a dummy | |
1254 | + function, returning 1 and thus enabling modem | |
1255 | + initialization. | |
1256 | 1256 | |
1257 | - If there are no modem init strings in the | |
1258 | - environment, U-Boot proceed to autoboot; the | |
1259 | - previous output (banner, info printfs) will be | |
1260 | - supressed, though. | |
1257 | + If there are no modem init strings in the | |
1258 | + environment, U-Boot proceed to autoboot; the | |
1259 | + previous output (banner, info printfs) will be | |
1260 | + supressed, though. | |
1261 | 1261 | |
1262 | 1262 | See also: doc/README.Modem |
1263 | 1263 | |
... | ... | @@ -1368,8 +1368,8 @@ |
1368 | 1368 | downloaded image) this option may be very useful. |
1369 | 1369 | |
1370 | 1370 | - CFG_FLASH_CFI: |
1371 | - Define if the flash driver uses extra elements in the | |
1372 | - common flash structure for storing flash geometry | |
1371 | + Define if the flash driver uses extra elements in the | |
1372 | + common flash structure for storing flash geometry | |
1373 | 1373 | |
1374 | 1374 | The following definitions that deal with the placement and management |
1375 | 1375 | of environment data (variable area); in general, we support the |
... | ... | @@ -1435,10 +1435,10 @@ |
1435 | 1435 | - CFG_ENV_ADDR_REDUND |
1436 | 1436 | CFG_ENV_SIZE_REDUND |
1437 | 1437 | |
1438 | - These settings describe a second storage area used to hold | |
1439 | - a redundand copy of the environment data, so that there is | |
1440 | - a valid backup copy in case there is a power failur during | |
1441 | - a "saveenv" operation. | |
1438 | + These settings describe a second storage area used to hold | |
1439 | + a redundand copy of the environment data, so that there is | |
1440 | + a valid backup copy in case there is a power failur during | |
1441 | + a "saveenv" operation. | |
1442 | 1442 | |
1443 | 1443 | BE CAREFUL! Any changes to the flash layout, and some changes to the |
1444 | 1444 | source code will make it necessary to adapt <board>/u-boot.lds* |
1445 | 1445 | |
... | ... | @@ -1501,26 +1501,7 @@ |
1501 | 1501 | - CFG_EEPROM_SIZE: |
1502 | 1502 | The size in bytes of the EEPROM device. |
1503 | 1503 | |
1504 | - - CFG_I2C_EEPROM_ADDR: | |
1505 | - If defined, specified the chip address of the EEPROM device. | |
1506 | - The default address is zero. | |
1507 | 1504 | |
1508 | - - CFG_EEPROM_PAGE_WRITE_BITS: | |
1509 | - If defined, the number of bits used to address bytes in a | |
1510 | - single page in the EEPROM device. A 64 byte page, for example | |
1511 | - would require six bits. | |
1512 | - | |
1513 | - - CFG_EEPROM_PAGE_WRITE_DELAY_MS: | |
1514 | - If defined, the number of milliseconds to delay between | |
1515 | - page writes. The default is zero milliseconds. | |
1516 | - | |
1517 | - - CFG_I2C_EEPROM_ADDR_LEN: | |
1518 | - The length in bytes of the EEPROM memory array address. Note | |
1519 | - that this is NOT the chip address length! | |
1520 | - | |
1521 | - - CFG_EEPROM_SIZE: | |
1522 | - The size in bytes of the EEPROM device. | |
1523 | - | |
1524 | 1505 | - CFG_SPI_INIT_OFFSET |
1525 | 1506 | |
1526 | 1507 | Defines offset to the initial SPI buffer area in DPRAM. The |
1527 | 1508 | |
1528 | 1509 | |
... | ... | @@ -1575,19 +1556,19 @@ |
1575 | 1556 | |
1576 | 1557 | CFG_ISA_IO_OFFSET |
1577 | 1558 | |
1578 | - defines the offset of register from address. It | |
1579 | - depends on which part of the data bus is connected to | |
1580 | - the fdc chipset. (default value 0) | |
1559 | + defines the offset of register from address. It | |
1560 | + depends on which part of the data bus is connected to | |
1561 | + the fdc chipset. (default value 0) | |
1581 | 1562 | |
1582 | - If CFG_ISA_IO_STRIDE CFG_ISA_IO_OFFSET and | |
1583 | - CFG_FDC_DRIVE_NUMBER are undefined, they take their | |
1584 | - default value. | |
1563 | + If CFG_ISA_IO_STRIDE CFG_ISA_IO_OFFSET and | |
1564 | + CFG_FDC_DRIVE_NUMBER are undefined, they take their | |
1565 | + default value. | |
1585 | 1566 | |
1586 | - if CFG_FDC_HW_INIT is defined, then the function | |
1587 | - fdc_hw_init() is called at the beginning of the FDC | |
1588 | - setup. fdc_hw_init() must be provided by the board | |
1589 | - source code. It is used to make hardware dependant | |
1590 | - initializations. | |
1567 | + if CFG_FDC_HW_INIT is defined, then the function | |
1568 | + fdc_hw_init() is called at the beginning of the FDC | |
1569 | + setup. fdc_hw_init() must be provided by the board | |
1570 | + source code. It is used to make hardware dependant | |
1571 | + initializations. | |
1591 | 1572 | |
1592 | 1573 | - CFG_IMMR: Physical address of the Internal Memory Mapped |
1593 | 1574 | Register; DO NOT CHANGE! (11-4) |
... | ... | @@ -1676,10 +1657,10 @@ |
1676 | 1657 | doc/README.MBX before setting this variable! |
1677 | 1658 | |
1678 | 1659 | - CFG_CPM_POST_WORD_ADDR: (MPC8xx, MPC8260 only) |
1679 | - Offset of the bootmode word in DPRAM used by post | |
1680 | - (Power On Self Tests). This definition overrides | |
1681 | - #define'd default value in commproc.h resp. | |
1682 | - cpm_8260.h. | |
1660 | + Offset of the bootmode word in DPRAM used by post | |
1661 | + (Power On Self Tests). This definition overrides | |
1662 | + #define'd default value in commproc.h resp. | |
1663 | + cpm_8260.h. | |
1683 | 1664 | |
1684 | 1665 | Building the Software: |
1685 | 1666 | ====================== |
... | ... | @@ -2535,6 +2516,44 @@ |
2535 | 2516 | models provide on-chip memory (like the IMMR area on MPC8xx and |
2536 | 2517 | MPC826x processors), on others (parts of) the data cache can be |
2537 | 2518 | locked as (mis-) used as memory, etc. |
2519 | + | |
2520 | + Chris Hallinan posted a good summy of these issues to the | |
2521 | + u-boot-users mailing list: | |
2522 | + | |
2523 | + Subject: RE: [U-Boot-Users] RE: More On Memory Bank x (nothingness)? | |
2524 | + From: "Chris Hallinan" <clh@net1plus.com> | |
2525 | + Date: Mon, 10 Feb 2003 16:43:46 -0500 (22:43 MET) | |
2526 | + ... | |
2527 | + | |
2528 | + Correct me if I'm wrong, folks, but the way I understand it | |
2529 | + is this: Using DCACHE as initial RAM for Stack, etc, does not | |
2530 | + require any physical RAM backing up the cache. The cleverness | |
2531 | + is that the cache is being used as a temporary supply of | |
2532 | + necessary storage before the SDRAM controller is setup. It's | |
2533 | + beyond the scope of this list to expain the details, but you | |
2534 | + can see how this works by studying the cache architecture and | |
2535 | + operation in the architecture and processor-specific manuals. | |
2536 | + | |
2537 | + OCM is On Chip Memory, which I believe the 405GP has 4K. It | |
2538 | + is another option for the system designer to use as an | |
2539 | + initial stack/ram area prior to SDRAM being available. Either | |
2540 | + option should work for you. Using CS 4 should be fine if your | |
2541 | + board designers haven't used it for something that would | |
2542 | + cause you grief during the initial boot! It is frequently not | |
2543 | + used. | |
2544 | + | |
2545 | + CFG_INIT_RAM_ADDR should be somewhere that won't interfere | |
2546 | + with your processor/board/system design. The default value | |
2547 | + you will find in any recent u-boot distribution in | |
2548 | + Walnut405.h should work for you. I'd set it to a value larger | |
2549 | + than your SDRAM module. If you have a 64MB SDRAM module, set | |
2550 | + it above 400_0000. Just make sure your board has no resources | |
2551 | + that are supposed to respond to that address! That code in | |
2552 | + start.S has been around a while and should work as is when | |
2553 | + you get the config right. | |
2554 | + | |
2555 | + -Chris Hallinan | |
2556 | + DS4.COM, Inc. | |
2538 | 2557 | |
2539 | 2558 | It is essential to remember this, since it has some impact on the C |
2540 | 2559 | code for the initialization procedures: |
board/innokom/Makefile
1 | +# | |
2 | +# (C) Copyright 2000 | |
3 | +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | +# | |
5 | +# See file CREDITS for list of people who contributed to this | |
6 | +# project. | |
7 | +# | |
8 | +# This program is free software; you can redistribute it and/or | |
9 | +# modify it under the terms of the GNU General Public License as | |
10 | +# published by the Free Software Foundation; either version 2 of | |
11 | +# the License, or (at your option) any later version. | |
12 | +# | |
13 | +# This program is distributed in the hope that it will be useful, | |
14 | +# but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | +# GNU General Public License for more details. | |
17 | +# | |
18 | +# You should have received a copy of the GNU General Public License | |
19 | +# along with this program; if not, write to the Free Software | |
20 | +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | +# MA 02111-1307 USA | |
22 | +# | |
23 | + | |
24 | +include $(TOPDIR)/config.mk | |
25 | + | |
26 | +LIB = lib$(BOARD).a | |
27 | + | |
28 | +OBJS := innokom.o flash.o | |
29 | +SOBJS := memsetup.o | |
30 | + | |
31 | +$(LIB): $(OBJS) $(SOBJS) | |
32 | + $(AR) crv $@ $^ | |
33 | + | |
34 | +clean: | |
35 | + rm -f $(SOBJS) $(OBJS) | |
36 | + | |
37 | +distclean: clean | |
38 | + rm -f $(LIB) core *.bak .depend | |
39 | + | |
40 | +######################################################################### | |
41 | + | |
42 | +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) | |
43 | + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ | |
44 | + | |
45 | +-include .depend | |
46 | + | |
47 | +######################################################################### |
board/innokom/config.mk
1 | +# | |
2 | +# Linux-Kernel is expected to be at c000'8000, entry c000'8000 | |
3 | +# | |
4 | +# we load ourself to c170'0000, the upper 1 MB of second bank | |
5 | +# | |
6 | +# download areas is c800'0000 | |
7 | +# | |
8 | + | |
9 | +# This is the address where U-Boot lives in flash: | |
10 | +#TEXT_BASE = 0 | |
11 | + | |
12 | +# FIXME: armboot does only work correctly when being compiled | |
13 | +# for the addresses _after_ relocation to RAM!! Otherwhise the | |
14 | +# .bss segment is assumed in flash... | |
15 | +TEXT_BASE = 0xa1fe0000 |
board/innokom/flash.c
1 | +/* | |
2 | + * (C) Copyright 2002 | |
3 | + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net | |
4 | + * | |
5 | + * (C) Copyright 2002 | |
6 | + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
7 | + * Marius Groeger <mgroeger@sysgo.de> | |
8 | + * | |
9 | + * (C) Copyright 2002 | |
10 | + * Robert Schwebel, Pengutronix, <r.schwebel@pengutronix.de> | |
11 | + * | |
12 | + * See file CREDITS for list of people who contributed to this | |
13 | + * project. | |
14 | + * | |
15 | + * This program is free software; you can redistribute it and/or | |
16 | + * modify it under the terms of the GNU General Public License as | |
17 | + * published by the Free Software Foundation; either version 2 of | |
18 | + * the License, or (at your option) any later version. | |
19 | + * | |
20 | + * This program is distributed in the hope that it will be useful, | |
21 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | + * GNU General Public License for more details. | |
24 | + * | |
25 | + * You should have received a copy of the GNU General Public License | |
26 | + * along with this program; if not, write to the Free Software | |
27 | + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
28 | + * MA 02111-1307 USA | |
29 | + */ | |
30 | + | |
31 | +#include <common.h> | |
32 | +#include <asm/arch/pxa-regs.h> | |
33 | + | |
34 | +#define FLASH_BANK_SIZE 0x02000000 | |
35 | +#define MAIN_SECT_SIZE 0x40000 /* 2x16 = 256k per sector */ | |
36 | + | |
37 | +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; | |
38 | + | |
39 | + | |
40 | +/** | |
41 | + * flash_init: - initialize data structures for flash chips | |
42 | + * | |
43 | + * @return: size of the flash | |
44 | + */ | |
45 | + | |
46 | +ulong flash_init(void) | |
47 | +{ | |
48 | + int i, j; | |
49 | + ulong size = 0; | |
50 | + | |
51 | + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { | |
52 | + ulong flashbase = 0; | |
53 | + flash_info[i].flash_id = | |
54 | + (INTEL_MANUFACT & FLASH_VENDMASK) | | |
55 | + (INTEL_ID_28F128J3 & FLASH_TYPEMASK); | |
56 | + flash_info[i].size = FLASH_BANK_SIZE; | |
57 | + flash_info[i].sector_count = CFG_MAX_FLASH_SECT; | |
58 | + memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT); | |
59 | + | |
60 | + switch (i) { | |
61 | + case 0: | |
62 | + flashbase = PHYS_FLASH_1; | |
63 | + break; | |
64 | + default: | |
65 | + panic("configured to many flash banks!\n"); | |
66 | + break; | |
67 | + } | |
68 | + for (j = 0; j < flash_info[i].sector_count; j++) { | |
69 | + flash_info[i].start[j] = flashbase + j*MAIN_SECT_SIZE; | |
70 | + } | |
71 | + size += flash_info[i].size; | |
72 | + } | |
73 | + | |
74 | + /* Protect monitor and environment sectors */ | |
75 | + flash_protect(FLAG_PROTECT_SET, | |
76 | + CFG_FLASH_BASE, | |
77 | + CFG_FLASH_BASE + _armboot_end_data - _armboot_start, | |
78 | + &flash_info[0]); | |
79 | + | |
80 | +#ifdef CFG_ENV_IS_IN_FLASH | |
81 | + flash_protect(FLAG_PROTECT_SET, | |
82 | + CFG_ENV_ADDR, | |
83 | + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, | |
84 | + &flash_info[0]); | |
85 | +#endif | |
86 | + | |
87 | + return size; | |
88 | +} | |
89 | + | |
90 | + | |
91 | +/** | |
92 | + * flash_print_info: - print information about the flash situation | |
93 | + * | |
94 | + * @param info: | |
95 | + */ | |
96 | + | |
97 | +void flash_print_info (flash_info_t *info) | |
98 | +{ | |
99 | + int i, j; | |
100 | + | |
101 | + for (j=0; j<CFG_MAX_FLASH_BANKS; j++) { | |
102 | + | |
103 | + switch (info->flash_id & FLASH_VENDMASK) { | |
104 | + | |
105 | + case (INTEL_MANUFACT & FLASH_VENDMASK): | |
106 | + printf("Intel: "); | |
107 | + break; | |
108 | + default: | |
109 | + printf("Unknown Vendor "); | |
110 | + break; | |
111 | + } | |
112 | + | |
113 | + switch (info->flash_id & FLASH_TYPEMASK) { | |
114 | + | |
115 | + case (INTEL_ID_28F128J3 & FLASH_TYPEMASK): | |
116 | + printf("28F128J3 (128Mbit)\n"); | |
117 | + break; | |
118 | + default: | |
119 | + printf("Unknown Chip Type\n"); | |
120 | + return; | |
121 | + } | |
122 | + | |
123 | + printf(" Size: %ld MB in %d Sectors\n", | |
124 | + info->size >> 20, info->sector_count); | |
125 | + | |
126 | + printf(" Sector Start Addresses:"); | |
127 | + for (i = 0; i < info->sector_count; i++) { | |
128 | + if ((i % 5) == 0) printf ("\n "); | |
129 | + | |
130 | + printf (" %08lX%s", info->start[i], | |
131 | + info->protect[i] ? " (RO)" : " "); | |
132 | + } | |
133 | + printf ("\n"); | |
134 | + info++; | |
135 | + } | |
136 | +} | |
137 | + | |
138 | + | |
139 | +/** | |
140 | + * flash_erase: - erase flash sectors | |
141 | + * | |
142 | + */ | |
143 | + | |
144 | +int flash_erase(flash_info_t *info, int s_first, int s_last) | |
145 | +{ | |
146 | + int flag, prot, sect; | |
147 | + int rc = ERR_OK; | |
148 | + | |
149 | + if (info->flash_id == FLASH_UNKNOWN) | |
150 | + return ERR_UNKNOWN_FLASH_TYPE; | |
151 | + | |
152 | + if ((s_first < 0) || (s_first > s_last)) { | |
153 | + return ERR_INVAL; | |
154 | + } | |
155 | + | |
156 | + if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK)) | |
157 | + return ERR_UNKNOWN_FLASH_VENDOR; | |
158 | + | |
159 | + prot = 0; | |
160 | + for (sect=s_first; sect<=s_last; ++sect) { | |
161 | + if (info->protect[sect]) prot++; | |
162 | + } | |
163 | + | |
164 | + if (prot) return ERR_PROTECTED; | |
165 | + | |
166 | + /* | |
167 | + * Disable interrupts which might cause a timeout | |
168 | + * here. Remember that our exception vectors are | |
169 | + * at address 0 in the flash, and we don't want a | |
170 | + * (ticker) exception to happen while the flash | |
171 | + * chip is in programming mode. | |
172 | + */ | |
173 | + | |
174 | + flag = disable_interrupts(); | |
175 | + | |
176 | + /* Start erase on unprotected sectors */ | |
177 | + for (sect = s_first; sect<=s_last && !ctrlc(); sect++) { | |
178 | + | |
179 | + printf("Erasing sector %2d ... ", sect); | |
180 | + | |
181 | + /* arm simple, non interrupt dependent timer */ | |
182 | + reset_timer_masked(); | |
183 | + | |
184 | + if (info->protect[sect] == 0) { /* not protected */ | |
185 | + u32 * volatile addr = (u32 * volatile)(info->start[sect]); | |
186 | + | |
187 | + /* erase sector: */ | |
188 | + /* The strata flashs are aligned side by side on */ | |
189 | + /* the data bus, so we have to write the commands */ | |
190 | + /* to both chips here: */ | |
191 | + | |
192 | + *addr = 0x00200020; /* erase setup */ | |
193 | + *addr = 0x00D000D0; /* erase confirm */ | |
194 | + | |
195 | + while ((*addr & 0x00800080) != 0x00800080) { | |
196 | + if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) { | |
197 | + *addr = 0x00B000B0; /* suspend erase*/ | |
198 | + *addr = 0x00FF00FF; /* read mode */ | |
199 | + rc = ERR_TIMOUT; | |
200 | + goto outahere; | |
201 | + } | |
202 | + } | |
203 | + | |
204 | + *addr = 0x00500050; /* clear status register cmd. */ | |
205 | + *addr = 0x00FF00FF; /* resest to read mode */ | |
206 | + | |
207 | + } | |
208 | + | |
209 | + printf("ok.\n"); | |
210 | + } | |
211 | + | |
212 | + if (ctrlc()) printf("User Interrupt!\n"); | |
213 | + | |
214 | + outahere: | |
215 | + | |
216 | + /* allow flash to settle - wait 10 ms */ | |
217 | + udelay_masked(10000); | |
218 | + | |
219 | + if (flag) enable_interrupts(); | |
220 | + | |
221 | + return rc; | |
222 | +} | |
223 | + | |
224 | + | |
225 | +/** | |
226 | + * write_word: - copy memory to flash | |
227 | + * | |
228 | + * @param info: | |
229 | + * @param dest: | |
230 | + * @param data: | |
231 | + * @return: | |
232 | + */ | |
233 | + | |
234 | +static int write_word (flash_info_t *info, ulong dest, ushort data) | |
235 | +{ | |
236 | + ushort *addr = (ushort *)dest, val; | |
237 | + int rc = ERR_OK; | |
238 | + int flag; | |
239 | + | |
240 | + /* Check if Flash is (sufficiently) erased */ | |
241 | + if ((*addr & data) != data) return ERR_NOT_ERASED; | |
242 | + | |
243 | + /* | |
244 | + * Disable interrupts which might cause a timeout | |
245 | + * here. Remember that our exception vectors are | |
246 | + * at address 0 in the flash, and we don't want a | |
247 | + * (ticker) exception to happen while the flash | |
248 | + * chip is in programming mode. | |
249 | + */ | |
250 | + flag = disable_interrupts(); | |
251 | + | |
252 | + /* clear status register command */ | |
253 | + *addr = 0x50; | |
254 | + | |
255 | + /* program set-up command */ | |
256 | + *addr = 0x40; | |
257 | + | |
258 | + /* latch address/data */ | |
259 | + *addr = data; | |
260 | + | |
261 | + /* arm simple, non interrupt dependent timer */ | |
262 | + reset_timer_masked(); | |
263 | + | |
264 | + /* wait while polling the status register */ | |
265 | + while(((val = *addr) & 0x80) != 0x80) { | |
266 | + if (get_timer_masked() > CFG_FLASH_WRITE_TOUT) { | |
267 | + rc = ERR_TIMOUT; | |
268 | + *addr = 0xB0; /* suspend program command */ | |
269 | + goto outahere; | |
270 | + } | |
271 | + } | |
272 | + | |
273 | + if(val & 0x1A) { /* check for error */ | |
274 | + printf("\nFlash write error %02x at address %08lx\n", | |
275 | + (int)val, (unsigned long)dest); | |
276 | + if(val & (1<<3)) { | |
277 | + printf("Voltage range error.\n"); | |
278 | + rc = ERR_PROG_ERROR; | |
279 | + goto outahere; | |
280 | + } | |
281 | + if(val & (1<<1)) { | |
282 | + printf("Device protect error.\n"); | |
283 | + rc = ERR_PROTECTED; | |
284 | + goto outahere; | |
285 | + } | |
286 | + if(val & (1<<4)) { | |
287 | + printf("Programming error.\n"); | |
288 | + rc = ERR_PROG_ERROR; | |
289 | + goto outahere; | |
290 | + } | |
291 | + rc = ERR_PROG_ERROR; | |
292 | + goto outahere; | |
293 | + } | |
294 | + | |
295 | + outahere: | |
296 | + | |
297 | + *addr = 0xFF; /* read array command */ | |
298 | + if (flag) enable_interrupts(); | |
299 | + | |
300 | + return rc; | |
301 | +} | |
302 | + | |
303 | + | |
304 | +/** | |
305 | + * write_buf: - Copy memory to flash. | |
306 | + * | |
307 | + * @param info: | |
308 | + * @param src: source of copy transaction | |
309 | + * @param addr: where to copy to | |
310 | + * @param cnt: number of bytes to copy | |
311 | + * | |
312 | + * @return error code | |
313 | + */ | |
314 | + | |
315 | +int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) | |
316 | +{ | |
317 | + ulong cp, wp; | |
318 | + ushort data; | |
319 | + int l; | |
320 | + int i, rc; | |
321 | + | |
322 | + wp = (addr & ~1); /* get lower word aligned address */ | |
323 | + | |
324 | + /* | |
325 | + * handle unaligned start bytes | |
326 | + */ | |
327 | + if ((l = addr - wp) != 0) { | |
328 | + data = 0; | |
329 | + for (i=0, cp=wp; i<l; ++i, ++cp) { | |
330 | + data = (data >> 8) | (*(uchar *)cp << 8); | |
331 | + } | |
332 | + for (; i<2 && cnt>0; ++i) { | |
333 | + data = (data >> 8) | (*src++ << 8); | |
334 | + --cnt; | |
335 | + ++cp; | |
336 | + } | |
337 | + for (; cnt==0 && i<2; ++i, ++cp) { | |
338 | + data = (data >> 8) | (*(uchar *)cp << 8); | |
339 | + } | |
340 | + | |
341 | + if ((rc = write_word(info, wp, data)) != 0) { | |
342 | + return (rc); | |
343 | + } | |
344 | + wp += 2; | |
345 | + } | |
346 | + | |
347 | + /* | |
348 | + * handle word aligned part | |
349 | + */ | |
350 | + while (cnt >= 2) { | |
351 | + /* data = *((vushort*)src); */ | |
352 | + data = *((ushort*)src); | |
353 | + if ((rc = write_word(info, wp, data)) != 0) { | |
354 | + return (rc); | |
355 | + } | |
356 | + src += 2; | |
357 | + wp += 2; | |
358 | + cnt -= 2; | |
359 | + } | |
360 | + | |
361 | + if (cnt == 0) return ERR_OK; | |
362 | + | |
363 | + /* | |
364 | + * handle unaligned tail bytes | |
365 | + */ | |
366 | + data = 0; | |
367 | + for (i=0, cp=wp; i<2 && cnt>0; ++i, ++cp) { | |
368 | + data = (data >> 8) | (*src++ << 8); | |
369 | + --cnt; | |
370 | + } | |
371 | + for (; i<2; ++i, ++cp) { | |
372 | + data = (data >> 8) | (*(uchar *)cp << 8); | |
373 | + } | |
374 | + | |
375 | + return write_word(info, wp, data); | |
376 | +} |
board/innokom/innokom.c
1 | +/* | |
2 | + * (C) Copyright 2002 | |
3 | + * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de | |
4 | + * Kyle Harris, Nexus Technologies, Inc., kharris@nexus-tech.net | |
5 | + * Marius Groeger, Sysgo Real-Time Solutions GmbH, mgroeger@sysgo.de | |
6 | + * | |
7 | + * See file CREDITS for list of people who contributed to this | |
8 | + * project. | |
9 | + * | |
10 | + * This program is free software; you can redistribute it and/or | |
11 | + * modify it under the terms of the GNU General Public License as | |
12 | + * published by the Free Software Foundation; either version 2 of | |
13 | + * the License, or (at your option) any later version. | |
14 | + * | |
15 | + * This program is distributed in the hope that it will be useful, | |
16 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | + * GNU General Public License for more details. | |
19 | + * | |
20 | + * You should have received a copy of the GNU General Public License | |
21 | + * along with this program; if not, write to the Free Software | |
22 | + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | + * MA 02111-1307 USA | |
24 | + */ | |
25 | + | |
26 | +#include <common.h> | |
27 | +#include <asm/arch/pxa-regs.h> | |
28 | + | |
29 | +#ifdef CONFIG_SHOW_BOOT_PROGRESS | |
30 | +# define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg) | |
31 | +#else | |
32 | +# define SHOW_BOOT_PROGRESS(arg) | |
33 | +#endif | |
34 | + | |
35 | +/* | |
36 | + * Miscelaneous platform dependent initialisations | |
37 | + */ | |
38 | + | |
39 | + | |
40 | +/** | |
41 | + * board_init: - setup some data structures | |
42 | + * | |
43 | + * @return: 0 in case of success | |
44 | + */ | |
45 | + | |
46 | +int board_init (void) | |
47 | +{ | |
48 | + DECLARE_GLOBAL_DATA_PTR; | |
49 | + | |
50 | + /* memory and cpu-speed are setup before relocation */ | |
51 | + /* so we do _nothing_ here */ | |
52 | + | |
53 | + /* arch number of Innokom board */ | |
54 | + gd->bd->bi_arch_number = 258; | |
55 | + | |
56 | + /* adress of boot parameters */ | |
57 | + gd->bd->bi_boot_params = 0xa0000100; | |
58 | + | |
59 | + return 0; | |
60 | +} | |
61 | + | |
62 | + | |
63 | +/** | |
64 | + * dram_init: - setup dynamic RAM | |
65 | + * | |
66 | + * @return: 0 in case of success | |
67 | + */ | |
68 | + | |
69 | +int dram_init (void) | |
70 | +{ | |
71 | + DECLARE_GLOBAL_DATA_PTR; | |
72 | + | |
73 | + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; | |
74 | + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; | |
75 | + | |
76 | + return 0; | |
77 | +} | |
78 | + | |
79 | + | |
80 | +/** | |
81 | + * innokom_set_led: - switch LEDs on or off | |
82 | + * | |
83 | + * @param led: LED to switch (0,1,2) | |
84 | + * @param state: switch on (1) or off (0) | |
85 | + */ | |
86 | + | |
87 | +void innokom_set_led(int led, int state) | |
88 | +{ | |
89 | + switch(led) { | |
90 | +/* | |
91 | + case 0: if (state==1) { | |
92 | + GPCR0 |= CSB226_USER_LED0; | |
93 | + } else if (state==0) { | |
94 | + GPSR0 |= CSB226_USER_LED0; | |
95 | + } | |
96 | + break; | |
97 | + | |
98 | + case 1: if (state==1) { | |
99 | + GPCR0 |= CSB226_USER_LED1; | |
100 | + } else if (state==0) { | |
101 | + GPSR0 |= CSB226_USER_LED1; | |
102 | + } | |
103 | + break; | |
104 | + | |
105 | + case 2: if (state==1) { | |
106 | + GPCR0 |= CSB226_USER_LED2; | |
107 | + } else if (state==0) { | |
108 | + GPSR0 |= CSB226_USER_LED2; | |
109 | + } | |
110 | + break; | |
111 | +*/ | |
112 | + } | |
113 | + | |
114 | + return; | |
115 | +} | |
116 | + | |
117 | + | |
118 | +/** | |
119 | + * show_boot_progress: - indicate state of the boot process | |
120 | + * | |
121 | + * @param status: Status number - see README for details. | |
122 | + * | |
123 | + * The CSB226 does only have 3 LEDs, so we switch them on at the most | |
124 | + * important states (1, 5, 15). | |
125 | + */ | |
126 | + | |
127 | +void show_boot_progress (int status) | |
128 | +{ | |
129 | + switch(status) { | |
130 | +/* | |
131 | + case 1: csb226_set_led(0,1); break; | |
132 | + case 5: csb226_set_led(1,1); break; | |
133 | + case 15: csb226_set_led(2,1); break; | |
134 | +*/ | |
135 | + } | |
136 | + | |
137 | + return; | |
138 | +} |
board/innokom/memsetup.S
1 | +/* | |
2 | + * Most of this taken from Redboot hal_platform_setup.h with cleanup | |
3 | + * | |
4 | + * NOTE: I haven't clean this up considerably, just enough to get it | |
5 | + * running. See hal_platform_setup.h for the source. See | |
6 | + * board/cradle/memsetup.S for another PXA250 setup that is | |
7 | + * much cleaner. | |
8 | + * | |
9 | + * See file CREDITS for list of people who contributed to this | |
10 | + * project. | |
11 | + * | |
12 | + * This program is free software; you can redistribute it and/or | |
13 | + * modify it under the terms of the GNU General Public License as | |
14 | + * published by the Free Software Foundation; either version 2 of | |
15 | + * the License, or (at your option) any later version. | |
16 | + * | |
17 | + * This program is distributed in the hope that it will be useful, | |
18 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | + * GNU General Public License for more details. | |
21 | + * | |
22 | + * You should have received a copy of the GNU General Public License | |
23 | + * along with this program; if not, write to the Free Software | |
24 | + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
25 | + * MA 02111-1307 USA | |
26 | + */ | |
27 | + | |
28 | +#include <config.h> | |
29 | +#include <version.h> | |
30 | +#include <asm/arch/pxa-regs.h> | |
31 | + | |
32 | +DRAM_SIZE: .long CFG_DRAM_SIZE | |
33 | + | |
34 | +/* wait for coprocessor write complete */ | |
35 | + .macro CPWAIT reg | |
36 | + mrc p15,0,\reg,c2,c0,0 | |
37 | + mov \reg,\reg | |
38 | + sub pc,pc,#4 | |
39 | + .endm | |
40 | + | |
41 | + | |
42 | +/* | |
43 | + * Memory setup | |
44 | + */ | |
45 | + | |
46 | +.globl memsetup | |
47 | +memsetup: | |
48 | + | |
49 | + mov r10, lr | |
50 | + | |
51 | + /* Set up GPIO pins first ----------------------------------------- */ | |
52 | + | |
53 | + ldr r0, =GPSR0 | |
54 | + ldr r1, =CFG_GPSR0_VAL | |
55 | + str r1, [r0] | |
56 | + | |
57 | + ldr r0, =GPSR1 | |
58 | + ldr r1, =CFG_GPSR1_VAL | |
59 | + str r1, [r0] | |
60 | + | |
61 | + ldr r0, =GPSR2 | |
62 | + ldr r1, =CFG_GPSR2_VAL | |
63 | + str r1, [r0] | |
64 | + | |
65 | + ldr r0, =GPCR0 | |
66 | + ldr r1, =CFG_GPCR0_VAL | |
67 | + str r1, [r0] | |
68 | + | |
69 | + ldr r0, =GPCR1 | |
70 | + ldr r1, =CFG_GPCR1_VAL | |
71 | + str r1, [r0] | |
72 | + | |
73 | + ldr r0, =GPCR2 | |
74 | + ldr r1, =CFG_GPCR2_VAL | |
75 | + str r1, [r0] | |
76 | + | |
77 | + ldr r0, =GPDR0 | |
78 | + ldr r1, =CFG_GPDR0_VAL | |
79 | + str r1, [r0] | |
80 | + | |
81 | + ldr r0, =GPDR1 | |
82 | + ldr r1, =CFG_GPDR1_VAL | |
83 | + str r1, [r0] | |
84 | + | |
85 | + ldr r0, =GPDR2 | |
86 | + ldr r1, =CFG_GPDR2_VAL | |
87 | + str r1, [r0] | |
88 | + | |
89 | + ldr r0, =GAFR0_L | |
90 | + ldr r1, =CFG_GAFR0_L_VAL | |
91 | + str r1, [r0] | |
92 | + | |
93 | + ldr r0, =GAFR0_U | |
94 | + ldr r1, =CFG_GAFR0_U_VAL | |
95 | + str r1, [r0] | |
96 | + | |
97 | + ldr r0, =GAFR1_L | |
98 | + ldr r1, =CFG_GAFR1_L_VAL | |
99 | + str r1, [r0] | |
100 | + | |
101 | + ldr r0, =GAFR1_U | |
102 | + ldr r1, =CFG_GAFR1_U_VAL | |
103 | + str r1, [r0] | |
104 | + | |
105 | + ldr r0, =GAFR2_L | |
106 | + ldr r1, =CFG_GAFR2_L_VAL | |
107 | + str r1, [r0] | |
108 | + | |
109 | + ldr r0, =GAFR2_U | |
110 | + ldr r1, =CFG_GAFR2_U_VAL | |
111 | + str r1, [r0] | |
112 | + | |
113 | + ldr r0, =PSSR /* enable GPIO pins */ | |
114 | + ldr r1, =CFG_PSSR_VAL | |
115 | + str r1, [r0] | |
116 | + | |
117 | +/* ldr r3, =MSC1 / low - bank 2 Lubbock Registers / SRAM */ | |
118 | +/* ldr r2, =CFG_MSC1_VAL / high - bank 3 Ethernet Controller */ | |
119 | +/* str r2, [r3] / need to set MSC1 before trying to write to the HEX LEDs */ | |
120 | +/* ldr r2, [r3] / need to read it back to make sure the value latches (see MSC section of manual) */ | |
121 | +/* */ | |
122 | +/* ldr r1, =LED_BLANK */ | |
123 | +/* mov r0, #0xFF */ | |
124 | +/* str r0, [r1] / turn on hex leds */ | |
125 | +/* */ | |
126 | +/*loop: */ | |
127 | +/* */ | |
128 | +/* ldr r0, =0xB0070001 */ | |
129 | +/* ldr r1, =_LED */ | |
130 | +/* str r0, [r1] / hex display */ | |
131 | + | |
132 | + | |
133 | + /* ---------------------------------------------------------------- */ | |
134 | + /* Enable memory interface */ | |
135 | + /* */ | |
136 | + /* The sequence below is based on the recommended init steps */ | |
137 | + /* detailed in the Intel PXA250 Operating Systems Developers Guide, */ | |
138 | + /* Chapter 10. */ | |
139 | + /* ---------------------------------------------------------------- */ | |
140 | + | |
141 | + /* ---------------------------------------------------------------- */ | |
142 | + /* Step 1: Wait for at least 200 microsedonds to allow internal */ | |
143 | + /* clocks to settle. Only necessary after hard reset... */ | |
144 | + /* FIXME: can be optimized later */ | |
145 | + /* ---------------------------------------------------------------- */ | |
146 | + | |
147 | + ldr r3, =OSCR /* reset the OS Timer Count to zero */ | |
148 | + mov r2, #0 | |
149 | + str r2, [r3] | |
150 | + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ | |
151 | + /* so 0x300 should be plenty */ | |
152 | +1: | |
153 | + ldr r2, [r3] | |
154 | + cmp r4, r2 | |
155 | + bgt 1b | |
156 | + | |
157 | +mem_init: | |
158 | + | |
159 | + ldr r1, =MEMC_BASE /* get memory controller base addr. */ | |
160 | + | |
161 | + /* ---------------------------------------------------------------- */ | |
162 | + /* Step 2a: Initialize Asynchronous static memory controller */ | |
163 | + /* ---------------------------------------------------------------- */ | |
164 | + | |
165 | + /* MSC registers: timing, bus width, mem type */ | |
166 | + | |
167 | + /* MSC0: nCS(0,1) */ | |
168 | + ldr r2, =CFG_MSC0_VAL | |
169 | + str r2, [r1, #MSC0_OFFSET] | |
170 | + ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */ | |
171 | + /* that data latches */ | |
172 | + /* MSC1: nCS(2,3) */ | |
173 | + ldr r2, =CFG_MSC1_VAL | |
174 | + str r2, [r1, #MSC1_OFFSET] | |
175 | + ldr r2, [r1, #MSC1_OFFSET] | |
176 | + | |
177 | + /* MSC2: nCS(4,5) */ | |
178 | + ldr r2, =CFG_MSC2_VAL | |
179 | + str r2, [r1, #MSC2_OFFSET] | |
180 | + ldr r2, [r1, #MSC2_OFFSET] | |
181 | + | |
182 | + /* ---------------------------------------------------------------- */ | |
183 | + /* Step 2b: Initialize Card Interface */ | |
184 | + /* ---------------------------------------------------------------- */ | |
185 | + | |
186 | + /* MECR: Memory Expansion Card Register */ | |
187 | + ldr r2, =CFG_MECR_VAL | |
188 | + str r2, [r1, #MECR_OFFSET] | |
189 | + ldr r2, [r1, #MECR_OFFSET] | |
190 | + | |
191 | + /* MCMEM0: Card Interface slot 0 timing */ | |
192 | + ldr r2, =CFG_MCMEM0_VAL | |
193 | + str r2, [r1, #MCMEM0_OFFSET] | |
194 | + ldr r2, [r1, #MCMEM0_OFFSET] | |
195 | + | |
196 | + /* MCMEM1: Card Interface slot 1 timing */ | |
197 | + ldr r2, =CFG_MCMEM1_VAL | |
198 | + str r2, [r1, #MCMEM1_OFFSET] | |
199 | + ldr r2, [r1, #MCMEM1_OFFSET] | |
200 | + | |
201 | + /* MCATT0: Card Interface Attribute Space Timing, slot 0 */ | |
202 | + ldr r2, =CFG_MCATT0_VAL | |
203 | + str r2, [r1, #MCATT0_OFFSET] | |
204 | + ldr r2, [r1, #MCATT0_OFFSET] | |
205 | + | |
206 | + /* MCATT1: Card Interface Attribute Space Timing, slot 1 */ | |
207 | + ldr r2, =CFG_MCATT1_VAL | |
208 | + str r2, [r1, #MCATT1_OFFSET] | |
209 | + ldr r2, [r1, #MCATT1_OFFSET] | |
210 | + | |
211 | + /* MCIO0: Card Interface I/O Space Timing, slot 0 */ | |
212 | + ldr r2, =CFG_MCIO0_VAL | |
213 | + str r2, [r1, #MCIO0_OFFSET] | |
214 | + ldr r2, [r1, #MCIO0_OFFSET] | |
215 | + | |
216 | + /* MCIO1: Card Interface I/O Space Timing, slot 1 */ | |
217 | + ldr r2, =CFG_MCIO1_VAL | |
218 | + str r2, [r1, #MCIO1_OFFSET] | |
219 | + ldr r2, [r1, #MCIO1_OFFSET] | |
220 | + | |
221 | + /* ---------------------------------------------------------------- */ | |
222 | + /* Step 2c: Write FLYCNFG FIXME: what's that??? */ | |
223 | + /* ---------------------------------------------------------------- */ | |
224 | + | |
225 | + | |
226 | + /* ---------------------------------------------------------------- */ | |
227 | + /* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */ | |
228 | + /* ---------------------------------------------------------------- */ | |
229 | + | |
230 | + /* Before accessing MDREFR we need a valid DRI field, so we set */ | |
231 | + /* this to power on defaults + DIR field. */ | |
232 | + | |
233 | + ldr r4, =0x03ca4fff | |
234 | + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ | |
235 | + ldr r4, [r1, #MDREFR_OFFSET] | |
236 | + | |
237 | + ldr r4, =0x03ca4030 | |
238 | + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ | |
239 | + ldr r4, [r1, #MDREFR_OFFSET] | |
240 | + | |
241 | + /* Note: preserve the mdrefr value in r4 */ | |
242 | + | |
243 | + | |
244 | + /* ---------------------------------------------------------------- */ | |
245 | + /* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */ | |
246 | + /* ---------------------------------------------------------------- */ | |
247 | + | |
248 | + /* Initialize SXCNFG register. Assert the enable bits */ | |
249 | + | |
250 | + /* Write SXMRS to cause an MRS command to all enabled banks of */ | |
251 | + /* synchronous static memory. Note that SXLCR need not be written */ | |
252 | + /* at this time. */ | |
253 | + | |
254 | + /* FIXME: we use async mode for now */ | |
255 | + | |
256 | + | |
257 | + /* ---------------------------------------------------------------- */ | |
258 | + /* Step 4: Initialize SDRAM */ | |
259 | + /* ---------------------------------------------------------------- */ | |
260 | + | |
261 | + /* Step 4a: assert MDREFR:K1RUN and MDREFR:K2RUN and configure */ | |
262 | + /* MDREFR:K1DB2 and MDREFR:K2DB2 as desired. */ | |
263 | + | |
264 | + orr r4, r4, #(MDREFR_K1RUN|MDREFR_K0RUN) | |
265 | + | |
266 | + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ | |
267 | + ldr r4, [r1, #MDREFR_OFFSET] | |
268 | + | |
269 | + | |
270 | + /* Step 4b: de-assert MDREFR:SLFRSH. */ | |
271 | + | |
272 | + bic r4, r4, #(MDREFR_SLFRSH) | |
273 | + | |
274 | + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ | |
275 | + ldr r4, [r1, #MDREFR_OFFSET] | |
276 | + | |
277 | + | |
278 | + /* Step 4c: assert MDREFR:E1PIN and E0PIO */ | |
279 | + | |
280 | + orr r4, r4, #(MDREFR_E1PIN|MDREFR_E0PIN) | |
281 | + | |
282 | + str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */ | |
283 | + ldr r4, [r1, #MDREFR_OFFSET] | |
284 | + | |
285 | + | |
286 | + /* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */ | |
287 | + /* configure but not enable each SDRAM partition pair. */ | |
288 | + | |
289 | + ldr r4, =CFG_MDCNFG_VAL | |
290 | + bic r4, r4, #(MDCNFG_DE0|MDCNFG_DE1) | |
291 | + | |
292 | + str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */ | |
293 | + ldr r4, [r1, #MDCNFG_OFFSET] | |
294 | + | |
295 | + | |
296 | + /* Step 4e: Wait for the clock to the SDRAMs to stabilize, */ | |
297 | + /* 100..200 ยตsec. */ | |
298 | + | |
299 | + ldr r3, =OSCR /* reset the OS Timer Count to zero */ | |
300 | + mov r2, #0 | |
301 | + str r2, [r3] | |
302 | + ldr r4, =0x300 /* really 0x2E1 is about 200usec, */ | |
303 | + /* so 0x300 should be plenty */ | |
304 | +1: | |
305 | + ldr r2, [r3] | |
306 | + cmp r4, r2 | |
307 | + bgt 1b | |
308 | + | |
309 | + | |
310 | + /* Step 4f: Trigger a number (usually 8) refresh cycles by */ | |
311 | + /* attempting non-burst read or write accesses to disabled */ | |
312 | + /* SDRAM, as commonly specified in the power up sequence */ | |
313 | + /* documented in SDRAM data sheets. The address(es) used */ | |
314 | + /* for this purpose must not be cacheable. */ | |
315 | + | |
316 | + ldr r3, =CFG_DRAM_BASE | |
317 | + str r2, [r3] | |
318 | + str r2, [r3] | |
319 | + str r2, [r3] | |
320 | + str r2, [r3] | |
321 | + str r2, [r3] | |
322 | + str r2, [r3] | |
323 | + str r2, [r3] | |
324 | + str r2, [r3] | |
325 | + | |
326 | + | |
327 | + /* Step 4g: Write MDCNFG with enable bits asserted */ | |
328 | + /* (MDCNFG:DEx set to 1). */ | |
329 | + | |
330 | + ldr r3, [r1, #MDCNFG_OFFSET] | |
331 | + orr r3, r3, #(MDCNFG_DE0|MDCNFG_DE1) | |
332 | + str r3, [r1, #MDCNFG_OFFSET] | |
333 | + | |
334 | + /* Step 4h: Write MDMRS. */ | |
335 | + | |
336 | + ldr r2, =CFG_MDMRS_VAL | |
337 | + str r2, [r1, #MDMRS_OFFSET] | |
338 | + | |
339 | + | |
340 | + /* We are finished with Intel's memory controller initialisation */ | |
341 | + | |
342 | + | |
343 | + /* ---------------------------------------------------------------- */ | |
344 | + /* Disable (mask) all interrupts at interrupt controller */ | |
345 | + /* ---------------------------------------------------------------- */ | |
346 | + | |
347 | +initirqs: | |
348 | + | |
349 | + mov r1, #0 /* clear int. level register (IRQ, not FIQ) */ | |
350 | + ldr r2, =ICLR | |
351 | + str r1, [r2] | |
352 | + | |
353 | + ldr r2, =ICMR /* mask all interrupts at the controller */ | |
354 | + str r1, [r2] | |
355 | + | |
356 | + | |
357 | + /* ---------------------------------------------------------------- */ | |
358 | + /* Clock initialisation */ | |
359 | + /* ---------------------------------------------------------------- */ | |
360 | + | |
361 | +initclks: | |
362 | + | |
363 | + /* Disable the peripheral clocks, and set the core clock frequency */ | |
364 | + /* (hard-coding at 398.12MHz for now). */ | |
365 | + | |
366 | + /* Turn Off ALL on-chip peripheral clocks for re-configuration */ | |
367 | + /* Note: See label 'ENABLECLKS' for the re-enabling */ | |
368 | + ldr r1, =CKEN | |
369 | + mov r2, #0 | |
370 | + str r2, [r1] | |
371 | + | |
372 | + | |
373 | + /* default value in case no valid rotary switch setting is found */ | |
374 | + ldr r2, =(CCCR_L27|CCCR_M2|CCCR_N10) /* DEFAULT: {200/200/100} */ | |
375 | + | |
376 | + /* ... and write the core clock config register */ | |
377 | + ldr r1, =CCCR | |
378 | + str r2, [r1] | |
379 | + | |
380 | + /* enable the 32Khz oscillator for RTC and PowerManager */ | |
381 | +/* | |
382 | + ldr r1, =OSCC | |
383 | + mov r2, #OSCC_OON | |
384 | + str r2, [r1] | |
385 | +*/ | |
386 | + /* NOTE: spin here until OSCC.OOK get set, meaning the PLL */ | |
387 | + /* has settled. */ | |
388 | +60: | |
389 | + ldr r2, [r1] | |
390 | + ands r2, r2, #1 | |
391 | + beq 60b | |
392 | + | |
393 | + /* ---------------------------------------------------------------- */ | |
394 | + /* */ | |
395 | + /* ---------------------------------------------------------------- */ | |
396 | + | |
397 | + /* Save SDRAM size */ | |
398 | + ldr r1, =DRAM_SIZE | |
399 | + str r8, [r1] | |
400 | + | |
401 | + /* Interrupt init: Mask all interrupts */ | |
402 | + ldr r0, =ICMR /* enable no sources */ | |
403 | + mov r1, #0 | |
404 | + str r1, [r0] | |
405 | + | |
406 | + /* FIXME */ | |
407 | + | |
408 | +#define NODEBUG | |
409 | +#ifdef NODEBUG | |
410 | + /*Disable software and data breakpoints */ | |
411 | + mov r0,#0 | |
412 | + mcr p15,0,r0,c14,c8,0 /* ibcr0 */ | |
413 | + mcr p15,0,r0,c14,c9,0 /* ibcr1 */ | |
414 | + mcr p15,0,r0,c14,c4,0 /* dbcon */ | |
415 | + | |
416 | + /*Enable all debug functionality */ | |
417 | + mov r0,#0x80000000 | |
418 | + mcr p14,0,r0,c10,c0,0 /* dcsr */ | |
419 | + | |
420 | +#endif | |
421 | + | |
422 | + /* ---------------------------------------------------------------- */ | |
423 | + /* End memsetup */ | |
424 | + /* ---------------------------------------------------------------- */ | |
425 | + | |
426 | +endmemsetup: | |
427 | + | |
428 | + mov pc, lr |
board/innokom/u-boot.lds
1 | +/* | |
2 | + * (C) Copyright 2000 | |
3 | + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | + * | |
5 | + * See file CREDITS for list of people who contributed to this | |
6 | + * project. | |
7 | + * | |
8 | + * This program is free software; you can redistribute it and/or | |
9 | + * modify it under the terms of the GNU General Public License as | |
10 | + * published by the Free Software Foundation; either version 2 of | |
11 | + * the License, or (at your option) any later version. | |
12 | + * | |
13 | + * This program is distributed in the hope that it will be useful, | |
14 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | + * GNU General Public License for more details. | |
17 | + * | |
18 | + * You should have received a copy of the GNU General Public License | |
19 | + * along with this program; if not, write to the Free Software | |
20 | + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | + * MA 02111-1307 USA | |
22 | + */ | |
23 | + | |
24 | +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") | |
25 | +OUTPUT_ARCH(arm) | |
26 | +ENTRY(_start) | |
27 | +SECTIONS | |
28 | +{ | |
29 | + . = 0x00000000; | |
30 | + | |
31 | + . = ALIGN(4); | |
32 | + .text : | |
33 | + { | |
34 | + cpu/xscale/start.o (.text) | |
35 | + *(.text) | |
36 | + } | |
37 | + | |
38 | + . = ALIGN(4); | |
39 | + .rodata : { *(.rodata) } | |
40 | + | |
41 | + . = ALIGN(4); | |
42 | + .data : { *(.data) } | |
43 | + | |
44 | + . = ALIGN(4); | |
45 | + .got : { *(.got) } | |
46 | + | |
47 | + armboot_end_data = .; | |
48 | + | |
49 | + . = ALIGN(4); | |
50 | + .bss : { *(.bss) } | |
51 | + | |
52 | + armboot_end = .; | |
53 | +} |
board/r360mpi/flash.c
... | ... | @@ -24,10 +24,12 @@ |
24 | 24 | * MA 02111-1307 USA |
25 | 25 | */ |
26 | 26 | |
27 | +/* #define DEBUG */ | |
28 | + | |
27 | 29 | #include <common.h> |
28 | 30 | #include <mpc8xx.h> |
29 | 31 | |
30 | -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ | |
32 | +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ | |
31 | 33 | |
32 | 34 | #if defined(CFG_ENV_IS_IN_FLASH) |
33 | 35 | # ifndef CFG_ENV_ADDR |
34 | 36 | |
35 | 37 | |
36 | 38 | |
37 | 39 | |
38 | 40 | |
39 | 41 | |
40 | 42 | |
... | ... | @@ -52,44 +54,44 @@ |
52 | 54 | #define FLASH_PORT_WIDTH16 |
53 | 55 | |
54 | 56 | #ifdef FLASH_PORT_WIDTH16 |
55 | -#define FLASH_PORT_WIDTH ushort | |
56 | -#define FLASH_PORT_WIDTHV vu_short | |
57 | +#define FLASH_PORT_WIDTH ushort | |
58 | +#define FLASH_PORT_WIDTHV vu_short | |
57 | 59 | #else |
58 | -#define FLASH_PORT_WIDTH ulong | |
59 | -#define FLASH_PORT_WIDTHV vu_long | |
60 | +#define FLASH_PORT_WIDTH ulong | |
61 | +#define FLASH_PORT_WIDTHV vu_long | |
60 | 62 | #endif |
61 | 63 | |
62 | -#define FPW FLASH_PORT_WIDTH | |
63 | -#define FPWV FLASH_PORT_WIDTHV | |
64 | +#define FPW FLASH_PORT_WIDTH | |
65 | +#define FPWV FLASH_PORT_WIDTHV | |
64 | 66 | |
65 | 67 | /*----------------------------------------------------------------------- |
66 | 68 | * Functions |
67 | 69 | */ |
68 | -static ulong flash_get_size (FPW *addr, flash_info_t *info); | |
69 | -static int write_data (flash_info_t *info, ulong dest, FPW data); | |
70 | -static void flash_get_offsets (ulong base, flash_info_t *info); | |
70 | +static ulong flash_get_size (FPW * addr, flash_info_t * info); | |
71 | +static int write_data (flash_info_t * info, ulong dest, FPW data); | |
72 | +static void flash_get_offsets (ulong base, flash_info_t * info); | |
71 | 73 | |
72 | 74 | /*----------------------------------------------------------------------- |
73 | 75 | */ |
74 | 76 | |
75 | 77 | unsigned long flash_init (void) |
76 | 78 | { |
77 | - volatile immap_t *immap = (immap_t *)CFG_IMMR; | |
79 | + volatile immap_t *immap = (immap_t *) CFG_IMMR; | |
78 | 80 | volatile memctl8xx_t *memctl = &immap->im_memctl; |
79 | 81 | unsigned long size_b0; |
80 | 82 | int i; |
81 | 83 | |
82 | 84 | /* Init: no FLASHes known */ |
83 | - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) { | |
85 | + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { | |
84 | 86 | flash_info[i].flash_id = FLASH_UNKNOWN; |
85 | 87 | } |
86 | 88 | |
87 | 89 | /* Static FLASH Bank configuration here - FIXME XXX */ |
88 | - size_b0 = flash_get_size((FPW *)FLASH_BASE0_PRELIM, &flash_info[0]); | |
90 | + size_b0 = flash_get_size ((FPW *) FLASH_BASE0_PRELIM, &flash_info[0]); | |
89 | 91 | |
90 | 92 | if (flash_info[0].flash_id == FLASH_UNKNOWN) { |
91 | 93 | printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", |
92 | - size_b0, size_b0<<20); | |
94 | + size_b0, size_b0 << 20); | |
93 | 95 | } |
94 | 96 | |
95 | 97 | /* Remap FLASH according to real size */ |
96 | 98 | |
97 | 99 | |
... | ... | @@ -97,24 +99,24 @@ |
97 | 99 | memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V; |
98 | 100 | |
99 | 101 | /* Re-do sizing to get full correct info */ |
100 | - size_b0 = flash_get_size((FPW *)CFG_FLASH_BASE, &flash_info[0]); | |
102 | + size_b0 = flash_get_size ((FPW *) CFG_FLASH_BASE, &flash_info[0]); | |
101 | 103 | |
102 | 104 | flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]); |
103 | 105 | |
104 | 106 | #if CFG_MONITOR_BASE >= CFG_FLASH_BASE |
105 | 107 | /* monitor protection ON by default */ |
106 | - (void)flash_protect(FLAG_PROTECT_SET, | |
107 | - CFG_FLASH_BASE, | |
108 | - CFG_FLASH_BASE+CFG_MONITOR_LEN-1, | |
109 | - &flash_info[0]); | |
108 | + (void) flash_protect (FLAG_PROTECT_SET, | |
109 | + CFG_FLASH_BASE, | |
110 | + CFG_FLASH_BASE + CFG_MONITOR_LEN - 1, | |
111 | + &flash_info[0]); | |
110 | 112 | #endif |
111 | 113 | |
112 | 114 | #ifdef CFG_ENV_IS_IN_FLASH |
113 | 115 | /* ENV protection ON by default */ |
114 | - flash_protect(FLAG_PROTECT_SET, | |
115 | - CFG_ENV_ADDR, | |
116 | - CFG_ENV_ADDR+CFG_ENV_SIZE-1, | |
117 | - &flash_info[0]); | |
116 | + flash_protect (FLAG_PROTECT_SET, | |
117 | + CFG_ENV_ADDR, | |
118 | + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, | |
119 | + &flash_info[0]); | |
118 | 120 | #endif |
119 | 121 | |
120 | 122 | flash_info[0].size = size_b0; |
... | ... | @@ -124,7 +126,7 @@ |
124 | 126 | |
125 | 127 | /*----------------------------------------------------------------------- |
126 | 128 | */ |
127 | -static void flash_get_offsets (ulong base, flash_info_t *info) | |
129 | +static void flash_get_offsets (ulong base, flash_info_t * info) | |
128 | 130 | { |
129 | 131 | int i; |
130 | 132 | |
... | ... | @@ -141,7 +143,7 @@ |
141 | 143 | |
142 | 144 | /*----------------------------------------------------------------------- |
143 | 145 | */ |
144 | -void flash_print_info (flash_info_t *info) | |
146 | +void flash_print_info (flash_info_t * info) | |
145 | 147 | { |
146 | 148 | int i; |
147 | 149 | |
148 | 150 | |
149 | 151 | |
150 | 152 | |
151 | 153 | |
... | ... | @@ -151,31 +153,39 @@ |
151 | 153 | } |
152 | 154 | |
153 | 155 | switch (info->flash_id & FLASH_VENDMASK) { |
154 | - case FLASH_MAN_INTEL: printf ("INTEL "); break; | |
155 | - default: printf ("Unknown Vendor "); break; | |
156 | + case FLASH_MAN_INTEL: | |
157 | + printf ("INTEL "); | |
158 | + break; | |
159 | + default: | |
160 | + printf ("Unknown Vendor "); | |
161 | + break; | |
156 | 162 | } |
157 | 163 | |
158 | 164 | switch (info->flash_id & FLASH_TYPEMASK) { |
159 | - case FLASH_28F320J3A: | |
160 | - printf ("28F320J3A\n"); break; | |
161 | - case FLASH_28F640J3A: | |
162 | - printf ("28F640J3A\n"); break; | |
163 | - case FLASH_28F128J3A: | |
164 | - printf ("28F128J3A\n"); break; | |
165 | - default: printf ("Unknown Chip Type\n"); break; | |
165 | + case FLASH_28F320J3A: | |
166 | + printf ("28F320J3A\n"); | |
167 | + break; | |
168 | + case FLASH_28F640J3A: | |
169 | + printf ("28F640J3A\n"); | |
170 | + break; | |
171 | + case FLASH_28F128J3A: | |
172 | + printf ("28F128J3A\n"); | |
173 | + break; | |
174 | + default: | |
175 | + printf ("Unknown Chip Type\n"); | |
176 | + break; | |
166 | 177 | } |
167 | 178 | |
168 | 179 | printf (" Size: %ld MB in %d Sectors\n", |
169 | - info->size >> 20, info->sector_count); | |
180 | + info->size >> 20, info->sector_count); | |
170 | 181 | |
171 | 182 | printf (" Sector Start Addresses:"); |
172 | - for (i=0; i<info->sector_count; ++i) { | |
183 | + for (i = 0; i < info->sector_count; ++i) { | |
173 | 184 | if ((i % 5) == 0) |
174 | 185 | printf ("\n "); |
175 | 186 | printf (" %08lX%s", |
176 | 187 | info->start[i], |
177 | - info->protect[i] ? " (RO)" : " " | |
178 | - ); | |
188 | + info->protect[i] ? " (RO)" : " "); | |
179 | 189 | } |
180 | 190 | printf ("\n"); |
181 | 191 | return; |
182 | 192 | |
183 | 193 | |
184 | 194 | |
185 | 195 | |
186 | 196 | |
187 | 197 | |
188 | 198 | |
189 | 199 | |
... | ... | @@ -192,50 +202,54 @@ |
192 | 202 | * The following code cannot be run from FLASH! |
193 | 203 | */ |
194 | 204 | |
195 | -static ulong flash_get_size (FPW *addr, flash_info_t *info) | |
205 | +static ulong flash_get_size (FPW * addr, flash_info_t * info) | |
196 | 206 | { |
197 | 207 | FPW value; |
198 | 208 | |
199 | 209 | /* Write auto select command: read Manufacturer ID */ |
200 | - addr[0x5555] = (FPW)0x00AA00AA; | |
201 | - addr[0x2AAA] = (FPW)0x00550055; | |
202 | - addr[0x5555] = (FPW)0x00900090; | |
210 | + addr[0x5555] = (FPW) 0x00AA00AA; | |
211 | + addr[0x2AAA] = (FPW) 0x00550055; | |
212 | + addr[0x5555] = (FPW) 0x00900090; | |
203 | 213 | |
204 | 214 | value = addr[0]; |
205 | 215 | |
206 | - switch (value) { | |
207 | - case (FPW)INTEL_MANUFACT: | |
208 | - info->flash_id = FLASH_MAN_INTEL; | |
209 | - break; | |
216 | + debug ("Manuf. ID @ 0x%08lx: 0x%08lx\n", (ulong)addr, value); | |
217 | + | |
218 | + switch (value) { | |
219 | + case (FPW) INTEL_MANUFACT: | |
220 | + info->flash_id = FLASH_MAN_INTEL; | |
221 | + break; | |
210 | 222 | default: |
211 | 223 | info->flash_id = FLASH_UNKNOWN; |
212 | 224 | info->sector_count = 0; |
213 | 225 | info->size = 0; |
214 | - addr[0] = (FPW)0x00FF00FF; /* restore read mode */ | |
215 | - return (0); /* no or unknown flash */ | |
226 | + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ | |
227 | + return (0); /* no or unknown flash */ | |
216 | 228 | } |
217 | 229 | |
218 | - value = addr[1]; /* device ID */ | |
230 | + value = addr[1]; /* device ID */ | |
219 | 231 | |
220 | - switch (value) { | |
221 | - case (FPW)INTEL_ID_28F320J3A: | |
222 | - info->flash_id += FLASH_28F320J3A; | |
223 | - info->sector_count = 32; | |
224 | - info->size = 0x00400000; | |
225 | - break; /* => 4 MB */ | |
232 | + debug ("Device ID @ 0x%08lx: 0x%08lx\n", (ulong)(&addr[1]), value); | |
226 | 233 | |
227 | - case (FPW)INTEL_ID_28F640J3A: | |
228 | - info->flash_id += FLASH_28F640J3A; | |
229 | - info->sector_count = 64; | |
230 | - info->size = 0x00800000; | |
231 | - break; /* => 8 MB */ | |
234 | + switch (value) { | |
235 | + case (FPW) INTEL_ID_28F320J3A: | |
236 | + info->flash_id += FLASH_28F320J3A; | |
237 | + info->sector_count = 32; | |
238 | + info->size = 0x00400000; | |
239 | + break; /* => 4 MB */ | |
232 | 240 | |
233 | - case (FPW)INTEL_ID_28F128J3A: | |
234 | - info->flash_id += FLASH_28F128J3A; | |
235 | - info->sector_count = 128; | |
236 | - info->size = 0x01000000; | |
237 | - break; /* => 16 MB */ | |
241 | + case (FPW) INTEL_ID_28F640J3A: | |
242 | + info->flash_id += FLASH_28F640J3A; | |
243 | + info->sector_count = 64; | |
244 | + info->size = 0x00800000; | |
245 | + break; /* => 8 MB */ | |
238 | 246 | |
247 | + case (FPW) INTEL_ID_28F128J3A: | |
248 | + info->flash_id += FLASH_28F128J3A; | |
249 | + info->sector_count = 128; | |
250 | + info->size = 0x01000000; | |
251 | + break; /* => 16 MB */ | |
252 | + | |
239 | 253 | default: |
240 | 254 | info->flash_id = FLASH_UNKNOWN; |
241 | 255 | break; |
242 | 256 | |
... | ... | @@ -243,11 +257,11 @@ |
243 | 257 | |
244 | 258 | if (info->sector_count > CFG_MAX_FLASH_SECT) { |
245 | 259 | printf ("** ERROR: sector count %d > max (%d) **\n", |
246 | - info->sector_count, CFG_MAX_FLASH_SECT); | |
260 | + info->sector_count, CFG_MAX_FLASH_SECT); | |
247 | 261 | info->sector_count = CFG_MAX_FLASH_SECT; |
248 | 262 | } |
249 | 263 | |
250 | - addr[0] = (FPW)0x00FF00FF; /* restore read mode */ | |
264 | + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ | |
251 | 265 | |
252 | 266 | return (info->size); |
253 | 267 | } |
... | ... | @@ -256,7 +270,7 @@ |
256 | 270 | /*----------------------------------------------------------------------- |
257 | 271 | */ |
258 | 272 | |
259 | -int flash_erase (flash_info_t *info, int s_first, int s_last) | |
273 | +int flash_erase (flash_info_t * info, int s_first, int s_last) | |
260 | 274 | { |
261 | 275 | int flag, prot, sect; |
262 | 276 | ulong type, start, now, last; |
... | ... | @@ -279,7 +293,7 @@ |
279 | 293 | } |
280 | 294 | |
281 | 295 | prot = 0; |
282 | - for (sect=s_first; sect<=s_last; ++sect) { | |
296 | + for (sect = s_first; sect <= s_last; ++sect) { | |
283 | 297 | if (info->protect[sect]) { |
284 | 298 | prot++; |
285 | 299 | } |
286 | 300 | |
287 | 301 | |
288 | 302 | |
289 | 303 | |
290 | 304 | |
291 | 305 | |
292 | 306 | |
293 | 307 | |
... | ... | @@ -293,44 +307,44 @@ |
293 | 307 | } |
294 | 308 | |
295 | 309 | start = get_timer (0); |
296 | - last = start; | |
310 | + last = start; | |
297 | 311 | /* Start erase on unprotected sectors */ |
298 | - for (sect = s_first; sect<=s_last; sect++) { | |
312 | + for (sect = s_first; sect <= s_last; sect++) { | |
299 | 313 | if (info->protect[sect] == 0) { /* not protected */ |
300 | - FPWV *addr = (FPWV *)(info->start[sect]); | |
314 | + FPWV *addr = (FPWV *) (info->start[sect]); | |
301 | 315 | FPW status; |
302 | 316 | |
303 | 317 | /* Disable interrupts which might cause a timeout here */ |
304 | - flag = disable_interrupts(); | |
318 | + flag = disable_interrupts (); | |
305 | 319 | |
306 | - *addr = (FPW)0x00500050; /* clear status register */ | |
307 | - *addr = (FPW)0x00200020; /* erase setup */ | |
308 | - *addr = (FPW)0x00D000D0; /* erase confirm */ | |
320 | + *addr = (FPW) 0x00500050; /* clear status register */ | |
321 | + *addr = (FPW) 0x00200020; /* erase setup */ | |
322 | + *addr = (FPW) 0x00D000D0; /* erase confirm */ | |
309 | 323 | |
310 | 324 | /* re-enable interrupts if necessary */ |
311 | 325 | if (flag) |
312 | - enable_interrupts(); | |
326 | + enable_interrupts (); | |
313 | 327 | |
314 | 328 | /* wait at least 80us - let's wait 1 ms */ |
315 | 329 | udelay (1000); |
316 | 330 | |
317 | - while (((status = *addr) & (FPW)0x00800080) != (FPW)0x00800080) { | |
318 | - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) { | |
319 | - printf ("Timeout\n"); | |
320 | - *addr = (FPW)0x00B000B0; /* suspend erase */ | |
321 | - *addr = (FPW)0x00FF00FF; /* reset to read mode */ | |
322 | - rcode = 1; | |
323 | - break; | |
324 | - } | |
331 | + while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { | |
332 | + if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) { | |
333 | + printf ("Timeout\n"); | |
334 | + *addr = (FPW) 0x00B000B0; /* suspend erase */ | |
335 | + *addr = (FPW) 0x00FF00FF; /* reset to read mode */ | |
336 | + rcode = 1; | |
337 | + break; | |
338 | + } | |
325 | 339 | |
326 | - /* show that we're waiting */ | |
327 | - if ((now - last) > 1000) { /* every second */ | |
328 | - putc ('.'); | |
329 | - last = now; | |
330 | - } | |
340 | + /* show that we're waiting */ | |
341 | + if ((now - last) > 1000) { /* every second */ | |
342 | + putc ('.'); | |
343 | + last = now; | |
344 | + } | |
331 | 345 | } |
332 | 346 | |
333 | - *addr = (FPW)0x00FF00FF; /* reset to read mode */ | |
347 | + *addr = (FPW) 0x00FF00FF; /* reset to read mode */ | |
334 | 348 | } |
335 | 349 | } |
336 | 350 | printf (" done\n"); |
337 | 351 | |
338 | 352 | |
... | ... | @@ -345,15 +359,12 @@ |
345 | 359 | * 4 - Flash not identified |
346 | 360 | */ |
347 | 361 | |
348 | -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) | |
362 | +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) | |
349 | 363 | { |
350 | 364 | ulong cp, wp; |
351 | 365 | FPW data; |
352 | -#if 0 | |
353 | - int count, i, l, rc, port_width; | |
354 | -#else | |
366 | + | |
355 | 367 | int i, l, rc, port_width; |
356 | -#endif | |
357 | 368 | |
358 | 369 | if (info->flash_id == FLASH_UNKNOWN) { |
359 | 370 | return 4; |
360 | 371 | |
361 | 372 | |
362 | 373 | |
... | ... | @@ -372,19 +383,19 @@ |
372 | 383 | */ |
373 | 384 | if ((l = addr - wp) != 0) { |
374 | 385 | data = 0; |
375 | - for (i=0, cp=wp; i<l; ++i, ++cp) { | |
376 | - data = (data << 8) | (*(uchar *)cp); | |
386 | + for (i = 0, cp = wp; i < l; ++i, ++cp) { | |
387 | + data = (data << 8) | (*(uchar *) cp); | |
377 | 388 | } |
378 | - for (; i<port_width && cnt>0; ++i) { | |
389 | + for (; i < port_width && cnt > 0; ++i) { | |
379 | 390 | data = (data << 8) | *src++; |
380 | 391 | --cnt; |
381 | 392 | ++cp; |
382 | 393 | } |
383 | - for (; cnt==0 && i<port_width; ++i, ++cp) { | |
384 | - data = (data << 8) | (*(uchar *)cp); | |
394 | + for (; cnt == 0 && i < port_width; ++i, ++cp) { | |
395 | + data = (data << 8) | (*(uchar *) cp); | |
385 | 396 | } |
386 | 397 | |
387 | - if ((rc = write_data(info, wp, data)) != 0) { | |
398 | + if ((rc = write_data (info, wp, data)) != 0) { | |
388 | 399 | return (rc); |
389 | 400 | } |
390 | 401 | wp += port_width; |
391 | 402 | |
392 | 403 | |
393 | 404 | |
394 | 405 | |
... | ... | @@ -393,26 +404,16 @@ |
393 | 404 | /* |
394 | 405 | * handle word aligned part |
395 | 406 | */ |
396 | -#if 0 | |
397 | - count = 0; | |
398 | -#endif | |
399 | 407 | while (cnt >= port_width) { |
400 | 408 | data = 0; |
401 | - for (i=0; i<port_width; ++i) { | |
409 | + for (i = 0; i < port_width; ++i) { | |
402 | 410 | data = (data << 8) | *src++; |
403 | 411 | } |
404 | - if ((rc = write_data(info, wp, data)) != 0) { | |
412 | + if ((rc = write_data (info, wp, data)) != 0) { | |
405 | 413 | return (rc); |
406 | 414 | } |
407 | - wp += port_width; | |
415 | + wp += port_width; | |
408 | 416 | cnt -= port_width; |
409 | -#if 0 | |
410 | - if (count++ > 0x20000) | |
411 | - { | |
412 | - putc('.'); | |
413 | - count = 0; | |
414 | - } | |
415 | -#endif | |
416 | 417 | } |
417 | 418 | |
418 | 419 | if (cnt == 0) { |
419 | 420 | |
420 | 421 | |
... | ... | @@ -423,15 +424,15 @@ |
423 | 424 | * handle unaligned tail bytes |
424 | 425 | */ |
425 | 426 | data = 0; |
426 | - for (i=0, cp=wp; i<port_width && cnt>0; ++i, ++cp) { | |
427 | + for (i = 0, cp = wp; i < port_width && cnt > 0; ++i, ++cp) { | |
427 | 428 | data = (data << 8) | *src++; |
428 | 429 | --cnt; |
429 | 430 | } |
430 | - for (; i<port_width; ++i, ++cp) { | |
431 | - data = (data << 8) | (*(uchar *)cp); | |
431 | + for (; i < port_width; ++i, ++cp) { | |
432 | + data = (data << 8) | (*(uchar *) cp); | |
432 | 433 | } |
433 | 434 | |
434 | - return (write_data(info, wp, data)); | |
435 | + return (write_data (info, wp, data)); | |
435 | 436 | } |
436 | 437 | |
437 | 438 | /*----------------------------------------------------------------------- |
438 | 439 | |
439 | 440 | |
440 | 441 | |
441 | 442 | |
442 | 443 | |
443 | 444 | |
444 | 445 | |
... | ... | @@ -440,38 +441,38 @@ |
440 | 441 | * 1 - write timeout |
441 | 442 | * 2 - Flash not erased |
442 | 443 | */ |
443 | -static int write_data (flash_info_t *info, ulong dest, FPW data) | |
444 | +static int write_data (flash_info_t * info, ulong dest, FPW data) | |
444 | 445 | { |
445 | - FPWV *addr = (FPWV *)dest; | |
446 | + FPWV *addr = (FPWV *) dest; | |
446 | 447 | ulong status; |
447 | 448 | ulong start; |
448 | 449 | int flag; |
449 | 450 | |
450 | 451 | /* Check if Flash is (sufficiently) erased */ |
451 | 452 | if ((*addr & data) != data) { |
452 | - printf("not erased at %08lx (%x)\n",(ulong)addr,*addr); | |
453 | + printf ("not erased at %08lx (%x)\n", (ulong) addr, *addr); | |
453 | 454 | return (2); |
454 | 455 | } |
455 | 456 | /* Disable interrupts which might cause a timeout here */ |
456 | - flag = disable_interrupts(); | |
457 | + flag = disable_interrupts (); | |
457 | 458 | |
458 | - *addr = (FPW)0x00400040; /* write setup */ | |
459 | + *addr = (FPW) 0x00400040; /* write setup */ | |
459 | 460 | *addr = data; |
460 | 461 | |
461 | 462 | /* re-enable interrupts if necessary */ |
462 | 463 | if (flag) |
463 | - enable_interrupts(); | |
464 | + enable_interrupts (); | |
464 | 465 | |
465 | 466 | start = get_timer (0); |
466 | 467 | |
467 | - while (((status = *addr) & (FPW)0x00800080) != (FPW)0x00800080) { | |
468 | - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { | |
469 | - *addr = (FPW)0x00FF00FF; /* restore read mode */ | |
468 | + while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) { | |
469 | + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { | |
470 | + *addr = (FPW) 0x00FF00FF; /* restore read mode */ | |
470 | 471 | return (1); |
471 | 472 | } |
472 | 473 | } |
473 | 474 | |
474 | - *addr = (FPW)0x00FF00FF; /* restore read mode */ | |
475 | + *addr = (FPW) 0x00FF00FF; /* restore read mode */ | |
475 | 476 | |
476 | 477 | return (0); |
477 | 478 | } |
common/env_flash.c
cpu/mpc824x/Makefile
... | ... | @@ -27,12 +27,15 @@ |
27 | 27 | |
28 | 28 | START = start.S drivers/i2c/i2c2.o |
29 | 29 | OBJS = traps.o cpu.o cpu_init.o interrupts.o speed.o \ |
30 | - drivers/epic/epic1.o drivers/i2c/i2c1.o pci.o | |
30 | + drivers/epic/epic1.o drivers/i2c/i2c1.o pci.o bedbug_603e.o | |
31 | 31 | |
32 | 32 | all: .depend $(START) $(LIB) |
33 | 33 | |
34 | 34 | $(LIB): $(OBJS) |
35 | 35 | $(AR) crv $@ $(OBJS) drivers/i2c/i2c2.o |
36 | + | |
37 | +bedbug_603e.c: | |
38 | + ln -s ../mpc8260/bedbug_603e.c bedbug_603e.c | |
36 | 39 | |
37 | 40 | ######################################################################### |
38 | 41 |
cpu/mpc824x/start.S
... | ... | @@ -336,7 +336,7 @@ |
336 | 336 | STD_EXCEPTION(EXC_OFF_ITME, InstructionTransMiss, UnknownException) |
337 | 337 | STD_EXCEPTION(EXC_OFF_DLTME, DataLoadTransMiss, UnknownException) |
338 | 338 | STD_EXCEPTION(EXC_OFF_DSTME, DataStoreTransMiss, UnknownException) |
339 | - STD_EXCEPTION(EXC_OFF_IABE, InstructionBreakpoint, UnknownException) | |
339 | + STD_EXCEPTION(EXC_OFF_IABE, InstructionBreakpoint, DebugException) | |
340 | 340 | STD_EXCEPTION(EXC_OFF_SMIE, SysManageInt, UnknownException) |
341 | 341 | STD_EXCEPTION(0x1500, Reserved5, UnknownException) |
342 | 342 | STD_EXCEPTION(0x1600, Reserved6, UnknownException) |
cpu/mpc824x/traps.c
... | ... | @@ -176,6 +176,21 @@ |
176 | 176 | _exception(0, regs); |
177 | 177 | } |
178 | 178 | |
179 | +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) | |
180 | +extern void do_bedbug_breakpoint(struct pt_regs *); | |
181 | +#endif | |
182 | + | |
183 | +void | |
184 | +DebugException(struct pt_regs *regs) | |
185 | +{ | |
186 | + | |
187 | + printf("Debugger trap at @ %lx\n", regs->nip ); | |
188 | + show_regs(regs); | |
189 | +#if (CONFIG_COMMANDS & CFG_CMD_BEDBUG) | |
190 | + do_bedbug_breakpoint( regs ); | |
191 | +#endif | |
192 | +} | |
193 | + | |
179 | 194 | /* Probe an address by reading. If not present, return -1, otherwise |
180 | 195 | * return 0. |
181 | 196 | */ |
cpu/xscale/Makefile
cpu/xscale/i2c.c
1 | +/* | |
2 | + * (C) Copyright 2000 | |
3 | + * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it | |
4 | + * | |
5 | + * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
6 | + * Marius Groeger <mgroeger@sysgo.de> | |
7 | + * | |
8 | + * (C) Copyright 2003 Pengutronix e.K. | |
9 | + * Robert Schwebel <r.schwebel@pengutronix.de> | |
10 | + * | |
11 | + * See file CREDITS for list of people who contributed to this | |
12 | + * project. | |
13 | + * | |
14 | + * This program is free software; you can redistribute it and/or | |
15 | + * modify it under the terms of the GNU General Public License as | |
16 | + * published by the Free Software Foundation; either version 2 of | |
17 | + * the License, or (at your option) any later version. | |
18 | + * | |
19 | + * This program is distributed in the hope that it will be useful, | |
20 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
21 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
22 | + * GNU General Public License for more details. | |
23 | + * | |
24 | + * You should have received a copy of the GNU General Public License | |
25 | + * along with this program; if not, write to the Free Software | |
26 | + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
27 | + * MA 02111-1307 USA | |
28 | + * | |
29 | + * Back ported to the 8xx platform (from the 8260 platform) by | |
30 | + * Murray.Jensen@cmst.csiro.au, 27-Jan-01. | |
31 | + */ | |
32 | + | |
33 | +/* FIXME: this file is PXA255 specific! What about other XScales? */ | |
34 | + | |
35 | +#include <common.h> | |
36 | + | |
37 | +#ifdef CONFIG_HARD_I2C | |
38 | + | |
39 | +/* | |
40 | + * - CFG_I2C_SPEED | |
41 | + * - I2C_PXA_SLAVE_ADDR | |
42 | + */ | |
43 | + | |
44 | +#include <asm/arch/pxa-regs.h> | |
45 | +#include <i2c.h> | |
46 | + | |
47 | +//#define DEBUG_I2C 1 /* activate local debugging output */ | |
48 | +#define I2C_PXA_SLAVE_ADDR 0x1 /* slave pxa unit address */ | |
49 | +#define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE) | |
50 | +#define I2C_ISR_INIT 0x7FF | |
51 | + | |
52 | +#ifdef DEBUG_I2C | |
53 | +#define PRINTD(x) printf x | |
54 | +#else | |
55 | +#define PRINTD(x) | |
56 | +#endif | |
57 | + | |
58 | + | |
59 | +/* Shall the current transfer have a start/stop condition? */ | |
60 | +#define I2C_COND_NORMAL 0 | |
61 | +#define I2C_COND_START 1 | |
62 | +#define I2C_COND_STOP 2 | |
63 | + | |
64 | +/* Shall the current transfer be ack/nacked or being waited for it? */ | |
65 | +#define I2C_ACKNAK_WAITACK 1 | |
66 | +#define I2C_ACKNAK_SENDACK 2 | |
67 | +#define I2C_ACKNAK_SENDNAK 4 | |
68 | + | |
69 | +/* Specify who shall transfer the data (master or slave) */ | |
70 | +#define I2C_READ 0 | |
71 | +#define I2C_WRITE 1 | |
72 | + | |
73 | +/* All transfers are described by this data structure */ | |
74 | +struct i2c_msg { | |
75 | + u8 condition; | |
76 | + u8 acknack; | |
77 | + u8 direction; | |
78 | + u8 data; | |
79 | +}; | |
80 | + | |
81 | + | |
82 | +/** | |
83 | + * i2c_pxa_reset: - reset the host controller | |
84 | + * | |
85 | + */ | |
86 | + | |
87 | +static void i2c_reset( void ) | |
88 | +{ | |
89 | + ICR &= ~ICR_IUE; /* disable unit */ | |
90 | + ICR |= ICR_UR; /* reset the unit */ | |
91 | + udelay(100); | |
92 | + ICR &= ~ICR_IUE; /* disable unit */ | |
93 | + CKEN |= CKEN14_I2C; /* set the global I2C clock on */ | |
94 | + ISAR = I2C_PXA_SLAVE_ADDR; /* set our slave address */ | |
95 | + ICR = I2C_ICR_INIT; /* set control register values */ | |
96 | + ISR = I2C_ISR_INIT; /* set clear interrupt bits */ | |
97 | + ICR |= ICR_IUE; /* enable unit */ | |
98 | + udelay(100); | |
99 | +} | |
100 | + | |
101 | + | |
102 | +/** | |
103 | + * i2c_isr_set_cleared: - wait until certain bits of the I2C status register | |
104 | + * are set and cleared | |
105 | + * | |
106 | + * @return: 0 in case of success, 1 means timeout (no match within 10 ms). | |
107 | + */ | |
108 | + | |
109 | +static int i2c_isr_set_cleared( unsigned long set_mask, unsigned long cleared_mask ) | |
110 | +{ | |
111 | + int timeout = 10000; | |
112 | + | |
113 | + while( ((ISR & set_mask)!=set_mask) || ((ISR & cleared_mask)!=0) ){ | |
114 | + udelay( 10 ); | |
115 | + if( timeout-- < 0 ) return 0; | |
116 | + } | |
117 | + | |
118 | + return 1; | |
119 | +} | |
120 | + | |
121 | + | |
122 | +/** | |
123 | + * i2c_transfer: - Transfer one byte over the i2c bus | |
124 | + * | |
125 | + * This function can tranfer a byte over the i2c bus in both directions. | |
126 | + * It is used by the public API functions. | |
127 | + * | |
128 | + * @return: 0: transfer successful | |
129 | + * -1: message is empty | |
130 | + * -2: transmit timeout | |
131 | + * -3: ACK missing | |
132 | + * -4: receive timeout | |
133 | + * -5: illegal parameters | |
134 | + * -6: bus is busy and couldn't be aquired | |
135 | + */ | |
136 | +int i2c_transfer(struct i2c_msg *msg) | |
137 | +{ | |
138 | + int ret; | |
139 | + | |
140 | + if (!msg) | |
141 | + goto transfer_error_msg_empty; | |
142 | + | |
143 | + switch(msg->direction) { | |
144 | + | |
145 | + case I2C_WRITE: | |
146 | + | |
147 | + /* check if bus is not busy */ | |
148 | + if (!i2c_isr_set_cleared(0,ISR_IBB)) | |
149 | + goto transfer_error_bus_busy; | |
150 | + | |
151 | + /* start transmission */ | |
152 | + ICR &= ~ICR_START; | |
153 | + ICR &= ~ICR_STOP; | |
154 | + IDBR = msg->data; | |
155 | + if (msg->condition == I2C_COND_START) ICR |= ICR_START; | |
156 | + if (msg->condition == I2C_COND_STOP) ICR |= ICR_STOP; | |
157 | + if (msg->acknack == I2C_ACKNAK_SENDNAK) ICR |= ICR_ACKNAK; | |
158 | + if (msg->acknack == I2C_ACKNAK_SENDACK) ICR &= ~ICR_ACKNAK; | |
159 | + ICR &= ~ICR_ALDIE; | |
160 | + ICR |= ICR_TB; | |
161 | + | |
162 | + /* transmit register empty? */ | |
163 | + if (!i2c_isr_set_cleared(ISR_ITE,0)) | |
164 | + goto transfer_error_transmit_timeout; | |
165 | + | |
166 | + /* clear 'transmit empty' state */ | |
167 | + ISR |= ISR_ITE; | |
168 | + | |
169 | + /* wait for ACK from slave */ | |
170 | + if (msg->acknack == I2C_ACKNAK_WAITACK) | |
171 | + if (!i2c_isr_set_cleared(0,ISR_ACKNAK)) | |
172 | + goto transfer_error_ack_missing; | |
173 | + break; | |
174 | + | |
175 | + case I2C_READ: | |
176 | + | |
177 | + /* check if bus is not busy */ | |
178 | + if (!i2c_isr_set_cleared(0,ISR_IBB)) | |
179 | + goto transfer_error_bus_busy; | |
180 | + | |
181 | + /* start receive */ | |
182 | + ICR &= ~ICR_START; | |
183 | + ICR &= ~ICR_STOP; | |
184 | + if (msg->condition == I2C_COND_START) ICR |= ICR_START; | |
185 | + if (msg->condition == I2C_COND_STOP) ICR |= ICR_STOP; | |
186 | + if (msg->acknack == I2C_ACKNAK_SENDNAK) ICR |= ICR_ACKNAK; | |
187 | + if (msg->acknack == I2C_ACKNAK_SENDACK) ICR &= ~ICR_ACKNAK; | |
188 | + ICR &= ~ICR_ALDIE; | |
189 | + ICR |= ICR_TB; | |
190 | + | |
191 | + /* receive register full? */ | |
192 | + if (!i2c_isr_set_cleared(ISR_IRF,0)) | |
193 | + goto transfer_error_receive_timeout; | |
194 | + | |
195 | + msg->data = IDBR; | |
196 | + | |
197 | + /* clear 'receive empty' state */ | |
198 | + ISR |= ISR_IRF; | |
199 | + | |
200 | + break; | |
201 | + | |
202 | + default: | |
203 | + | |
204 | + goto transfer_error_illegal_param; | |
205 | + | |
206 | + } | |
207 | + | |
208 | + return 0; | |
209 | + | |
210 | +transfer_error_msg_empty: | |
211 | + PRINTD(("i2c_transfer: error: 'msg' is empty\n")); | |
212 | + ret = -1; goto i2c_transfer_finish; | |
213 | + | |
214 | +transfer_error_transmit_timeout: | |
215 | + PRINTD(("i2c_transfer: error: transmit timeout\n")); | |
216 | + ret = -2; goto i2c_transfer_finish; | |
217 | + | |
218 | +transfer_error_ack_missing: | |
219 | + PRINTD(("i2c_transfer: error: ACK missing\n")); | |
220 | + ret = -3; goto i2c_transfer_finish; | |
221 | + | |
222 | +transfer_error_receive_timeout: | |
223 | + PRINTD(("i2c_transfer: error: receive timeout\n")); | |
224 | + ret = -4; goto i2c_transfer_finish; | |
225 | + | |
226 | +transfer_error_illegal_param: | |
227 | + PRINTD(("i2c_transfer: error: illegal parameters\n")); | |
228 | + ret = -5; goto i2c_transfer_finish; | |
229 | + | |
230 | +transfer_error_bus_busy: | |
231 | + PRINTD(("i2c_transfer: error: bus is busy\n")); | |
232 | + ret = -6; goto i2c_transfer_finish; | |
233 | + | |
234 | +i2c_transfer_finish: | |
235 | + PRINTD(("i2c_transfer: ISR: 0x%04x\n",ISR)); | |
236 | + i2c_reset(); | |
237 | + return ret; | |
238 | + | |
239 | +} | |
240 | + | |
241 | +/* ------------------------------------------------------------------------ */ | |
242 | +/* API Functions */ | |
243 | +/* ------------------------------------------------------------------------ */ | |
244 | + | |
245 | +void i2c_init(int speed, int slaveaddr) | |
246 | +{ | |
247 | +} | |
248 | + | |
249 | + | |
250 | +/** | |
251 | + * i2c_probe: - Test if a chip answers for a given i2c address | |
252 | + * | |
253 | + * @chip: address of the chip which is searched for | |
254 | + * @return: 0 if a chip was found, -1 otherwhise | |
255 | + */ | |
256 | + | |
257 | +int i2c_probe(uchar chip) | |
258 | +{ | |
259 | + struct i2c_msg msg; | |
260 | + | |
261 | + i2c_reset(); | |
262 | + | |
263 | + msg.condition = I2C_COND_START; | |
264 | + msg.acknack = I2C_ACKNAK_WAITACK; | |
265 | + msg.direction = I2C_WRITE; | |
266 | + msg.data = (chip << 1) + 1; | |
267 | + if (i2c_transfer(&msg)) return -1; | |
268 | + | |
269 | + msg.condition = I2C_COND_STOP; | |
270 | + msg.acknack = I2C_ACKNAK_SENDNAK; | |
271 | + msg.direction = I2C_READ; | |
272 | + msg.data = 0x00; | |
273 | + if (i2c_transfer(&msg)) return -1; | |
274 | + | |
275 | + return 0; | |
276 | +} | |
277 | + | |
278 | + | |
279 | +/** | |
280 | + * i2c_read: - Read multiple bytes from an i2c device | |
281 | + * | |
282 | + * The higher level routines take into account that this function is only | |
283 | + * called with len < page length of the device (see configuration file) | |
284 | + * | |
285 | + * @chip: address of the chip which is to be read | |
286 | + * @addr: i2c data address within the chip | |
287 | + * @alen: length of the i2c data address (1..2 bytes) | |
288 | + * @buffer: where to write the data | |
289 | + * @len: how much byte do we want to read | |
290 | + * @return: 0 in case of success | |
291 | + */ | |
292 | + | |
293 | +int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) | |
294 | +{ | |
295 | + struct i2c_msg msg; | |
296 | + u8 addr_bytes[3]; /* lowest...highest byte of data address */ | |
297 | + int ret; | |
298 | + | |
299 | + PRINTD(("i2c_read(chip=0x%02x, addr=0x%02x, alen=0x%02x, len=0x%02x)\n",chip,addr,alen,len)); | |
300 | + | |
301 | + i2c_reset(); | |
302 | + | |
303 | + /* dummy chip address write */ | |
304 | + PRINTD(("i2c_read: dummy chip address write\n")); | |
305 | + msg.condition = I2C_COND_START; | |
306 | + msg.acknack = I2C_ACKNAK_WAITACK; | |
307 | + msg.direction = I2C_WRITE; | |
308 | + msg.data = (chip << 1); | |
309 | + msg.data &= 0xFE; | |
310 | + if ((ret=i2c_transfer(&msg))) return -1; | |
311 | + | |
312 | + /* | |
313 | + * send memory address bytes; | |
314 | + * alen defines how much bytes we have to send. | |
315 | + */ | |
316 | + //addr &= ((1 << CFG_EEPROM_PAGE_WRITE_BITS)-1); | |
317 | + addr_bytes[0] = (u8)((addr >> 0) & 0x000000FF); | |
318 | + addr_bytes[1] = (u8)((addr >> 8) & 0x000000FF); | |
319 | + addr_bytes[2] = (u8)((addr >> 16) & 0x000000FF); | |
320 | + | |
321 | + while (--alen >= 0) { | |
322 | + | |
323 | + PRINTD(("i2c_read: send memory word address byte %1d\n",alen)); | |
324 | + msg.condition = I2C_COND_NORMAL; | |
325 | + msg.acknack = I2C_ACKNAK_WAITACK; | |
326 | + msg.direction = I2C_WRITE; | |
327 | + msg.data = addr_bytes[alen]; | |
328 | + if ((ret=i2c_transfer(&msg))) return -1; | |
329 | + } | |
330 | + | |
331 | + | |
332 | + /* start read sequence */ | |
333 | + PRINTD(("i2c_read: start read sequence\n")); | |
334 | + msg.condition = I2C_COND_START; | |
335 | + msg.acknack = I2C_ACKNAK_WAITACK; | |
336 | + msg.direction = I2C_WRITE; | |
337 | + msg.data = (chip << 1); | |
338 | + msg.data |= 0x01; | |
339 | + if ((ret=i2c_transfer(&msg))) return -1; | |
340 | + | |
341 | + /* read bytes; send NACK at last byte */ | |
342 | + while (len--) { | |
343 | + | |
344 | + if (len==0) { | |
345 | + msg.condition = I2C_COND_STOP; | |
346 | + msg.acknack = I2C_ACKNAK_SENDNAK; | |
347 | + } else { | |
348 | + msg.condition = I2C_COND_NORMAL; | |
349 | + msg.acknack = I2C_ACKNAK_SENDACK; | |
350 | + } | |
351 | + | |
352 | + msg.direction = I2C_READ; | |
353 | + msg.data = 0x00; | |
354 | + if ((ret=i2c_transfer(&msg))) return -1; | |
355 | + | |
356 | + *(buffer++) = msg.data; | |
357 | + | |
358 | + PRINTD(("i2c_read: reading byte (0x%08x)=0x%02x\n",(unsigned int)buffer,*buffer)); | |
359 | + | |
360 | + } | |
361 | + | |
362 | + i2c_reset(); | |
363 | + | |
364 | + return 0; | |
365 | +} | |
366 | + | |
367 | + | |
368 | +/** | |
369 | + * i2c_write: - Write multiple bytes to an i2c device | |
370 | + * | |
371 | + * The higher level routines take into account that this function is only | |
372 | + * called with len < page length of the device (see configuration file) | |
373 | + * | |
374 | + * @chip: address of the chip which is to be written | |
375 | + * @addr: i2c data address within the chip | |
376 | + * @alen: length of the i2c data address (1..2 bytes) | |
377 | + * @buffer: where to find the data to be written | |
378 | + * @len: how much byte do we want to read | |
379 | + * @return: 0 in case of success | |
380 | + */ | |
381 | + | |
382 | +int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) | |
383 | +{ | |
384 | + struct i2c_msg msg; | |
385 | + u8 addr_bytes[3]; /* lowest...highest byte of data address */ | |
386 | + | |
387 | + PRINTD(("i2c_write(chip=0x%02x, addr=0x%02x, alen=0x%02x, len=0x%02x)\n",chip,addr,alen,len)); | |
388 | + | |
389 | + i2c_reset(); | |
390 | + | |
391 | + /* chip address write */ | |
392 | + PRINTD(("i2c_write: chip address write\n")); | |
393 | + msg.condition = I2C_COND_START; | |
394 | + msg.acknack = I2C_ACKNAK_WAITACK; | |
395 | + msg.direction = I2C_WRITE; | |
396 | + msg.data = (chip << 1); | |
397 | + msg.data &= 0xFE; | |
398 | + if (i2c_transfer(&msg)) return -1; | |
399 | + | |
400 | + /* | |
401 | + * send memory address bytes; | |
402 | + * alen defines how much bytes we have to send. | |
403 | + */ | |
404 | + addr_bytes[0] = (u8)((addr >> 0) & 0x000000FF); | |
405 | + addr_bytes[1] = (u8)((addr >> 8) & 0x000000FF); | |
406 | + addr_bytes[2] = (u8)((addr >> 16) & 0x000000FF); | |
407 | + | |
408 | + while (--alen >= 0) { | |
409 | + | |
410 | + PRINTD(("i2c_write: send memory word address\n")); | |
411 | + msg.condition = I2C_COND_NORMAL; | |
412 | + msg.acknack = I2C_ACKNAK_WAITACK; | |
413 | + msg.direction = I2C_WRITE; | |
414 | + msg.data = addr_bytes[alen]; | |
415 | + if (i2c_transfer(&msg)) return -1; | |
416 | + } | |
417 | + | |
418 | + /* write bytes; send NACK at last byte */ | |
419 | + while (len--) { | |
420 | + | |
421 | + PRINTD(("i2c_write: writing byte (0x%08x)=0x%02x\n",(unsigned int)buffer,*buffer)); | |
422 | + | |
423 | + if (len==0) | |
424 | + msg.condition = I2C_COND_STOP; | |
425 | + else | |
426 | + msg.condition = I2C_COND_NORMAL; | |
427 | + | |
428 | + msg.acknack = I2C_ACKNAK_WAITACK; | |
429 | + msg.direction = I2C_WRITE; | |
430 | + msg.data = *(buffer++); | |
431 | + | |
432 | + if (i2c_transfer(&msg)) return -1; | |
433 | + | |
434 | + } | |
435 | + | |
436 | + i2c_reset(); | |
437 | + | |
438 | + return 0; | |
439 | + | |
440 | +} | |
441 | + | |
442 | +uchar i2c_reg_read (uchar chip, uchar reg) | |
443 | +{ | |
444 | + PRINTD(("i2c_reg_read(chip=0x%02x, reg=0x%02x)\n",chip,reg)); | |
445 | + return 0; | |
446 | +} | |
447 | + | |
448 | +void i2c_reg_write(uchar chip, uchar reg, uchar val) | |
449 | +{ | |
450 | + PRINTD(("i2c_reg_write(chip=0x%02x, reg=0x%02x, val=0x%02x)\n",chip,reg,val)); | |
451 | +} | |
452 | + | |
453 | +#endif /* CONFIG_HARD_I2C */ |
doc/README.POST
1 | +Power-On-Self-Test support in U-Boot | |
2 | +------------------------------------ | |
3 | + | |
4 | +This project is to support Power-On-Self-Test (POST) in U-Boot. | |
5 | + | |
6 | +1. High-level requirements | |
7 | + | |
8 | +The key rquirements for this project are as follows: | |
9 | + | |
10 | +1) The project shall develop a flexible framework for implementing | |
11 | + and running Power-On-Self-Test in U-Boot. This framework shall | |
12 | + possess the following features: | |
13 | + | |
14 | + o) Extensibility | |
15 | + | |
16 | + The framework shall allow adding/removing/replacing POST tests. | |
17 | + Also, standalone POST tests shall be supported. | |
18 | + | |
19 | + o) Configurability | |
20 | + | |
21 | + The framework shall allow run-time configuration of the lists | |
22 | + of tests running on normal/power-fail booting. | |
23 | + | |
24 | + o) Controllability | |
25 | + | |
26 | + The framework shall support manual running of the POST tests. | |
27 | + | |
28 | +2) The results of tests shall be saved so that it will be possible to | |
29 | + retrieve them from Linux. | |
30 | + | |
31 | +3) The following POST tests shall be developed for MPC823E-based | |
32 | + boards: | |
33 | + | |
34 | + o) CPU test | |
35 | + o) Cache test | |
36 | + o) Memory test | |
37 | + o) Ethernet test | |
38 | + o) Serial channels test | |
39 | + o) Watchdog timer test | |
40 | + o) RTC test | |
41 | + o) I2C test | |
42 | + o) SPI test | |
43 | + o) USB test | |
44 | + | |
45 | +4) The LWMON board shall be used for reference. | |
46 | + | |
47 | +2. Design | |
48 | + | |
49 | +This section details the key points of the design for the project. | |
50 | +The whole project can be divided into two independent tasks: | |
51 | +enhancing U-Boot/Linux to provide a common framework for running POST | |
52 | +tests and developing such tests for particular hardware. | |
53 | + | |
54 | +2.1. Hardware-independent POST layer | |
55 | + | |
56 | +A new optional module will be added to U-Boot, which will run POST | |
57 | +tests and collect their results at boot time. Also, U-Boot will | |
58 | +support running POST tests manually at any time by executing a | |
59 | +special command from the system console. | |
60 | + | |
61 | +The list of available POST tests will be configured at U-Boot build | |
62 | +time. The POST layer will allow the developer to add any custom POST | |
63 | +tests. All POST tests will be divided into the following groups: | |
64 | + | |
65 | + 1) Tests running on power-on booting only | |
66 | + | |
67 | + This group will contain those tests that run only once on | |
68 | + power-on reset (e.g. watchdog test) | |
69 | + | |
70 | + 2) Tests running on normal booting only | |
71 | + | |
72 | + This group will contain those tests that do not take much | |
73 | + time and can be run on the regular basis (e.g. CPU test) | |
74 | + | |
75 | + 3) Tests running on power-fail booting only | |
76 | + | |
77 | + This group will contain POST tests that consume much time | |
78 | + and cannot be run regularly (e.g. I2C test) | |
79 | + | |
80 | + 4) Manually executed tests | |
81 | + | |
82 | + This group will contain those tests that can be run manually. | |
83 | + | |
84 | +If necessary, some tests may belong to several groups simultaneously. | |
85 | +For example, SDRAM test may run on both noarmal and power-fail | |
86 | +booting. On normal booting, SDRAM test may perform a fast superficial | |
87 | +memory test only, while running on power-fail booting it may perform | |
88 | +a full memory check-up. | |
89 | + | |
90 | +Also, all tests will be discriminated by the moment they run at. | |
91 | +Specifically, the following groups will be singled out: | |
92 | + | |
93 | + 1) Tests running before relocating to RAM | |
94 | + | |
95 | + These tests will run immediatelly after initializing RAM | |
96 | + as to enable modifying it without taking care of its | |
97 | + contents. Basically, this group will contain memory tests | |
98 | + only. | |
99 | + | |
100 | + 2) Tests running after relocating to RAM | |
101 | + | |
102 | + These tests will run immediately before entering the main | |
103 | + loop as to guarantee full hardware initialization. | |
104 | + | |
105 | +The POST layer will also distinguish a special group of tests that | |
106 | +may cause system rebooting (e.g. watchdog test). For such tests, the | |
107 | +layer will automatically detect rebooting and will notify the test | |
108 | +about it. | |
109 | + | |
110 | +2.1.1. POST layer interfaces | |
111 | + | |
112 | +This section details the interfaces between the POST layer and the | |
113 | +rest of U-Boot. | |
114 | + | |
115 | +The following flags will be defined: | |
116 | + | |
117 | +#define POST_ROM 0x01 /* test runs in ROM */ | |
118 | +#define POST_RAM 0x02 /* test runs in RAM */ | |
119 | +#define POST_POWERON 0x04 /* test runs on power-on booting */ | |
120 | +#define POST_NORMAL 0x08 /* test runs on normal booting */ | |
121 | +#define POST_SHUTDOWN 0x10 /* test runs on power-fail booting */ | |
122 | +#define POST_MANUAL 0x20 /* test can be executed manually */ | |
123 | +#define POST_REBOOT 0x80 /* test may cause rebooting */ | |
124 | + | |
125 | +The POST layer will export the following interface routines: | |
126 | + | |
127 | + o) int post_run(bd_t *bd, char *name, int flags); | |
128 | + | |
129 | + This routine will run the test (or the group of tests) specified | |
130 | + by the name and flag arguments. More specifically, if the name | |
131 | + argument is not NULL, the test with this name will be performed, | |
132 | + otherwise all tests running in ROM/RAM (depending on the flag | |
133 | + argument) will be executed. This routine will be called at least | |
134 | + twice with name set to NULL, once from board_init_f() and once | |
135 | + from board_init_r(). The flags argument will also specify the | |
136 | + mode the test is executed in (power-on, normal, power-fail, | |
137 | + manual). | |
138 | + | |
139 | + o) void post_reloc(ulong offset); | |
140 | + | |
141 | + This routine will be called from board_init_r() and will | |
142 | + relocate the POST test table. | |
143 | + | |
144 | + o) int post_info(char *name); | |
145 | + | |
146 | + This routine will print the list of all POST tests that can be | |
147 | + executed manually if name is NULL, and the description of a | |
148 | + particular test if name is not NULL. | |
149 | + | |
150 | + o) int post_log(char *format, ...); | |
151 | + | |
152 | + This routine will be called from POST tests to log their | |
153 | + results. Basically, this routine will print the results to | |
154 | + stderr. The format of the arguments and the return value | |
155 | + will be identical to the printf() routine. | |
156 | + | |
157 | +Also, the following board-specific routines will be called from the | |
158 | +U-Boot common code: | |
159 | + | |
160 | + o) int board_power_mode(void) | |
161 | + | |
162 | + This routine will return the mode the system is running in | |
163 | + (POST_POWERON, POST_NORMAL or POST_SHUTDOWN). | |
164 | + | |
165 | + o) void board_poweroff(void) | |
166 | + | |
167 | + This routine will turn off the power supply of the board. It | |
168 | + will be called on power-fail booting after running all POST | |
169 | + tests. | |
170 | + | |
171 | +The list of available POST tests be kept in the post_tests array | |
172 | +filled at U-Boot build time. The format of entry in this array will | |
173 | +be as follows: | |
174 | + | |
175 | +struct post_test { | |
176 | + char *name; | |
177 | + char *cmd; | |
178 | + char *desc; | |
179 | + int flags; | |
180 | + int (*test)(bd_t *bd, int flags); | |
181 | +}; | |
182 | + | |
183 | + o) name | |
184 | + | |
185 | + This field will contain a short name of the test, which will be | |
186 | + used in logs and on listing POST tests (e.g. CPU test). | |
187 | + | |
188 | + o) cmd | |
189 | + | |
190 | + This field will keep a name for identifying the test on manual | |
191 | + testing (e.g. cpu). For more information, refer to section | |
192 | + "Command line interface". | |
193 | + | |
194 | + o) desc | |
195 | + | |
196 | + This field will contain a detailed description of the test, | |
197 | + which will be printed on user request. For more information, see | |
198 | + section "Command line interface". | |
199 | + | |
200 | + o) flags | |
201 | + | |
202 | + This field will contain a combination of the bit flags described | |
203 | + above, which will specify the mode the test is running in | |
204 | + (power-on, normal, power-fail or manual mode), the moment it | |
205 | + should be run at (before or after relocating to RAM), whether it | |
206 | + can cause system rebooting or not. | |
207 | + | |
208 | + o) test | |
209 | + | |
210 | + This field will contain a pointer to the routine that will | |
211 | + perform the test, which will take 2 arguments. The first | |
212 | + argument will be a pointer to the board info structure, while | |
213 | + the second will be a combination of bit flags specifying the | |
214 | + mode the test is running in (POST_POWERON, POST_NORMAL, | |
215 | + POST_POWERFAIL, POST_MANUAL) and whether the last execution of | |
216 | + the test caused system rebooting (POST_REBOOT). The routine will | |
217 | + return 0 on successful execution of the test, and 1 if the test | |
218 | + failed. | |
219 | + | |
220 | +The lists of the POST tests that should be run at power-on/normal/ | |
221 | +power-fail booting will be kept in the environment. Namely, the | |
222 | +following environment variables will be used: post_poweron, | |
223 | +powet_normal, post_shutdown. | |
224 | + | |
225 | +2.1.2. Test results | |
226 | + | |
227 | +The results of tests will be collected by the POST layer. The POST | |
228 | +log will have the following format: | |
229 | + | |
230 | +... | |
231 | +-------------------------------------------- | |
232 | +START <name> | |
233 | +<test-specific output> | |
234 | +[PASSED|FAILED] | |
235 | +-------------------------------------------- | |
236 | +... | |
237 | + | |
238 | +Basically, the results of tests will be printed to stderr. This | |
239 | +feature may be enhanced in future to spool the log to a serial line, | |
240 | +save it in non-volatile RAM (NVRAM), transfer it to a dedicated | |
241 | +storage server and etc. | |
242 | + | |
243 | +2.1.3. Integration issues | |
244 | + | |
245 | +All POST-related code will be #ifdef'ed with the CONFIG_POST macro. | |
246 | +This macro will be defined in the config_<board>.h file for those | |
247 | +boards that need POST. The CONFIG_POST macro will contain the list of | |
248 | +POST tests for the board. The macro will have the format of array | |
249 | +composed of post_test structures: | |
250 | + | |
251 | +#define CONFIG_POST \ | |
252 | + { | |
253 | + "On-board peripherals test", "board", \ | |
254 | + " This test performs full check-up of the " \ | |
255 | + "on-board hardware.", \ | |
256 | + POST_RAM | POST_POWERFAIL, \ | |
257 | + &board_post_test \ | |
258 | + } | |
259 | + | |
260 | +A new file, post.h, will be created in the include/ directory. This | |
261 | +file will contain common POST declarations and will define a set of | |
262 | +macros that will be reused for defining CONFIG_POST. As an example, | |
263 | +the following macro may be defined: | |
264 | + | |
265 | +#define POST_CACHE \ | |
266 | + { | |
267 | + "Cache test", "cache", \ | |
268 | + " This test verifies the CPU cache operation.", \ | |
269 | + POST_RAM | POST_NORMAL, \ | |
270 | + &cache_post_test \ | |
271 | + } | |
272 | + | |
273 | +A new subdirectory will be created in the U-Boot root directory. It | |
274 | +will contain the source code of the POST layer and most of POST | |
275 | +tests. Each POST test in this directory will be placed into a | |
276 | +separate file (it will be needed for building standalone tests). Some | |
277 | +POST tests (mainly those for testing peripheral devices) will be | |
278 | +located in the source files of the drivers for those devices. This | |
279 | +way will be used only if the test subtantially uses the driver. | |
280 | + | |
281 | +2.1.4. Standalone tests | |
282 | + | |
283 | +The POST framework will allow to develop and run standalone tests. A | |
284 | +user-space library will be developed to provide the POST interface | |
285 | +functions to standalone tests. | |
286 | + | |
287 | +2.1.5. Command line interface | |
288 | + | |
289 | +A new command, diag, will be added to U-Boot. This command will be | |
290 | +used for listing all available hardware tests, getting detailed | |
291 | +descriptions of them and running these tests. | |
292 | + | |
293 | +More specifically, being run without any arguments, this command will | |
294 | +print the list of all available hardware tests: | |
295 | + | |
296 | +=> diag | |
297 | +Available hardware tests: | |
298 | + cache - cache test | |
299 | + cpu - CPU test | |
300 | + enet - SCC/FCC ethernet test | |
301 | +Use 'diag [<test1> [<test2>]] ... ' to get more info. | |
302 | +Use 'diag run [<test1> [<test2>]] ... ' to run tests. | |
303 | +=> | |
304 | + | |
305 | +If the first argument to the diag command is not 'run', detailed | |
306 | +descriptions of the specified tests will be printed: | |
307 | + | |
308 | +=> diag cpu cache | |
309 | +cpu - CPU test | |
310 | + This test verifies the arithmetic logic unit of CPU. | |
311 | +cache - cache test | |
312 | + This test verifies the CPU cache operation. | |
313 | +=> | |
314 | + | |
315 | +If the first argument to diag is 'run', the specified tests will be | |
316 | +executed. If no tests are specified, all available tests will be | |
317 | +executed. | |
318 | + | |
319 | +It will be prohibited to execute tests running in ROM manually. The | |
320 | +'diag' command will not display such tests and/or run them. | |
321 | + | |
322 | +2.1.6. Power failure handling | |
323 | + | |
324 | +The Linux kernel will be modified to detect power failures and | |
325 | +automatically reboot the system in such cases. It will be assumed | |
326 | +that the power failure causes a system interrupt. | |
327 | + | |
328 | +To perform correct system shutdown, the kernel will register a | |
329 | +handler of the power-fail IRQ on booting. Being called, the handler | |
330 | +will run /sbin/reboot using the call_usermodehelper() routine. | |
331 | +/sbin/reboot will automatically bring the system down in a secure | |
332 | +way. This feature will be configured in/out from the kernel | |
333 | +configuration file. | |
334 | + | |
335 | +The POST layer of U-Boot will check whether the system runs in | |
336 | +power-fail mode. If it does, the system will be powered off after | |
337 | +executing all hardware tests. | |
338 | + | |
339 | +2.1.7. Hazardous tests | |
340 | + | |
341 | +Some tests may cause system rebooting during their execution. For | |
342 | +some tests, this will indicate a failure, while for the Watchdog | |
343 | +test, this means successful operation of the timer. | |
344 | + | |
345 | +In order to support such tests, the following scheme will be | |
346 | +implemented. All the tests that may cause system rebooting will have | |
347 | +the POST_REBOOT bit flag set in the flag field of the correspondent | |
348 | +post_test structure. Before starting tests marked with this bit flag, | |
349 | +the POST layer will store an identification number of the test in a | |
350 | +location in IMMR. On booting, the POST layer will check the value of | |
351 | +this variable and if it is set will skip over the tests preceding the | |
352 | +failed one. On second execution of the failed test, the POST_REBOOT | |
353 | +bit flag will be set in the flag argument to the test routine. This | |
354 | +will allow to detect system rebooting on the previous iteration. For | |
355 | +example, the watchdog timer test may have the following | |
356 | +declaration/body: | |
357 | + | |
358 | +... | |
359 | +#define POST_WATCHDOG \ | |
360 | + { | |
361 | + "Watchdog timer test", "watchdog", \ | |
362 | + " This test checks the watchdog timer.", \ | |
363 | + POST_RAM | POST_POWERON | POST_REBOOT, \ | |
364 | + &watchdog_post_test \ | |
365 | + } | |
366 | +... | |
367 | + | |
368 | +... | |
369 | +int watchdog_post_test(bd_t *bd, int flags) | |
370 | +{ | |
371 | + unsigned long start_time; | |
372 | + | |
373 | + if (flags & POST_REBOOT) { | |
374 | + /* Test passed */ | |
375 | + return 0; | |
376 | + } else { | |
377 | + /* disable interrupts */ | |
378 | + disable_interrupts(); | |
379 | + /* 10-second delay */ | |
380 | + ... | |
381 | + /* if we've reached this, the watchdog timer does not work */ | |
382 | + enable_interrupts(); | |
383 | + return 1; | |
384 | + } | |
385 | +} | |
386 | +... | |
387 | + | |
388 | +2.2. Hardware-specific details | |
389 | + | |
390 | +This project will also develop a set of POST tests for MPC8xx- based | |
391 | +systems. This section provides technical details of how it will be | |
392 | +done. | |
393 | + | |
394 | +2.2.1. Generic PPC tests | |
395 | + | |
396 | +The following generic POST tests will be developed: | |
397 | + | |
398 | + o) CPU test | |
399 | + | |
400 | + This test will check the arithmetic logic unit (ALU) of CPU. The | |
401 | + test will take several milliseconds and will run on normal | |
402 | + booting. | |
403 | + | |
404 | + o) Cache test | |
405 | + | |
406 | + This test will verify the CPU cache (L1 cache). The test will | |
407 | + run on normal booting. | |
408 | + | |
409 | + o) Memory test | |
410 | + | |
411 | + This test will examine RAM and check it for errors. The test | |
412 | + will always run on booting. On normal booting, only a limited | |
413 | + amount of RAM will be checked. On power-fail booting a fool | |
414 | + memory check-up will be performed. | |
415 | + | |
416 | +2.2.1.1. CPU test | |
417 | + | |
418 | +This test will verify the following ALU instructions: | |
419 | + | |
420 | + o) Condition register istructions | |
421 | + | |
422 | + This group will contain: mtcrf, mfcr, mcrxr, crand, crandc, | |
423 | + cror, crorc, crxor, crnand, crnor, creqv, mcrf. | |
424 | + | |
425 | + The mtcrf/mfcr instructions will be tested by loading different | |
426 | + values into the condition register (mtcrf), moving its value to | |
427 | + a general-purpose register (mfcr) and comparing this value with | |
428 | + the expected one. The mcrxr instruction will be tested by | |
429 | + loading a fixed value into the XER register (mtspr), moving XER | |
430 | + value to the condition register (mcrxr), moving it to a | |
431 | + general-purpose register (mfcr) and comparing the value of this | |
432 | + register with the expected one. The rest of instructions will be | |
433 | + tested by loading a fixed value into the condition register | |
434 | + (mtcrf), executing each instruction several times to modify all | |
435 | + 4-bit condition fields, moving the value of the conditional | |
436 | + register to a general-purpose register (mfcr) and comparing it | |
437 | + with the expected one. | |
438 | + | |
439 | + o) Integer compare instructions | |
440 | + | |
441 | + This group will contain: cmp, cmpi, cmpl, cmpli. | |
442 | + | |
443 | + To verify these instructions the test will run them with | |
444 | + different combinations of operands, read the condition register | |
445 | + value and compare it with the expected one. More specifically, | |
446 | + the test will contain a pre-built table containing the | |
447 | + description of each test case: the instruction, the values of | |
448 | + the operands, the condition field to save the result in and the | |
449 | + expected result. | |
450 | + | |
451 | + o) Arithmetic instructions | |
452 | + | |
453 | + This group will contain: add, addc, adde, addme, addze, subf, | |
454 | + subfc, subfe, subme, subze, mullw, mulhw, mulhwu, divw, divwu, | |
455 | + extsb, extsh. | |
456 | + | |
457 | + The test will contain a pre-built table of instructions, | |
458 | + operands, expected results and expected states of the condition | |
459 | + register. For each table entry, the test will cyclically use | |
460 | + different sets of operand registers and result registers. For | |
461 | + example, for instructions that use 3 registers on the first | |
462 | + iteration r0/r1 will be used as operands and r2 for result. On | |
463 | + the second iteration, r1/r2 will be used as operands and r3 as | |
464 | + for result and so on. This will enable to verify all | |
465 | + general-purpose registers. | |
466 | + | |
467 | + o) Logic instructions | |
468 | + | |
469 | + This group will contain: and, andc, andi, andis, or, orc, ori, | |
470 | + oris, xor, xori, xoris, nand, nor, neg, eqv, cntlzw. | |
471 | + | |
472 | + The test scheme will be identical to that from the previous | |
473 | + point. | |
474 | + | |
475 | + o) Shift instructions | |
476 | + | |
477 | + This group will contain: slw, srw, sraw, srawi, rlwinm, rlwnm, | |
478 | + rlwimi | |
479 | + | |
480 | + The test scheme will be identical to that from the previous | |
481 | + point. | |
482 | + | |
483 | + o) Branch instructions | |
484 | + | |
485 | + This group will contain: b, bl, bc. | |
486 | + | |
487 | + The first 2 instructions (b, bl) will be verified by jumping to | |
488 | + a fixed address and checking whether control was transfered to | |
489 | + that very point. For the bl instruction the value of the link | |
490 | + register will be checked as well (using mfspr). To verify the bc | |
491 | + instruction various combinations of the BI/BO fields, the CTR | |
492 | + and the condition register values will be checked. The list of | |
493 | + such combinations will be pre-built and linked in U-Boot at | |
494 | + build time. | |
495 | + | |
496 | + o) Load/store instructions | |
497 | + | |
498 | + This group will contain: lbz(x)(u), lhz(x)(u), lha(x)(u), | |
499 | + lwz(x)(u), stb(x)(u), sth(x)(u), stw(x)(u). | |
500 | + | |
501 | + All operations will be performed on a 16-byte array. The array | |
502 | + will be 4-byte aligned. The base register will point to offset | |
503 | + 8. The immediate offset (index register) will range in [-8 ... | |
504 | + +7]. The test cases will be composed so that they will not cause | |
505 | + alignment exceptions. The test will contain a pre-built table | |
506 | + describing all test cases. For store instructions, the table | |
507 | + entry will contain: the instruction opcode, the value of the | |
508 | + index register and the value of the source register. After | |
509 | + executing the instruction, the test will verify the contents of | |
510 | + the array and the value of the base register (it must change for | |
511 | + "store with update" instructions). For load instructions, the | |
512 | + table entry will contain: the instruction opcode, the array | |
513 | + contents, the value of the index register and the expected value | |
514 | + of the destination register. After executing the instruction, | |
515 | + the test will verify the value of the destination register and | |
516 | + the value of the base register (it must change for "load with | |
517 | + update" instructions). | |
518 | + | |
519 | + o) Load/store multiple/string instructions | |
520 | + | |
521 | + | |
522 | +The CPU test will run in RAM in order to allow run-time modification | |
523 | +of the code to reduce the memory footprint. | |
524 | + | |
525 | +2.2.1.2 Special-Purpose Registers Tests | |
526 | + | |
527 | +TBD. | |
528 | + | |
529 | +2.2.1.3. Cache test | |
530 | + | |
531 | +To verify the data cache operation the following test scenarios will | |
532 | +be used: | |
533 | + | |
534 | + 1) Basic test #1 | |
535 | + | |
536 | + - turn on the data cache | |
537 | + - switch the data cache to write-back or write-through mode | |
538 | + - invalidate the data cache | |
539 | + - write the negative pattern to a cached area | |
540 | + - read the area | |
541 | + | |
542 | + The negative pattern must be read at the last step | |
543 | + | |
544 | + 2) Basic test #2 | |
545 | + | |
546 | + - turn on the data cache | |
547 | + - switch the data cache to write-back or write-through mode | |
548 | + - invalidate the data cache | |
549 | + - write the zero pattern to a cached area | |
550 | + - turn off the data cache | |
551 | + - write the negative pattern to the area | |
552 | + - turn on the data cache | |
553 | + - read the area | |
554 | + | |
555 | + The negative pattern must be read at the last step | |
556 | + | |
557 | + 3) Write-through mode test | |
558 | + | |
559 | + - turn on the data cache | |
560 | + - switch the data cache to write-through mode | |
561 | + - invalidate the data cache | |
562 | + - write the zero pattern to a cached area | |
563 | + - flush the data cache | |
564 | + - write the negative pattern to the area | |
565 | + - turn off the data cache | |
566 | + - read the area | |
567 | + | |
568 | + The negative pattern must be read at the last step | |
569 | + | |
570 | + 4) Write-back mode test | |
571 | + | |
572 | + - turn on the data cache | |
573 | + - switch the data cache to write-back mode | |
574 | + - invalidate the data cache | |
575 | + - write the negative pattern to a cached area | |
576 | + - flush the data cache | |
577 | + - write the zero pattern to the area | |
578 | + - invalidate the data cache | |
579 | + - read the area | |
580 | + | |
581 | + The negative pattern must be read at the last step | |
582 | + | |
583 | +To verify the instruction cache operation the following test | |
584 | +scenarios will be used: | |
585 | + | |
586 | + 1) Basic test #1 | |
587 | + | |
588 | + - turn on the instruction cache | |
589 | + - unlock the entire instruction cache | |
590 | + - invalidate the instruction cache | |
591 | + - lock a branch instruction in the instruction cache | |
592 | + - replace the branch instruction with "nop" | |
593 | + - jump to the branch instruction | |
594 | + - check that the branch instruction was executed | |
595 | + | |
596 | + 2) Basic test #2 | |
597 | + | |
598 | + - turn on the instruction cache | |
599 | + - unlock the entire instruction cache | |
600 | + - invalidate the instruction cache | |
601 | + - jump to a branch instruction | |
602 | + - check that the branch instruction was executed | |
603 | + - replace the branch instruction with "nop" | |
604 | + - invalidate the instruction cache | |
605 | + - jump to the branch instruction | |
606 | + - check that the "nop" instruction was executed | |
607 | + | |
608 | +The CPU test will run in RAM in order to allow run-time modification | |
609 | +of the code. | |
610 | + | |
611 | +2.2.1.4. Memory test | |
612 | + | |
613 | +The memory test will verify RAM using sequential writes and reads | |
614 | +to/from RAM. Specifically, there will be several test cases that will | |
615 | +use different patterns to verify RAM. Each test case will first fill | |
616 | +a region of RAM with one pattern and then read the region back and | |
617 | +compare its contents with the pattern. The following patterns will be | |
618 | +used: | |
619 | + | |
620 | + 1) zero pattern (0x00000000) | |
621 | + 2) negative pattern (0xffffffff) | |
622 | + 3) checkerboard pattern (0x55555555, 0xaaaaaaaa) | |
623 | + 4) bit-flip pattern ((1 << (offset % 32)), ~(1 << (offset % 32))) | |
624 | + 5) address pattern (offset, ~offset) | |
625 | + | |
626 | +Patterns #1, #2 will help to find unstable bits. Patterns #3, #4 will | |
627 | +be used to detect adherent bits, i.e. bits whose state may randomly | |
628 | +change if adjacent bits are modified. The last pattern will be used | |
629 | +to detect far-located errors, i.e. situations when writing to one | |
630 | +location modifies an area located far from it. Also, usage of the | |
631 | +last pattern will help to detect memory controller misconfigurations | |
632 | +when RAM represents a cyclically repeated portion of a smaller size. | |
633 | + | |
634 | +Being run in normal mode, the test will verify only small 4Kb regions | |
635 | +of RAM around each 1Mb boundary. For example, for 64Mb RAM the | |
636 | +following areas will be verified: 0x00000000-0x00000800, | |
637 | +0x000ff800-0x00100800, 0x001ff800-0x00200800, ..., 0x03fff800- | |
638 | +0x04000000. If the test is run in power-fail mode, it will verify the | |
639 | +whole RAM. | |
640 | + | |
641 | +The memory test will run in ROM before relocating U-Boot to RAM in | |
642 | +order to allow RAM modification without saving its contents. | |
643 | + | |
644 | +2.2.2. Common tests | |
645 | + | |
646 | +This section describes tests that are not based on any hardware | |
647 | +peculiarities and use common U-Boot interfaces only. These tests do | |
648 | +not need any modifications for porting them to another board/CPU. | |
649 | + | |
650 | +2.2.2.1. I2C test | |
651 | + | |
652 | +For verifying the I2C bus, a full I2C bus scanning will be performed | |
653 | +using the i2c_probe() routine. If any I2C device is found, the test | |
654 | +will be considered as passed, otherwise failed. This particular way | |
655 | +will be used because it provides the most common method of testing. | |
656 | +For example, using the internal loopback mode of the CPM I2C | |
657 | +controller for testing would not work on boards where the software | |
658 | +I2C driver (also known as bit-banged driver) is used. | |
659 | + | |
660 | +2.2.2.2. Watchdog timer test | |
661 | + | |
662 | +To test the watchdog timer the scheme mentioned above (refer to | |
663 | +section "Hazardous tests") will be used. Namely, this test will be | |
664 | +marked with the POST_REBOOT bit flag. On the first iteration, the | |
665 | +test routine will make a 10-second delay. If the system does not | |
666 | +reboot during this delay, the watchdog timer is not operational and | |
667 | +the test fails. If the system reboots, on the second iteration the | |
668 | +POST_REBOOT bit will be set in the flag argument to the test routine. | |
669 | +The test routine will check this bit and report a success if it is | |
670 | +set. | |
671 | + | |
672 | +2.2.2.3. RTC test | |
673 | + | |
674 | +The RTC test will use the rtc_get()/rtc_set() routines. The following | |
675 | +features will be verified: | |
676 | + | |
677 | + o) Time uniformity | |
678 | + | |
679 | + This will be verified by reading RTC in polling within a short | |
680 | + period of time (5-10 seconds). | |
681 | + | |
682 | + o) Passing month boundaries | |
683 | + | |
684 | + This will be checked by setting RTC to a second before a month | |
685 | + boundary and reading it after its passing the boundary. The test | |
686 | + will be performed for both leap- and nonleap-years. | |
687 | + | |
688 | +2.2.3. MPC8xx peripherals tests | |
689 | + | |
690 | +This project will develop a set of tests verifying the peripheral | |
691 | +units of MPC8xx processors. Namely, the following controllers of the | |
692 | +MPC8xx communication processor module (CPM) will be tested: | |
693 | + | |
694 | + o) Serial Management Controllers (SMC) | |
695 | + | |
696 | + o) Serial Communication Controllers (SCC) | |
697 | + | |
698 | +2.2.3.1. Ethernet tests (SCC) | |
699 | + | |
700 | +The internal (local) loopback mode will be used to test SCC. To do | |
701 | +that the controllers will be configured accordingly and several | |
702 | +packets will be transmitted. These tests may be enhanced in future to | |
703 | +use external loopback for testing. That will need appropriate | |
704 | +reconfiguration of the physical interface chip. | |
705 | + | |
706 | +The test routines for the SCC ethernet tests will be located in | |
707 | +cpu/mpc8xx/scc.c. | |
708 | + | |
709 | +2.2.3.2. UART tests (SMC/SCC) | |
710 | + | |
711 | +To perform these tests the internal (local) loopback mode will be | |
712 | +used. The SMC/SCC controllers will be configured to connect the | |
713 | +transmitter output to the receiver input. After that, several bytes | |
714 | +will be transmitted. These tests may be enhanced to make to perform | |
715 | +"external" loopback test using a loopback cable. In this case, the | |
716 | +test will be executed manually. | |
717 | + | |
718 | +The test routine for the SMC/SCC UART tests will be located in | |
719 | +cpu/mpc8xx/serial.c. | |
720 | + | |
721 | +2.2.3.3. USB test | |
722 | + | |
723 | +TBD | |
724 | + | |
725 | +2.2.3.4. SPI test | |
726 | + | |
727 | +TBD | |
728 | + | |
729 | +2.3. Design notes | |
730 | + | |
731 | +Currently it is unknown how we will power off the board after running | |
732 | +all power-fail POST tests. This point needs further clarification. |
include/asm-arm/arch-pxa/pxa-regs.h
... | ... | @@ -10,6 +10,8 @@ |
10 | 10 | * published by the Free Software Foundation. |
11 | 11 | */ |
12 | 12 | |
13 | +#ifndef PXA_REGS_H | |
14 | +#define PXA_REGS_H 1 | |
13 | 15 | |
14 | 16 | /* FIXME hack so that SA-1111.h will work [cb] */ |
15 | 17 | |
16 | 18 | |
... | ... | @@ -425,7 +427,39 @@ |
425 | 427 | #define ISR __REG(0x40301698) /* I2C Status Register - ISR */ |
426 | 428 | #define ISAR __REG(0x403016A0) /* I2C Slave Address Register - ISAR */ |
427 | 429 | |
430 | +/* ----- Control register bits ---------------------------------------- */ | |
428 | 431 | |
432 | +#define ICR_START 0x1 /* start bit */ | |
433 | +#define ICR_STOP 0x2 /* stop bit */ | |
434 | +#define ICR_ACKNAK 0x4 /* send ACK(0) or NAK(1) */ | |
435 | +#define ICR_TB 0x8 /* transfer byte bit */ | |
436 | +#define ICR_MA 0x10 /* master abort */ | |
437 | +#define ICR_SCLE 0x20 /* master clock enable */ | |
438 | +#define ICR_IUE 0x40 /* unit enable */ | |
439 | +#define ICR_GCD 0x80 /* general call disable */ | |
440 | +#define ICR_ITEIE 0x100 /* enable tx interrupts */ | |
441 | +#define ICR_IRFIE 0x200 /* enable rx interrupts */ | |
442 | +#define ICR_BEIE 0x400 /* enable bus error ints */ | |
443 | +#define ICR_SSDIE 0x800 /* slave STOP detected int enable */ | |
444 | +#define ICR_ALDIE 0x1000 /* enable arbitration interrupt */ | |
445 | +#define ICR_SADIE 0x2000 /* slave address detected int enable */ | |
446 | +#define ICR_UR 0x4000 /* unit reset */ | |
447 | + | |
448 | +/* ----- Status register bits ----------------------------------------- */ | |
449 | + | |
450 | +#define ISR_RWM 0x1 /* read/write mode */ | |
451 | +#define ISR_ACKNAK 0x2 /* ack/nak status */ | |
452 | +#define ISR_UB 0x4 /* unit busy */ | |
453 | +#define ISR_IBB 0x8 /* bus busy */ | |
454 | +#define ISR_SSD 0x10 /* slave stop detected */ | |
455 | +#define ISR_ALD 0x20 /* arbitration loss detected */ | |
456 | +#define ISR_ITE 0x40 /* tx buffer empty */ | |
457 | +#define ISR_IRF 0x80 /* rx buffer full */ | |
458 | +#define ISR_GCAD 0x100 /* general call address detected */ | |
459 | +#define ISR_SAD 0x200 /* slave address detected */ | |
460 | +#define ISR_BED 0x400 /* bus error no ACK/NAK */ | |
461 | + | |
462 | + | |
429 | 463 | /* |
430 | 464 | * Serial Audio Controller |
431 | 465 | */ |
... | ... | @@ -1127,4 +1161,6 @@ |
1127 | 1161 | #define MCIO0_OFFSET 0x38 |
1128 | 1162 | #define MCIO1_OFFSET 0x3C |
1129 | 1163 | #define MDMRS_OFFSET 0x40 |
1164 | + | |
1165 | +#endif /* PXA_REGS_H */ |
include/asm-arm/arch-xscale/pxa-regs.h
1 | 1 | /* |
2 | 2 | * linux/include/asm-arm/arch-pxa/pxa-regs.h |
3 | - * | |
3 | + * | |
4 | 4 | * Author: Nicolas Pitre |
5 | 5 | * Created: Jun 15, 2001 |
6 | 6 | * Copyright: MontaVista Software Inc. |
7 | - * | |
7 | + * | |
8 | 8 | * This program is free software; you can redistribute it and/or modify |
9 | 9 | * it under the terms of the GNU General Public License version 2 as |
10 | 10 | * published by the Free Software Foundation. |
11 | + * | |
12 | + * - 2003/01/20: Robert Schwebel <r.schwebel@pengutronix.de | |
13 | + * Original file taken from linux-2.4.19-rmk4-pxa1. Added some definitions. | |
14 | + * Added include for hardware.h (for __REG definition) | |
11 | 15 | */ |
16 | +#ifndef _PXA_REGS_H_ | |
17 | +#define _PXA_REGS_H_ | |
12 | 18 | |
19 | +#include "bitfield.h" | |
20 | +#include "hardware.h" | |
13 | 21 | |
14 | 22 | /* FIXME hack so that SA-1111.h will work [cb] */ |
15 | 23 | |
... | ... | @@ -22,13 +30,6 @@ |
22 | 30 | typedef void (*ExcpHndlr) (void) ; |
23 | 31 | #endif |
24 | 32 | |
25 | -#ifndef __ASSEMBLY__ | |
26 | -#define io_p2v(PhAdd) (PhAdd) | |
27 | -#define __REG(x) (*((volatile u32 *)io_p2v(x))) | |
28 | -#else | |
29 | -#define __REG(x) (x) | |
30 | -#endif | |
31 | - | |
32 | 33 | /* |
33 | 34 | * PXA Chip selects |
34 | 35 | */ |
... | ... | @@ -369,7 +370,7 @@ |
369 | 370 | #define LSR_OE (1 << 1) /* Overrun Error */ |
370 | 371 | #define LSR_DR (1 << 0) /* Data Ready */ |
371 | 372 | |
372 | -#define MCR_LOOP (1 << 4) */ | |
373 | +#define MCR_LOOP (1 << 4) */ | |
373 | 374 | #define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */ |
374 | 375 | #define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */ |
375 | 376 | #define MCR_RTS (1 << 1) /* Request to Send */ |
... | ... | @@ -414,7 +415,6 @@ |
414 | 415 | IrSR_RCVEIR_UART_MODE | \ |
415 | 416 | IrSR_XMITIR_IR_MODE) |
416 | 417 | |
417 | - | |
418 | 418 | /* |
419 | 419 | * I2C registers |
420 | 420 | */ |
421 | 421 | |
... | ... | @@ -425,7 +425,39 @@ |
425 | 425 | #define ISR __REG(0x40301698) /* I2C Status Register - ISR */ |
426 | 426 | #define ISAR __REG(0x403016A0) /* I2C Slave Address Register - ISAR */ |
427 | 427 | |
428 | +/* ----- Control register bits ---------------------------------------- */ | |
428 | 429 | |
430 | +#define ICR_START 0x1 /* start bit */ | |
431 | +#define ICR_STOP 0x2 /* stop bit */ | |
432 | +#define ICR_ACKNAK 0x4 /* send ACK(0) or NAK(1) */ | |
433 | +#define ICR_TB 0x8 /* transfer byte bit */ | |
434 | +#define ICR_MA 0x10 /* master abort */ | |
435 | +#define ICR_SCLE 0x20 /* master clock enable */ | |
436 | +#define ICR_IUE 0x40 /* unit enable */ | |
437 | +#define ICR_GCD 0x80 /* general call disable */ | |
438 | +#define ICR_ITEIE 0x100 /* enable tx interrupts */ | |
439 | +#define ICR_IRFIE 0x200 /* enable rx interrupts */ | |
440 | +#define ICR_BEIE 0x400 /* enable bus error ints */ | |
441 | +#define ICR_SSDIE 0x800 /* slave STOP detected int enable */ | |
442 | +#define ICR_ALDIE 0x1000 /* enable arbitration interrupt */ | |
443 | +#define ICR_SADIE 0x2000 /* slave address detected int enable */ | |
444 | +#define ICR_UR 0x4000 /* unit reset */ | |
445 | +#define ICR_FM 0x8000 /* Fast Mode */ | |
446 | + | |
447 | +/* ----- Status register bits ----------------------------------------- */ | |
448 | + | |
449 | +#define ISR_RWM 0x1 /* read/write mode */ | |
450 | +#define ISR_ACKNAK 0x2 /* ack/nak status */ | |
451 | +#define ISR_UB 0x4 /* unit busy */ | |
452 | +#define ISR_IBB 0x8 /* bus busy */ | |
453 | +#define ISR_SSD 0x10 /* slave stop detected */ | |
454 | +#define ISR_ALD 0x20 /* arbitration loss detected */ | |
455 | +#define ISR_ITE 0x40 /* tx buffer empty */ | |
456 | +#define ISR_IRF 0x80 /* rx buffer full */ | |
457 | +#define ISR_GCAD 0x100 /* general call address detected */ | |
458 | +#define ISR_SAD 0x200 /* slave address detected */ | |
459 | +#define ISR_BED 0x400 /* bus error no ACK/NAK */ | |
460 | + | |
429 | 461 | /* |
430 | 462 | * Serial Audio Controller |
431 | 463 | */ |
432 | 464 | |
433 | 465 | |
434 | 466 | |
435 | 467 | |
436 | 468 | |
437 | 469 | |
438 | 470 | |
439 | 471 | |
440 | 472 | |
... | ... | @@ -524,24 +556,92 @@ |
524 | 556 | /* |
525 | 557 | * USB Device Controller |
526 | 558 | */ |
559 | +#define UDC_RES1 __REG(0x40600004) /* UDC Undocumented - Reserved1 */ | |
560 | +#define UDC_RES2 __REG(0x40600008) /* UDC Undocumented - Reserved2 */ | |
561 | +#define UDC_RES3 __REG(0x4060000C) /* UDC Undocumented - Reserved3 */ | |
527 | 562 | |
528 | 563 | #define UDCCR __REG(0x40600000) /* UDC Control Register */ |
564 | +#define UDCCR_UDE (1 << 0) /* UDC enable */ | |
565 | +#define UDCCR_UDA (1 << 1) /* UDC active */ | |
566 | +#define UDCCR_RSM (1 << 2) /* Device resume */ | |
567 | +#define UDCCR_RESIR (1 << 3) /* Resume interrupt request */ | |
568 | +#define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */ | |
569 | +#define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */ | |
570 | +#define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */ | |
571 | +#define UDCCR_REM (1 << 7) /* Reset interrupt mask */ | |
572 | + | |
529 | 573 | #define UDCCS0 __REG(0x40600010) /* UDC Endpoint 0 Control/Status Register */ |
574 | +#define UDCCS0_OPR (1 << 0) /* OUT packet ready */ | |
575 | +#define UDCCS0_IPR (1 << 1) /* IN packet ready */ | |
576 | +#define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */ | |
577 | +#define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */ | |
578 | +#define UDCCS0_SST (1 << 4) /* Sent stall */ | |
579 | +#define UDCCS0_FST (1 << 5) /* Force stall */ | |
580 | +#define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */ | |
581 | +#define UDCCS0_SA (1 << 7) /* Setup active */ | |
582 | + | |
583 | +/* Bulk IN - Endpoint 1,6,11 */ | |
530 | 584 | #define UDCCS1 __REG(0x40600014) /* UDC Endpoint 1 (IN) Control/Status Register */ |
531 | -#define UDCCS2 __REG(0x40600018) /* UDC Endpoint 2 (OUT) Control/Status Register */ | |
532 | -#define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */ | |
533 | -#define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */ | |
534 | -#define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */ | |
535 | 585 | #define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */ |
536 | -#define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */ | |
537 | -#define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */ | |
538 | -#define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */ | |
539 | -#define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */ | |
540 | 586 | #define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */ |
587 | + | |
588 | +#define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */ | |
589 | +#define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */ | |
590 | +#define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */ | |
591 | +#define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */ | |
592 | +#define UDCCS_BI_SST (1 << 4) /* Sent stall */ | |
593 | +#define UDCCS_BI_FST (1 << 5) /* Force stall */ | |
594 | +#define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */ | |
595 | + | |
596 | +/* Bulk OUT - Endpoint 2,7,12 */ | |
597 | +#define UDCCS2 __REG(0x40600018) /* UDC Endpoint 2 (OUT) Control/Status Register */ | |
598 | +#define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */ | |
541 | 599 | #define UDCCS12 __REG(0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */ |
600 | + | |
601 | +#define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */ | |
602 | +#define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */ | |
603 | +#define UDCCS_BO_DME (1 << 3) /* DMA enable */ | |
604 | +#define UDCCS_BO_SST (1 << 4) /* Sent stall */ | |
605 | +#define UDCCS_BO_FST (1 << 5) /* Force stall */ | |
606 | +#define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */ | |
607 | +#define UDCCS_BO_RSP (1 << 7) /* Receive short packet */ | |
608 | + | |
609 | +/* Isochronous IN - Endpoint 3,8,13 */ | |
610 | +#define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */ | |
611 | +#define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */ | |
542 | 612 | #define UDCCS13 __REG(0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */ |
613 | + | |
614 | +#define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */ | |
615 | +#define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */ | |
616 | +#define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */ | |
617 | +#define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */ | |
618 | +#define UDCCS_II_TSP (1 << 7) /* Transmit short packet */ | |
619 | + | |
620 | +/* Isochronous OUT - Endpoint 4,9,14 */ | |
621 | +#define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */ | |
622 | +#define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */ | |
543 | 623 | #define UDCCS14 __REG(0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */ |
624 | + | |
625 | +#define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */ | |
626 | +#define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */ | |
627 | +#define UDCCS_IO_ROF (1 << 3) /* Receive overflow */ | |
628 | +#define UDCCS_IO_DME (1 << 3) /* DMA enable */ | |
629 | +#define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */ | |
630 | +#define UDCCS_IO_RSP (1 << 7) /* Receive short packet */ | |
631 | + | |
632 | +/* Interrupt IN - Endpoint 5,10,15 */ | |
633 | +#define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */ | |
634 | +#define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */ | |
544 | 635 | #define UDCCS15 __REG(0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */ |
636 | + | |
637 | +#define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */ | |
638 | +#define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */ | |
639 | +#define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */ | |
640 | +#define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */ | |
641 | +#define UDCCS_INT_SST (1 << 4) /* Sent stall */ | |
642 | +#define UDCCS_INT_FST (1 << 5) /* Force stall */ | |
643 | +#define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */ | |
644 | + | |
545 | 645 | #define UFNRH __REG(0x40600060) /* UDC Frame Number Register High */ |
546 | 646 | #define UFNRL __REG(0x40600064) /* UDC Frame Number Register Low */ |
547 | 647 | #define UBCR2 __REG(0x40600068) /* UDC Byte Count Reg 2 */ |
548 | 648 | |
549 | 649 | |
550 | 650 | |
551 | 651 | |
552 | 652 | |
... | ... | @@ -566,12 +666,52 @@ |
566 | 666 | #define UDDR13 __REG(0x40600C00) /* UDC Endpoint 13 Data Register */ |
567 | 667 | #define UDDR14 __REG(0x40600E00) /* UDC Endpoint 14 Data Register */ |
568 | 668 | #define UDDR15 __REG(0x406000E0) /* UDC Endpoint 15 Data Register */ |
669 | + | |
569 | 670 | #define UICR0 __REG(0x40600050) /* UDC Interrupt Control Register 0 */ |
671 | + | |
672 | +#define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */ | |
673 | +#define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */ | |
674 | +#define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */ | |
675 | +#define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */ | |
676 | +#define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */ | |
677 | +#define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */ | |
678 | +#define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */ | |
679 | +#define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */ | |
680 | + | |
570 | 681 | #define UICR1 __REG(0x40600054) /* UDC Interrupt Control Register 1 */ |
682 | + | |
683 | +#define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */ | |
684 | +#define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */ | |
685 | +#define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */ | |
686 | +#define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */ | |
687 | +#define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */ | |
688 | +#define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */ | |
689 | +#define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */ | |
690 | +#define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */ | |
691 | + | |
571 | 692 | #define USIR0 __REG(0x40600058) /* UDC Status Interrupt Register 0 */ |
693 | + | |
694 | +#define USIR0_IR0 (1 << 0) /* Interrup request ep 0 */ | |
695 | +#define USIR0_IR1 (1 << 1) /* Interrup request ep 1 */ | |
696 | +#define USIR0_IR2 (1 << 2) /* Interrup request ep 2 */ | |
697 | +#define USIR0_IR3 (1 << 3) /* Interrup request ep 3 */ | |
698 | +#define USIR0_IR4 (1 << 4) /* Interrup request ep 4 */ | |
699 | +#define USIR0_IR5 (1 << 5) /* Interrup request ep 5 */ | |
700 | +#define USIR0_IR6 (1 << 6) /* Interrup request ep 6 */ | |
701 | +#define USIR0_IR7 (1 << 7) /* Interrup request ep 7 */ | |
702 | + | |
572 | 703 | #define USIR1 __REG(0x4060005C) /* UDC Status Interrupt Register 1 */ |
573 | 704 | |
705 | +#define USIR1_IR8 (1 << 0) /* Interrup request ep 8 */ | |
706 | +#define USIR1_IR9 (1 << 1) /* Interrup request ep 9 */ | |
707 | +#define USIR1_IR10 (1 << 2) /* Interrup request ep 10 */ | |
708 | +#define USIR1_IR11 (1 << 3) /* Interrup request ep 11 */ | |
709 | +#define USIR1_IR12 (1 << 4) /* Interrup request ep 12 */ | |
710 | +#define USIR1_IR13 (1 << 5) /* Interrup request ep 13 */ | |
711 | +#define USIR1_IR14 (1 << 6) /* Interrup request ep 14 */ | |
712 | +#define USIR1_IR15 (1 << 7) /* Interrup request ep 15 */ | |
574 | 713 | |
714 | + | |
575 | 715 | /* |
576 | 716 | * Fast Infrared Communication Port |
577 | 717 | */ |
578 | 718 | |
... | ... | @@ -917,7 +1057,23 @@ |
917 | 1057 | #define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */ |
918 | 1058 | #define RCSR __REG(0x40F00030) /* Reset Controller Status Register */ |
919 | 1059 | |
1060 | +#define PSSR_RDH (1 << 5) /* Read Disable Hold */ | |
1061 | +#define PSSR_PH (1 << 4) /* Peripheral Control Hold */ | |
1062 | +#define PSSR_VFS (1 << 2) /* VDD Fault Status */ | |
1063 | +#define PSSR_BFS (1 << 1) /* Battery Fault Status */ | |
1064 | +#define PSSR_SSS (1 << 0) /* Software Sleep Status */ | |
920 | 1065 | |
1066 | +#define PCFR_DS (1 << 3) /* Deep Sleep Mode */ | |
1067 | +#define PCFR_FS (1 << 2) /* Float Static Chip Selects */ | |
1068 | +#define PCFR_FP (1 << 1) /* Float PCMCIA controls */ | |
1069 | +#define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */ | |
1070 | + | |
1071 | +#define RCSR_GPR (1 << 3) /* GPIO Reset */ | |
1072 | +#define RCSR_SMR (1 << 2) /* Sleep Mode */ | |
1073 | +#define RCSR_WDR (1 << 1) /* Watchdog Reset */ | |
1074 | +#define RCSR_HWR (1 << 0) /* Hardware Reset */ | |
1075 | + | |
1076 | + | |
921 | 1077 | /* |
922 | 1078 | * SSP Serial Port Registers |
923 | 1079 | */ |
924 | 1080 | |
925 | 1081 | |
926 | 1082 | |
927 | 1083 | |
... | ... | @@ -1040,19 +1196,91 @@ |
1040 | 1196 | #define LCCR0_BM (1 << 20) /* Branch mask */ |
1041 | 1197 | #define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */ |
1042 | 1198 | |
1199 | +#define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */ | |
1200 | +#define LCCR1_DisWdth(Pixel) /* Display Width [1..800 pix.] */ \ | |
1201 | + (((Pixel) - 1) << FShft (LCCR1_PPL)) | |
1202 | + | |
1203 | +#define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */ | |
1204 | +#define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \ | |
1205 | + /* pulse Width [1..64 Tpix] */ \ | |
1206 | + (((Tpix) - 1) << FShft (LCCR1_HSW)) | |
1207 | + | |
1208 | +#define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */ | |
1209 | + /* count - 1 [Tpix] */ | |
1210 | +#define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \ | |
1211 | + /* [1..256 Tpix] */ \ | |
1212 | + (((Tpix) - 1) << FShft (LCCR1_ELW)) | |
1213 | + | |
1214 | +#define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */ | |
1215 | + /* Wait count - 1 [Tpix] */ | |
1216 | +#define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \ | |
1217 | + /* [1..256 Tpix] */ \ | |
1218 | + (((Tpix) - 1) << FShft (LCCR1_BLW)) | |
1219 | + | |
1220 | + | |
1221 | +#define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */ | |
1222 | +#define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \ | |
1223 | + (((Line) - 1) << FShft (LCCR2_LPP)) | |
1224 | + | |
1225 | +#define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */ | |
1226 | + /* Width - 1 [Tln] (L_FCLK) */ | |
1227 | +#define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \ | |
1228 | + /* Width [1..64 Tln] */ \ | |
1229 | + (((Tln) - 1) << FShft (LCCR2_VSW)) | |
1230 | + | |
1231 | +#define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */ | |
1232 | + /* count [Tln] */ | |
1233 | +#define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \ | |
1234 | + /* [0..255 Tln] */ \ | |
1235 | + ((Tln) << FShft (LCCR2_EFW)) | |
1236 | + | |
1237 | +#define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */ | |
1238 | + /* Wait count [Tln] */ | |
1239 | +#define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \ | |
1240 | + /* [0..255 Tln] */ \ | |
1241 | + ((Tln) << FShft (LCCR2_BFW)) | |
1242 | + | |
1243 | +#if 0 | |
1043 | 1244 | #define LCCR3_PCD (0xff) /* Pixel clock divisor */ |
1044 | 1245 | #define LCCR3_ACB (0xff << 8) /* AC Bias pin frequency */ |
1045 | 1246 | #define LCCR3_ACB_S 8 |
1247 | +#endif | |
1248 | + | |
1046 | 1249 | #define LCCR3_API (0xf << 16) /* AC Bias pin trasitions per interrupt */ |
1047 | 1250 | #define LCCR3_API_S 16 |
1048 | 1251 | #define LCCR3_VSP (1 << 20) /* vertical sync polarity */ |
1049 | 1252 | #define LCCR3_HSP (1 << 21) /* horizontal sync polarity */ |
1050 | 1253 | #define LCCR3_PCP (1 << 22) /* pixel clock polarity */ |
1051 | 1254 | #define LCCR3_OEP (1 << 23) /* output enable polarity */ |
1255 | +#if 0 | |
1052 | 1256 | #define LCCR3_BPP (7 << 24) /* bits per pixel */ |
1053 | 1257 | #define LCCR3_BPP_S 24 |
1258 | +#endif | |
1054 | 1259 | #define LCCR3_DPC (1 << 27) /* double pixel clock mode */ |
1055 | 1260 | |
1261 | + | |
1262 | +#define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */ | |
1263 | +#define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor */ \ | |
1264 | + (((Div) << FShft (LCCR3_PCD))) | |
1265 | + | |
1266 | + | |
1267 | +#define LCCR3_BPP Fld (3, 24) /* Bit Per Pixel */ | |
1268 | +#define LCCR3_Bpp(Bpp) /* Bit Per Pixel */ \ | |
1269 | + (((Bpp) << FShft (LCCR3_BPP))) | |
1270 | + | |
1271 | +#define LCCR3_ACB Fld (8, 8) /* AC Bias */ | |
1272 | +#define LCCR3_Acb(Acb) /* BAC Bias */ \ | |
1273 | + (((Acb) << FShft (LCCR3_ACB))) | |
1274 | + | |
1275 | +#define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */ | |
1276 | + /* pulse active High */ | |
1277 | +#define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */ | |
1278 | + | |
1279 | +#define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */ | |
1280 | + /* active High */ | |
1281 | +#define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */ | |
1282 | + /* active Low */ | |
1283 | + | |
1056 | 1284 | #define LCSR_LDD (1 << 0) /* LCD Disable Done */ |
1057 | 1285 | #define LCSR_SOF (1 << 1) /* Start of frame */ |
1058 | 1286 | #define LCSR_BER (1 << 2) /* Bus error */ |
1059 | 1287 | |
1060 | 1288 | |
... | ... | @@ -1067,12 +1295,50 @@ |
1067 | 1295 | |
1068 | 1296 | #define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */ |
1069 | 1297 | |
1298 | +#define LCSR_LDD (1 << 0) /* LCD Disable Done */ | |
1299 | +#define LCSR_SOF (1 << 1) /* Start of frame */ | |
1300 | +#define LCSR_BER (1 << 2) /* Bus error */ | |
1301 | +#define LCSR_ABC (1 << 3) /* AC Bias count */ | |
1302 | +#define LCSR_IUL (1 << 4) /* input FIFO underrun Lower panel */ | |
1303 | +#define LCSR_IUU (1 << 5) /* input FIFO underrun Upper panel */ | |
1304 | +#define LCSR_OU (1 << 6) /* output FIFO underrun */ | |
1305 | +#define LCSR_QD (1 << 7) /* quick disable */ | |
1306 | +#define LCSR_EOF (1 << 8) /* end of frame */ | |
1307 | +#define LCSR_BS (1 << 9) /* branch status */ | |
1308 | +#define LCSR_SINT (1 << 10) /* subsequent interrupt */ | |
1309 | + | |
1310 | +#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */ | |
1311 | + | |
1070 | 1312 | /* |
1071 | 1313 | * Memory controller |
1072 | 1314 | */ |
1073 | 1315 | |
1074 | -#define MEMC_BASE __REG(0x48000000) /* Base of Memoriy Controller */ | |
1316 | +#define MEMC_BASE __REG(0x48000000) /* Base of Memory Controller */ | |
1317 | +#define MDCNFG_OFFSET 0x0 | |
1318 | +#define MDREFR_OFFSET 0x4 | |
1319 | +#define MSC0_OFFSET 0x8 | |
1320 | +#define MSC1_OFFSET 0xC | |
1321 | +#define MSC2_OFFSET 0x10 | |
1322 | +#define MECR_OFFSET 0x14 | |
1323 | +#define SXLCR_OFFSET 0x18 | |
1324 | +#define SXCNFG_OFFSET 0x1C | |
1325 | +#define FLYCNFG_OFFSET 0x20 | |
1326 | +#define SXMRS_OFFSET 0x24 | |
1327 | +#define MCMEM0_OFFSET 0x28 | |
1328 | +#define MCMEM1_OFFSET 0x2C | |
1329 | +#define MCATT0_OFFSET 0x30 | |
1330 | +#define MCATT1_OFFSET 0x34 | |
1331 | +#define MCIO0_OFFSET 0x38 | |
1332 | +#define MCIO1_OFFSET 0x3C | |
1333 | +#define MDMRS_OFFSET 0x40 | |
1334 | + | |
1075 | 1335 | #define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */ |
1336 | +#define MDCNFG_DE0 0x00000001 | |
1337 | +#define MDCNFG_DE1 0x00000002 | |
1338 | +#define MDCNFG_DE2 0x00010000 | |
1339 | +#define MDCNFG_DE3 0x00020000 | |
1340 | +#define MDCNFG_DWID0 0x00000004 | |
1341 | + | |
1076 | 1342 | #define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */ |
1077 | 1343 | #define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */ |
1078 | 1344 | #define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */ |
1079 | 1345 | |
1080 | 1346 | |
... | ... | @@ -1090,41 +1356,20 @@ |
1090 | 1356 | #define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */ |
1091 | 1357 | #define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */ |
1092 | 1358 | |
1093 | -#define MDCNFG_DE0 0x00000001 | |
1094 | -#define MDCNFG_DE1 0x00000002 | |
1095 | -#define MDCNFG_DE2 0x00010000 | |
1096 | -#define MDCNFG_DE3 0x00020000 | |
1097 | -#define MDCNFG_DWID0 0x00000004 | |
1359 | +#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */ | |
1360 | +#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */ | |
1361 | +#define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */ | |
1362 | +#define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */ | |
1363 | +#define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */ | |
1364 | +#define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */ | |
1365 | +#define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */ | |
1366 | +#define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */ | |
1367 | +#define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */ | |
1368 | +#define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */ | |
1369 | +#define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */ | |
1370 | +#define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */ | |
1371 | +#define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */ | |
1098 | 1372 | |
1099 | -#define MDREFR_E0PIN 0x00001000 | |
1100 | -#define MDREFR_K0RUN 0x00002000 | |
1101 | -#define MDREFR_K0DB2 0x00004000 | |
1102 | -#define MDREFR_E1PIN 0x00008000 | |
1103 | -#define MDREFR_K1RUN 0x00010000 | |
1104 | -#define MDREFR_K1DB2 0x00020000 | |
1105 | -#define MDREFR_K2RUN 0x00040000 | |
1106 | -#define MDREFR_K2DB2 0x00080000 | |
1107 | -#define MDREFR_APD 0x00100000 | |
1108 | -#define MDREFR_SLFRSH 0x00400000 | |
1109 | -#define MDREFR_K0FREE 0x00800000 | |
1110 | -#define MDREFR_K1FREE 0x01000000 | |
1111 | -#define MDREFR_K2FREE 0x02000000 | |
1112 | 1373 | |
1113 | -#define MDCNFG_OFFSET 0x0 | |
1114 | -#define MDREFR_OFFSET 0x4 | |
1115 | -#define MSC0_OFFSET 0x8 | |
1116 | -#define MSC1_OFFSET 0xC | |
1117 | -#define MSC2_OFFSET 0x10 | |
1118 | -#define MECR_OFFSET 0x14 | |
1119 | -#define SXLCR_OFFSET 0x18 | |
1120 | -#define SXCNFG_OFFSET 0x1C | |
1121 | -#define FLYCNFG_OFFSET 0x20 | |
1122 | -#define SXMRS_OFFSET 0x24 | |
1123 | -#define MCMEM0_OFFSET 0x28 | |
1124 | -#define MCMEM1_OFFSET 0x2C | |
1125 | -#define MCATT0_OFFSET 0x30 | |
1126 | -#define MCATT1_OFFSET 0x34 | |
1127 | -#define MCIO0_OFFSET 0x38 | |
1128 | -#define MCIO1_OFFSET 0x3C | |
1129 | -#define MDMRS_OFFSET 0x40 | |
1374 | +#endif |
include/asm-arm/proc-armv/ptrace.h
include/configs/innokom.h
1 | +/* | |
2 | + * (C) Copyright 2000, 2001, 2002 | |
3 | + * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de. | |
4 | + * | |
5 | + * Configuration for the Auerswald Innokom CPU board. | |
6 | + * | |
7 | + * See file CREDITS for list of people who contributed to this | |
8 | + * project. | |
9 | + * | |
10 | + * This program is free software; you can redistribute it and/or | |
11 | + * modify it under the terms of the GNU General Public License as | |
12 | + * published by the Free Software Foundation; either version 2 of | |
13 | + * the License, or (at your option) any later version. | |
14 | + * | |
15 | + * This program is distributed in the hope that it will be useful, | |
16 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | + * GNU General Public License for more details. | |
19 | + * | |
20 | + * You should have received a copy of the GNU General Public License | |
21 | + * along with this program; if not, write to the Free Software | |
22 | + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | + * MA 02111-1307 USA | |
24 | + */ | |
25 | + | |
26 | +/* | |
27 | + * include/configs/innokom.h - configuration options, board specific | |
28 | + */ | |
29 | + | |
30 | +#ifndef __CONFIG_H | |
31 | +#define __CONFIG_H | |
32 | + | |
33 | +#define DEBUG 1 | |
34 | + | |
35 | +/* | |
36 | + * If we are developing, we might want to start U-Boot from ram | |
37 | + * so we MUST NOT initialize critical regs like mem-timing ... | |
38 | + */ | |
39 | +#define CONFIG_INIT_CRITICAL /* undef for developing */ | |
40 | + | |
41 | +/* | |
42 | + * High Level Configuration Options | |
43 | + * (easy to change) | |
44 | + */ | |
45 | +#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ | |
46 | +#define CONFIG_INNOKOM 1 /* on an Auerswald Innokom board */ | |
47 | + | |
48 | +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ | |
49 | + /* for timer/console/ethernet */ | |
50 | +/* | |
51 | + * Hardware drivers | |
52 | + */ | |
53 | + | |
54 | +/* | |
55 | + * select serial console configuration | |
56 | + */ | |
57 | +#define CONFIG_FFUART 1 /* we use FFUART on CSB226 */ | |
58 | + | |
59 | +/* allow to overwrite serial and ethaddr */ | |
60 | +#define CONFIG_ENV_OVERWRITE | |
61 | + | |
62 | +#define CONFIG_BAUDRATE 19200 | |
63 | + | |
64 | +#define CONFIG_COMMANDS ((CONFIG_CMD_DFL | CFG_CMD_I2C | CFG_CMD_EEPROM) & ~CFG_CMD_NET) | |
65 | + | |
66 | +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ | |
67 | +#include <cmd_confdefs.h> | |
68 | + | |
69 | +#define CONFIG_BOOTDELAY 3 | |
70 | +/* #define CONFIG_BOOTARGS "root=/dev/nfs ip=bootp console=ttyS0,19200" */ | |
71 | +#define CONFIG_BOOTARGS "console=ttyS0,19200" | |
72 | +#define CONFIG_ETHADDR FF:FF:FF:FF:FF:FF | |
73 | +#define CONFIG_NETMASK 255.255.255.0 | |
74 | +#define CONFIG_IPADDR 192.168.1.56 | |
75 | +#define CONFIG_SERVERIP 192.168.1.2 | |
76 | +#define CONFIG_BOOTCOMMAND "bootm 0x40000" | |
77 | +#define CONFIG_SHOW_BOOT_PROGRESS | |
78 | + | |
79 | +#define CONFIG_CMDLINE_TAG 1 | |
80 | + | |
81 | +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
82 | +#define CONFIG_KGDB_BAUDRATE 19200 /* speed to run kgdb serial port */ | |
83 | +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
84 | +#endif | |
85 | + | |
86 | +/* | |
87 | + * Miscellaneous configurable options | |
88 | + */ | |
89 | + | |
90 | +/* | |
91 | + * Size of malloc() pool; this lives below the uppermost 128 KiB which are | |
92 | + * used for the RAM copy of the uboot code | |
93 | + */ | |
94 | +/* #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) */ | |
95 | +#define CFG_MALLOC_LEN (128*1024) | |
96 | + | |
97 | +#define CFG_LONGHELP /* undef to save memory */ | |
98 | +#define CFG_PROMPT "uboot> " /* Monitor Command Prompt */ | |
99 | +#define CFG_CBSIZE 128 /* Console I/O Buffer Size */ | |
100 | +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
101 | +#define CFG_MAXARGS 16 /* max number of command args */ | |
102 | +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
103 | + | |
104 | +#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ | |
105 | +#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ | |
106 | + | |
107 | +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ | |
108 | + | |
109 | +#define CFG_LOAD_ADDR 0xa7fe0000 /* default load address */ | |
110 | + /* RS: where is this documented? */ | |
111 | + /* RS: is this where U-Boot is */ | |
112 | + /* RS: relocated to in RAM? */ | |
113 | + | |
114 | +#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ | |
115 | + /* RS: the oscillator is actually 3680130?? */ | |
116 | + | |
117 | +#define CFG_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */ | |
118 | + /* 0101000001 */ | |
119 | + /* ^^^^^ Memory Speed 99.53 MHz */ | |
120 | + /* ^^ Run Mode Speed = 2x Mem Speed */ | |
121 | + /* ^^ Turbo Mode Sp. = 1x Run M. Sp. */ | |
122 | + | |
123 | +#define CFG_MONITOR_LEN 0x20000 /* 128 KiB */ | |
124 | + | |
125 | + /* valid baudrates */ | |
126 | +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
127 | + | |
128 | +/* | |
129 | + * I2C bus | |
130 | + */ | |
131 | +#define CONFIG_HARD_I2C 1 | |
132 | +#define CFG_I2C_SPEED 50000 | |
133 | +#define CFG_I2C_SLAVE 0xfe | |
134 | + | |
135 | +#define CFG_ENV_IS_IN_EEPROM 1 | |
136 | + | |
137 | +#define CFG_ENV_OFFSET 0x00 /* environment starts here */ | |
138 | +#define CFG_ENV_SIZE 1024 /* 1 KiB */ | |
139 | +#define CFG_I2C_EEPROM_ADDR 0x50 /* A0 = 0 (hardwired) */ | |
140 | +#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */ | |
141 | +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* between stop and start */ | |
142 | +#define CFG_I2C_EEPROM_ADDR_LEN 2 /* length of address */ | |
143 | +#define CFG_EEPROM_SIZE 4096 /* size in bytes */ | |
144 | + | |
145 | +/* | |
146 | + * Stack sizes | |
147 | + * | |
148 | + * The stack sizes are set up in start.S using the settings below | |
149 | + */ | |
150 | +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ | |
151 | +#ifdef CONFIG_USE_IRQ | |
152 | +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ | |
153 | +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ | |
154 | +#endif | |
155 | + | |
156 | +/* | |
157 | + * Physical Memory Map | |
158 | + */ | |
159 | +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ | |
160 | +#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ | |
161 | +#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ | |
162 | + | |
163 | +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ | |
164 | +#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */ | |
165 | + | |
166 | +#define CFG_DRAM_BASE 0xa0000000 /* RAM starts here */ | |
167 | +#define CFG_DRAM_SIZE 0x04000000 | |
168 | + | |
169 | +#define CFG_FLASH_BASE PHYS_FLASH_1 | |
170 | + | |
171 | +/* | |
172 | + * GPIO settings; | |
173 | + */ | |
174 | + | |
175 | +/* GP15 == nCS1 is 1 | |
176 | + * GP24 == SFRM is 1 | |
177 | + * GP25 == TXD is 1 | |
178 | + * GP33 == nCS5 is 1 | |
179 | + * GP39 == FFTXD is 1 | |
180 | + * GP41 == RTS is 1 | |
181 | + * GP47 == TXD is 1 | |
182 | + * GP49 == nPWE is 1 | |
183 | + * GP62 == LED_B is 1 | |
184 | + * GP63 == TDM_OE is 1 | |
185 | + * GP78 == nCS2 is 1 | |
186 | + * GP79 == nCS3 is 1 | |
187 | + * GP80 == nCS4 is 1 | |
188 | + */ | |
189 | +#define CFG_GPSR0_VAL 0x03008000 | |
190 | +#define CFG_GPSR1_VAL 0xC0028282 | |
191 | +#define CFG_GPSR2_VAL 0x0001C000 | |
192 | + | |
193 | +/* GP02 == DON_RST is 0 | |
194 | + * GP23 == SCLK is 0 | |
195 | + * GP45 == USB_ACT is 0 | |
196 | + * GP60 == PLLEN is 0 | |
197 | + * GP61 == LED_A is 0 | |
198 | + * GP73 == SWUPD_LED is 0 | |
199 | + */ | |
200 | +#define CFG_GPCR0_VAL 0x00800004 | |
201 | +#define CFG_GPCR1_VAL 0x30002000 | |
202 | +#define CFG_GPCR2_VAL 0x00000100 | |
203 | + | |
204 | +/* GP00 == DON_READY is input | |
205 | + * GP01 == DON_OK is input | |
206 | + * GP02 == DON_RST is output | |
207 | + * GP03 == RESET_IND is input | |
208 | + * GP07 == RES11 is input | |
209 | + * GP09 == RES12 is input | |
210 | + * GP11 == SWUPDATE is input | |
211 | + * GP14 == nPOWEROK is input | |
212 | + * GP15 == nCS1 is output | |
213 | + * GP17 == RES22 is input | |
214 | + * GP18 == RDY is input | |
215 | + * GP23 == SCLK is output | |
216 | + * GP24 == SFRM is output | |
217 | + * GP25 == TXD is output | |
218 | + * GP26 == RXD is input | |
219 | + * GP32 == RES21 is input | |
220 | + * GP33 == nCS5 is output | |
221 | + * GP34 == FFRXD is input | |
222 | + * GP35 == CTS is input | |
223 | + * GP39 == FFTXD is output | |
224 | + * GP41 == RTS is output | |
225 | + * GP42 == USB_OK is input | |
226 | + * GP45 == USB_ACT is output | |
227 | + * GP46 == RXD is input | |
228 | + * GP47 == TXD is output | |
229 | + * GP49 == nPWE is output | |
230 | + * GP58 == nCPUBUSINT is input | |
231 | + * GP59 == LANINT is input | |
232 | + * GP60 == PLLEN is output | |
233 | + * GP61 == LED_A is output | |
234 | + * GP62 == LED_B is output | |
235 | + * GP63 == TDM_OE is output | |
236 | + * GP64 == nDSPINT is input | |
237 | + * GP65 == STRAP0 is input | |
238 | + * GP67 == STRAP1 is input | |
239 | + * GP69 == STRAP2 is input | |
240 | + * GP70 == STRAP3 is input | |
241 | + * GP71 == STRAP4 is input | |
242 | + * GP73 == SWUPD_LED is output | |
243 | + * GP78 == nCS2 is output | |
244 | + * GP79 == nCS3 is output | |
245 | + * GP80 == nCS4 is output | |
246 | + */ | |
247 | +#define CFG_GPDR0_VAL 0x03808004 | |
248 | +#define CFG_GPDR1_VAL 0xF002A282 | |
249 | +#define CFG_GPDR2_VAL 0x0001C200 | |
250 | + | |
251 | +/* GP15 == nCS1 is AF10 | |
252 | + * GP18 == RDY is AF01 | |
253 | + * GP23 == SCLK is AF10 | |
254 | + * GP24 == SFRM is AF10 | |
255 | + * GP25 == TXD is AF10 | |
256 | + * GP26 == RXD is AF01 | |
257 | + * GP33 == nCS5 is AF10 | |
258 | + * GP34 == FFRXD is AF01 | |
259 | + * GP35 == CTS is AF01 | |
260 | + * GP39 == FFTXD is AF10 | |
261 | + * GP41 == RTS is AF10 | |
262 | + * GP46 == RXD is AF10 | |
263 | + * GP47 == TXD is AF01 | |
264 | + * GP49 == nPWE is AF10 | |
265 | + * GP78 == nCS2 is AF10 | |
266 | + * GP79 == nCS3 is AF10 | |
267 | + * GP80 == nCS4 is AF10 | |
268 | + */ | |
269 | +#define CFG_GAFR0_L_VAL 0x80000000 | |
270 | +#define CFG_GAFR0_U_VAL 0x001A8010 | |
271 | +#define CFG_GAFR1_L_VAL 0x60088058 | |
272 | +#define CFG_GAFR1_U_VAL 0x00000008 | |
273 | +#define CFG_GAFR2_L_VAL 0xA0000000 | |
274 | +#define CFG_GAFR2_U_VAL 0x00000002 | |
275 | + | |
276 | +/* FIXME: set GPIO_RER/FER */ | |
277 | + | |
278 | +/* RDH = 1 | |
279 | + * PH = 1 | |
280 | + * VFS = 1 | |
281 | + * BFS = 1 | |
282 | + * SSS = 1 | |
283 | + */ | |
284 | +#define CFG_PSSR_VAL 0x37 | |
285 | + | |
286 | +/* | |
287 | + * Memory settings | |
288 | + */ | |
289 | + | |
290 | +/* This is the configuration for nCS0/1 -> flash banks | |
291 | + * configuration for nCS1: | |
292 | + * [31] 0 - Slower Device | |
293 | + * [30:28] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns | |
294 | + * [27:24] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns | |
295 | + * [23:20] 1011 - " for first access: (11+2)*MemClk = 130 ns | |
296 | + * [19] 1 - 16 Bit bus width | |
297 | + * [18:16] 000 - nonburst RAM or FLASH | |
298 | + * configuration for nCS0: | |
299 | + * [15] 0 - Slower Device | |
300 | + * [14:12] 010 - CS deselect to CS time: 2*(2*MemClk) = 40 ns | |
301 | + * [11:08] 0101 - Address to data valid in bursts: (5+1)*MemClk = 60 ns | |
302 | + * [07:04] 1011 - " for first access: (11+2)*MemClk = 130 ns | |
303 | + * [03] 1 - 16 Bit bus width | |
304 | + * [02:00] 000 - nonburst RAM or FLASH | |
305 | + */ | |
306 | +#define CFG_MSC0_VAL 0x25b825b8 /* flash banks */ | |
307 | + | |
308 | +/* This is the configuration for nCS2/3 -> TDM-Switch, DSP | |
309 | + * configuration for nCS3: DSP | |
310 | + * [31] 0 - Slower Device | |
311 | + * [30:28] 001 - RRR3: CS deselect to CS time: 1*(2*MemClk) = 20 ns | |
312 | + * [27:24] 0010 - RDN3: Address to data valid in bursts: (2+1)*MemClk = 30 ns | |
313 | + * [23:20] 0011 - RDF3: Address for first access: (3+1)*MemClk = 40 ns | |
314 | + * [19] 1 - 16 Bit bus width | |
315 | + * [18:16] 100 - variable latency I/O | |
316 | + * configuration for nCS2: TDM-Switch | |
317 | + * [15] 0 - Slower Device | |
318 | + * [14:12] 101 - RRR2: CS deselect to CS time: 5*(2*MemClk) = 100 ns | |
319 | + * [11:08] 1001 - RDN2: Address to data valid in bursts: (9+1)*MemClk = 100 ns | |
320 | + * [07:04] 0011 - RDF2: Address for first access: (3+1)*MemClk = 40 ns | |
321 | + * [03] 1 - 16 Bit bus width | |
322 | + * [02:00] 100 - variable latency I/O | |
323 | + */ | |
324 | +#define CFG_MSC1_VAL 0x132C593C /* TDM switch, DSP */ | |
325 | + | |
326 | +/* This is the configuration for nCS4/5 -> ExtBus, LAN Controller | |
327 | + * | |
328 | + * configuration for nCS5: LAN Controller | |
329 | + * [31] 0 - Slower Device | |
330 | + * [30:28] 001 - RRR5: CS deselect to CS time: 1*(2*MemClk) = 20 ns | |
331 | + * [27:24] 0010 - RDN5: Address to data valid in bursts: (2+1)*MemClk = 30 ns | |
332 | + * [23:20] 0011 - RDF5: Address for first access: (3+1)*MemClk = 40 ns | |
333 | + * [19] 1 - 16 Bit bus width | |
334 | + * [18:16] 100 - variable latency I/O | |
335 | + * configuration for nCS4: ExtBus | |
336 | + * [15] 0 - Slower Device | |
337 | + * [14:12] 110 - RRR4: CS deselect to CS time: 6*(2*MemClk) = 120 ns | |
338 | + * [11:08] 1100 - RDN4: Address to data valid in bursts: (12+1)*MemClk = 130 ns | |
339 | + * [07:04] 1101 - RDF4: Address for first access: 13->(15+1)*MemClk = 160 ns | |
340 | + * [03] 1 - 16 Bit bus width | |
341 | + * [02:00] 100 - variable latency I/O | |
342 | + */ | |
343 | +#define CFG_MSC2_VAL 0x132C6CDC /* extra bus, LAN controller */ | |
344 | + | |
345 | +/* MDCNFG: SDRAM Configuration Register | |
346 | + * | |
347 | + * [31:29] 000 - reserved | |
348 | + * [28] 0 - no SA1111 compatiblity mode | |
349 | + * [27] 0 - latch return data with return clock | |
350 | + * [26] 0 - alternate addressing for pair 2/3 | |
351 | + * [25:24] 00 - timings | |
352 | + * [23] 0 - internal banks in lower partition 2/3 (not used) | |
353 | + * [22:21] 00 - row address bits for partition 2/3 (not used) | |
354 | + * [20:19] 00 - column address bits for partition 2/3 (not used) | |
355 | + * [18] 0 - SDRAM partition 2/3 width is 32 bit | |
356 | + * [17] 0 - SDRAM partition 3 disabled | |
357 | + * [16] 0 - SDRAM partition 2 disabled | |
358 | + * [15:13] 000 - reserved | |
359 | + * [12] 1 - SA1111 compatiblity mode | |
360 | + * [11] 1 - latch return data with return clock | |
361 | + * [10] 0 - no alternate addressing for pair 0/1 | |
362 | + * [09:08] 01 - tRP=2*MemClk; CL=2; tRCD=2*MemClk; tRAS=5*MemClk; tRC=8*MemClk | |
363 | + * [7] 1 - 4 internal banks in lower partition pair | |
364 | + * [06:05] 10 - 13 row address bits for partition 0/1 | |
365 | + * [04:03] 01 - 9 column address bits for partition 0/1 | |
366 | + * [02] 0 - SDRAM partition 0/1 width is 32 bit | |
367 | + * [01] 0 - disable SDRAM partition 1 | |
368 | + * [00] 1 - enable SDRAM partition 0 | |
369 | + * | |
370 | + * use the configuration above but disable partition 0 | |
371 | + */ | |
372 | +#define CFG_MDCNFG_VAL 0x000019c8 | |
373 | + | |
374 | +/* MDREFR: SDRAM Refresh Control Register | |
375 | + * | |
376 | + * [32:26] 0 - reserved | |
377 | + * [25] 0 - K2FREE: not free running | |
378 | + * [24] 0 - K1FREE: not free running | |
379 | + * [23] 0 - K0FREE: not free running | |
380 | + * [22] 0 - SLFRSH: self refresh disabled | |
381 | + * [21] 0 - reserved | |
382 | + * [20] 0 - APD: no auto power down | |
383 | + * [19] 0 - K2DB2: SDCLK2 is MemClk | |
384 | + * [18] 0 - K2RUN: disable SDCLK2 | |
385 | + * [17] 0 - K1DB2: SDCLK1 is MemClk | |
386 | + * [16] 1 - K1RUN: enable SDCLK1 | |
387 | + * [15] 1 - E1PIN: SDRAM clock enable | |
388 | + * [14] 1 - K0DB2: SDCLK0 is MemClk | |
389 | + * [13] 1 - K0RUN: disable SDCLK0 | |
390 | + * [12] 1 - E0PIN: disable SDCKE0 | |
391 | + * [11:00] 000000011000 - (64ms/8192)*MemClkFreq/32 = 24 | |
392 | + */ | |
393 | +#define CFG_MDREFR_VAL 0x0001F018 | |
394 | + | |
395 | +/* MDMRS: Mode Register Set Configuration Register | |
396 | + * | |
397 | + * [31] 0 - reserved | |
398 | + * [30:23] 00000000- MDMRS2: SDRAM2/3 MRS Value. (not used) | |
399 | + * [22:20] 000 - MDCL2: SDRAM2/3 Cas Latency. (not used) | |
400 | + * [19] 0 - MDADD2: SDRAM2/3 burst Type. Fixed to sequential. (not used) | |
401 | + * [18:16] 010 - MDBL2: SDRAM2/3 burst Length. Fixed to 4. (not used) | |
402 | + * [15] 0 - reserved | |
403 | + * [14:07] 00000000- MDMRS0: SDRAM0/1 MRS Value. | |
404 | + * [06:04] 010 - MDCL0: SDRAM0/1 Cas Latency. | |
405 | + * [03] 0 - MDADD0: SDRAM0/1 burst Type. Fixed to sequential. | |
406 | + * [02:00] 010 - MDBL0: SDRAM0/1 burst Length. Fixed to 4. | |
407 | + */ | |
408 | +#define CFG_MDMRS_VAL 0x00020022 | |
409 | + | |
410 | +/* | |
411 | + * PCMCIA and CF Interfaces | |
412 | + */ | |
413 | +#define CFG_MECR_VAL 0x00000000 | |
414 | +#define CFG_MCMEM0_VAL 0x00000000 | |
415 | +#define CFG_MCMEM1_VAL 0x00000000 | |
416 | +#define CFG_MCATT0_VAL 0x00000000 | |
417 | +#define CFG_MCATT1_VAL 0x00000000 | |
418 | +#define CFG_MCIO0_VAL 0x00000000 | |
419 | +#define CFG_MCIO1_VAL 0x00000000 | |
420 | + | |
421 | +/* | |
422 | +#define CSB226_USER_LED0 0x00000008 | |
423 | +#define CSB226_USER_LED1 0x00000010 | |
424 | +#define CSB226_USER_LED2 0x00000020 | |
425 | +*/ | |
426 | + | |
427 | +/* | |
428 | + * FLASH and environment organization | |
429 | + */ | |
430 | +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
431 | +#define CFG_MAX_FLASH_SECT 128 /* max number of sect. on one chip */ | |
432 | + | |
433 | +/* timeout values are in ticks */ | |
434 | +#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ | |
435 | +#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ | |
436 | + | |
437 | +#if 0 | |
438 | +#define CFG_ENV_IS_IN_FLASH 1 | |
439 | +#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x1C000) | |
440 | + /* Addr of Environment Sector */ | |
441 | +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ | |
442 | +#endif | |
443 | + | |
444 | +#endif /* __CONFIG_H */ |
include/configs/trab.h
... | ... | @@ -123,6 +123,7 @@ |
123 | 123 | #define CONFIG_BOOTARGS "console=ttyS0" |
124 | 124 | #define CONFIG_NETMASK 255.255.0.0 |
125 | 125 | #define CONFIG_IPADDR 192.168.3.68 |
126 | +#define CONFIG_HOSTNAME trab | |
126 | 127 | #define CONFIG_SERVERIP 192.168.3.1 |
127 | 128 | #define CONFIG_BOOTCOMMAND "run flash_nfs" |
128 | 129 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
129 | 130 | |
... | ... | @@ -220,7 +221,11 @@ |
220 | 221 | * FLASH and environment organization |
221 | 222 | */ |
222 | 223 | #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
224 | +#ifndef CONFIG_BIG_FLASH | |
225 | +#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ | |
226 | +#else | |
223 | 227 | #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ |
228 | +#endif | |
224 | 229 | |
225 | 230 | /* timeout values are in ticks */ |
226 | 231 | #define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ |
227 | 232 | |
228 | 233 | |
... | ... | @@ -229,11 +234,18 @@ |
229 | 234 | #define CFG_ENV_IS_IN_FLASH 1 |
230 | 235 | |
231 | 236 | /* Address and size of Primary Environment Sector */ |
237 | +#ifndef CONFIG_BIG_FLASH | |
232 | 238 | #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x4000) |
233 | 239 | #define CFG_ENV_SIZE 0x4000 |
240 | +#define CFG_ENV_SECT_SIZE 0x4000 | |
241 | +#else | |
242 | +#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x40000) | |
243 | +#define CFG_ENV_SIZE 0x4000 | |
244 | +#define CFG_ENV_SECT_SIZE 0x20000 | |
245 | +#endif | |
234 | 246 | |
235 | 247 | /* Address and size of Redundant Environment Sector */ |
236 | -#define CFG_ENV_OFFSET_REDUND (CFG_ENV_ADDR+CFG_ENV_SIZE) | |
248 | +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_ADDR+CFG_ENV_SECT_SIZE) | |
237 | 249 | #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) |
238 | 250 | |
239 | 251 | #endif /* __CONFIG_H */ |
tools/envcrc.c
... | ... | @@ -36,15 +36,33 @@ |
36 | 36 | # ifndef CFG_ENV_OFFSET |
37 | 37 | # define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE) |
38 | 38 | # endif |
39 | +# if !defined(CFG_ENV_ADDR_REDUND) && defined(CFG_ENV_OFFSET_REDUND) | |
40 | +# define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + CFG_ENV_OFFSET_REDUND) | |
41 | +# endif | |
39 | 42 | # ifndef CFG_ENV_SIZE |
40 | 43 | # define CFG_ENV_SIZE CFG_ENV_SECT_SIZE |
41 | 44 | # endif |
42 | -# if ((CFG_ENV_ADDR >= CFG_MONITOR_BASE) && \ | |
43 | - ((CFG_ENV_ADDR+CFG_ENV_SIZE) <= (CFG_MONITOR_BASE + CFG_MONITOR_LEN))) | |
44 | -# define ENV_IS_EMBEDDED | |
45 | +# if defined(CFG_ENV_ADDR_REDUND) && !defined(CFG_ENV_SIZE_REDUND) | |
46 | +# define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE | |
45 | 47 | # endif |
48 | +# if (CFG_ENV_ADDR >= CFG_MONITOR_BASE) && \ | |
49 | + ((CFG_ENV_ADDR + CFG_ENV_SIZE) <= (CFG_MONITOR_BASE + CFG_MONITOR_LEN)) | |
50 | +# define ENV_IS_EMBEDDED 1 | |
51 | +# endif | |
52 | +# if defined(CFG_ENV_ADDR_REDUND) || defined(CFG_ENV_OFFSET_REDUND) | |
53 | +# define CFG_REDUNDAND_ENVIRONMENT 1 | |
54 | +# endif | |
46 | 55 | #endif /* CFG_ENV_IS_IN_FLASH */ |
47 | 56 | |
57 | +#ifdef CFG_REDUNDAND_ENVIRONMENT | |
58 | +# define ENV_HEADER_SIZE (sizeof(unsigned long) + 1) | |
59 | +#else | |
60 | +# define ENV_HEADER_SIZE (sizeof(unsigned long)) | |
61 | +#endif | |
62 | + | |
63 | +#define ENV_SIZE (CFG_ENV_SIZE - ENV_HEADER_SIZE) | |
64 | + | |
65 | + | |
48 | 66 | extern unsigned long crc32 (unsigned long, const unsigned char *, unsigned int); |
49 | 67 | |
50 | 68 | #ifdef ENV_IS_EMBEDDED |
... | ... | @@ -57,9 +75,8 @@ |
57 | 75 | #ifdef ENV_IS_EMBEDDED |
58 | 76 | int crc ; |
59 | 77 | unsigned char *envptr = &environment, |
60 | - *dataptr = envptr + sizeof(unsigned int) + 1; | |
61 | - unsigned int datasize = env_size - (dataptr - envptr) ; | |
62 | - | |
78 | + *dataptr = envptr + ENV_HEADER_SIZE; | |
79 | + unsigned int datasize = ENV_SIZE; | |
63 | 80 | |
64 | 81 | crc = crc32(0, dataptr, datasize) ; |
65 | 82 |