Commit 43dd22f5fc4c368616721a69e5ea0769abf292dc
Committed by
Simon Glass
Simon Glass
1 parent
0e98a1473a
Exists in
v2017.01-smarct4x
and in
33 other branches
x86: Setup fixed range MTRRs for legacy regions
We should setup fixed range MTRRs for some legacy regions like VGA RAM and PCI ROM areas as uncacheable. Note FSP may setup these to other cache settings, but we can override this in x86_cpu_init_f(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
Showing 2 changed files with 38 additions and 11 deletions Side-by-side Diff
arch/x86/cpu/cpu.c
| ... | ... | @@ -28,6 +28,8 @@ |
| 28 | 28 | #include <asm/cpu.h> |
| 29 | 29 | #include <asm/lapic.h> |
| 30 | 30 | #include <asm/mp.h> |
| 31 | +#include <asm/msr.h> | |
| 32 | +#include <asm/mtrr.h> | |
| 31 | 33 | #include <asm/post.h> |
| 32 | 34 | #include <asm/processor.h> |
| 33 | 35 | #include <asm/processor-flags.h> |
| ... | ... | @@ -350,6 +352,26 @@ |
| 350 | 352 | gd->arch.x86_device = cpu.device; |
| 351 | 353 | |
| 352 | 354 | gd->arch.has_mtrr = has_mtrr(); |
| 355 | + } | |
| 356 | + | |
| 357 | + /* Configure fixed range MTRRs for some legacy regions */ | |
| 358 | + if (gd->arch.has_mtrr) { | |
| 359 | + u64 mtrr_cap; | |
| 360 | + | |
| 361 | + mtrr_cap = native_read_msr(MTRR_CAP_MSR); | |
| 362 | + if (mtrr_cap & MTRR_CAP_FIX) { | |
| 363 | + /* Mark the VGA RAM area as uncacheable */ | |
| 364 | + native_write_msr(MTRR_FIX_16K_A0000_MSR, 0, 0); | |
| 365 | + | |
| 366 | + /* Mark the PCI ROM area as uncacheable */ | |
| 367 | + native_write_msr(MTRR_FIX_4K_C0000_MSR, 0, 0); | |
| 368 | + native_write_msr(MTRR_FIX_4K_C8000_MSR, 0, 0); | |
| 369 | + native_write_msr(MTRR_FIX_4K_D0000_MSR, 0, 0); | |
| 370 | + native_write_msr(MTRR_FIX_4K_D8000_MSR, 0, 0); | |
| 371 | + | |
| 372 | + /* Enable the fixed range MTRRs */ | |
| 373 | + msr_setbits_64(MTRR_DEF_TYPE_MSR, MTRR_DEF_TYPE_FIX_EN); | |
| 374 | + } | |
| 353 | 375 | } |
| 354 | 376 | |
| 355 | 377 | return 0; |
arch/x86/include/asm/mtrr.h
| ... | ... | @@ -21,6 +21,11 @@ |
| 21 | 21 | #define MTRR_CAP_MSR 0x0fe |
| 22 | 22 | #define MTRR_DEF_TYPE_MSR 0x2ff |
| 23 | 23 | |
| 24 | +#define MTRR_CAP_SMRR (1 << 11) | |
| 25 | +#define MTRR_CAP_WC (1 << 10) | |
| 26 | +#define MTRR_CAP_FIX (1 << 8) | |
| 27 | +#define MTRR_CAP_VCNT_MASK 0xff | |
| 28 | + | |
| 24 | 29 | #define MTRR_DEF_TYPE_EN (1 << 11) |
| 25 | 30 | #define MTRR_DEF_TYPE_FIX_EN (1 << 10) |
| 26 | 31 | |
| ... | ... | @@ -38,17 +43,17 @@ |
| 38 | 43 | #define RANGES_PER_FIXED_MTRR 8 |
| 39 | 44 | #define NUM_FIXED_RANGES (NUM_FIXED_MTRRS * RANGES_PER_FIXED_MTRR) |
| 40 | 45 | |
| 41 | -#define MTRR_FIX_64K_00000_MSR 0x250 | |
| 42 | -#define MTRR_FIX_16K_80000_MSR 0x258 | |
| 43 | -#define MTRR_FIX_16K_A0000_MSR 0x259 | |
| 44 | -#define MTRR_FIX_4K_C0000_MSR 0x268 | |
| 45 | -#define MTRR_FIX_4K_C8000_MSR 0x269 | |
| 46 | -#define MTRR_FIX_4K_D0000_MSR 0x26a | |
| 47 | -#define MTRR_FIX_4K_D8000_MSR 0x26b | |
| 48 | -#define MTRR_FIX_4K_E0000_MSR 0x26c | |
| 49 | -#define MTRR_FIX_4K_E8000_MSR 0x26d | |
| 50 | -#define MTRR_FIX_4K_F0000_MSR 0x26e | |
| 51 | -#define MTRR_FIX_4K_F8000_MSR 0x26f | |
| 46 | +#define MTRR_FIX_64K_00000_MSR 0x250 | |
| 47 | +#define MTRR_FIX_16K_80000_MSR 0x258 | |
| 48 | +#define MTRR_FIX_16K_A0000_MSR 0x259 | |
| 49 | +#define MTRR_FIX_4K_C0000_MSR 0x268 | |
| 50 | +#define MTRR_FIX_4K_C8000_MSR 0x269 | |
| 51 | +#define MTRR_FIX_4K_D0000_MSR 0x26a | |
| 52 | +#define MTRR_FIX_4K_D8000_MSR 0x26b | |
| 53 | +#define MTRR_FIX_4K_E0000_MSR 0x26c | |
| 54 | +#define MTRR_FIX_4K_E8000_MSR 0x26d | |
| 55 | +#define MTRR_FIX_4K_F0000_MSR 0x26e | |
| 56 | +#define MTRR_FIX_4K_F8000_MSR 0x26f | |
| 52 | 57 | |
| 53 | 58 | #if !defined(__ASSEMBLER__) |
| 54 | 59 |