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Commit 4425e6285679a22522638bd4bb5281611635a30e

Authored by Marek Vasut
1 parent 09f7e314e4
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

arm: socfpga: clock: Drop nonsense inlining from clock manager code 

The inlining is done by GCC when needed, there is no need to do it
explicitly. Furthermore, the inline keyword does not force-inline
the code, but is only a hint for the compiler. Scrub this hint.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <clsee@altera.com>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Tom Rini <trini@ti.com>
Cc: Wolfgang Denk <wd@denx.de>
Cc: Pavel Machek <pavel@denx.de>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Pavel Machek <pavel@denx.de>

Showing 1 changed file with 6 additions and 6 deletions Inline Diff

arch/arm/cpu/armv7/socfpga/clock_manager.c
Diff comments   View file @ 4425e62
1 /* 1 /*
2 * Copyright (C) 2013 Altera Corporation <www.altera.com> 2 * Copyright (C) 2013 Altera Corporation <www.altera.com>
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #include <common.h> 7 #include <common.h>
8 #include <asm/io.h> 8 #include <asm/io.h>
9 #include <asm/arch/clock_manager.h> 9 #include <asm/arch/clock_manager.h>
10 10
11 static const struct socfpga_clock_manager *clock_manager_base = 11 static const struct socfpga_clock_manager *clock_manager_base =
12 (void *)SOCFPGA_CLKMGR_ADDRESS; 12 (void *)SOCFPGA_CLKMGR_ADDRESS;
13 13
14 #define CLKMGR_BYPASS_ENABLE 1 14 #define CLKMGR_BYPASS_ENABLE 1
15 #define CLKMGR_BYPASS_DISABLE 0 15 #define CLKMGR_BYPASS_DISABLE 0
16 #define CLKMGR_STAT_IDLE 0 16 #define CLKMGR_STAT_IDLE 0
17 #define CLKMGR_STAT_BUSY 1 17 #define CLKMGR_STAT_BUSY 1
18 #define CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1 0 18 #define CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1 0
19 #define CLKMGR_BYPASS_PERPLLSRC_SELECT_INPUT_MUX 1 19 #define CLKMGR_BYPASS_PERPLLSRC_SELECT_INPUT_MUX 1
20 #define CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1 0 20 #define CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1 0
21 #define CLKMGR_BYPASS_SDRPLLSRC_SELECT_INPUT_MUX 1 21 #define CLKMGR_BYPASS_SDRPLLSRC_SELECT_INPUT_MUX 1
22 22
23 #define CLEAR_BGP_EN_PWRDN \ 23 #define CLEAR_BGP_EN_PWRDN \
24 (CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \ 24 (CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
25 CLKMGR_MAINPLLGRP_VCO_EN_SET(0)| \ 25 CLKMGR_MAINPLLGRP_VCO_EN_SET(0)| \
26 CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0)) 26 CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
27 27
28 #define VCO_EN_BASE \ 28 #define VCO_EN_BASE \
29 (CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \ 29 (CLKMGR_MAINPLLGRP_VCO_PWRDN_SET(0)| \
30 CLKMGR_MAINPLLGRP_VCO_EN_SET(1)| \ 30 CLKMGR_MAINPLLGRP_VCO_EN_SET(1)| \
31 CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0)) 31 CLKMGR_MAINPLLGRP_VCO_BGPWRDN_SET(0))
32 32
33 static inline void cm_wait_for_lock(uint32_t mask) 33 static void cm_wait_for_lock(uint32_t mask)
34 { 34 {
35 register uint32_t inter_val; 35 register uint32_t inter_val;
36 do { 36 do {
37 inter_val = readl(&clock_manager_base->inter) & mask; 37 inter_val = readl(&clock_manager_base->inter) & mask;
38 } while (inter_val != mask); 38 } while (inter_val != mask);
39 } 39 }
40 40
41 /* function to poll in the fsm busy bit */ 41 /* function to poll in the fsm busy bit */
42 static inline void cm_wait_for_fsm(void) 42 static void cm_wait_for_fsm(void)
43 { 43 {
44 while (readl(&clock_manager_base->stat) & CLKMGR_STAT_BUSY) 44 while (readl(&clock_manager_base->stat) & CLKMGR_STAT_BUSY)
45 ; 45 ;
46 } 46 }
47 47
48 /* 48 /*
49 * function to write the bypass register which requires a poll of the 49 * function to write the bypass register which requires a poll of the
50 * busy bit 50 * busy bit
51 */ 51 */
52 static inline void cm_write_bypass(uint32_t val) 52 static void cm_write_bypass(uint32_t val)
53 { 53 {
54 writel(val, &clock_manager_base->bypass); 54 writel(val, &clock_manager_base->bypass);
55 cm_wait_for_fsm(); 55 cm_wait_for_fsm();
56 } 56 }
57 57
58 /* function to write the ctrl register which requires a poll of the busy bit */ 58 /* function to write the ctrl register which requires a poll of the busy bit */
59 static inline void cm_write_ctrl(uint32_t val) 59 static void cm_write_ctrl(uint32_t val)
60 { 60 {
61 writel(val, &clock_manager_base->ctrl); 61 writel(val, &clock_manager_base->ctrl);
62 cm_wait_for_fsm(); 62 cm_wait_for_fsm();
63 } 63 }
64 64
65 /* function to write a clock register that has phase information */ 65 /* function to write a clock register that has phase information */
66 static inline void cm_write_with_phase(uint32_t value, 66 static void cm_write_with_phase(uint32_t value,
67 uint32_t reg_address, uint32_t mask) 67 uint32_t reg_address, uint32_t mask)
68 { 68 {
69 /* poll until phase is zero */ 69 /* poll until phase is zero */
70 while (readl(reg_address) & mask) 70 while (readl(reg_address) & mask)
71 ; 71 ;
72 72
73 writel(value, reg_address); 73 writel(value, reg_address);
74 74
75 while (readl(reg_address) & mask) 75 while (readl(reg_address) & mask)
76 ; 76 ;
77 } 77 }
78 78
79 /* 79 /*
80 * Setup clocks while making no assumptions about previous state of the clocks. 80 * Setup clocks while making no assumptions about previous state of the clocks.
81 * 81 *
82 * Start by being paranoid and gate all sw managed clocks 82 * Start by being paranoid and gate all sw managed clocks
83 * Put all plls in bypass 83 * Put all plls in bypass
84 * Put all plls VCO registers back to reset value (bandgap power down). 84 * Put all plls VCO registers back to reset value (bandgap power down).
85 * Put peripheral and main pll src to reset value to avoid glitch. 85 * Put peripheral and main pll src to reset value to avoid glitch.
86 * Delay 5 us. 86 * Delay 5 us.
87 * Deassert bandgap power down and set numerator and denominator 87 * Deassert bandgap power down and set numerator and denominator
88 * Start 7 us timer. 88 * Start 7 us timer.
89 * set internal dividers 89 * set internal dividers
90 * Wait for 7 us timer. 90 * Wait for 7 us timer.
91 * Enable plls 91 * Enable plls
92 * Set external dividers while plls are locking 92 * Set external dividers while plls are locking
93 * Wait for pll lock 93 * Wait for pll lock
94 * Assert/deassert outreset all. 94 * Assert/deassert outreset all.
95 * Take all pll's out of bypass 95 * Take all pll's out of bypass
96 * Clear safe mode 96 * Clear safe mode
97 * set source main and peripheral clocks 97 * set source main and peripheral clocks
98 * Ungate clocks 98 * Ungate clocks
99 */ 99 */
100 100
101 void cm_basic_init(const cm_config_t *cfg) 101 void cm_basic_init(const cm_config_t *cfg)
102 { 102 {
103 uint32_t start, timeout; 103 uint32_t start, timeout;
104 104
105 /* Start by being paranoid and gate all sw managed clocks */ 105 /* Start by being paranoid and gate all sw managed clocks */
106 106
107 /* 107 /*
108 * We need to disable nandclk 108 * We need to disable nandclk
109 * and then do another apb access before disabling 109 * and then do another apb access before disabling
110 * gatting off the rest of the periperal clocks. 110 * gatting off the rest of the periperal clocks.
111 */ 111 */
112 writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK & 112 writel(~CLKMGR_PERPLLGRP_EN_NANDCLK_MASK &
113 readl(&clock_manager_base->per_pll.en), 113 readl(&clock_manager_base->per_pll.en),
114 &clock_manager_base->per_pll.en); 114 &clock_manager_base->per_pll.en);
115 115
116 /* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */ 116 /* DO NOT GATE OFF DEBUG CLOCKS & BRIDGE CLOCKS */
117 writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK | 117 writel(CLKMGR_MAINPLLGRP_EN_DBGTIMERCLK_MASK |
118 CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK | 118 CLKMGR_MAINPLLGRP_EN_DBGTRACECLK_MASK |
119 CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK | 119 CLKMGR_MAINPLLGRP_EN_DBGCLK_MASK |
120 CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK | 120 CLKMGR_MAINPLLGRP_EN_DBGATCLK_MASK |
121 CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK | 121 CLKMGR_MAINPLLGRP_EN_S2FUSER0CLK_MASK |
122 CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK, 122 CLKMGR_MAINPLLGRP_EN_L4MPCLK_MASK,
123 &clock_manager_base->main_pll.en); 123 &clock_manager_base->main_pll.en);
124 124
125 writel(0, &clock_manager_base->sdr_pll.en); 125 writel(0, &clock_manager_base->sdr_pll.en);
126 126
127 /* now we can gate off the rest of the peripheral clocks */ 127 /* now we can gate off the rest of the peripheral clocks */
128 writel(0, &clock_manager_base->per_pll.en); 128 writel(0, &clock_manager_base->per_pll.en);
129 129
130 /* Put all plls in bypass */ 130 /* Put all plls in bypass */
131 cm_write_bypass( 131 cm_write_bypass(
132 CLKMGR_BYPASS_PERPLLSRC_SET( 132 CLKMGR_BYPASS_PERPLLSRC_SET(
133 CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) | 133 CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) |
134 CLKMGR_BYPASS_SDRPLLSRC_SET( 134 CLKMGR_BYPASS_SDRPLLSRC_SET(
135 CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) | 135 CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) |
136 CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_ENABLE) | 136 CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_ENABLE) |
137 CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_ENABLE) | 137 CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_ENABLE) |
138 CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_ENABLE)); 138 CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_ENABLE));
139 139
140 /* 140 /*
141 * Put all plls VCO registers back to reset value. 141 * Put all plls VCO registers back to reset value.
142 * Some code might have messed with them. 142 * Some code might have messed with them.
143 */ 143 */
144 writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE, 144 writel(CLKMGR_MAINPLLGRP_VCO_RESET_VALUE,
145 &clock_manager_base->main_pll.vco); 145 &clock_manager_base->main_pll.vco);
146 writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE, 146 writel(CLKMGR_PERPLLGRP_VCO_RESET_VALUE,
147 &clock_manager_base->per_pll.vco); 147 &clock_manager_base->per_pll.vco);
148 writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE, 148 writel(CLKMGR_SDRPLLGRP_VCO_RESET_VALUE,
149 &clock_manager_base->sdr_pll.vco); 149 &clock_manager_base->sdr_pll.vco);
150 150
151 /* 151 /*
152 * The clocks to the flash devices and the L4_MAIN clocks can 152 * The clocks to the flash devices and the L4_MAIN clocks can
153 * glitch when coming out of safe mode if their source values 153 * glitch when coming out of safe mode if their source values
154 * are different from their reset value. So the trick it to 154 * are different from their reset value. So the trick it to
155 * put them back to their reset state, and change input 155 * put them back to their reset state, and change input
156 * after exiting safe mode but before ungating the clocks. 156 * after exiting safe mode but before ungating the clocks.
157 */ 157 */
158 writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE, 158 writel(CLKMGR_PERPLLGRP_SRC_RESET_VALUE,
159 &clock_manager_base->per_pll.src); 159 &clock_manager_base->per_pll.src);
160 writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE, 160 writel(CLKMGR_MAINPLLGRP_L4SRC_RESET_VALUE,
161 &clock_manager_base->main_pll.l4src); 161 &clock_manager_base->main_pll.l4src);
162 162
163 /* read back for the required 5 us delay. */ 163 /* read back for the required 5 us delay. */
164 readl(&clock_manager_base->main_pll.vco); 164 readl(&clock_manager_base->main_pll.vco);
165 readl(&clock_manager_base->per_pll.vco); 165 readl(&clock_manager_base->per_pll.vco);
166 readl(&clock_manager_base->sdr_pll.vco); 166 readl(&clock_manager_base->sdr_pll.vco);
167 167
168 168
169 /* 169 /*
170 * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN 170 * We made sure bgpwr down was assert for 5 us. Now deassert BG PWR DN
171 * with numerator and denominator. 171 * with numerator and denominator.
172 */ 172 */
173 writel(cfg->main_vco_base | CLEAR_BGP_EN_PWRDN | 173 writel(cfg->main_vco_base | CLEAR_BGP_EN_PWRDN |
174 CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK, 174 CLKMGR_MAINPLLGRP_VCO_REGEXTSEL_MASK,
175 &clock_manager_base->main_pll.vco); 175 &clock_manager_base->main_pll.vco);
176 176
177 writel(cfg->peri_vco_base | CLEAR_BGP_EN_PWRDN | 177 writel(cfg->peri_vco_base | CLEAR_BGP_EN_PWRDN |
178 CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK, 178 CLKMGR_PERPLLGRP_VCO_REGEXTSEL_MASK,
179 &clock_manager_base->per_pll.vco); 179 &clock_manager_base->per_pll.vco);
180 180
181 writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) | 181 writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) |
182 CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) | 182 CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
183 cfg->sdram_vco_base | CLEAR_BGP_EN_PWRDN | 183 cfg->sdram_vco_base | CLEAR_BGP_EN_PWRDN |
184 CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK, 184 CLKMGR_SDRPLLGRP_VCO_REGEXTSEL_MASK,
185 &clock_manager_base->sdr_pll.vco); 185 &clock_manager_base->sdr_pll.vco);
186 186
187 /* 187 /*
188 * Time starts here 188 * Time starts here
189 * must wait 7 us from BGPWRDN_SET(0) to VCO_ENABLE_SET(1) 189 * must wait 7 us from BGPWRDN_SET(0) to VCO_ENABLE_SET(1)
190 */ 190 */
191 start = get_timer(0); 191 start = get_timer(0);
192 /* timeout in unit of us as CONFIG_SYS_HZ = 1000*1000 */ 192 /* timeout in unit of us as CONFIG_SYS_HZ = 1000*1000 */
193 timeout = 7; 193 timeout = 7;
194 194
195 /* main mpu */ 195 /* main mpu */
196 writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk); 196 writel(cfg->mpuclk, &clock_manager_base->main_pll.mpuclk);
197 197
198 /* main main clock */ 198 /* main main clock */
199 writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk); 199 writel(cfg->mainclk, &clock_manager_base->main_pll.mainclk);
200 200
201 /* main for dbg */ 201 /* main for dbg */
202 writel(cfg->dbgatclk, &clock_manager_base->main_pll.dbgatclk); 202 writel(cfg->dbgatclk, &clock_manager_base->main_pll.dbgatclk);
203 203
204 /* main for cfgs2fuser0clk */ 204 /* main for cfgs2fuser0clk */
205 writel(cfg->cfg2fuser0clk, 205 writel(cfg->cfg2fuser0clk,
206 &clock_manager_base->main_pll.cfgs2fuser0clk); 206 &clock_manager_base->main_pll.cfgs2fuser0clk);
207 207
208 /* Peri emac0 50 MHz default to RMII */ 208 /* Peri emac0 50 MHz default to RMII */
209 writel(cfg->emac0clk, &clock_manager_base->per_pll.emac0clk); 209 writel(cfg->emac0clk, &clock_manager_base->per_pll.emac0clk);
210 210
211 /* Peri emac1 50 MHz default to RMII */ 211 /* Peri emac1 50 MHz default to RMII */
212 writel(cfg->emac1clk, &clock_manager_base->per_pll.emac1clk); 212 writel(cfg->emac1clk, &clock_manager_base->per_pll.emac1clk);
213 213
214 /* Peri QSPI */ 214 /* Peri QSPI */
215 writel(cfg->mainqspiclk, &clock_manager_base->main_pll.mainqspiclk); 215 writel(cfg->mainqspiclk, &clock_manager_base->main_pll.mainqspiclk);
216 216
217 writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk); 217 writel(cfg->perqspiclk, &clock_manager_base->per_pll.perqspiclk);
218 218
219 /* Peri pernandsdmmcclk */ 219 /* Peri pernandsdmmcclk */
220 writel(cfg->pernandsdmmcclk, 220 writel(cfg->pernandsdmmcclk,
221 &clock_manager_base->per_pll.pernandsdmmcclk); 221 &clock_manager_base->per_pll.pernandsdmmcclk);
222 222
223 /* Peri perbaseclk */ 223 /* Peri perbaseclk */
224 writel(cfg->perbaseclk, &clock_manager_base->per_pll.perbaseclk); 224 writel(cfg->perbaseclk, &clock_manager_base->per_pll.perbaseclk);
225 225
226 /* Peri s2fuser1clk */ 226 /* Peri s2fuser1clk */
227 writel(cfg->s2fuser1clk, &clock_manager_base->per_pll.s2fuser1clk); 227 writel(cfg->s2fuser1clk, &clock_manager_base->per_pll.s2fuser1clk);
228 228
229 /* 7 us must have elapsed before we can enable the VCO */ 229 /* 7 us must have elapsed before we can enable the VCO */
230 while (get_timer(start) < timeout) 230 while (get_timer(start) < timeout)
231 ; 231 ;
232 232
233 /* Enable vco */ 233 /* Enable vco */
234 /* main pll vco */ 234 /* main pll vco */
235 writel(cfg->main_vco_base | VCO_EN_BASE, 235 writel(cfg->main_vco_base | VCO_EN_BASE,
236 &clock_manager_base->main_pll.vco); 236 &clock_manager_base->main_pll.vco);
237 237
238 /* periferal pll */ 238 /* periferal pll */
239 writel(cfg->peri_vco_base | VCO_EN_BASE, 239 writel(cfg->peri_vco_base | VCO_EN_BASE,
240 &clock_manager_base->per_pll.vco); 240 &clock_manager_base->per_pll.vco);
241 241
242 /* sdram pll vco */ 242 /* sdram pll vco */
243 writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) | 243 writel(CLKMGR_SDRPLLGRP_VCO_OUTRESET_SET(0) |
244 CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) | 244 CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
245 cfg->sdram_vco_base | VCO_EN_BASE, 245 cfg->sdram_vco_base | VCO_EN_BASE,
246 &clock_manager_base->sdr_pll.vco); 246 &clock_manager_base->sdr_pll.vco);
247 247
248 /* L3 MP and L3 SP */ 248 /* L3 MP and L3 SP */
249 writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv); 249 writel(cfg->maindiv, &clock_manager_base->main_pll.maindiv);
250 250
251 writel(cfg->dbgdiv, &clock_manager_base->main_pll.dbgdiv); 251 writel(cfg->dbgdiv, &clock_manager_base->main_pll.dbgdiv);
252 252
253 writel(cfg->tracediv, &clock_manager_base->main_pll.tracediv); 253 writel(cfg->tracediv, &clock_manager_base->main_pll.tracediv);
254 254
255 /* L4 MP, L4 SP, can0, and can1 */ 255 /* L4 MP, L4 SP, can0, and can1 */
256 writel(cfg->perdiv, &clock_manager_base->per_pll.div); 256 writel(cfg->perdiv, &clock_manager_base->per_pll.div);
257 257
258 writel(cfg->gpiodiv, &clock_manager_base->per_pll.gpiodiv); 258 writel(cfg->gpiodiv, &clock_manager_base->per_pll.gpiodiv);
259 259
260 #define LOCKED_MASK \ 260 #define LOCKED_MASK \
261 (CLKMGR_INTER_SDRPLLLOCKED_MASK | \ 261 (CLKMGR_INTER_SDRPLLLOCKED_MASK | \
262 CLKMGR_INTER_PERPLLLOCKED_MASK | \ 262 CLKMGR_INTER_PERPLLLOCKED_MASK | \
263 CLKMGR_INTER_MAINPLLLOCKED_MASK) 263 CLKMGR_INTER_MAINPLLLOCKED_MASK)
264 264
265 cm_wait_for_lock(LOCKED_MASK); 265 cm_wait_for_lock(LOCKED_MASK);
266 266
267 /* write the sdram clock counters before toggling outreset all */ 267 /* write the sdram clock counters before toggling outreset all */
268 writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK, 268 writel(cfg->ddrdqsclk & CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_MASK,
269 &clock_manager_base->sdr_pll.ddrdqsclk); 269 &clock_manager_base->sdr_pll.ddrdqsclk);
270 270
271 writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK, 271 writel(cfg->ddr2xdqsclk & CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_MASK,
272 &clock_manager_base->sdr_pll.ddr2xdqsclk); 272 &clock_manager_base->sdr_pll.ddr2xdqsclk);
273 273
274 writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK, 274 writel(cfg->ddrdqclk & CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_MASK,
275 &clock_manager_base->sdr_pll.ddrdqclk); 275 &clock_manager_base->sdr_pll.ddrdqclk);
276 276
277 writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK, 277 writel(cfg->s2fuser2clk & CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_MASK,
278 &clock_manager_base->sdr_pll.s2fuser2clk); 278 &clock_manager_base->sdr_pll.s2fuser2clk);
279 279
280 /* 280 /*
281 * after locking, but before taking out of bypass 281 * after locking, but before taking out of bypass
282 * assert/deassert outresetall 282 * assert/deassert outresetall
283 */ 283 */
284 uint32_t mainvco = readl(&clock_manager_base->main_pll.vco); 284 uint32_t mainvco = readl(&clock_manager_base->main_pll.vco);
285 285
286 /* assert main outresetall */ 286 /* assert main outresetall */
287 writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK, 287 writel(mainvco | CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
288 &clock_manager_base->main_pll.vco); 288 &clock_manager_base->main_pll.vco);
289 289
290 uint32_t periphvco = readl(&clock_manager_base->per_pll.vco); 290 uint32_t periphvco = readl(&clock_manager_base->per_pll.vco);
291 291
292 /* assert pheriph outresetall */ 292 /* assert pheriph outresetall */
293 writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK, 293 writel(periphvco | CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
294 &clock_manager_base->per_pll.vco); 294 &clock_manager_base->per_pll.vco);
295 295
296 /* assert sdram outresetall */ 296 /* assert sdram outresetall */
297 writel(cfg->sdram_vco_base | VCO_EN_BASE| 297 writel(cfg->sdram_vco_base | VCO_EN_BASE|
298 CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(1), 298 CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(1),
299 &clock_manager_base->sdr_pll.vco); 299 &clock_manager_base->sdr_pll.vco);
300 300
301 /* deassert main outresetall */ 301 /* deassert main outresetall */
302 writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK, 302 writel(mainvco & ~CLKMGR_MAINPLLGRP_VCO_OUTRESETALL_MASK,
303 &clock_manager_base->main_pll.vco); 303 &clock_manager_base->main_pll.vco);
304 304
305 /* deassert pheriph outresetall */ 305 /* deassert pheriph outresetall */
306 writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK, 306 writel(periphvco & ~CLKMGR_PERPLLGRP_VCO_OUTRESETALL_MASK,
307 &clock_manager_base->per_pll.vco); 307 &clock_manager_base->per_pll.vco);
308 308
309 /* deassert sdram outresetall */ 309 /* deassert sdram outresetall */
310 writel(CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) | 310 writel(CLKMGR_SDRPLLGRP_VCO_OUTRESETALL_SET(0) |
311 cfg->sdram_vco_base | VCO_EN_BASE, 311 cfg->sdram_vco_base | VCO_EN_BASE,
312 &clock_manager_base->sdr_pll.vco); 312 &clock_manager_base->sdr_pll.vco);
313 313
314 /* 314 /*
315 * now that we've toggled outreset all, all the clocks 315 * now that we've toggled outreset all, all the clocks
316 * are aligned nicely; so we can change any phase. 316 * are aligned nicely; so we can change any phase.
317 */ 317 */
318 cm_write_with_phase(cfg->ddrdqsclk, 318 cm_write_with_phase(cfg->ddrdqsclk,
319 (uint32_t)&clock_manager_base->sdr_pll.ddrdqsclk, 319 (uint32_t)&clock_manager_base->sdr_pll.ddrdqsclk,
320 CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK); 320 CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_MASK);
321 321
322 /* SDRAM DDR2XDQSCLK */ 322 /* SDRAM DDR2XDQSCLK */
323 cm_write_with_phase(cfg->ddr2xdqsclk, 323 cm_write_with_phase(cfg->ddr2xdqsclk,
324 (uint32_t)&clock_manager_base->sdr_pll.ddr2xdqsclk, 324 (uint32_t)&clock_manager_base->sdr_pll.ddr2xdqsclk,
325 CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK); 325 CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_MASK);
326 326
327 cm_write_with_phase(cfg->ddrdqclk, 327 cm_write_with_phase(cfg->ddrdqclk,
328 (uint32_t)&clock_manager_base->sdr_pll.ddrdqclk, 328 (uint32_t)&clock_manager_base->sdr_pll.ddrdqclk,
329 CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK); 329 CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_MASK);
330 330
331 cm_write_with_phase(cfg->s2fuser2clk, 331 cm_write_with_phase(cfg->s2fuser2clk,
332 (uint32_t)&clock_manager_base->sdr_pll.s2fuser2clk, 332 (uint32_t)&clock_manager_base->sdr_pll.s2fuser2clk,
333 CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK); 333 CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_MASK);
334 334
335 /* Take all three PLLs out of bypass when safe mode is cleared. */ 335 /* Take all three PLLs out of bypass when safe mode is cleared. */
336 cm_write_bypass( 336 cm_write_bypass(
337 CLKMGR_BYPASS_PERPLLSRC_SET( 337 CLKMGR_BYPASS_PERPLLSRC_SET(
338 CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) | 338 CLKMGR_BYPASS_PERPLLSRC_SELECT_EOSC1) |
339 CLKMGR_BYPASS_SDRPLLSRC_SET( 339 CLKMGR_BYPASS_SDRPLLSRC_SET(
340 CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) | 340 CLKMGR_BYPASS_SDRPLLSRC_SELECT_EOSC1) |
341 CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_DISABLE) | 341 CLKMGR_BYPASS_PERPLL_SET(CLKMGR_BYPASS_DISABLE) |
342 CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_DISABLE) | 342 CLKMGR_BYPASS_SDRPLL_SET(CLKMGR_BYPASS_DISABLE) |
343 CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_DISABLE)); 343 CLKMGR_BYPASS_MAINPLL_SET(CLKMGR_BYPASS_DISABLE));
344 344
345 /* clear safe mode */ 345 /* clear safe mode */
346 cm_write_ctrl(readl(&clock_manager_base->ctrl) | 346 cm_write_ctrl(readl(&clock_manager_base->ctrl) |
347 CLKMGR_CTRL_SAFEMODE_SET(CLKMGR_CTRL_SAFEMODE_MASK)); 347 CLKMGR_CTRL_SAFEMODE_SET(CLKMGR_CTRL_SAFEMODE_MASK));
348 348
349 /* 349 /*
350 * now that safe mode is clear with clocks gated 350 * now that safe mode is clear with clocks gated
351 * it safe to change the source mux for the flashes the the L4_MAIN 351 * it safe to change the source mux for the flashes the the L4_MAIN
352 */ 352 */
353 writel(cfg->persrc, &clock_manager_base->per_pll.src); 353 writel(cfg->persrc, &clock_manager_base->per_pll.src);
354 writel(cfg->l4src, &clock_manager_base->main_pll.l4src); 354 writel(cfg->l4src, &clock_manager_base->main_pll.l4src);
355 355
356 /* Now ungate non-hw-managed clocks */ 356 /* Now ungate non-hw-managed clocks */
357 writel(~0, &clock_manager_base->main_pll.en); 357 writel(~0, &clock_manager_base->main_pll.en);
358 writel(~0, &clock_manager_base->per_pll.en); 358 writel(~0, &clock_manager_base->per_pll.en);
359 writel(~0, &clock_manager_base->sdr_pll.en); 359 writel(~0, &clock_manager_base->sdr_pll.en);
360 } 360 }
361 361