Eric Lee / smarc-uboot | Embedian Git Server

Commit 44262327aa288b111a41ce067bed235759db4c1c

Authored by Ahmed Mansour 2017-12-16 05:01:00 +0800

Committed by York Sun 2018-01-11 04:28:47 +0800

Exists in smarc_8mq_lf_v2020.04 and in 17 other branches

drivers/misc: Share qbman init between archs

This patch adds changes necessary to move functionality present in
PowerPC folders with ARM architectures that have DPAA1 QBMan hardware

- Create new board/freescale/common/fsl_portals.c to house shared
  device tree fixups for DPAA1 devices with ARM and PowerPC cores
- Add new header file to top includes directory to allow files in
  both architectures to grab the function prototypes
- Port inhibit_portals() from PowerPC to ARM. This function is used in
  setup to disable interrupts on all QMan and BMan portals. It is
  needed because the interrupts are enabled by default for all portals
  including unused/uninitialised portals. When the kernel attempts to
  go to deep sleep the unused portals prevent it from doing so

Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

Showing 18 changed files with 454 additions and 351 deletions Inline Diff

arch/arm/cpu/armv8/fsl-layerscape/cpu.c
arch/arm/cpu/armv8/fsl-layerscape/fdt.c
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
arch/arm/include/asm/arch-fsl-layerscape/speed.h
arch/powerpc/cpu/mpc85xx/cpu_init.c
arch/powerpc/cpu/mpc85xx/fdt.c
arch/powerpc/cpu/mpc85xx/portals.c
arch/powerpc/include/asm/fsl_liodn.h
arch/powerpc/include/asm/fsl_portals.h
arch/powerpc/include/asm/immap_85xx.h
board/freescale/p1023rdb/p1023rdb.c
board/keymile/kmp204x/kmp204x.c
board/varisys/cyrus/cyrus.c
drivers/misc/Makefile
drivers/misc/fsl_portals.c
include/configs/ls1043a_common.h
include/fsl_qbman.h

arch/arm/cpu/armv8/fsl-layerscape/cpu.c

Diff comments View file @ 4426232

 /*
  * Copyright 2017 NXP
  * Copyright 2014-2015 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
 #include <fsl_ddr_sdram.h>
 #include <asm/io.h>
 #include <linux/errno.h>
 #include <asm/system.h>
 #include <asm/armv8/mmu.h>
 #include <asm/io.h>
 #include <asm/arch/fsl_serdes.h>
 #include <asm/arch/soc.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/speed.h>
 #include <fsl_immap.h>
 #include <asm/arch/mp.h>
 #include <efi_loader.h>
 #include <fm_eth.h>
 #include <fsl-mc/fsl_mc.h>
 #ifdef CONFIG_FSL_ESDHC
 #include <fsl_esdhc.h>
 #endif
 #include <asm/armv8/sec_firmware.h>
 #ifdef CONFIG_SYS_FSL_DDR
 #include <fsl_ddr.h>
 #endif
 #include <asm/arch/clock.h>
 #include <hwconfig.h>
+#include <fsl_qbman.h>
 DECLARE_GLOBAL_DATA_PTR;
 struct mm_region *mem_map = early_map;
 void cpu_name(char *name)
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	unsigned int i, svr, ver;
 	svr = gur_in32(&gur->svr);
 	ver = SVR_SOC_VER(svr);
 	for (i = 0; i < ARRAY_SIZE(cpu_type_list); i++)
 		if ((cpu_type_list[i].soc_ver & SVR_WO_E) == ver) {
 			strcpy(name, cpu_type_list[i].name);
 			if (IS_E_PROCESSOR(svr))
 				strcat(name, "E");
 			sprintf(name + strlen(name), " Rev%d.%d",
 				SVR_MAJ(svr), SVR_MIN(svr));
 			break;
 		}
 	if (i == ARRAY_SIZE(cpu_type_list))
 		strcpy(name, "unknown");
 }
 #ifndef CONFIG_SYS_DCACHE_OFF
 /*
  * To start MMU before DDR is available, we create MMU table in SRAM.
  * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
  * levels of translation tables here to cover 40-bit address space.
  * We use 4KB granule size, with 40 bits physical address, T0SZ=24
  * Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose.
  * Note, the debug print in cache_v8.c is not usable for debugging
  * these early MMU tables because UART is not yet available.
  */
 static inline void early_mmu_setup(void)
 {
 	unsigned int el = current_el();
 	/* global data is already setup, no allocation yet */
 	gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
 	gd->arch.tlb_fillptr = gd->arch.tlb_addr;
 	gd->arch.tlb_size = EARLY_PGTABLE_SIZE;
 	/* Create early page tables */
 	setup_pgtables();
 	/* point TTBR to the new table */
 	set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
 			  get_tcr(el, NULL, NULL) &
 			  ~(TCR_ORGN_MASK | TCR_IRGN_MASK),
 			  MEMORY_ATTRIBUTES);
 	set_sctlr(get_sctlr() | CR_M);
 }
 static void fix_pcie_mmu_map(void)
 {
 #ifdef CONFIG_ARCH_LS2080A
 	unsigned int i;
 	u32 svr, ver;
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	svr = gur_in32(&gur->svr);
 	ver = SVR_SOC_VER(svr);
 	/* Fix PCIE base and size for LS2088A */
 	if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) ||
 	    (ver == SVR_LS2048A) || (ver == SVR_LS2044A) ||
 	    (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) {
 		for (i = 0; i < ARRAY_SIZE(final_map); i++) {
 			switch (final_map[i].phys) {
 			case CONFIG_SYS_PCIE1_PHYS_ADDR:
 				final_map[i].phys = 0x2000000000ULL;
 				final_map[i].virt = 0x2000000000ULL;
 				final_map[i].size = 0x800000000ULL;
 				break;
 			case CONFIG_SYS_PCIE2_PHYS_ADDR:
 				final_map[i].phys = 0x2800000000ULL;
 				final_map[i].virt = 0x2800000000ULL;
 				final_map[i].size = 0x800000000ULL;
 				break;
 			case CONFIG_SYS_PCIE3_PHYS_ADDR:
 				final_map[i].phys = 0x3000000000ULL;
 				final_map[i].virt = 0x3000000000ULL;
 				final_map[i].size = 0x800000000ULL;
 				break;
 			case CONFIG_SYS_PCIE4_PHYS_ADDR:
 				final_map[i].phys = 0x3800000000ULL;
 				final_map[i].virt = 0x3800000000ULL;
 				final_map[i].size = 0x800000000ULL;
 				break;
 			default:
 				break;
 			}
 		}
 	}
 #endif
 }
 /*
  * The final tables look similar to early tables, but different in detail.
  * These tables are in DRAM. Sub tables are added to enable cache for
  * QBMan and OCRAM.
  *
  * Put the MMU table in secure memory if gd->arch.secure_ram is valid.
  * OCRAM will be not used for this purpose so gd->arch.secure_ram can't be 0.
  */
 static inline void final_mmu_setup(void)
 {
 	u64 tlb_addr_save = gd->arch.tlb_addr;
 	unsigned int el = current_el();
 	int index;
 	/* fix the final_map before filling in the block entries */
 	fix_pcie_mmu_map();
 	mem_map = final_map;
 	/* Update mapping for DDR to actual size */
 	for (index = 0; index < ARRAY_SIZE(final_map) - 2; index++) {
 		/*
 		 * Find the entry for DDR mapping and update the address and
 		 * size. Zero-sized mapping will be skipped when creating MMU
 		 * table.
 		 */
 		switch (final_map[index].virt) {
 		case CONFIG_SYS_FSL_DRAM_BASE1:
 			final_map[index].virt = gd->bd->bi_dram[0].start;
 			final_map[index].phys = gd->bd->bi_dram[0].start;
 			final_map[index].size = gd->bd->bi_dram[0].size;
 			break;
 #ifdef CONFIG_SYS_FSL_DRAM_BASE2
 		case CONFIG_SYS_FSL_DRAM_BASE2:
 #if (CONFIG_NR_DRAM_BANKS >= 2)
 			final_map[index].virt = gd->bd->bi_dram[1].start;
 			final_map[index].phys = gd->bd->bi_dram[1].start;
 			final_map[index].size = gd->bd->bi_dram[1].size;
 #else
 			final_map[index].size = 0;
 #endif
 		break;
 #endif
 #ifdef CONFIG_SYS_FSL_DRAM_BASE3
 		case CONFIG_SYS_FSL_DRAM_BASE3:
 #if (CONFIG_NR_DRAM_BANKS >= 3)
 			final_map[index].virt = gd->bd->bi_dram[2].start;
 			final_map[index].phys = gd->bd->bi_dram[2].start;
 			final_map[index].size = gd->bd->bi_dram[2].size;
 #else
 			final_map[index].size = 0;
 #endif
 		break;
 #endif
 		default:
 			break;
 		}
 	}
 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 	if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
 		if (el == 3) {
 			/*
 			 * Only use gd->arch.secure_ram if the address is
 			 * recalculated. Align to 4KB for MMU table.
 			 */
 			/* put page tables in secure ram */
 			index = ARRAY_SIZE(final_map) - 2;
 			gd->arch.tlb_addr = gd->arch.secure_ram & ~0xfff;
 			final_map[index].virt = gd->arch.secure_ram & ~0x3;
 			final_map[index].phys = final_map[index].virt;
 			final_map[index].size = CONFIG_SYS_MEM_RESERVE_SECURE;
 			final_map[index].attrs = PTE_BLOCK_OUTER_SHARE;
 			gd->arch.secure_ram |= MEM_RESERVE_SECURE_SECURED;
 			tlb_addr_save = gd->arch.tlb_addr;
 		} else {
 			/* Use allocated (board_f.c) memory for TLB */
 			tlb_addr_save = gd->arch.tlb_allocated;
 			gd->arch.tlb_addr = tlb_addr_save;
 		}
 	}
 #endif
 	/* Reset the fill ptr */
 	gd->arch.tlb_fillptr = tlb_addr_save;
 	/* Create normal system page tables */
 	setup_pgtables();
 	/* Create emergency page tables */
 	gd->arch.tlb_addr = gd->arch.tlb_fillptr;
 	gd->arch.tlb_emerg = gd->arch.tlb_addr;
 	setup_pgtables();
 	gd->arch.tlb_addr = tlb_addr_save;
 	/* Disable cache and MMU */
 	dcache_disable();	/* TLBs are invalidated */
 	invalidate_icache_all();
 	/* point TTBR to the new table */
 	set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
 			  MEMORY_ATTRIBUTES);
 	set_sctlr(get_sctlr() | CR_M);
 }
 u64 get_page_table_size(void)
 {
 	return 0x10000;
 }
 int arch_cpu_init(void)
 {
 	/*
 	 * This function is called before U-Boot relocates itself to speed up
 	 * on system running. It is not necessary to run if performance is not
 	 * critical. Skip if MMU is already enabled by SPL or other means.
 	 */
 	if (get_sctlr() & CR_M)
 		return 0;
 	icache_enable();
 	__asm_invalidate_dcache_all();
 	__asm_invalidate_tlb_all();
 	early_mmu_setup();
 	set_sctlr(get_sctlr() | CR_C);
 	return 0;
 }
 void mmu_setup(void)
 {
 	final_mmu_setup();
 }
 /*
  * This function is called from common/board_r.c.
  * It recreates MMU table in main memory.
  */
 void enable_caches(void)
 {
 	mmu_setup();
 	__asm_invalidate_tlb_all();
 	icache_enable();
 	dcache_enable();
 }
 #endif
 u32 initiator_type(u32 cluster, int init_id)
 {
 	struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
 	u32 type = 0;
 	type = gur_in32(&gur->tp_ityp[idx]);
 	if (type & TP_ITYP_AV)
 		return type;
 	return 0;
 }
 u32 cpu_pos_mask(void)
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	int i = 0;
 	u32 cluster, type, mask = 0;
 	do {
 		int j;
 		cluster = gur_in32(&gur->tp_cluster[i].lower);
 		for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 			type = initiator_type(cluster, j);
 			if (type && (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM))
 				mask |= 1 << (i * TP_INIT_PER_CLUSTER + j);
 		}
 		i++;
 	} while ((cluster & TP_CLUSTER_EOC) == 0x0);
 	return mask;
 }
 u32 cpu_mask(void)
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	int i = 0, count = 0;
 	u32 cluster, type, mask = 0;
 	do {
 		int j;
 		cluster = gur_in32(&gur->tp_cluster[i].lower);
 		for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 			type = initiator_type(cluster, j);
 			if (type) {
 				if (TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
 					mask |= 1 << count;
 				count++;
 			}
 		}
 		i++;
 	} while ((cluster & TP_CLUSTER_EOC) == 0x0);
 	return mask;
 }
 /*
  * Return the number of cores on this SOC.
  */
 int cpu_numcores(void)
 {
 	return hweight32(cpu_mask());
 }
 int fsl_qoriq_core_to_cluster(unsigned int core)
 {
 	struct ccsr_gur __iomem *gur =
 		(void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	int i = 0, count = 0;
 	u32 cluster;
 	do {
 		int j;
 		cluster = gur_in32(&gur->tp_cluster[i].lower);
 		for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 			if (initiator_type(cluster, j)) {
 				if (count == core)
 					return i;
 				count++;
 			}
 		}
 		i++;
 	} while ((cluster & TP_CLUSTER_EOC) == 0x0);
 	return -1;      /* cannot identify the cluster */
 }
 u32 fsl_qoriq_core_to_type(unsigned int core)
 {
 	struct ccsr_gur __iomem *gur =
 		(void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	int i = 0, count = 0;
 	u32 cluster, type;
 	do {
 		int j;
 		cluster = gur_in32(&gur->tp_cluster[i].lower);
 		for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
 			type = initiator_type(cluster, j);
 			if (type) {
 				if (count == core)
 					return type;
 				count++;
 			}
 		}
 		i++;
 	} while ((cluster & TP_CLUSTER_EOC) == 0x0);
 	return -1;      /* cannot identify the cluster */
 }
 #ifndef CONFIG_FSL_LSCH3
 uint get_svr(void)
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	return gur_in32(&gur->svr);
 }
 #endif
 #ifdef CONFIG_DISPLAY_CPUINFO
 int print_cpuinfo(void)
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	struct sys_info sysinfo;
 	char buf[32];
 	unsigned int i, core;
 	u32 type, rcw, svr = gur_in32(&gur->svr);
 	puts("SoC: ");
 	cpu_name(buf);
 	printf(" %s (0x%x)\n", buf, svr);
 	memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
 	get_sys_info(&sysinfo);
 	puts("Clock Configuration:");
 	for_each_cpu(i, core, cpu_numcores(), cpu_mask()) {
 		if (!(i % 3))
 			puts("\n       ");
 		type = TP_ITYP_VER(fsl_qoriq_core_to_type(core));
 		printf("CPU%d(%s):%-4s MHz  ", core,
 		       type == TY_ITYP_VER_A7 ? "A7 " :
 		       (type == TY_ITYP_VER_A53 ? "A53" :
 		       (type == TY_ITYP_VER_A57 ? "A57" :
 		       (type == TY_ITYP_VER_A72 ? "A72" : "   "))),
 		       strmhz(buf, sysinfo.freq_processor[core]));
 	}
 	/* Display platform clock as Bus frequency. */
 	printf("\n       Bus:      %-4s MHz  ",
 	       strmhz(buf, sysinfo.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV));
 	printf("DDR:      %-4s MT/s", strmhz(buf, sysinfo.freq_ddrbus));
 #ifdef CONFIG_SYS_DPAA_FMAN
 	printf("  FMAN:     %-4s MHz", strmhz(buf, sysinfo.freq_fman[0]));
 #endif
 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
 	if (soc_has_dp_ddr()) {
 		printf("     DP-DDR:   %-4s MT/s",
 		       strmhz(buf, sysinfo.freq_ddrbus2));
 	}
 #endif
 	puts("\n");
 	/*
 	 * Display the RCW, so that no one gets confused as to what RCW
 	 * we're actually using for this boot.
 	 */
 	puts("Reset Configuration Word (RCW):");
 	for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
 		rcw = gur_in32(&gur->rcwsr[i]);
 		if ((i % 4) == 0)
 			printf("\n       %08x:", i * 4);
 		printf(" %08x", rcw);
 	}
 	puts("\n");
 	return 0;
 }
 #endif
 #ifdef CONFIG_FSL_ESDHC
 int cpu_mmc_init(bd_t *bis)
 {
 	return fsl_esdhc_mmc_init(bis);
 }
 #endif
 int cpu_eth_init(bd_t *bis)
 {
 	int error = 0;
 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
 	error = fsl_mc_ldpaa_init(bis);
 #endif
 #ifdef CONFIG_FMAN_ENET
 	fm_standard_init(bis);
 #endif
 	return error;
 }
 static inline int check_psci(void)
 {
 	unsigned int psci_ver;
 	psci_ver = sec_firmware_support_psci_version();
 	if (psci_ver == PSCI_INVALID_VER)
 		return 1;
 	return 0;
 }
 static void config_core_prefetch(void)
 {
 	char *buf = NULL;
 	char buffer[HWCONFIG_BUFFER_SIZE];
 	const char *prefetch_arg = NULL;
 	size_t arglen;
 	unsigned int mask;
 	struct pt_regs regs;
 	if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
 		buf = buffer;
 	prefetch_arg = hwconfig_subarg_f("core_prefetch", "disable",
 					 &arglen, buf);
 	if (prefetch_arg) {
 		mask = simple_strtoul(prefetch_arg, NULL, 0) & 0xff;
 		if (mask & 0x1) {
 			printf("Core0 prefetch can't be disabled\n");
 			return;
 		}
 #define SIP_PREFETCH_DISABLE_64 0xC200FF13
 		regs.regs[0] = SIP_PREFETCH_DISABLE_64;
 		regs.regs[1] = mask;
 		smc_call(&regs);
 		if (regs.regs[0])
 			printf("Prefetch disable config failed for mask ");
 		else
 			printf("Prefetch disable config passed for mask ");
 		printf("0x%x\n", mask);
 	}
 }
 int arch_early_init_r(void)
 {
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009635
 	u32 svr_dev_id;
 	/*
 	 * erratum A009635 is valid only for LS2080A SoC and
 	 * its personalitiesi
 	 */
 	svr_dev_id = get_svr();
 	if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
 		erratum_a009635();
 #endif
 #if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
 	erratum_a009942_check_cpo();
 #endif
 	if (check_psci()) {
 		debug("PSCI: PSCI does not exist.\n");
 		/* if PSCI does not exist, boot secondary cores here */
 		if (fsl_layerscape_wake_seconday_cores())
 			printf("Did not wake secondary cores\n");
 	}
 #ifdef CONFIG_SYS_FSL_HAS_RGMII
 	fsl_rgmii_init();
 #endif
 	config_core_prefetch();
 #ifdef CONFIG_SYS_HAS_SERDES
 	fsl_serdes_init();
 #endif
 #ifdef CONFIG_FMAN_ENET
 	fman_enet_init();
+#endif
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	setup_qbman_portals();
 #endif
 	return 0;
 }
 int timer_init(void)
 {
 	u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
 #ifdef CONFIG_FSL_LSCH3
 	u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
 #endif
 #ifdef CONFIG_ARCH_LS2080A
 	u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
 	u32 svr_dev_id;
 #endif
 #ifdef COUNTER_FREQUENCY_REAL
 	unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
 	/* Update with accurate clock frequency */
 	if (current_el() == 3)
 		asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
 #endif
 #ifdef CONFIG_FSL_LSCH3
 	/* Enable timebase for all clusters.
 	 * It is safe to do so even some clusters are not enabled.
 	 */
 	out_le32(cltbenr, 0xf);
 #endif
 #ifdef CONFIG_ARCH_LS2080A
 	/*
 	 * In certain Layerscape SoCs, the clock for each core's
 	 * has an enable bit in the PMU Physical Core Time Base Enable
 	 * Register (PCTBENR), which allows the watchdog to operate.
 	 */
 	setbits_le32(pctbenr, 0xff);
 	/*
 	 * For LS2080A SoC and its personalities, timer controller
 	 * offset is different
 	 */
 	svr_dev_id = get_svr();
 	if (IS_SVR_DEV(svr_dev_id, SVR_DEV(SVR_LS2080A)))
 		cntcr = (u32 *)SYS_FSL_LS2080A_LS2085A_TIMER_ADDR;
 #endif
 	/* Enable clock for timer
 	 * This is a global setting.
 	 */
 	out_le32(cntcr, 0x1);
 	return 0;
 }
 __efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
 void __efi_runtime reset_cpu(ulong addr)
 {
 	u32 val;
 	/* Raise RESET_REQ_B */
 	val = scfg_in32(rstcr);
 	val |= 0x02;
 	scfg_out32(rstcr, val);
 }
 #ifdef CONFIG_EFI_LOADER
 void __efi_runtime EFIAPI efi_reset_system(
 		       enum efi_reset_type reset_type,
 		       efi_status_t reset_status,
 		       unsigned long data_size, void *reset_data)
 {
 	switch (reset_type) {
 	case EFI_RESET_COLD:
 	case EFI_RESET_WARM:
 		reset_cpu(0);
 		break;
 	case EFI_RESET_SHUTDOWN:
 		/* Nothing we can do */
 		break;
 	}
 	while (1) { }
 }
 void efi_reset_system_init(void)
 {
        efi_add_runtime_mmio(&rstcr, sizeof(*rstcr));
 }
 #endif
 /*
  * Calculate reserved memory with given memory bank
  * Return aligned memory size on success
  * Return (ram_size + needed size) for failure
  */
 phys_size_t board_reserve_ram_top(phys_size_t ram_size)
 {
 	phys_size_t ram_top = ram_size;
 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
 	ram_top = mc_get_dram_block_size();
 	if (ram_top > ram_size)
 		return ram_size + ram_top;
 	ram_top = ram_size - ram_top;
 	/* The start address of MC reserved memory needs to be aligned. */
 	ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1);
 #endif
 	return ram_size - ram_top;
 }
 phys_size_t get_effective_memsize(void)
 {
 	phys_size_t ea_size, rem = 0;
 	/*
 	 * For ARMv8 SoCs, DDR memory is split into two or three regions. The
 	 * first region is 2GB space at 0x8000_0000. Secure memory needs to
 	 * allocated from first region. If the memory extends to  the second
 	 * region (or the third region if applicable), Management Complex (MC)
 	 * memory should be put into the highest region, i.e. the end of DDR
 	 * memory. CONFIG_MAX_MEM_MAPPED is set to the size of first region so
 	 * U-Boot doesn't relocate itself into higher address. Should DDR be
 	 * configured to skip the first region, this function needs to be
 	 * adjusted.
 	 */
 	if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
 		ea_size = CONFIG_MAX_MEM_MAPPED;
 		rem = gd->ram_size - ea_size;
 	} else {
 		ea_size = gd->ram_size;
 	}
 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 	/* Check if we have enough space for secure memory */
 	if (ea_size > CONFIG_SYS_MEM_RESERVE_SECURE)
 		ea_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
 	else
 		printf("Error: No enough space for secure memory.\n");
 #endif
 	/* Check if we have enough memory for MC */
 	if (rem < board_reserve_ram_top(rem)) {
 		/* Not enough memory in high region to reserve */
 		if (ea_size > board_reserve_ram_top(ea_size))
 			ea_size -= board_reserve_ram_top(ea_size);
 		else
 			printf("Error: No enough space for reserved memory.\n");
 	}
 	return ea_size;
 }
 int dram_init_banksize(void)
 {
 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
 	phys_size_t dp_ddr_size;
 #endif
 	/*
 	 * gd->ram_size has the total size of DDR memory, less reserved secure
 	 * memory. The DDR extends from low region to high region(s) presuming
 	 * no hole is created with DDR configuration. gd->arch.secure_ram tracks
 	 * the location of secure memory. gd->arch.resv_ram tracks the location
 	 * of reserved memory for Management Complex (MC). Because gd->ram_size
 	 * is reduced by this function if secure memory is reserved, checking
 	 * gd->arch.secure_ram should be done to avoid running it repeatedly.
 	 */
 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 	if (gd->arch.secure_ram & MEM_RESERVE_SECURE_MAINTAINED) {
 		debug("No need to run again, skip %s\n", __func__);
 		return 0;
 	}
 #endif
 	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
 	if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) {
 		gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE;
 		gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
 		gd->bd->bi_dram[1].size = gd->ram_size -
 					  CONFIG_SYS_DDR_BLOCK1_SIZE;
 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
 		if (gd->bi_dram[1].size > CONFIG_SYS_DDR_BLOCK2_SIZE) {
 			gd->bd->bi_dram[2].start = CONFIG_SYS_DDR_BLOCK3_BASE;
 			gd->bd->bi_dram[2].size = gd->bd->bi_dram[1].size -
 						  CONFIG_SYS_DDR_BLOCK2_SIZE;
 			gd->bd->bi_dram[1].size = CONFIG_SYS_DDR_BLOCK2_SIZE;
 		}
 #endif
 	} else {
 		gd->bd->bi_dram[0].size = gd->ram_size;
 	}
 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 	if (gd->bd->bi_dram[0].size >
 				CONFIG_SYS_MEM_RESERVE_SECURE) {
 		gd->bd->bi_dram[0].size -=
 				CONFIG_SYS_MEM_RESERVE_SECURE;
 		gd->arch.secure_ram = gd->bd->bi_dram[0].start +
 				      gd->bd->bi_dram[0].size;
 		gd->arch.secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
 		gd->ram_size -= CONFIG_SYS_MEM_RESERVE_SECURE;
 	}
 #endif	/* CONFIG_SYS_MEM_RESERVE_SECURE */
 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
 	/* Assign memory for MC */
 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
 	if (gd->bd->bi_dram[2].size >=
 	    board_reserve_ram_top(gd->bd->bi_dram[2].size)) {
 		gd->arch.resv_ram = gd->bd->bi_dram[2].start +
 			    gd->bd->bi_dram[2].size -
 			    board_reserve_ram_top(gd->bd->bi_dram[2].size);
 	} else
 #endif
 	{
 		if (gd->bd->bi_dram[1].size >=
 		    board_reserve_ram_top(gd->bd->bi_dram[1].size)) {
 			gd->arch.resv_ram = gd->bd->bi_dram[1].start +
 				gd->bd->bi_dram[1].size -
 				board_reserve_ram_top(gd->bd->bi_dram[1].size);
 		} else if (gd->bd->bi_dram[0].size >
 			   board_reserve_ram_top(gd->bd->bi_dram[0].size)) {
 			gd->arch.resv_ram = gd->bd->bi_dram[0].start +
 				gd->bd->bi_dram[0].size -
 				board_reserve_ram_top(gd->bd->bi_dram[0].size);
 		}
 	}
 #endif	/* CONFIG_FSL_MC_ENET */
 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
 #error "This SoC shouldn't have DP DDR"
 #endif
 	if (soc_has_dp_ddr()) {
 		/* initialize DP-DDR here */
 		puts("DP-DDR:  ");
 		/*
 		 * DDR controller use 0 as the base address for binding.
 		 * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
 		 */
 		dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
 					  CONFIG_DP_DDR_CTRL,
 					  CONFIG_DP_DDR_NUM_CTRLS,
 					  CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
 					  NULL, NULL, NULL);
 		if (dp_ddr_size) {
 			gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
 			gd->bd->bi_dram[2].size = dp_ddr_size;
 		} else {
 			puts("Not detected");
 		}
 	}
 #endif
 #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
 	debug("%s is called. gd->ram_size is reduced to %lu\n",
 	      __func__, (ulong)gd->ram_size);
 #endif
 	return 0;
 }
 #if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_SPL_BUILD)
 void efi_add_known_memory(void)
 {
 	int i;
 	phys_addr_t ram_start, start;
 	phys_size_t ram_size;
 	u64 pages;
 	/* Add RAM */
 	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 #ifdef CONFIG_SYS_DP_DDR_BASE_PHY
 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
 #error "This SoC shouldn't have DP DDR"
 #endif
 		if (i == 2)
 			continue;	/* skip DP-DDR */
 #endif
 		ram_start = gd->bd->bi_dram[i].start;
 		ram_size = gd->bd->bi_dram[i].size;
 #ifdef CONFIG_RESV_RAM
 		if (gd->arch.resv_ram >= ram_start &&
 		    gd->arch.resv_ram < ram_start + ram_size)
 			ram_size = gd->arch.resv_ram - ram_start;
 #endif
 		start = (ram_start + EFI_PAGE_MASK) & ~EFI_PAGE_MASK;
 		pages = (ram_size + EFI_PAGE_MASK) >> EFI_PAGE_SHIFT;
 		efi_add_memory_map(start, pages, EFI_CONVENTIONAL_MEMORY,
 				   false);
 	}
 }
 #endif
 /*
  * Before DDR size is known, early MMU table have DDR mapped as device memory
  * to avoid speculative access. To relocate U-Boot to DDR, "normal memory"
  * needs to be set for these mappings.
  * If a special case configures DDR with holes in the mapping, the holes need
  * to be marked as invalid. This is not implemented in this function.
  */
 void update_early_mmu_table(void)
 {
 	if (!gd->arch.tlb_addr)
 		return;
 	if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) {
 		mmu_change_region_attr(
 					CONFIG_SYS_SDRAM_BASE,
 					gd->ram_size,
 					PTE_BLOCK_MEMTYPE(MT_NORMAL)	|
 					PTE_BLOCK_OUTER_SHARE		|
 					PTE_BLOCK_NS			|
 					PTE_TYPE_VALID);
 	} else {
 		mmu_change_region_attr(
 					CONFIG_SYS_SDRAM_BASE,
 					CONFIG_SYS_DDR_BLOCK1_SIZE,
 					PTE_BLOCK_MEMTYPE(MT_NORMAL)	|
 					PTE_BLOCK_OUTER_SHARE		|
 					PTE_BLOCK_NS			|
 					PTE_TYPE_VALID);
 #ifdef CONFIG_SYS_DDR_BLOCK3_BASE
 #ifndef CONFIG_SYS_DDR_BLOCK2_SIZE
 #error "Missing CONFIG_SYS_DDR_BLOCK2_SIZE"
 #endif
 		if (gd->ram_size - CONFIG_SYS_DDR_BLOCK1_SIZE >
 		    CONFIG_SYS_DDR_BLOCK2_SIZE) {
 			mmu_change_region_attr(
 					CONFIG_SYS_DDR_BLOCK2_BASE,
 					CONFIG_SYS_DDR_BLOCK2_SIZE,
 					PTE_BLOCK_MEMTYPE(MT_NORMAL)	|
 					PTE_BLOCK_OUTER_SHARE		|
 					PTE_BLOCK_NS			|
 					PTE_TYPE_VALID);
 			mmu_change_region_attr(
 					CONFIG_SYS_DDR_BLOCK3_BASE,
 					gd->ram_size -
 					CONFIG_SYS_DDR_BLOCK1_SIZE -
 					CONFIG_SYS_DDR_BLOCK2_SIZE,
 					PTE_BLOCK_MEMTYPE(MT_NORMAL)	|
 					PTE_BLOCK_OUTER_SHARE		|
 					PTE_BLOCK_NS			|
 					PTE_TYPE_VALID);
 		} else
 #endif
 		{
 			mmu_change_region_attr(
 					CONFIG_SYS_DDR_BLOCK2_BASE,
 					gd->ram_size -
 					CONFIG_SYS_DDR_BLOCK1_SIZE,
 					PTE_BLOCK_MEMTYPE(MT_NORMAL)	|
 					PTE_BLOCK_OUTER_SHARE		|
 					PTE_BLOCK_NS			|
 					PTE_TYPE_VALID);
 		}
 	}
 }
 __weak int dram_init(void)
 {
 	fsl_initdram();
 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
 	/* This will break-before-make MMU for DDR */
 	update_early_mmu_table();
 #endif
 	return 0;
 }

arch/arm/cpu/armv8/fsl-layerscape/fdt.c

Diff comments View file @ 4426232

 /*
  * Copyright 2014-2015 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
 #include <efi_loader.h>
 #include <libfdt.h>
 #include <fdt_support.h>
 #include <phy.h>
 #ifdef CONFIG_FSL_LSCH3
 #include <asm/arch/fdt.h>
 #endif
 #ifdef CONFIG_FSL_ESDHC
 #include <fsl_esdhc.h>
 #endif
 #ifdef CONFIG_SYS_DPAA_FMAN
 #include <fsl_fman.h>
 #endif
 #ifdef CONFIG_MP
 #include <asm/arch/mp.h>
 #endif
 #include <fsl_sec.h>
 #include <asm/arch-fsl-layerscape/soc.h>
 #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
 #include <asm/armv8/sec_firmware.h>
 #endif
+#include <asm/arch/speed.h>
+#include <fsl_qbman.h>
 int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
 {
 	return fdt_setprop_string(blob, offset, "phy-connection-type",
 					 phy_string_for_interface(phyc));
 }
 #ifdef CONFIG_MP
 void ft_fixup_cpu(void *blob)
 {
 	int off;
 	__maybe_unused u64 spin_tbl_addr = (u64)get_spin_tbl_addr();
 	fdt32_t *reg;
 	int addr_cells;
 	u64 val, core_id;
 	size_t *boot_code_size = &(__secondary_boot_code_size);
 	u32 mask = cpu_pos_mask();
 	int off_prev = -1;
 	off = fdt_path_offset(blob, "/cpus");
 	if (off < 0) {
 		puts("couldn't find /cpus node\n");
 		return;
 	}
 	fdt_support_default_count_cells(blob, off, &addr_cells, NULL);
 	off = fdt_node_offset_by_prop_value(blob, off_prev, "device_type",
 					    "cpu", 4);
 	while (off != -FDT_ERR_NOTFOUND) {
 		reg = (fdt32_t *)fdt_getprop(blob, off, "reg", 0);
 		if (reg) {
 			core_id = fdt_read_number(reg, addr_cells);
 			if (!test_bit(id_to_core(core_id), &mask)) {
 				fdt_del_node(blob, off);
 				off = off_prev;
 			}
 		}
 		off_prev = off;
 		off = fdt_node_offset_by_prop_value(blob, off_prev,
 						    "device_type", "cpu", 4);
 	}
 #if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \
 	defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI)
 	int node;
 	u32 psci_ver;
 	/* Check the psci version to determine if the psci is supported */
 	psci_ver = sec_firmware_support_psci_version();
 	if (psci_ver == 0xffffffff) {
 		/* remove psci DT node */
 		node = fdt_path_offset(blob, "/psci");
 		if (node >= 0)
 			goto remove_psci_node;
 		node = fdt_node_offset_by_compatible(blob, -1, "arm,psci");
 		if (node >= 0)
 			goto remove_psci_node;
 		node = fdt_node_offset_by_compatible(blob, -1, "arm,psci-0.2");
 		if (node >= 0)
 			goto remove_psci_node;
 		node = fdt_node_offset_by_compatible(blob, -1, "arm,psci-1.0");
 		if (node >= 0)
 			goto remove_psci_node;
 remove_psci_node:
 		if (node >= 0)
 			fdt_del_node(blob, node);
 	} else {
 		return;
 	}
 #endif
 	off = fdt_path_offset(blob, "/cpus");
 	if (off < 0) {
 		puts("couldn't find /cpus node\n");
 		return;
 	}
 	fdt_support_default_count_cells(blob, off, &addr_cells, NULL);
 	off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 	while (off != -FDT_ERR_NOTFOUND) {
 		reg = (fdt32_t *)fdt_getprop(blob, off, "reg", 0);
 		if (reg) {
 			core_id = fdt_read_number(reg, addr_cells);
 			if (core_id  == 0 || (is_core_online(core_id))) {
 				val = spin_tbl_addr;
 				val += id_to_core(core_id) *
 				       SPIN_TABLE_ELEM_SIZE;
 				val = cpu_to_fdt64(val);
 				fdt_setprop_string(blob, off, "enable-method",
 						   "spin-table");
 				fdt_setprop(blob, off, "cpu-release-addr",
 					    &val, sizeof(val));
 			} else {
 				debug("skipping offline core\n");
 			}
 		} else {
 			puts("Warning: found cpu node without reg property\n");
 		}
 		off = fdt_node_offset_by_prop_value(blob, off, "device_type",
 						    "cpu", 4);
 	}
 	fdt_add_mem_rsv(blob, (uintptr_t)&secondary_boot_code,
 			*boot_code_size);
 #if defined(CONFIG_EFI_LOADER) && !defined(CONFIG_SPL_BUILD)
 	efi_add_memory_map((uintptr_t)&secondary_boot_code,
 			   ALIGN(*boot_code_size, EFI_PAGE_SIZE) >> EFI_PAGE_SHIFT,
 			   EFI_RESERVED_MEMORY_TYPE, false);
 #endif
 }
 #endif
 void fsl_fdt_disable_usb(void *blob)
 {
 	int off;
 	/*
 	 * SYSCLK is used as a reference clock for USB. When the USB
 	 * controller is used, SYSCLK must meet the additional requirement
 	 * of 100 MHz.
 	 */
 	if (CONFIG_SYS_CLK_FREQ != 100000000) {
 		off = fdt_node_offset_by_compatible(blob, -1, "snps,dwc3");
 		while (off != -FDT_ERR_NOTFOUND) {
 			fdt_status_disabled(blob, off);
 			off = fdt_node_offset_by_compatible(blob, off,
 							    "snps,dwc3");
 		}
 	}
 }
 #ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
 static void fdt_fixup_gic(void *blob)
 {
 	int offset, err;
 	u64 reg[8];
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	unsigned int val;
 	struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
 	int align_64k = 0;
 	val = gur_in32(&gur->svr);
 	if (!IS_SVR_DEV(val, SVR_DEV(SVR_LS1043A))) {
 		align_64k = 1;
 	} else if (SVR_REV(val) != REV1_0) {
 		val = scfg_in32(&scfg->gic_align) & (0x01 << GIC_ADDR_BIT);
 		if (!val)
 			align_64k = 1;
 	}
 	offset = fdt_subnode_offset(blob, 0, "interrupt-controller@1400000");
 	if (offset < 0) {
 		printf("WARNING: fdt_subnode_offset can't find node %s: %s\n",
 		       "interrupt-controller@1400000", fdt_strerror(offset));
 		return;
 	}
 	/* Fixup gic node align with 64K */
 	if (align_64k) {
 		reg[0] = cpu_to_fdt64(GICD_BASE_64K);
 		reg[1] = cpu_to_fdt64(GICD_SIZE_64K);
 		reg[2] = cpu_to_fdt64(GICC_BASE_64K);
 		reg[3] = cpu_to_fdt64(GICC_SIZE_64K);
 		reg[4] = cpu_to_fdt64(GICH_BASE_64K);
 		reg[5] = cpu_to_fdt64(GICH_SIZE_64K);
 		reg[6] = cpu_to_fdt64(GICV_BASE_64K);
 		reg[7] = cpu_to_fdt64(GICV_SIZE_64K);
 	} else {
 	/* Fixup gic node align with default */
 		reg[0] = cpu_to_fdt64(GICD_BASE);
 		reg[1] = cpu_to_fdt64(GICD_SIZE);
 		reg[2] = cpu_to_fdt64(GICC_BASE);
 		reg[3] = cpu_to_fdt64(GICC_SIZE);
 		reg[4] = cpu_to_fdt64(GICH_BASE);
 		reg[5] = cpu_to_fdt64(GICH_SIZE);
 		reg[6] = cpu_to_fdt64(GICV_BASE);
 		reg[7] = cpu_to_fdt64(GICV_SIZE);
 	}
 	err = fdt_setprop(blob, offset, "reg", reg, sizeof(reg));
 	if (err < 0) {
 		printf("WARNING: fdt_setprop can't set %s from node %s: %s\n",
 		       "reg", "interrupt-controller@1400000",
 		       fdt_strerror(err));
 		return;
 	}
 	return;
 }
 #endif
 #ifdef CONFIG_HAS_FEATURE_ENHANCED_MSI
 static int _fdt_fixup_msi_node(void *blob, const char *name,
 				  int irq_0, int irq_1, int rev)
 {
 	int err, offset, len;
 	u32 tmp[4][3];
 	void *p;
 	offset = fdt_path_offset(blob, name);
 	if (offset < 0) {
 		printf("WARNING: fdt_path_offset can't find path %s: %s\n",
 		       name, fdt_strerror(offset));
 		return 0;
 	}
 	/*fixup the property of interrupts*/
 	tmp[0][0] = cpu_to_fdt32(0x0);
 	tmp[0][1] = cpu_to_fdt32(irq_0);
 	tmp[0][2] = cpu_to_fdt32(0x4);
 	if (rev > REV1_0) {
 		tmp[1][0] = cpu_to_fdt32(0x0);
 		tmp[1][1] = cpu_to_fdt32(irq_1);
 		tmp[1][2] = cpu_to_fdt32(0x4);
 		tmp[2][0] = cpu_to_fdt32(0x0);
 		tmp[2][1] = cpu_to_fdt32(irq_1 + 1);
 		tmp[2][2] = cpu_to_fdt32(0x4);
 		tmp[3][0] = cpu_to_fdt32(0x0);
 		tmp[3][1] = cpu_to_fdt32(irq_1 + 2);
 		tmp[3][2] = cpu_to_fdt32(0x4);
 		len = sizeof(tmp);
 	} else {
 		len = sizeof(tmp[0]);
 	}
 	err = fdt_setprop(blob, offset, "interrupts", tmp, len);
 	if (err < 0) {
 		printf("WARNING: fdt_setprop can't set %s from node %s: %s\n",
 		       "interrupts", name, fdt_strerror(err));
 		return 0;
 	}
 	/*fixup the property of reg*/
 	p = (char *)fdt_getprop(blob, offset, "reg", &len);
 	if (!p) {
 		printf("WARNING: fdt_getprop can't get %s from node %s\n",
 		       "reg", name);
 		return 0;
 	}
 	memcpy((char *)tmp, p, len);
 	if (rev > REV1_0)
 		*((u32 *)tmp + 3) = cpu_to_fdt32(0x1000);
 	else
 		*((u32 *)tmp + 3) = cpu_to_fdt32(0x8);
 	err = fdt_setprop(blob, offset, "reg", tmp, len);
 	if (err < 0) {
 		printf("WARNING: fdt_setprop can't set %s from node %s: %s\n",
 		       "reg", name, fdt_strerror(err));
 		return 0;
 	}
 	/*fixup the property of compatible*/
 	if (rev > REV1_0)
 		err = fdt_setprop_string(blob, offset, "compatible",
 					 "fsl,ls1043a-v1.1-msi");
 	else
 		err = fdt_setprop_string(blob, offset, "compatible",
 					 "fsl,ls1043a-msi");
 	if (err < 0) {
 		printf("WARNING: fdt_setprop can't set %s from node %s: %s\n",
 		       "compatible", name, fdt_strerror(err));
 		return 0;
 	}
 	return 1;
 }
 static int _fdt_fixup_pci_msi(void *blob, const char *name, int rev)
 {
 	int offset, len, err;
 	void *p;
 	int val;
 	u32 tmp[4][8];
 	offset = fdt_path_offset(blob, name);
 	if (offset < 0) {
 		printf("WARNING: fdt_path_offset can't find path %s: %s\n",
 		       name, fdt_strerror(offset));
 		return 0;
 	}
 	p = (char *)fdt_getprop(blob, offset, "interrupt-map", &len);
 	if (!p || len != sizeof(tmp)) {
 		printf("WARNING: fdt_getprop can't get %s from node %s\n",
 		       "interrupt-map", name);
 		return 0;
 	}
 	memcpy((char *)tmp, p, len);
 	val = fdt32_to_cpu(tmp[0][6]);
 	if (rev > REV1_0) {
 		tmp[1][6] = cpu_to_fdt32(val + 1);
 		tmp[2][6] = cpu_to_fdt32(val + 2);
 		tmp[3][6] = cpu_to_fdt32(val + 3);
 	} else {
 		tmp[1][6] = cpu_to_fdt32(val);
 		tmp[2][6] = cpu_to_fdt32(val);
 		tmp[3][6] = cpu_to_fdt32(val);
 	}
 	err = fdt_setprop(blob, offset, "interrupt-map", tmp, sizeof(tmp));
 	if (err < 0) {
 		printf("WARNING: fdt_setprop can't set %s from node %s: %s.\n",
 		       "interrupt-map", name, fdt_strerror(err));
 		return 0;
 	}
 	return 1;
 }
 /* Fixup msi node for ls1043a rev1.1*/
 static void fdt_fixup_msi(void *blob)
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	unsigned int rev;
 	rev = gur_in32(&gur->svr);
 	if (!IS_SVR_DEV(rev, SVR_DEV(SVR_LS1043A)))
 		return;
 	rev = SVR_REV(rev);
 	_fdt_fixup_msi_node(blob, "/soc/msi-controller1@1571000",
 			    116, 111, rev);
 	_fdt_fixup_msi_node(blob, "/soc/msi-controller2@1572000",
 			    126, 121, rev);
 	_fdt_fixup_msi_node(blob, "/soc/msi-controller3@1573000",
 			    160, 155, rev);
 	_fdt_fixup_pci_msi(blob, "/soc/pcie@3400000", rev);
 	_fdt_fixup_pci_msi(blob, "/soc/pcie@3500000", rev);
 	_fdt_fixup_pci_msi(blob, "/soc/pcie@3600000", rev);
 }
 #endif
 #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
 /* Remove JR node used by SEC firmware */
 void fdt_fixup_remove_jr(void *blob)
 {
 	int jr_node, addr_cells, len;
 	int crypto_node = fdt_path_offset(blob, "crypto");
 	u64 jr_offset, used_jr;
 	fdt32_t *reg;
 	used_jr = sec_firmware_used_jobring_offset();
 	fdt_support_default_count_cells(blob, crypto_node, &addr_cells, NULL);
 	jr_node = fdt_node_offset_by_compatible(blob, crypto_node,
 						"fsl,sec-v4.0-job-ring");
 	while (jr_node != -FDT_ERR_NOTFOUND) {
 		reg = (fdt32_t *)fdt_getprop(blob, jr_node, "reg", &len);
 		jr_offset = fdt_read_number(reg, addr_cells);
 		if (jr_offset == used_jr) {
 			fdt_del_node(blob, jr_node);
 			break;
 		}
 		jr_node = fdt_node_offset_by_compatible(blob, jr_node,
 							"fsl,sec-v4.0-job-ring");
 	}
 }
 #endif
 void ft_cpu_setup(void *blob, bd_t *bd)
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 	unsigned int svr = gur_in32(&gur->svr);
 	/* delete crypto node if not on an E-processor */
 	if (!IS_E_PROCESSOR(svr))
 		fdt_fixup_crypto_node(blob, 0);
 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
 	else {
 		ccsr_sec_t __iomem *sec;
 #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
 		if (fdt_fixup_kaslr(blob))
 			fdt_fixup_remove_jr(blob);
 #endif
 		sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
 		fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
 	}
 #endif
 #ifdef CONFIG_MP
 	ft_fixup_cpu(blob);
 #endif
 #ifdef CONFIG_SYS_NS16550
 	do_fixup_by_compat_u32(blob, "fsl,ns16550",
 			       "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
 #endif
 	do_fixup_by_path_u32(blob, "/sysclk", "clock-frequency",
 			     CONFIG_SYS_CLK_FREQ, 1);
 #ifdef CONFIG_PCI
 	ft_pci_setup(blob, bd);
 #endif
 #ifdef CONFIG_FSL_ESDHC
 	fdt_fixup_esdhc(blob, bd);
+#endif
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	fdt_fixup_bportals(blob);
+	fdt_fixup_qportals(blob);
+	do_fixup_by_compat_u32(blob, "fsl,qman",
+			       "clock-frequency", get_qman_freq(), 1);
 #endif
 #ifdef CONFIG_SYS_DPAA_FMAN
 	fdt_fixup_fman_firmware(blob);
 #endif
 #ifndef CONFIG_ARCH_LS1012A
 	fsl_fdt_disable_usb(blob);
 #endif
 #ifdef CONFIG_HAS_FEATURE_GIC64K_ALIGN
 	fdt_fixup_gic(blob);
 #endif
 #ifdef CONFIG_HAS_FEATURE_ENHANCED_MSI
 	fdt_fixup_msi(blob);
 #endif
 }

arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c

Diff comments View file @ 4426232

 /*
  * Copyright 2015 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
 #include <linux/compiler.h>
 #include <asm/io.h>
 #include <asm/processor.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/soc.h>
 #include <fsl_ifc.h>
 #include "cpu.h"
 DECLARE_GLOBAL_DATA_PTR;
 #ifndef CONFIG_SYS_FSL_NUM_CC_PLLS
 #define CONFIG_SYS_FSL_NUM_CC_PLLS      2
 #endif
 void get_sys_info(struct sys_info *sys_info)
 {
 	struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 #if (defined(CONFIG_FSL_ESDHC) &&\
 	defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)) ||\
 	defined(CONFIG_SYS_DPAA_FMAN)
 	u32 rcw_tmp;
 #endif
 	struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
 	unsigned int cpu;
 	const u8 core_cplx_pll[8] = {
 		[0] = 0,	/* CC1 PPL / 1 */
 		[1] = 0,	/* CC1 PPL / 2 */
 		[4] = 1,	/* CC2 PPL / 1 */
 		[5] = 1,	/* CC2 PPL / 2 */
 	};
 	const u8 core_cplx_pll_div[8] = {
 		[0] = 1,	/* CC1 PPL / 1 */
 		[1] = 2,	/* CC1 PPL / 2 */
 		[4] = 1,	/* CC2 PPL / 1 */
 		[5] = 2,	/* CC2 PPL / 2 */
 	};
 	uint i, cluster;
 	uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
 	uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
 	unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
 	unsigned long cluster_clk;
 	sys_info->freq_systembus = sysclk;
 #ifndef CONFIG_CLUSTER_CLK_FREQ
 #define CONFIG_CLUSTER_CLK_FREQ	CONFIG_SYS_CLK_FREQ
 #endif
 	cluster_clk = CONFIG_CLUSTER_CLK_FREQ;
 #ifdef CONFIG_DDR_CLK_FREQ
 	sys_info->freq_ddrbus = CONFIG_DDR_CLK_FREQ;
 #else
 	sys_info->freq_ddrbus = sysclk;
 #endif
 	/* The freq_systembus is used to record frequency of platform PLL */
 	sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
 			FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
 			FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
 #ifdef CONFIG_ARCH_LS1012A
 	sys_info->freq_ddrbus = 2 * sys_info->freq_systembus;
 #else
 	sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
 			FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT) &
 			FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
 #endif
 	for (i = 0; i < CONFIG_SYS_FSL_NUM_CC_PLLS; i++) {
 		ratio[i] = (in_be32(&clk->pllcgsr[i].pllcngsr) >> 1) & 0xff;
 		if (ratio[i] > 4)
 			freq_c_pll[i] = cluster_clk * ratio[i];
 		else
 			freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
 	}
 	for_each_cpu(i, cpu, cpu_numcores(), cpu_mask()) {
 		cluster = fsl_qoriq_core_to_cluster(cpu);
 		u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
 				& 0xf;
 		u32 cplx_pll = core_cplx_pll[c_pll_sel];
 		sys_info->freq_processor[cpu] =
 			freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
 	}
 #define HWA_CGA_M1_CLK_SEL	0xe0000000
 #define HWA_CGA_M1_CLK_SHIFT	29
 #ifdef CONFIG_SYS_DPAA_FMAN
 	rcw_tmp = in_be32(&gur->rcwsr[7]);
 	switch ((rcw_tmp & HWA_CGA_M1_CLK_SEL) >> HWA_CGA_M1_CLK_SHIFT) {
 	case 2:
 		sys_info->freq_fman[0] = freq_c_pll[0] / 2;
 		break;
 	case 3:
 		sys_info->freq_fman[0] = freq_c_pll[0] / 3;
 		break;
 	case 4:
 		sys_info->freq_fman[0] = freq_c_pll[0] / 4;
 		break;
 	case 5:
 		sys_info->freq_fman[0] = sys_info->freq_systembus;
 		break;
 	case 6:
 		sys_info->freq_fman[0] = freq_c_pll[1] / 2;
 		break;
 	case 7:
 		sys_info->freq_fman[0] = freq_c_pll[1] / 3;
 		break;
 	default:
 		printf("Error: Unknown FMan1 clock select!\n");
 		break;
 	}
 #endif
 #define HWA_CGA_M2_CLK_SEL	0x00000007
 #define HWA_CGA_M2_CLK_SHIFT	0
 #ifdef CONFIG_FSL_ESDHC
 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
 	rcw_tmp = in_be32(&gur->rcwsr[15]);
 	switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) {
 	case 1:
 		sys_info->freq_sdhc = freq_c_pll[1];
 		break;
 	case 2:
 		sys_info->freq_sdhc = freq_c_pll[1] / 2;
 		break;
 	case 3:
 		sys_info->freq_sdhc = freq_c_pll[1] / 3;
 		break;
 	case 6:
 		sys_info->freq_sdhc = freq_c_pll[0] / 2;
 		break;
 	default:
 		printf("Error: Unknown ESDHC clock select!\n");
 		break;
 	}
 #else
 	sys_info->freq_sdhc = (sys_info->freq_systembus /
 				CONFIG_SYS_FSL_PCLK_DIV) /
 				CONFIG_SYS_FSL_SDHC_CLK_DIV;
 #endif
 #endif
 #if defined(CONFIG_FSL_IFC)
 	sys_info->freq_localbus = sys_info->freq_systembus /
 						CONFIG_SYS_FSL_IFC_CLK_DIV;
 #endif
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	sys_info->freq_qman = sys_info->freq_systembus;
+#endif
 }
+#ifdef CONFIG_SYS_DPAA_QBMAN
+unsigned long get_qman_freq(void)
+{
+	struct sys_info sys_info;
+	get_sys_info(&sys_info);
+	return sys_info.freq_qman;
+}
+#endif
 int get_clocks(void)
 {
 	struct sys_info sys_info;
 	get_sys_info(&sys_info);
 	gd->cpu_clk = sys_info.freq_processor[0];
 	gd->bus_clk = sys_info.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV;
 	gd->mem_clk = sys_info.freq_ddrbus;
 #ifdef CONFIG_FSL_ESDHC
 	gd->arch.sdhc_clk = sys_info.freq_sdhc;
 #endif
 	if (gd->cpu_clk != 0)
 		return 0;
 	else
 		return 1;
 }
 /********************************************
  * get_bus_freq
  * return platform clock in Hz
  *********************************************/
 ulong get_bus_freq(ulong dummy)
 {
 	if (!gd->bus_clk)
 		get_clocks();
 	return gd->bus_clk;
 }
 ulong get_ddr_freq(ulong dummy)
 {
 	if (!gd->mem_clk)
 		get_clocks();
 	return gd->mem_clk;
 }
 #ifdef CONFIG_FSL_ESDHC
 int get_sdhc_freq(ulong dummy)
 {
 	if (!gd->arch.sdhc_clk)
 		get_clocks();
 	return gd->arch.sdhc_clk;
 }
 #endif
 int get_serial_clock(void)
 {
 	return get_bus_freq(0) / CONFIG_SYS_FSL_DUART_CLK_DIV;
 }
 int get_i2c_freq(ulong dummy)
 {
 	return get_bus_freq(0) / CONFIG_SYS_FSL_I2C_CLK_DIV;
 }
 int get_dspi_freq(ulong dummy)
 {
 	return get_bus_freq(0) / CONFIG_SYS_FSL_DSPI_CLK_DIV;
 }
 #ifdef CONFIG_FSL_LPUART
 int get_uart_freq(ulong dummy)
 {
 	return get_bus_freq(0) / CONFIG_SYS_FSL_LPUART_CLK_DIV;
 }
 #endif
 unsigned int mxc_get_clock(enum mxc_clock clk)
 {
 	switch (clk) {
 	case MXC_I2C_CLK:
 		return get_i2c_freq(0);
 #if defined(CONFIG_FSL_ESDHC)
 	case MXC_ESDHC_CLK:
 		return get_sdhc_freq(0);
 #endif
 	case MXC_DSPI_CLK:
 		return get_dspi_freq(0);
 #ifdef CONFIG_FSL_LPUART
 	case MXC_UART_CLK:
 		return get_uart_freq(0);
 #endif
 	default:
 		printf("Unsupported clock\n");
 	}
 	return 0;
 }

arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h

Diff comments View file @ 4426232

 /*
  * Copyright 2013-2015 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef __ARCH_FSL_LSCH2_IMMAP_H__
 #define __ARCH_FSL_LSCH2_IMMAP_H__
 #include <fsl_immap.h>
 #define CONFIG_SYS_IMMR				0x01000000
 #define CONFIG_SYS_DCSRBAR			0x20000000
 #define CONFIG_SYS_DCSR_DCFG_ADDR	(CONFIG_SYS_DCSRBAR + 0x00140000)
 #define CONFIG_SYS_DCSR_COP_CCP_ADDR	(CONFIG_SYS_DCSRBAR + 0x02008040)
 #define CONFIG_SYS_FSL_DDR_ADDR			(CONFIG_SYS_IMMR + 0x00080000)
 #define CONFIG_SYS_GIC400_ADDR			(CONFIG_SYS_IMMR + 0x00400000)
 #define CONFIG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR + 0x00530000)
 #define SYS_FSL_QSPI_ADDR			(CONFIG_SYS_IMMR + 0x00550000)
 #define CONFIG_SYS_FSL_ESDHC_ADDR		(CONFIG_SYS_IMMR + 0x00560000)
 #define CONFIG_SYS_FSL_CSU_ADDR			(CONFIG_SYS_IMMR + 0x00510000)
 #define CONFIG_SYS_FSL_GUTS_ADDR		(CONFIG_SYS_IMMR + 0x00ee0000)
 #define CONFIG_SYS_FSL_RST_ADDR			(CONFIG_SYS_IMMR + 0x00ee00b0)
 #define CONFIG_SYS_FSL_SCFG_ADDR		(CONFIG_SYS_IMMR + 0x00570000)
+#define CONFIG_SYS_FSL_BMAN_ADDR		(CONFIG_SYS_IMMR + 0x00890000)
+#define CONFIG_SYS_FSL_QMAN_ADDR		(CONFIG_SYS_IMMR + 0x00880000)
 #define CONFIG_SYS_FSL_FMAN_ADDR		(CONFIG_SYS_IMMR + 0x00a00000)
 #define CONFIG_SYS_FSL_SERDES_ADDR		(CONFIG_SYS_IMMR + 0x00ea0000)
 #define CONFIG_SYS_FSL_DCFG_ADDR		(CONFIG_SYS_IMMR + 0x00ee0000)
 #define CONFIG_SYS_FSL_CLK_ADDR			(CONFIG_SYS_IMMR + 0x00ee1000)
 #define CONFIG_SYS_NS16550_COM1			(CONFIG_SYS_IMMR + 0x011c0500)
 #define CONFIG_SYS_NS16550_COM2			(CONFIG_SYS_IMMR + 0x011c0600)
 #define CONFIG_SYS_NS16550_COM3			(CONFIG_SYS_IMMR + 0x011d0500)
 #define CONFIG_SYS_NS16550_COM4			(CONFIG_SYS_IMMR + 0x011d0600)
 #define CONFIG_SYS_XHCI_USB1_ADDR		(CONFIG_SYS_IMMR + 0x01f00000)
 #define CONFIG_SYS_XHCI_USB2_ADDR		(CONFIG_SYS_IMMR + 0x02000000)
 #define CONFIG_SYS_XHCI_USB3_ADDR		(CONFIG_SYS_IMMR + 0x02100000)
 #define CONFIG_SYS_EHCI_USB1_ADDR		(CONFIG_SYS_IMMR + 0x07600000)
 #define CONFIG_SYS_PCIE1_ADDR			(CONFIG_SYS_IMMR + 0x2400000)
 #define CONFIG_SYS_PCIE2_ADDR			(CONFIG_SYS_IMMR + 0x2500000)
 #define CONFIG_SYS_PCIE3_ADDR			(CONFIG_SYS_IMMR + 0x2600000)
 #define CONFIG_SYS_SEC_MON_ADDR			(CONFIG_SYS_IMMR + 0xe90000)
 #define CONFIG_SYS_SFP_ADDR			(CONFIG_SYS_IMMR + 0xe80200)
+#define CONFIG_SYS_BMAN_NUM_PORTALS	10
+#define CONFIG_SYS_BMAN_MEM_BASE	0x508000000
+#define CONFIG_SYS_BMAN_MEM_PHYS	(0xf00000000ull + \
+						CONFIG_SYS_BMAN_MEM_BASE)
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x08000000
+#define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x10000
+#define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x10000
+#define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
+#define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
+					CONFIG_SYS_BMAN_CENA_SIZE)
+#define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_BMAN_SWP_ISDR_REG    0x3E80
+#define CONFIG_SYS_QMAN_NUM_PORTALS	10
+#define CONFIG_SYS_QMAN_MEM_BASE	0x500000000
+#define CONFIG_SYS_QMAN_MEM_PHYS	(0xf00000000ull + \
+						CONFIG_SYS_QMAN_MEM_BASE)
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x08000000
+#define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x10000
+#define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x10000
+#define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
+#define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
+					CONFIG_SYS_QMAN_CENA_SIZE)
+#define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
+#define CONFIG_SYS_QMAN_SWP_ISDR_REG	0x3680
 #define CONFIG_SYS_FSL_TIMER_ADDR		0x02b00000
 #define I2C1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01180000)
 #define I2C2_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01190000)
 #define I2C3_BASE_ADDR				(CONFIG_SYS_IMMR + 0x011a0000)
 #define I2C4_BASE_ADDR				(CONFIG_SYS_IMMR + 0x011b0000)
 #define WDOG1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01ad0000)
 #define QSPI0_BASE_ADDR				(CONFIG_SYS_IMMR + 0x00550000)
 #define DSPI1_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01100000)
 #define LPUART_BASE				(CONFIG_SYS_IMMR + 0x01950000)
 #define AHCI_BASE_ADDR				(CONFIG_SYS_IMMR + 0x02200000)
 #define CONFIG_SYS_PCIE1_PHYS_ADDR		0x4000000000ULL
 #define CONFIG_SYS_PCIE2_PHYS_ADDR		0x4800000000ULL
 #define CONFIG_SYS_PCIE3_PHYS_ADDR		0x5000000000ULL
 /* LUT registers */
 #ifdef CONFIG_ARCH_LS1012A
 #define PCIE_LUT_BASE				0xC0000
 #else
 #define PCIE_LUT_BASE				0x10000
 #endif
 #define PCIE_LUT_LCTRL0				0x7F8
 #define PCIE_LUT_DBG				0x7FC
 /* TZ Address Space Controller Definitions */
 #define TZASC1_BASE			0x01100000	/* as per CCSR map. */
 #define TZASC2_BASE			0x01110000	/* as per CCSR map. */
 #define TZASC3_BASE			0x01120000	/* as per CCSR map. */
 #define TZASC4_BASE			0x01130000	/* as per CCSR map. */
 #define TZASC_BUILD_CONFIG_REG(x)	((TZASC1_BASE + (x * 0x10000)))
 #define TZASC_ACTION_REG(x)		((TZASC1_BASE + (x * 0x10000)) + 0x004)
 #define TZASC_GATE_KEEPER(x)		((TZASC1_BASE + (x * 0x10000)) + 0x008)
 #define TZASC_REGION_BASE_LOW_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x100)
 #define TZASC_REGION_BASE_HIGH_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x104)
 #define TZASC_REGION_TOP_LOW_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x108)
 #define TZASC_REGION_TOP_HIGH_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x10C)
 #define TZASC_REGION_ATTRIBUTES_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x110)
 #define TZASC_REGION_ID_ACCESS_0(x)	((TZASC1_BASE + (x * 0x10000)) + 0x114)
 #define TP_ITYP_AV              0x00000001      /* Initiator available */
 #define TP_ITYP_TYPE(x) (((x) & 0x6) >> 1)      /* Initiator Type */
 #define TP_ITYP_TYPE_ARM        0x0
 #define TP_ITYP_TYPE_PPC        0x1             /* PowerPC */
 #define TP_ITYP_TYPE_OTHER      0x2             /* StarCore DSP */
 #define TP_ITYP_TYPE_HA         0x3             /* HW Accelerator */
 #define TP_ITYP_THDS(x) (((x) & 0x18) >> 3)     /* # threads */
 #define TP_ITYP_VER(x)  (((x) & 0xe0) >> 5)     /* Initiator Version */
 #define TY_ITYP_VER_A7          0x1
 #define TY_ITYP_VER_A53         0x2
 #define TY_ITYP_VER_A57         0x3
 #define TY_ITYP_VER_A72		0x4
 #define TP_CLUSTER_EOC		0xc0000000      /* end of clusters */
 #define TP_CLUSTER_INIT_MASK    0x0000003f      /* initiator mask */
 #define TP_INIT_PER_CLUSTER     4
 /*
  * Define default values for some CCSR macros to make header files cleaner*
  *
  * To completely disable CCSR relocation in a board header file, define
  * CONFIG_SYS_CCSR_DO_NOT_RELOCATE.  This will force CONFIG_SYS_CCSRBAR_PHYS
  * to a value that is the same as CONFIG_SYS_CCSRBAR.
  */
 #ifdef CONFIG_SYS_CCSRBAR_PHYS
 #error "Do not define CONFIG_SYS_CCSRBAR_PHYS directly.  Use \
 CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead."
 #endif
 #ifdef CONFIG_SYS_CCSR_DO_NOT_RELOCATE
 #undef CONFIG_SYS_CCSRBAR_PHYS_HIGH
 #undef CONFIG_SYS_CCSRBAR_PHYS_LOW
 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0
 #endif
 #ifndef CONFIG_SYS_CCSRBAR
 #define CONFIG_SYS_CCSRBAR		0x01000000
 #endif
 #ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH	0
 #endif
 #ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
 #define CONFIG_SYS_CCSRBAR_PHYS_LOW	0x01000000
 #endif
 #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
 				 CONFIG_SYS_CCSRBAR_PHYS_LOW)
 struct sys_info {
 	unsigned long freq_processor[CONFIG_MAX_CPUS];
 	/* frequency of platform PLL */
 	unsigned long freq_systembus;
 	unsigned long freq_ddrbus;
 	unsigned long freq_localbus;
 	unsigned long freq_sdhc;
 #ifdef CONFIG_SYS_DPAA_FMAN
 	unsigned long freq_fman[CONFIG_SYS_NUM_FMAN];
 #endif
 	unsigned long freq_qman;
 };
 #define CONFIG_SYS_FSL_FM1_OFFSET		0xa00000
 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET	0xa88000
 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET	0xa89000
 #define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET	0xa8a000
 #define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET	0xa8b000
 #define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET	0xa8c000
 #define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET	0xa8d000
 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET	0xae0000
 #define CONFIG_SYS_FSL_FM1_ADDR			\
 		(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
 #define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR		\
 		(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
 #define CONFIG_SYS_FSL_SEC_OFFSET		0x700000ull
 #define CONFIG_SYS_FSL_JR0_OFFSET		0x710000ull
 #define CONFIG_SYS_FSL_SEC_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
 #define CONFIG_SYS_FSL_JR0_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
 /* Device Configuration and Pin Control */
 #define DCFG_DCSR_PORCR1		0x0
 struct ccsr_gur {
 	u32     porsr1;         /* POR status 1 */
 #define FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK	0xFF800000
 	u32     porsr2;         /* POR status 2 */
 	u8      res_008[0x20-0x8];
 	u32     gpporcr1;       /* General-purpose POR configuration */
 	u32	gpporcr2;
 #define FSL_CHASSIS2_DCFG_FUSESR_VID_SHIFT	25
 #define FSL_CHASSIS2_DCFG_FUSESR_VID_MASK	0x1F
 #define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_SHIFT	20
 #define FSL_CHASSIS2_DCFG_FUSESR_ALTVID_MASK	0x1F
 	u32     dcfg_fusesr;    /* Fuse status register */
 	u8      res_02c[0x70-0x2c];
 	u32     devdisr;        /* Device disable control */
 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_1	0x80000000
 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_2	0x40000000
 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_3	0x20000000
 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_4	0x10000000
 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_5	0x08000000
 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_6	0x04000000
 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_9	0x00800000
 #define FSL_CHASSIS2_DEVDISR2_DTSEC1_10	0x00400000
 #define FSL_CHASSIS2_DEVDISR2_10GEC1_1	0x00800000
 #define FSL_CHASSIS2_DEVDISR2_10GEC1_2	0x00400000
 #define FSL_CHASSIS2_DEVDISR2_10GEC1_3	0x80000000
 #define FSL_CHASSIS2_DEVDISR2_10GEC1_4	0x40000000
 	u32     devdisr2;       /* Device disable control 2 */
 	u32     devdisr3;       /* Device disable control 3 */
 	u32     devdisr4;       /* Device disable control 4 */
 	u32     devdisr5;       /* Device disable control 5 */
 	u32     devdisr6;       /* Device disable control 6 */
 	u32     devdisr7;       /* Device disable control 7 */
 	u8      res_08c[0x94-0x8c];
 	u32     coredisru;      /* uppper portion for support of 64 cores */
 	u32     coredisrl;      /* lower portion for support of 64 cores */
 	u8      res_09c[0xa0-0x9c];
 	u32     pvr;            /* Processor version */
 	u32     svr;            /* System version */
 	u32     mvr;            /* Manufacturing version */
 	u8	res_0ac[0xb0-0xac];
 	u32	rstcr;		/* Reset control */
 	u32	rstrqpblsr;	/* Reset request preboot loader status */
 	u8	res_0b8[0xc0-0xb8];
 	u32	rstrqmr1;	/* Reset request mask */
 	u8	res_0c4[0xc8-0xc4];
 	u32	rstrqsr1;	/* Reset request status */
 	u8	res_0cc[0xd4-0xcc];
 	u32	rstrqwdtmrl;	/* Reset request WDT mask */
 	u8	res_0d8[0xdc-0xd8];
 	u32	rstrqwdtsrl;	/* Reset request WDT status */
 	u8	res_0e0[0xe4-0xe0];
 	u32	brrl;		/* Boot release */
 	u8      res_0e8[0x100-0xe8];
 	u32     rcwsr[16];      /* Reset control word status */
 #define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT	25
 #define FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK	0x1f
 #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_SHIFT	16
 #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK	0x3f
 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK	0xffff0000
 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT	16
 #define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK	0x0000ffff
 #define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT	0
 #define RCW_SB_EN_REG_INDEX	7
 #define RCW_SB_EN_MASK		0x00200000
 	u8      res_140[0x200-0x140];
 	u32     scratchrw[4];  /* Scratch Read/Write */
 	u8      res_210[0x300-0x210];
 	u32     scratchw1r[4];  /* Scratch Read (Write once) */
 	u8      res_310[0x400-0x310];
 	u32	crstsr[12];
 	u8	res_430[0x500-0x430];
 	/* PCI Express n Logical I/O Device Number register */
 	u32 dcfg_ccsr_pex1liodnr;
 	u32 dcfg_ccsr_pex2liodnr;
 	u32 dcfg_ccsr_pex3liodnr;
 	u32 dcfg_ccsr_pex4liodnr;
 	/* RIO n Logical I/O Device Number register */
 	u32 dcfg_ccsr_rio1liodnr;
 	u32 dcfg_ccsr_rio2liodnr;
 	u32 dcfg_ccsr_rio3liodnr;
 	u32 dcfg_ccsr_rio4liodnr;
 	/* USB Logical I/O Device Number register */
 	u32 dcfg_ccsr_usb1liodnr;
 	u32 dcfg_ccsr_usb2liodnr;
 	u32 dcfg_ccsr_usb3liodnr;
 	u32 dcfg_ccsr_usb4liodnr;
 	/* SD/MMC Logical I/O Device Number register */
 	u32 dcfg_ccsr_sdmmc1liodnr;
 	u32 dcfg_ccsr_sdmmc2liodnr;
 	u32 dcfg_ccsr_sdmmc3liodnr;
 	u32 dcfg_ccsr_sdmmc4liodnr;
 	/* RIO Message Unit Logical I/O Device Number register */
 	u32 dcfg_ccsr_riomaintliodnr;
 	u8      res_544[0x550-0x544];
 	u32	sataliodnr[4];
 	u8	res_560[0x570-0x560];
 	u32 dcfg_ccsr_misc1liodnr;
 	u32 dcfg_ccsr_misc2liodnr;
 	u32 dcfg_ccsr_misc3liodnr;
 	u32 dcfg_ccsr_misc4liodnr;
 	u32 dcfg_ccsr_dma1liodnr;
 	u32 dcfg_ccsr_dma2liodnr;
 	u32 dcfg_ccsr_dma3liodnr;
 	u32 dcfg_ccsr_dma4liodnr;
 	u32 dcfg_ccsr_spare1liodnr;
 	u32 dcfg_ccsr_spare2liodnr;
 	u32 dcfg_ccsr_spare3liodnr;
 	u32 dcfg_ccsr_spare4liodnr;
 	u8	res_5a0[0x600-0x5a0];
 	u32 dcfg_ccsr_pblsr;
 	u32	pamubypenr;
 	u32	dmacr1;
 	u8	res_60c[0x610-0x60c];
 	u32 dcfg_ccsr_gensr1;
 	u32 dcfg_ccsr_gensr2;
 	u32 dcfg_ccsr_gensr3;
 	u32 dcfg_ccsr_gensr4;
 	u32 dcfg_ccsr_gencr1;
 	u32 dcfg_ccsr_gencr2;
 	u32 dcfg_ccsr_gencr3;
 	u32 dcfg_ccsr_gencr4;
 	u32 dcfg_ccsr_gencr5;
 	u32 dcfg_ccsr_gencr6;
 	u32 dcfg_ccsr_gencr7;
 	u8	res_63c[0x658-0x63c];
 	u32 dcfg_ccsr_cgensr1;
 	u32 dcfg_ccsr_cgensr0;
 	u8	res_660[0x678-0x660];
 	u32 dcfg_ccsr_cgencr1;
 	u32 dcfg_ccsr_cgencr0;
 	u8	res_680[0x700-0x680];
 	u32 dcfg_ccsr_sriopstecr;
 	u32 dcfg_ccsr_dcsrcr;
 	u8      res_708[0x740-0x708];   /* add more registers when needed */
 	u32     tp_ityp[64];    /* Topology Initiator Type Register */
 	struct {
 		u32     upper;
 		u32     lower;
 	} tp_cluster[16];
 	u8      res_8c0[0xa00-0x8c0];   /* add more registers when needed */
 	u32 dcfg_ccsr_qmbm_warmrst;
 	u8      res_a04[0xa20-0xa04];   /* add more registers when needed */
 	u32 dcfg_ccsr_reserved0;
 	u32 dcfg_ccsr_reserved1;
 };
 #define SCFG_QSPI_CLKSEL		0x40100000
 #define SCFG_USBDRVVBUS_SELCR_USB1	0x00000000
 #define SCFG_USBDRVVBUS_SELCR_USB2	0x00000001
 #define SCFG_USBDRVVBUS_SELCR_USB3	0x00000002
 #define SCFG_USBPWRFAULT_INACTIVE	0x00000000
 #define SCFG_USBPWRFAULT_SHARED		0x00000001
 #define SCFG_USBPWRFAULT_DEDICATED	0x00000002
 #define SCFG_USBPWRFAULT_USB3_SHIFT	4
 #define SCFG_USBPWRFAULT_USB2_SHIFT	2
 #define SCFG_USBPWRFAULT_USB1_SHIFT	0
 #define SCFG_BASE			0x01570000
 #define SCFG_USB3PRM1CR_USB1		0x070
 #define SCFG_USB3PRM2CR_USB1		0x074
 #define SCFG_USB3PRM1CR_USB2		0x07C
 #define SCFG_USB3PRM2CR_USB2		0x080
 #define SCFG_USB3PRM1CR_USB3		0x088
 #define SCFG_USB3PRM2CR_USB3		0x08c
 #define SCFG_USB_TXVREFTUNE			0x9
 #define SCFG_USB_SQRXTUNE_MASK		0x7
 #define SCFG_USB_PCSTXSWINGFULL		0x47
 #define SCFG_USB_PHY1			0x084F0000
 #define SCFG_USB_PHY2			0x08500000
 #define SCFG_USB_PHY3			0x08510000
 #define SCFG_USB_PHY_RX_OVRD_IN_HI		0x200c
 #define USB_PHY_RX_EQ_VAL_1		0x0000
 #define USB_PHY_RX_EQ_VAL_2		0x0080
 #define USB_PHY_RX_EQ_VAL_3		0x0380
 #define USB_PHY_RX_EQ_VAL_4		0x0b80
 #define SCFG_SNPCNFGCR_SECRDSNP		0x80000000
 #define SCFG_SNPCNFGCR_SECWRSNP		0x40000000
 #define SCFG_SNPCNFGCR_SATARDSNP	0x00800000
 #define SCFG_SNPCNFGCR_SATAWRSNP	0x00400000
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
 	u8 res_000[0x100-0x000];
 	u32 usb2_icid;
 	u32 usb3_icid;
 	u8 res_108[0x114-0x108];
 	u32 dma_icid;
 	u32 sata_icid;
 	u32 usb1_icid;
 	u32 qe_icid;
 	u32 sdhc_icid;
 	u32 edma_icid;
 	u32 etr_icid;
 	u32 core_sft_rst[4];
 	u8 res_140[0x158-0x140];
 	u32 altcbar;
 	u32 qspi_cfg;
 	u8 res_160[0x180-0x160];
 	u32 dmamcr;
 	u8 res_184[0x188-0x184];
 	u32 gic_align;
 	u32 debug_icid;
 	u8 res_190[0x1a4-0x190];
 	u32 snpcnfgcr;
 	u8 res_1a8[0x1ac-0x1a8];
 	u32 intpcr;
 	u8 res_1b0[0x204-0x1b0];
 	u32 coresrencr;
 	u8 res_208[0x220-0x208];
 	u32 rvbar0_0;
 	u32 rvbar0_1;
 	u32 rvbar1_0;
 	u32 rvbar1_1;
 	u32 rvbar2_0;
 	u32 rvbar2_1;
 	u32 rvbar3_0;
 	u32 rvbar3_1;
 	u32 lpmcsr;
 	u8 res_244[0x400-0x244];
 	u32 qspidqscr;
 	u32 ecgtxcmcr;
 	u32 sdhciovselcr;
 	u32 rcwpmuxcr0;
 	u32 usbdrvvbus_selcr;
 	u32 usbpwrfault_selcr;
 	u32 usb_refclk_selcr1;
 	u32 usb_refclk_selcr2;
 	u32 usb_refclk_selcr3;
 	u8 res_424[0x600-0x424];
 	u32 scratchrw[4];
 	u8 res_610[0x680-0x610];
 	u32 corebcr;
 	u8 res_684[0x1000-0x684];
 	u32 pex1msiir;
 	u32 pex1msir;
 	u8 res_1008[0x2000-0x1008];
 	u32 pex2;
 	u32 pex2msir;
 	u8 res_2008[0x3000-0x2008];
 	u32 pex3msiir;
 	u32 pex3msir;
 };
 /* Clocking */
 struct ccsr_clk {
 	struct {
 		u32 clkcncsr;	/* core cluster n clock control status */
 		u8  res_004[0x0c];
 		u32 clkcghwacsr; /* Clock generator n hardware accelerator */
 		u8  res_014[0x0c];
 	} clkcsr[4];
 	u8	res_040[0x780]; /* 0x100 */
 	struct {
 		u32 pllcngsr;
 		u8 res_804[0x1c];
 	} pllcgsr[2];
 	u8	res_840[0x1c0];
 	u32	clkpcsr;	/* 0xa00 Platform clock domain control/status */
 	u8	res_a04[0x1fc];
 	u32	pllpgsr;	/* 0xc00 Platform PLL General Status */
 	u8	res_c04[0x1c];
 	u32	plldgsr;	/* 0xc20 DDR PLL General Status */
 	u8	res_c24[0x3dc];
 };
 /* System Counter */
 struct sctr_regs {
 	u32 cntcr;
 	u32 cntsr;
 	u32 cntcv1;
 	u32 cntcv2;
 	u32 resv1[4];
 	u32 cntfid0;
 	u32 cntfid1;
 	u32 resv2[1002];
 	u32 counterid[12];
 };
 #define SRDS_MAX_LANES		4
 struct ccsr_serdes {
 	struct {
 		u32	rstctl;	/* Reset Control Register */
 #define SRDS_RSTCTL_RST		0x80000000
 #define SRDS_RSTCTL_RSTDONE	0x40000000
 #define SRDS_RSTCTL_RSTERR	0x20000000
 #define SRDS_RSTCTL_SWRST	0x10000000
 #define SRDS_RSTCTL_SDEN	0x00000020
 #define SRDS_RSTCTL_SDRST_B	0x00000040
 #define SRDS_RSTCTL_PLLRST_B	0x00000080
 		u32	pllcr0; /* PLL Control Register 0 */
 #define SRDS_PLLCR0_POFF		0x80000000
 #define SRDS_PLLCR0_RFCK_SEL_MASK	0x70000000
 #define SRDS_PLLCR0_RFCK_SEL_100	0x00000000
 #define SRDS_PLLCR0_RFCK_SEL_125	0x10000000
 #define SRDS_PLLCR0_RFCK_SEL_156_25	0x20000000
 #define SRDS_PLLCR0_RFCK_SEL_150	0x30000000
 #define SRDS_PLLCR0_RFCK_SEL_161_13	0x40000000
 #define SRDS_PLLCR0_RFCK_SEL_122_88	0x50000000
 #define SRDS_PLLCR0_PLL_LCK		0x00800000
 #define SRDS_PLLCR0_FRATE_SEL_MASK	0x000f0000
 #define SRDS_PLLCR0_FRATE_SEL_5		0x00000000
 #define SRDS_PLLCR0_FRATE_SEL_3_75	0x00050000
 #define SRDS_PLLCR0_FRATE_SEL_5_15	0x00060000
 #define SRDS_PLLCR0_FRATE_SEL_4		0x00070000
 #define SRDS_PLLCR0_FRATE_SEL_3_12	0x00090000
 #define SRDS_PLLCR0_FRATE_SEL_3		0x000a0000
 		u32	pllcr1; /* PLL Control Register 1 */
 #define SRDS_PLLCR1_PLL_BWSEL	0x08000000
 		u32	res_0c;	/* 0x00c */
 		u32	pllcr3;
 		u32	pllcr4;
 		u32	pllcr5; /* 0x018 SerDes PLL1 Control 5 */
 		u8	res_1c[0x20-0x1c];
 	} bank[2];
 	u8	res_40[0x90-0x40];
 	u32	srdstcalcr;	/* 0x90 TX Calibration Control */
 	u8	res_94[0xa0-0x94];
 	u32	srdsrcalcr;	/* 0xa0 RX Calibration Control */
 	u8	res_a4[0xb0-0xa4];
 	u32	srdsgr0;	/* 0xb0 General Register 0 */
 	u8	res_b4[0x100-0xb4];
 	struct {
 		u32	lnpssr0;	/* 0x100, 0x120, 0x140, 0x160 */
 		u8	res_104[0x120-0x104];
 	} lnpssr[4];	/* Lane A, B, C, D */
 	u8	res_180[0x200-0x180];
 	u32	srdspccr0;	/* 0x200 Protocol Configuration 0 */
 	u32	srdspccr1;	/* 0x204 Protocol Configuration 1 */
 	u32	srdspccr2;	/* 0x208 Protocol Configuration 2 */
 	u32	srdspccr3;	/* 0x20c Protocol Configuration 3 */
 	u32	srdspccr4;	/* 0x210 Protocol Configuration 4 */
 	u32	srdspccr5;	/* 0x214 Protocol Configuration 5 */
 	u32	srdspccr6;	/* 0x218 Protocol Configuration 6 */
 	u32	srdspccr7;	/* 0x21c Protocol Configuration 7 */
 	u32	srdspccr8;	/* 0x220 Protocol Configuration 8 */
 	u32	srdspccr9;	/* 0x224 Protocol Configuration 9 */
 	u32	srdspccra;	/* 0x228 Protocol Configuration A */
 	u32	srdspccrb;	/* 0x22c Protocol Configuration B */
 	u8	res_230[0x800-0x230];
 	struct {
 		u32	gcr0;	/* 0x800 General Control Register 0 */
 		u32	gcr1;	/* 0x804 General Control Register 1 */
 		u32	gcr2;	/* 0x808 General Control Register 2 */
 		u32	sscr0;
 		u32	recr0;	/* 0x810 Receive Equalization Control */
 		u32	recr1;
 		u32	tecr0;	/* 0x818 Transmit Equalization Control */
 		u32	sscr1;
 		u32	ttlcr0;	/* 0x820 Transition Tracking Loop Ctrl 0 */
 		u8	res_824[0x83c-0x824];
 		u32	tcsr3;
 	} lane[4];	/* Lane A, B, C, D */
 	u8	res_900[0x1000-0x900];	/* from 0x900 to 0xfff */
 	struct {
 		u32	srdspexcr0;	/* 0x1000, 0x1040, 0x1080 */
 		u8	res_1004[0x1040-0x1004];
 	} pcie[3];
 	u8	res_10c0[0x1800-0x10c0];
 	struct {
 		u8	res_1800[0x1804-0x1800];
 		u32	srdssgmiicr1;	/* 0x1804 SGMII Protocol Control 1 */
 		u8	res_1808[0x180c-0x1808];
 		u32	srdssgmiicr3;	/* 0x180c SGMII Protocol Control 3 */
 	} sgmii[4];	/* Lane A, B, C, D */
 	u8	res_1840[0x1880-0x1840];
 	struct {
 		u8	res_1880[0x1884-0x1880];
 		u32	srdsqsgmiicr1;	/* 0x1884 QSGMII Protocol Control 1 */
 		u8	res_1888[0x188c-0x1888];
 		u32	srdsqsgmiicr3;	/* 0x188c QSGMII Protocol Control 3 */
 	} qsgmii[2];	/* Lane A, B */
 	u8	res_18a0[0x1980-0x18a0];
 	struct {
 		u8	res_1980[0x1984-0x1980];
 		u32	srdsxficr1;	/* 0x1984 XFI Protocol Control 1 */
 		u8	res_1988[0x198c-0x1988];
 		u32	srdsxficr3;	/* 0x198c XFI Protocol Control 3 */
 	} xfi[2];	/* Lane A, B */
 	u8	res_19a0[0x2000-0x19a0];	/* from 0x19a0 to 0x1fff */
 };
 /* MMU 500 */
 #define SMMU_SCR0			(SMMU_BASE + 0x0)
 #define SMMU_SCR1			(SMMU_BASE + 0x4)
 #define SMMU_SCR2			(SMMU_BASE + 0x8)
 #define SMMU_SACR			(SMMU_BASE + 0x10)
 #define SMMU_IDR0			(SMMU_BASE + 0x20)
 #define SMMU_IDR1			(SMMU_BASE + 0x24)
 #define SMMU_NSCR0			(SMMU_BASE + 0x400)
 #define SMMU_NSCR2			(SMMU_BASE + 0x408)
 #define SMMU_NSACR			(SMMU_BASE + 0x410)
 #define SCR0_CLIENTPD_MASK		0x00000001
 #define SCR0_USFCFG_MASK		0x00000400
 uint get_svr(void);
 #endif	/* __ARCH_FSL_LSCH2_IMMAP_H__*/

arch/arm/include/asm/arch-fsl-layerscape/speed.h

Diff comments View file @ 4426232

 /*
  * Copyright 2014-2015, Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef _FSL_LAYERSCAPE_SPEED_H
 #define _FSL_LAYERSCAPE_SPEED_H
 void get_sys_info(struct sys_info *sys_info);
+#ifdef CONFIG_SYS_DPAA_QBMAN
+unsigned long get_qman_freq(void);
+#endif
 #endif /* _FSL_LAYERSCAPE_SPEED_H */

arch/powerpc/cpu/mpc85xx/cpu_init.c

Diff comments View file @ 4426232

 /*
  * Copyright 2007-2011 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2003 Motorola Inc.
  * Modified by Xianghua Xiao, X.Xiao@motorola.com
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
 #include <watchdog.h>
 #include <asm/processor.h>
 #include <ioports.h>
 #include <sata.h>
 #include <fm_eth.h>
 #include <asm/io.h>
 #include <asm/cache.h>
 #include <asm/mmu.h>
 #include <fsl_errata.h>
 #include <asm/fsl_law.h>
 #include <asm/fsl_serdes.h>
 #include <asm/fsl_srio.h>
 #ifdef CONFIG_FSL_CORENET
 #include <asm/fsl_portals.h>
 #include <asm/fsl_liodn.h>
+#include <fsl_qbman.h>
 #endif
 #include <fsl_usb.h>
 #include <hwconfig.h>
 #include <linux/compiler.h>
 #include "mp.h"
 #ifdef CONFIG_CHAIN_OF_TRUST
 #include <fsl_validate.h>
 #endif
 #ifdef CONFIG_FSL_CAAM
 #include <fsl_sec.h>
 #endif
 #if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET)
 #include <asm/fsl_pamu.h>
 #include <fsl_secboot_err.h>
 #endif
 #ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #include <nand.h>
 #include <errno.h>
 #endif
 #ifndef CONFIG_ARCH_QEMU_E500
 #include <fsl_ddr.h>
 #endif
 #include "../../../../drivers/ata/fsl_sata.h"
 #ifdef CONFIG_U_QE
 #include <fsl_qe.h>
 #endif
 DECLARE_GLOBAL_DATA_PTR;
 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
 /*
  * For deriving usb clock from 100MHz sysclk, reference divisor is set
  * to a value of 5, which gives an intermediate value 20(100/5). The
  * multiplication factor integer is set to 24, which when multiplied to
  * above intermediate value provides clock for usb ip.
  */
 void usb_single_source_clk_configure(struct ccsr_usb_phy *usb_phy)
 {
 	sys_info_t sysinfo;
 	get_sys_info(&sysinfo);
 	if (sysinfo.diff_sysclk == 1) {
 		clrbits_be32(&usb_phy->pllprg[1],
 			     CONFIG_SYS_FSL_USB_PLLPRG2_MFI);
 		setbits_be32(&usb_phy->pllprg[1],
 			     CONFIG_SYS_FSL_USB_PLLPRG2_REF_DIV_INTERNAL_CLK |
 			     CONFIG_SYS_FSL_USB_PLLPRG2_MFI_INTERNAL_CLK |
 			     CONFIG_SYS_FSL_USB_INTERNAL_SOC_CLK_EN);
 		}
 }
 #endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
 void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
 {
 #ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
 	u32 xcvrprg = in_be32(&usb_phy->port1.xcvrprg);
 	/* Increase Disconnect Threshold by 50mV */
 	xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
 						INC_DCNT_THRESHOLD_50MV;
 	/* Enable programming of USB High speed Disconnect threshold */
 	xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
 	out_be32(&usb_phy->port1.xcvrprg, xcvrprg);
 	xcvrprg = in_be32(&usb_phy->port2.xcvrprg);
 	/* Increase Disconnect Threshold by 50mV */
 	xcvrprg &= ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
 						INC_DCNT_THRESHOLD_50MV;
 	/* Enable programming of USB High speed Disconnect threshold */
 	xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
 	out_be32(&usb_phy->port2.xcvrprg, xcvrprg);
 #else
 	u32 temp = 0;
 	u32 status = in_be32(&usb_phy->status1);
 	u32 squelch_prog_rd_0_2 =
 		(status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0)
 			& CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
 	u32 squelch_prog_rd_3_5 =
 		(status >> CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3)
 			& CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
 	setbits_be32(&usb_phy->config1,
 		     CONFIG_SYS_FSL_USB_HS_DISCNCT_INC);
 	setbits_be32(&usb_phy->config2,
 		     CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
 	temp = squelch_prog_rd_0_2 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
 	out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
 	temp = squelch_prog_rd_3_5 << CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
 	out_be32(&usb_phy->config2, in_be32(&usb_phy->config2) | temp);
 #endif
 }
 #endif
 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
 extern qe_iop_conf_t qe_iop_conf_tab[];
 extern void qe_config_iopin(u8 port, u8 pin, int dir,
 				int open_drain, int assign);
 extern void qe_init(uint qe_base);
 extern void qe_reset(void);
 static void config_qe_ioports(void)
 {
 	u8      port, pin;
 	int     dir, open_drain, assign;
 	int     i;
 	for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
 		port		= qe_iop_conf_tab[i].port;
 		pin		= qe_iop_conf_tab[i].pin;
 		dir		= qe_iop_conf_tab[i].dir;
 		open_drain	= qe_iop_conf_tab[i].open_drain;
 		assign		= qe_iop_conf_tab[i].assign;
 		qe_config_iopin(port, pin, dir, open_drain, assign);
 	}
 }
 #endif
 #ifdef CONFIG_CPM2
 void config_8560_ioports (volatile ccsr_cpm_t * cpm)
 {
 	int portnum;
 	for (portnum = 0; portnum < 4; portnum++) {
 		uint pmsk = 0,
 		     ppar = 0,
 		     psor = 0,
 		     pdir = 0,
 		     podr = 0,
 		     pdat = 0;
 		iop_conf_t *iopc = (iop_conf_t *) & iop_conf_tab[portnum][0];
 		iop_conf_t *eiopc = iopc + 32;
 		uint msk = 1;
 		/*
 		 * NOTE:
 		 * index 0 refers to pin 31,
 		 * index 31 refers to pin 0
 		 */
 		while (iopc < eiopc) {
 			if (iopc->conf) {
 				pmsk |= msk;
 				if (iopc->ppar)
 					ppar |= msk;
 				if (iopc->psor)
 					psor |= msk;
 				if (iopc->pdir)
 					pdir |= msk;
 				if (iopc->podr)
 					podr |= msk;
 				if (iopc->pdat)
 					pdat |= msk;
 			}
 			msk <<= 1;
 			iopc++;
 		}
 		if (pmsk != 0) {
 			volatile ioport_t *iop = ioport_addr (cpm, portnum);
 			uint tpmsk = ~pmsk;
 			/*
 			 * the (somewhat confused) paragraph at the
 			 * bottom of page 35-5 warns that there might
 			 * be "unknown behaviour" when programming
 			 * PSORx and PDIRx, if PPARx = 1, so I
 			 * decided this meant I had to disable the
 			 * dedicated function first, and enable it
 			 * last.
 			 */
 			iop->ppar &= tpmsk;
 			iop->psor = (iop->psor & tpmsk) | psor;
 			iop->podr = (iop->podr & tpmsk) | podr;
 			iop->pdat = (iop->pdat & tpmsk) | pdat;
 			iop->pdir = (iop->pdir & tpmsk) | pdir;
 			iop->ppar |= ppar;
 		}
 	}
 }
 #endif
 #ifdef CONFIG_SYS_FSL_CPC
 #if defined(CONFIG_RAMBOOT_PBL) || defined(CONFIG_SYS_CPC_REINIT_F)
 void disable_cpc_sram(void)
 {
 	int i;
 	cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
 	for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
 		if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
 			/* find and disable LAW of SRAM */
 			struct law_entry law = find_law(CONFIG_SYS_INIT_L3_ADDR);
 			if (law.index == -1) {
 				printf("\nFatal error happened\n");
 				return;
 			}
 			disable_law(law.index);
 			clrbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_CDQ_SPEC_DIS);
 			out_be32(&cpc->cpccsr0, 0);
 			out_be32(&cpc->cpcsrcr0, 0);
 		}
 	}
 }
 #endif
 #if defined(T1040_TDM_QUIRK_CCSR_BASE)
 #ifdef CONFIG_POST
 #error POST memory test cannot be enabled with TDM
 #endif
 static void enable_tdm_law(void)
 {
 	int ret;
 	char buffer[HWCONFIG_BUFFER_SIZE] = {0};
 	int tdm_hwconfig_enabled = 0;
 	/*
 	 * Extract hwconfig from environment since environment
 	 * is not setup properly yet. Search for tdm entry in
 	 * hwconfig.
 	 */
 	ret = env_get_f("hwconfig", buffer, sizeof(buffer));
 	if (ret > 0) {
 		tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
 		/* If tdm is defined in hwconfig, set law for tdm workaround */
 		if (tdm_hwconfig_enabled)
 			set_next_law(T1040_TDM_QUIRK_CCSR_BASE, LAW_SIZE_16M,
 				     LAW_TRGT_IF_CCSR);
 	}
 }
 #endif
 void enable_cpc(void)
 {
 	int i;
 	int ret;
 	u32 size = 0;
 	u32 cpccfg0;
 	char buffer[HWCONFIG_BUFFER_SIZE];
 	char cpc_subarg[16];
 	bool have_hwconfig = false;
 	int cpc_args = 0;
 	cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
 	/* Extract hwconfig from environment */
 	ret = env_get_f("hwconfig", buffer, sizeof(buffer));
 	if (ret > 0) {
 		/*
 		 * If "en_cpc" is not defined in hwconfig then by default all
 		 * cpcs are enable. If this config is defined then individual
 		 * cpcs which have to be enabled should also be defined.
 		 * e.g en_cpc:cpc1,cpc2;
 		 */
 		if (hwconfig_f("en_cpc", buffer))
 			have_hwconfig = true;
 	}
 	for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
 		if (have_hwconfig) {
 			sprintf(cpc_subarg, "cpc%u", i + 1);
 			cpc_args = hwconfig_sub_f("en_cpc", cpc_subarg, buffer);
 			if (cpc_args == 0)
 				continue;
 		}
 		cpccfg0 = in_be32(&cpc->cpccfg0);
 		size += CPC_CFG0_SZ_K(cpccfg0);
 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
 		setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_TAG_ECC_SCRUB_DIS);
 #endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
 		setbits_be32(&cpc->cpchdbcr0, CPC_HDBCR0_DATA_ECC_SCRUB_DIS);
 #endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_A006593
 		setbits_be32(&cpc->cpchdbcr0, 1 << (31 - 21));
 #endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_A006379
 		if (has_erratum_a006379()) {
 			setbits_be32(&cpc->cpchdbcr0,
 				     CPC_HDBCR0_SPLRU_LEVEL_EN);
 		}
 #endif
 		out_be32(&cpc->cpccsr0, CPC_CSR0_CE | CPC_CSR0_PE);
 		/* Read back to sync write */
 		in_be32(&cpc->cpccsr0);
 	}
 	puts("Corenet Platform Cache: ");
 	print_size(size * 1024, " enabled\n");
 }
 static void invalidate_cpc(void)
 {
 	int i;
 	cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
 	for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
 		/* skip CPC when it used as all SRAM */
 		if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN)
 			continue;
 		/* Flash invalidate the CPC and clear all the locks */
 		out_be32(&cpc->cpccsr0, CPC_CSR0_FI | CPC_CSR0_LFC);
 		while (in_be32(&cpc->cpccsr0) & (CPC_CSR0_FI | CPC_CSR0_LFC))
 			;
 	}
 }
 #else
 #define enable_cpc()
 #define invalidate_cpc()
 #define disable_cpc_sram()
 #endif /* CONFIG_SYS_FSL_CPC */
 /*
  * Breathe some life into the CPU...
  *
  * Set up the memory map
  * initialize a bunch of registers
  */
 #ifdef CONFIG_FSL_CORENET
 static void corenet_tb_init(void)
 {
 	volatile ccsr_rcpm_t *rcpm =
 		(void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
 	volatile ccsr_pic_t *pic =
 		(void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR);
 	u32 whoami = in_be32(&pic->whoami);
 	/* Enable the timebase register for this core */
 	out_be32(&rcpm->ctbenrl, (1 << whoami));
 }
 #endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
 void fsl_erratum_a007212_workaround(void)
 {
 	ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	u32 ddr_pll_ratio;
 	u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20);
 	u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28);
 	u32 __iomem *dpdovrcr4 = (void *)(CONFIG_SYS_DCSRBAR + 0x21e80);
 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
 	u32 __iomem *plldgdcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c40);
 	u32 __iomem *plldadcr2 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c48);
 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
 	u32 __iomem *plldgdcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c60);
 	u32 __iomem *plldadcr3 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c68);
 #endif
 #endif
 	/*
 	 * Even this workaround applies to selected version of SoCs, it is
 	 * safe to apply to all versions, with the limitation of odd ratios.
 	 * If RCW has disabled DDR PLL, we have to apply this workaround,
 	 * otherwise DDR will not work.
 	 */
 	ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
 		FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT) &
 		FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
 	/* check if RCW sets ratio to 0, required by this workaround */
 	if (ddr_pll_ratio != 0)
 		return;
 	ddr_pll_ratio = (in_be32(&gur->rcwsr[0]) >>
 		FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT) &
 		FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK;
 	/* check if reserved bits have the desired ratio */
 	if (ddr_pll_ratio == 0) {
 		printf("Error: Unknown DDR PLL ratio!\n");
 		return;
 	}
 	ddr_pll_ratio >>= 1;
 	setbits_be32(plldadcr1, 0x02000001);
 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
 	setbits_be32(plldadcr2, 0x02000001);
 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
 	setbits_be32(plldadcr3, 0x02000001);
 #endif
 #endif
 	setbits_be32(dpdovrcr4, 0xe0000000);
 	out_be32(plldgdcr1, 0x08000001 | (ddr_pll_ratio << 1));
 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
 	out_be32(plldgdcr2, 0x08000001 | (ddr_pll_ratio << 1));
 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
 	out_be32(plldgdcr3, 0x08000001 | (ddr_pll_ratio << 1));
 #endif
 #endif
 	udelay(100);
 	clrbits_be32(plldadcr1, 0x02000001);
 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 2)
 	clrbits_be32(plldadcr2, 0x02000001);
 #if (CONFIG_SYS_NUM_DDR_CTLRS >= 3)
 	clrbits_be32(plldadcr3, 0x02000001);
 #endif
 #endif
 	clrbits_be32(dpdovrcr4, 0xe0000000);
 }
 #endif
 ulong cpu_init_f(void)
 {
 	extern void m8560_cpm_reset (void);
 #ifdef CONFIG_SYS_DCSRBAR_PHYS
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #endif
 #if defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SYS_RAMBOOT)
 	struct law_entry law;
 #endif
 #ifdef CONFIG_ARCH_MPC8548
 	ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
 	uint svr = get_svr();
 	/*
 	 * CPU2 errata workaround: A core hang possible while executing
 	 * a msync instruction and a snoopable transaction from an I/O
 	 * master tagged to make quick forward progress is present.
 	 * Fixed in silicon rev 2.1.
 	 */
 	if ((SVR_MAJ(svr) == 1) || ((SVR_MAJ(svr) == 2 && SVR_MIN(svr) == 0x0)))
 		out_be32(&ecm->eebpcr, in_be32(&ecm->eebpcr) | (1 << 16));
 #endif
 	disable_tlb(14);
 	disable_tlb(15);
 #if defined(CONFIG_SECURE_BOOT) && !defined(CONFIG_SYS_RAMBOOT)
 	/* Disable the LAW created for NOR flash by the PBI commands */
 	law = find_law(CONFIG_SYS_PBI_FLASH_BASE);
 	if (law.index != -1)
 		disable_law(law.index);
 #if defined(CONFIG_SYS_CPC_REINIT_F)
 	disable_cpc_sram();
 #endif
 #endif
 #ifdef CONFIG_CPM2
 	config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
 #endif
        init_early_memctl_regs();
 #if defined(CONFIG_CPM2)
 	m8560_cpm_reset();
 #endif
 #if defined(CONFIG_QE) && !defined(CONFIG_U_QE)
 	/* Config QE ioports */
 	config_qe_ioports();
 #endif
 #if defined(CONFIG_FSL_DMA)
 	dma_init();
 #endif
 #ifdef CONFIG_FSL_CORENET
 	corenet_tb_init();
 #endif
 	init_used_tlb_cams();
 	/* Invalidate the CPC before DDR gets enabled */
 	invalidate_cpc();
  #ifdef CONFIG_SYS_DCSRBAR_PHYS
 	/* set DCSRCR so that DCSR space is 1G */
 	setbits_be32(&gur->dcsrcr, FSL_CORENET_DCSR_SZ_1G);
 	in_be32(&gur->dcsrcr);
 #endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_A007212
 	fsl_erratum_a007212_workaround();
 #endif
 	return 0;
 }
 /* Implement a dummy function for those platforms w/o SERDES */
 static void __fsl_serdes__init(void)
 {
 	return ;
 }
 __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
 int enable_cluster_l2(void)
 {
 	int i = 0;
 	u32 cluster, svr = get_svr();
 	ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	struct ccsr_cluster_l2 __iomem *l2cache;
 	/* only the L2 of first cluster should be enabled as expected on T4080,
 	 * but there is no EOC in the first cluster as HW sake, so return here
 	 * to skip enabling L2 cache of the 2nd cluster.
 	 */
 	if (SVR_SOC_VER(svr) == SVR_T4080)
 		return 0;
 	cluster = in_be32(&gur->tp_cluster[i].lower);
 	if (cluster & TP_CLUSTER_EOC)
 		return 0;
 	/* The first cache has already been set up, so skip it */
 	i++;
 	/* Look through the remaining clusters, and set up their caches */
 	do {
 		int j, cluster_valid = 0;
 		l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
 		cluster = in_be32(&gur->tp_cluster[i].lower);
 		/* check that at least one core/accel is enabled in cluster */
 		for (j = 0; j < 4; j++) {
 			u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK;
 			u32 type = in_be32(&gur->tp_ityp[idx]);
 			if ((type & TP_ITYP_AV) &&
 			    TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC)
 				cluster_valid = 1;
 		}
 		if (cluster_valid) {
 			/* set stash ID to (cluster) * 2 + 32 + 1 */
 			clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
 			printf("enable l2 for cluster %d %p\n", i, l2cache);
 			out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
 			while ((in_be32(&l2cache->l2csr0)
 				& (L2CSR0_L2FI|L2CSR0_L2LFC)) != 0)
 					;
 			out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE);
 		}
 		i++;
 	} while (!(cluster & TP_CLUSTER_EOC));
 	return 0;
 }
 #endif
 /*
  * Initialize L2 as cache.
  */
 int l2cache_init(void)
 {
 	__maybe_unused u32 svr = get_svr();
 #ifdef CONFIG_L2_CACHE
 	ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR;
 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
 	struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
 #endif
 	puts ("L2:    ");
 #if defined(CONFIG_L2_CACHE)
 	volatile uint cache_ctl;
 	uint ver;
 	u32 l2siz_field;
 	ver = SVR_SOC_VER(svr);
 	asm("msync;isync");
 	cache_ctl = l2cache->l2ctl;
 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
 	if (cache_ctl & MPC85xx_L2CTL_L2E) {
 		/* Clear L2 SRAM memory-mapped base address */
 		out_be32(&l2cache->l2srbar0, 0x0);
 		out_be32(&l2cache->l2srbar1, 0x0);
 		/* set MBECCDIS=0, SBECCDIS=0 */
 		clrbits_be32(&l2cache->l2errdis,
 				(MPC85xx_L2ERRDIS_MBECC |
 				 MPC85xx_L2ERRDIS_SBECC));
 		/* set L2E=0, L2SRAM=0 */
 		clrbits_be32(&l2cache->l2ctl,
 				(MPC85xx_L2CTL_L2E |
 				 MPC85xx_L2CTL_L2SRAM_ENTIRE));
 	}
 #endif
 	l2siz_field = (cache_ctl >> 28) & 0x3;
 	switch (l2siz_field) {
 	case 0x0:
 		printf(" unknown size (0x%08x)\n", cache_ctl);
 		return -1;
 		break;
 	case 0x1:
 		if (ver == SVR_8540 || ver == SVR_8560   ||
 		    ver == SVR_8541 || ver == SVR_8555) {
 			puts("128 KiB ");
 			/* set L2E=1, L2I=1, & L2BLKSZ=1 (128 KiBibyte) */
 			cache_ctl = 0xc4000000;
 		} else {
 			puts("256 KiB ");
 			cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */
 		}
 		break;
 	case 0x2:
 		if (ver == SVR_8540 || ver == SVR_8560   ||
 		    ver == SVR_8541 || ver == SVR_8555) {
 			puts("256 KiB ");
 			/* set L2E=1, L2I=1, & L2BLKSZ=2 (256 KiBibyte) */
 			cache_ctl = 0xc8000000;
 		} else {
 			puts("512 KiB ");
 			/* set L2E=1, L2I=1, & L2SRAM=0 */
 			cache_ctl = 0xc0000000;
 		}
 		break;
 	case 0x3:
 		puts("1024 KiB ");
 		/* set L2E=1, L2I=1, & L2SRAM=0 */
 		cache_ctl = 0xc0000000;
 		break;
 	}
 	if (l2cache->l2ctl & MPC85xx_L2CTL_L2E) {
 		puts("already enabled");
 #if defined(CONFIG_SYS_INIT_L2_ADDR) && defined(CONFIG_SYS_FLASH_BASE)
 		u32 l2srbar = l2cache->l2srbar0;
 		if (l2cache->l2ctl & MPC85xx_L2CTL_L2SRAM_ENTIRE
 				&& l2srbar >= CONFIG_SYS_FLASH_BASE) {
 			l2srbar = CONFIG_SYS_INIT_L2_ADDR;
 			l2cache->l2srbar0 = l2srbar;
 			printf(", moving to 0x%08x", CONFIG_SYS_INIT_L2_ADDR);
 		}
 #endif /* CONFIG_SYS_INIT_L2_ADDR */
 		puts("\n");
 	} else {
 		asm("msync;isync");
 		l2cache->l2ctl = cache_ctl; /* invalidate & enable */
 		asm("msync;isync");
 		puts("enabled\n");
 	}
 #elif defined(CONFIG_BACKSIDE_L2_CACHE)
 	if (SVR_SOC_VER(svr) == SVR_P2040) {
 		puts("N/A\n");
 		goto skip_l2;
 	}
 	u32 l2cfg0 = mfspr(SPRN_L2CFG0);
 	/* invalidate the L2 cache */
 	mtspr(SPRN_L2CSR0, (L2CSR0_L2FI|L2CSR0_L2LFC));
 	while (mfspr(SPRN_L2CSR0) & (L2CSR0_L2FI|L2CSR0_L2LFC))
 		;
 #ifdef CONFIG_SYS_CACHE_STASHING
 	/* set stash id to (coreID) * 2 + 32 + L2 (1) */
 	mtspr(SPRN_L2CSR1, (32 + 1));
 #endif
 	/* enable the cache */
 	mtspr(SPRN_L2CSR0, CONFIG_SYS_INIT_L2CSR0);
 	if (CONFIG_SYS_INIT_L2CSR0 & L2CSR0_L2E) {
 		while (!(mfspr(SPRN_L2CSR0) & L2CSR0_L2E))
 			;
 		print_size((l2cfg0 & 0x3fff) * 64 * 1024, " enabled\n");
 	}
 skip_l2:
 #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
 	if (l2cache->l2csr0 & L2CSR0_L2E)
 		print_size((l2cache->l2cfg0 & 0x3fff) * 64 * 1024,
 			   " enabled\n");
 	enable_cluster_l2();
 #else
 	puts("disabled\n");
 #endif
 	return 0;
 }
 /*
  *
  * The newer 8548, etc, parts have twice as much cache, but
  * use the same bit-encoding as the older 8555, etc, parts.
  *
  */
 int cpu_init_r(void)
 {
 	__maybe_unused u32 svr = get_svr();
 #ifdef CONFIG_SYS_LBC_LCRR
 	fsl_lbc_t *lbc = (void __iomem *)LBC_BASE_ADDR;
 #endif
 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
 	extern int spin_table_compat;
 	const char *spin;
 #endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
 	ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
 #endif
 #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
 	defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
 	/*
 	 * CPU22 and NMG_CPU_A011 share the same workaround.
 	 * CPU22 applies to P4080 rev 1.0, 2.0, fixed in 3.0
 	 * NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
 	 * also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1, both
 	 * fixed in 2.0. NMG_CPU_A011 is activated by default and can
 	 * be disabled by hwconfig with syntax:
 	 *
 	 * fsl_cpu_a011:disable
 	 */
 	extern int enable_cpu_a011_workaround;
 #ifdef CONFIG_SYS_P4080_ERRATUM_CPU22
 	enable_cpu_a011_workaround = (SVR_MAJ(svr) < 3);
 #else
 	char buffer[HWCONFIG_BUFFER_SIZE];
 	char *buf = NULL;
 	int n, res;
 	n = env_get_f("hwconfig", buffer, sizeof(buffer));
 	if (n > 0)
 		buf = buffer;
 	res = hwconfig_arg_cmp_f("fsl_cpu_a011", "disable", buf);
 	if (res > 0) {
 		enable_cpu_a011_workaround = 0;
 	} else {
 		if (n >= HWCONFIG_BUFFER_SIZE) {
 			printf("fsl_cpu_a011 was not found. hwconfig variable "
 				"may be too long\n");
 		}
 		enable_cpu_a011_workaround =
 			(SVR_SOC_VER(svr) == SVR_P4080 && SVR_MAJ(svr) < 3) ||
 			(SVR_SOC_VER(svr) != SVR_P4080 && SVR_MAJ(svr) < 2);
 	}
 #endif
 	if (enable_cpu_a011_workaround) {
 		flush_dcache();
 		mtspr(L1CSR2, (mfspr(L1CSR2) | L1CSR2_DCWS));
 		sync();
 	}
 #endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_A007907
 	flush_dcache();
 	mtspr(L1CSR2, (mfspr(L1CSR2) & ~L1CSR2_DCSTASHID));
 	sync();
 #endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_A005812
 	/*
 	 * A-005812 workaround sets bit 32 of SPR 976 for SoCs running
 	 * in write shadow mode. Checking DCWS before setting SPR 976.
 	 */
 	if (mfspr(L1CSR2) & L1CSR2_DCWS)
 		mtspr(SPRN_HDBCR0, (mfspr(SPRN_HDBCR0) | 0x80000000));
 #endif
 #if defined(CONFIG_PPC_SPINTABLE_COMPATIBLE) && defined(CONFIG_MP)
 	spin = env_get("spin_table_compat");
 	if (spin && (*spin == 'n'))
 		spin_table_compat = 0;
 	else
 		spin_table_compat = 1;
 #endif
 #ifdef CONFIG_FSL_CORENET
 	set_liodns();
 #ifdef CONFIG_SYS_DPAA_QBMAN
-	setup_portals();
+	setup_qbman_portals();
 #endif
 #endif
 	l2cache_init();
 #if defined(CONFIG_RAMBOOT_PBL)
 	disable_cpc_sram();
 #endif
 	enable_cpc();
 #if defined(T1040_TDM_QUIRK_CCSR_BASE)
 	enable_tdm_law();
 #endif
 #ifndef CONFIG_SYS_FSL_NO_SERDES
 	/* needs to be in ram since code uses global static vars */
 	fsl_serdes_init();
 #endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
 #define MCFGR_AXIPIPE 0x000000f0
 	if (IS_SVR_REV(svr, 1, 0))
 		sec_clrbits32(&sec->mcfgr, MCFGR_AXIPIPE);
 #endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_A005871
 	if (IS_SVR_REV(svr, 1, 0)) {
 		int i;
 		__be32 *p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb004c;
 		for (i = 0; i < 12; i++) {
 			p += i + (i > 5 ? 11 : 0);
 			out_be32(p, 0x2);
 		}
 		p = (void __iomem *)CONFIG_SYS_DCSRBAR + 0xb0108;
 		out_be32(p, 0x34);
 	}
 #endif
 #ifdef CONFIG_SYS_SRIO
 	srio_init();
 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
 	char *s = env_get("bootmaster");
 	if (s) {
 		if (!strcmp(s, "SRIO1")) {
 			srio_boot_master(1);
 			srio_boot_master_release_slave(1);
 		}
 		if (!strcmp(s, "SRIO2")) {
 			srio_boot_master(2);
 			srio_boot_master_release_slave(2);
 		}
 	}
 #endif
 #endif
 #if defined(CONFIG_MP)
 	setup_mp();
 #endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC13
 	{
 		if (SVR_MAJ(svr) < 3) {
 			void *p;
 			p = (void *)CONFIG_SYS_DCSRBAR + 0x20520;
 			setbits_be32(p, 1 << (31 - 14));
 		}
 	}
 #endif
 #ifdef CONFIG_SYS_LBC_LCRR
 	/*
 	 * Modify the CLKDIV field of LCRR register to improve the writing
 	 * speed for NOR flash.
 	 */
 	clrsetbits_be32(&lbc->lcrr, LCRR_CLKDIV, CONFIG_SYS_LBC_LCRR);
 	__raw_readl(&lbc->lcrr);
 	isync();
 #ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
 	udelay(100);
 #endif
 #endif
 #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE
 	{
 		struct ccsr_usb_phy __iomem *usb_phy1 =
 			(void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
 		if (has_erratum_a006261())
 			fsl_erratum_a006261_workaround(usb_phy1);
 #endif
 		out_be32(&usb_phy1->usb_enable_override,
 				CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
 	}
 #endif
 #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE
 	{
 		struct ccsr_usb_phy __iomem *usb_phy2 =
 			(void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
 		if (has_erratum_a006261())
 			fsl_erratum_a006261_workaround(usb_phy2);
 #endif
 		out_be32(&usb_phy2->usb_enable_override,
 				CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
 	}
 #endif
 #ifdef CONFIG_SYS_FSL_ERRATUM_USB14
 	/* On P204x/P304x/P50x0 Rev1.0, USB transmit will result internal
 	 * multi-bit ECC errors which has impact on performance, so software
 	 * should disable all ECC reporting from USB1 and USB2.
 	 */
 	if (IS_SVR_REV(get_svr(), 1, 0)) {
 		struct dcsr_dcfg_regs *dcfg = (struct dcsr_dcfg_regs *)
 			(CONFIG_SYS_DCSRBAR + CONFIG_SYS_DCSR_DCFG_OFFSET);
 		setbits_be32(&dcfg->ecccr1,
 				(DCSR_DCFG_ECC_DISABLE_USB1 |
 				 DCSR_DCFG_ECC_DISABLE_USB2));
 	}
 #endif
 #if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE)
 		struct ccsr_usb_phy __iomem *usb_phy =
 			(void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
 		setbits_be32(&usb_phy->pllprg[1],
 			     CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN |
 			     CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN |
 			     CONFIG_SYS_FSL_USB_PLLPRG2_MFI |
 			     CONFIG_SYS_FSL_USB_PLLPRG2_PLL_EN);
 #ifdef CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
 		usb_single_source_clk_configure(usb_phy);
 #endif
 		setbits_be32(&usb_phy->port1.ctrl,
 			     CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
 		setbits_be32(&usb_phy->port1.drvvbuscfg,
 			     CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
 		setbits_be32(&usb_phy->port1.pwrfltcfg,
 			     CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
 		setbits_be32(&usb_phy->port2.ctrl,
 			     CONFIG_SYS_FSL_USB_CTRL_PHY_EN);
 		setbits_be32(&usb_phy->port2.drvvbuscfg,
 			     CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
 		setbits_be32(&usb_phy->port2.pwrfltcfg,
 			     CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
 #ifdef CONFIG_SYS_FSL_ERRATUM_A006261
 		if (has_erratum_a006261())
 			fsl_erratum_a006261_workaround(usb_phy);
 #endif
 #endif /* CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE */
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
 	erratum_a009942_check_cpo();
 #endif
 #ifdef CONFIG_FMAN_ENET
 	fman_enet_init();
 #endif
 #if defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET)
 	if (pamu_init() < 0)
 		fsl_secboot_handle_error(ERROR_ESBC_PAMU_INIT);
 #endif
 #ifdef CONFIG_FSL_CAAM
 	sec_init();
 #if defined(CONFIG_ARCH_C29X)
 	if ((SVR_SOC_VER(svr) == SVR_C292) ||
 	    (SVR_SOC_VER(svr) == SVR_C293))
 		sec_init_idx(1);
 	if (SVR_SOC_VER(svr) == SVR_C293)
 		sec_init_idx(2);
 #endif
 #endif
 #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_SYS_FSL_ERRATUM_SATA_A001)
 	/*
 	 * For P1022/1013 Rev1.0 silicon, after power on SATA host
 	 * controller is configured in legacy mode instead of the
 	 * expected enterprise mode. Software needs to clear bit[28]
 	 * of HControl register to change to enterprise mode from
 	 * legacy mode.  We assume that the controller is offline.
 	 */
 	if (IS_SVR_REV(svr, 1, 0) &&
 	    ((SVR_SOC_VER(svr) == SVR_P1022) ||
 	     (SVR_SOC_VER(svr) == SVR_P1013))) {
 		fsl_sata_reg_t *reg;
 		/* first SATA controller */
 		reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR;
 		clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
 		/* second SATA controller */
 		reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR;
 		clrbits_le32(&reg->hcontrol, HCONTROL_ENTERPRISE_EN);
 	}
 #endif
 	init_used_tlb_cams();
 	return 0;
 }
 void arch_preboot_os(void)
 {
 	u32 msr;
 	/*
 	 * We are changing interrupt offsets and are about to boot the OS so
 	 * we need to make sure we disable all async interrupts. EE is already
 	 * disabled by the time we get called.
 	 */
 	msr = mfmsr();
 	msr &= ~(MSR_ME|MSR_CE);
 	mtmsr(msr);
 }
 #if defined(CONFIG_SATA) && defined(CONFIG_FSL_SATA)
 int sata_initialize(void)
 {
 	if (is_serdes_configured(SATA1) || is_serdes_configured(SATA2))
 		return __sata_initialize();
 	return 1;
 }
 #endif
 void cpu_secondary_init_r(void)
 {
 #ifdef CONFIG_U_QE
 	uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */
 #elif defined CONFIG_QE
 	uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
 #endif
 #ifdef CONFIG_QE
 	qe_init(qe_base);
 	qe_reset();
 #endif
 }
 #ifdef CONFIG_BOARD_LATE_INIT
 int board_late_init(void)
 {
 #ifdef CONFIG_CHAIN_OF_TRUST
 	fsl_setenv_chain_of_trust();
 #endif
 	return 0;
 }
 #endif

arch/powerpc/cpu/mpc85xx/fdt.c

Diff comments View file @ 4426232

 /*
  * Copyright 2007-2011 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
 #include <libfdt.h>
 #include <fdt_support.h>
 #include <asm/processor.h>
 #include <linux/ctype.h>
 #include <asm/io.h>
 #include <asm/fsl_fdt.h>
 #include <asm/fsl_portals.h>
+#include <fsl_qbman.h>
 #include <hwconfig.h>
 #ifdef CONFIG_FSL_ESDHC
 #include <fsl_esdhc.h>
 #endif
 #ifdef CONFIG_SYS_DPAA_FMAN
 #include <fsl_fman.h>
 #endif
 DECLARE_GLOBAL_DATA_PTR;
 extern void ft_qe_setup(void *blob);
 extern void ft_fixup_num_cores(void *blob);
 extern void ft_srio_setup(void *blob);
 #ifdef CONFIG_MP
 #include "mp.h"
 void ft_fixup_cpu(void *blob, u64 memory_limit)
 {
 	int off;
 	phys_addr_t spin_tbl_addr = get_spin_phys_addr();
 	u32 bootpg = determine_mp_bootpg(NULL);
 	u32 id = get_my_id();
 	const char *enable_method;
 #if defined(T1040_TDM_QUIRK_CCSR_BASE)
 	int ret;
 	int tdm_hwconfig_enabled = 0;
 	char buffer[HWCONFIG_BUFFER_SIZE] = {0};
 #endif
 	off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 	while (off != -FDT_ERR_NOTFOUND) {
 		u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
 		if (reg) {
 			u32 phys_cpu_id = thread_to_core(*reg);
 			u64 val = phys_cpu_id * SIZE_BOOT_ENTRY + spin_tbl_addr;
 			val = cpu_to_fdt64(val);
 			if (*reg == id) {
 				fdt_setprop_string(blob, off, "status",
 								"okay");
 			} else {
 				fdt_setprop_string(blob, off, "status",
 								"disabled");
 			}
 			if (hold_cores_in_reset(0)) {
 #ifdef CONFIG_FSL_CORENET
 				/* Cores held in reset, use BRR to release */
 				enable_method = "fsl,brr-holdoff";
 #else
 				/* Cores held in reset, use EEBPCR to release */
 				enable_method = "fsl,eebpcr-holdoff";
 #endif
 			} else {
 				/* Cores out of reset and in a spin-loop */
 				enable_method = "spin-table";
 				fdt_setprop(blob, off, "cpu-release-addr",
 						&val, sizeof(val));
 			}
 			fdt_setprop_string(blob, off, "enable-method",
 							enable_method);
 		} else {
 			printf ("cpu NULL\n");
 		}
 		off = fdt_node_offset_by_prop_value(blob, off,
 				"device_type", "cpu", 4);
 	}
 #if defined(T1040_TDM_QUIRK_CCSR_BASE)
 #define	CONFIG_MEM_HOLE_16M	0x1000000
 	/*
 	 * Extract hwconfig from environment.
 	 * Search for tdm entry in hwconfig.
 	 */
 	ret = env_get_f("hwconfig", buffer, sizeof(buffer));
 	if (ret > 0)
 		tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
 	/* Reserve the memory hole created by TDM LAW, so OSes dont use it */
 	if (tdm_hwconfig_enabled) {
 		off = fdt_add_mem_rsv(blob, T1040_TDM_QUIRK_CCSR_BASE,
 				      CONFIG_MEM_HOLE_16M);
 		if (off < 0)
 			printf("Failed  to reserve memory for tdm: %s\n",
 			       fdt_strerror(off));
 	}
 #endif
 	/* Reserve the boot page so OSes dont use it */
 	if ((u64)bootpg < memory_limit) {
 		off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);
 		if (off < 0)
 			printf("Failed to reserve memory for bootpg: %s\n",
 				fdt_strerror(off));
 	}
 #ifndef CONFIG_MPC8xxx_DISABLE_BPTR
 	/*
 	 * Reserve the default boot page so OSes dont use it.
 	 * The default boot page is always mapped to bootpg above using
 	 * boot page translation.
 	 */
 	if (0xfffff000ull < memory_limit) {
 		off = fdt_add_mem_rsv(blob, 0xfffff000ull, (u64)4096);
 		if (off < 0) {
 			printf("Failed to reserve memory for 0xfffff000: %s\n",
 				fdt_strerror(off));
 		}
 	}
 #endif
 	/* Reserve spin table page */
 	if (spin_tbl_addr < memory_limit) {
 		off = fdt_add_mem_rsv(blob,
 			(spin_tbl_addr & ~0xffful), 4096);
 		if (off < 0)
 			printf("Failed to reserve memory for spin table: %s\n",
 				fdt_strerror(off));
 	}
 #ifdef CONFIG_DEEP_SLEEP
 #ifdef CONFIG_SPL_MMC_BOOT
 	off = fdt_add_mem_rsv(blob, CONFIG_SYS_MMC_U_BOOT_START,
 		CONFIG_SYS_MMC_U_BOOT_SIZE);
 	if (off < 0)
 		printf("Failed to reserve memory for SD deep sleep: %s\n",
 		       fdt_strerror(off));
 #elif defined(CONFIG_SPL_SPI_BOOT)
 	off = fdt_add_mem_rsv(blob, CONFIG_SYS_SPI_FLASH_U_BOOT_START,
 		CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE);
 	if (off < 0)
 		printf("Failed to reserve memory for SPI deep sleep: %s\n",
 		       fdt_strerror(off));
 #endif
 #endif
 }
 #endif
 #ifdef CONFIG_SYS_FSL_CPC
 static inline void ft_fixup_l3cache(void *blob, int off)
 {
 	u32 line_size, num_ways, size, num_sets;
 	cpc_corenet_t *cpc = (void *)CONFIG_SYS_FSL_CPC_ADDR;
 	u32 cfg0 = in_be32(&cpc->cpccfg0);
 	size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC;
 	num_ways = CPC_CFG0_NUM_WAYS(cfg0);
 	line_size = CPC_CFG0_LINE_SZ(cfg0);
 	num_sets = size / (line_size * num_ways);
 	fdt_setprop(blob, off, "cache-unified", NULL, 0);
 	fdt_setprop_cell(blob, off, "cache-block-size", line_size);
 	fdt_setprop_cell(blob, off, "cache-size", size);
 	fdt_setprop_cell(blob, off, "cache-sets", num_sets);
 	fdt_setprop_cell(blob, off, "cache-level", 3);
 #ifdef CONFIG_SYS_CACHE_STASHING
 	fdt_setprop_cell(blob, off, "cache-stash-id", 1);
 #endif
 }
 #else
 #define ft_fixup_l3cache(x, y)
 #endif
 #if defined(CONFIG_L2_CACHE) || \
 	defined(CONFIG_BACKSIDE_L2_CACHE) || \
 	defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
 static inline void ft_fixup_l2cache_compatible(void *blob, int off)
 {
 	int len;
 	struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr()));
 	if (cpu) {
 		char buf[40];
 		if (isdigit(cpu->name[0])) {
 			/* MPCxxxx, where xxxx == 4-digit number */
 			len = sprintf(buf, "fsl,mpc%s-l2-cache-controller",
 				cpu->name) + 1;
 		} else {
 			/* Pxxxx or Txxxx, where xxxx == 4-digit number */
 			len = sprintf(buf, "fsl,%c%s-l2-cache-controller",
 			tolower(cpu->name[0]), cpu->name + 1) + 1;
 		}
 		/*
 		 * append "cache" after the NULL character that the previous
 		 * sprintf wrote.  This is how a device tree stores multiple
 		 * strings in a property.
 		 */
 		len += sprintf(buf + len, "cache") + 1;
 		fdt_setprop(blob, off, "compatible", buf, len);
 	}
 }
 #endif
 #if defined(CONFIG_L2_CACHE)
 /* return size in kilobytes */
 static inline u32 l2cache_size(void)
 {
 	volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
 	volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3;
 	u32 ver = SVR_SOC_VER(get_svr());
 	switch (l2siz_field) {
 	case 0x0:
 		break;
 	case 0x1:
 		if (ver == SVR_8540 || ver == SVR_8560   ||
 		    ver == SVR_8541 || ver == SVR_8555)
 			return 128;
 		else
 			return 256;
 		break;
 	case 0x2:
 		if (ver == SVR_8540 || ver == SVR_8560   ||
 		    ver == SVR_8541 || ver == SVR_8555)
 			return 256;
 		else
 			return 512;
 		break;
 	case 0x3:
 		return 1024;
 		break;
 	}
 	return 0;
 }
 static inline void ft_fixup_l2cache(void *blob)
 {
 	int off;
 	u32 *ph;
 	const u32 line_size = 32;
 	const u32 num_ways = 8;
 	const u32 size = l2cache_size() * 1024;
 	const u32 num_sets = size / (line_size * num_ways);
 	off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 	if (off < 0) {
 		debug("no cpu node fount\n");
 		return;
 	}
 	ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
 	if (ph == NULL) {
 		debug("no next-level-cache property\n");
 		return ;
 	}
 	off = fdt_node_offset_by_phandle(blob, *ph);
 	if (off < 0) {
 		printf("%s: %s\n", __func__, fdt_strerror(off));
 		return ;
 	}
 	ft_fixup_l2cache_compatible(blob, off);
 	fdt_setprop(blob, off, "cache-unified", NULL, 0);
 	fdt_setprop_cell(blob, off, "cache-block-size", line_size);
 	fdt_setprop_cell(blob, off, "cache-size", size);
 	fdt_setprop_cell(blob, off, "cache-sets", num_sets);
 	fdt_setprop_cell(blob, off, "cache-level", 2);
 	/* we dont bother w/L3 since no platform of this type has one */
 }
 #elif defined(CONFIG_BACKSIDE_L2_CACHE) || \
 	defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
 static inline void ft_fixup_l2cache(void *blob)
 {
 	int off, l2_off, l3_off = -1;
 	u32 *ph;
 #ifdef	CONFIG_BACKSIDE_L2_CACHE
 	u32 l2cfg0 = mfspr(SPRN_L2CFG0);
 #else
 	struct ccsr_cluster_l2 *l2cache =
 		(struct ccsr_cluster_l2 __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2);
 	u32 l2cfg0 = in_be32(&l2cache->l2cfg0);
 #endif
 	u32 size, line_size, num_ways, num_sets;
 	int has_l2 = 1;
 	/* P2040/P2040E has no L2, so dont set any L2 props */
 	if (SVR_SOC_VER(get_svr()) == SVR_P2040)
 		has_l2 = 0;
 	size = (l2cfg0 & 0x3fff) * 64 * 1024;
 	num_ways = ((l2cfg0 >> 14) & 0x1f) + 1;
 	line_size = (((l2cfg0 >> 23) & 0x3) + 1) * 32;
 	num_sets = size / (line_size * num_ways);
 	off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 	while (off != -FDT_ERR_NOTFOUND) {
 		ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
 		if (ph == NULL) {
 			debug("no next-level-cache property\n");
 			goto next;
 		}
 		l2_off = fdt_node_offset_by_phandle(blob, *ph);
 		if (l2_off < 0) {
 			printf("%s: %s\n", __func__, fdt_strerror(off));
 			goto next;
 		}
 		if (has_l2) {
 #ifdef CONFIG_SYS_CACHE_STASHING
 			u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
 			/* Only initialize every eighth thread */
 			if (reg && !((*reg) % 8)) {
 				fdt_setprop_cell(blob, l2_off, "cache-stash-id",
 						 (*reg / 4) + 32 + 1);
 			}
 #else
 			if (reg) {
 				fdt_setprop_cell(blob, l2_off, "cache-stash-id",
 						 (*reg * 2) + 32 + 1);
 			}
 #endif
 #endif
 			fdt_setprop(blob, l2_off, "cache-unified", NULL, 0);
 			fdt_setprop_cell(blob, l2_off, "cache-block-size",
 						line_size);
 			fdt_setprop_cell(blob, l2_off, "cache-size", size);
 			fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets);
 			fdt_setprop_cell(blob, l2_off, "cache-level", 2);
 			ft_fixup_l2cache_compatible(blob, l2_off);
 		}
 		if (l3_off < 0) {
 			ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0);
 			if (ph == NULL) {
 				debug("no next-level-cache property\n");
 				goto next;
 			}
 			l3_off = *ph;
 		}
 next:
 		off = fdt_node_offset_by_prop_value(blob, off,
 				"device_type", "cpu", 4);
 	}
 	if (l3_off > 0) {
 		l3_off = fdt_node_offset_by_phandle(blob, l3_off);
 		if (l3_off < 0) {
 			printf("%s: %s\n", __func__, fdt_strerror(off));
 			return ;
 		}
 		ft_fixup_l3cache(blob, l3_off);
 	}
 }
 #else
 #define ft_fixup_l2cache(x)
 #endif
 static inline void ft_fixup_cache(void *blob)
 {
 	int off;
 	off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 	while (off != -FDT_ERR_NOTFOUND) {
 		u32 l1cfg0 = mfspr(SPRN_L1CFG0);
 		u32 l1cfg1 = mfspr(SPRN_L1CFG1);
 		u32 isize, iline_size, inum_sets, inum_ways;
 		u32 dsize, dline_size, dnum_sets, dnum_ways;
 		/* d-side config */
 		dsize = (l1cfg0 & 0x7ff) * 1024;
 		dnum_ways = ((l1cfg0 >> 11) & 0xff) + 1;
 		dline_size = (((l1cfg0 >> 23) & 0x3) + 1) * 32;
 		dnum_sets = dsize / (dline_size * dnum_ways);
 		fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size);
 		fdt_setprop_cell(blob, off, "d-cache-size", dsize);
 		fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets);
 #ifdef CONFIG_SYS_CACHE_STASHING
 		{
 			u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
 			if (reg)
 				fdt_setprop_cell(blob, off, "cache-stash-id",
 					 (*reg * 2) + 32 + 0);
 		}
 #endif
 		/* i-side config */
 		isize = (l1cfg1 & 0x7ff) * 1024;
 		inum_ways = ((l1cfg1 >> 11) & 0xff) + 1;
 		iline_size = (((l1cfg1 >> 23) & 0x3) + 1) * 32;
 		inum_sets = isize / (iline_size * inum_ways);
 		fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size);
 		fdt_setprop_cell(blob, off, "i-cache-size", isize);
 		fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets);
 		off = fdt_node_offset_by_prop_value(blob, off,
 				"device_type", "cpu", 4);
 	}
 	ft_fixup_l2cache(blob);
 }
 void fdt_add_enet_stashing(void *fdt)
 {
 	do_fixup_by_compat(fdt, "gianfar", "bd-stash", NULL, 0, 1);
 	do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-len", 96, 1);
 	do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1);
 	do_fixup_by_compat(fdt, "fsl,etsec2", "bd-stash", NULL, 0, 1);
 	do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-len", 96, 1);
 	do_fixup_by_compat_u32(fdt, "fsl,etsec2", "rx-stash-idx", 0, 1);
 }
 #if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME)
 #ifdef CONFIG_SYS_DPAA_FMAN
 static void ft_fixup_clks(void *blob, const char *compat, u32 offset,
 			  unsigned long freq)
 {
 	phys_addr_t phys = offset + CONFIG_SYS_CCSRBAR_PHYS;
 	int off = fdt_node_offset_by_compat_reg(blob, compat, phys);
 	if (off >= 0) {
 		off = fdt_setprop_cell(blob, off, "clock-frequency", freq);
 		if (off > 0)
 			printf("WARNING enable to set clock-frequency "
 				"for %s: %s\n", compat, fdt_strerror(off));
 	}
 }
 #endif
 static void ft_fixup_dpaa_clks(void *blob)
 {
 	sys_info_t sysinfo;
 	get_sys_info(&sysinfo);
 #ifdef CONFIG_SYS_DPAA_FMAN
 	ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET,
 			sysinfo.freq_fman[0]);
 #if (CONFIG_SYS_NUM_FMAN == 2)
 	ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET,
 			sysinfo.freq_fman[1]);
 #endif
 #endif
 #ifdef CONFIG_SYS_DPAA_QBMAN
 	do_fixup_by_compat_u32(blob, "fsl,qman",
 			"clock-frequency", sysinfo.freq_qman, 1);
 #endif
 #ifdef CONFIG_SYS_DPAA_PME
 	do_fixup_by_compat_u32(blob, "fsl,pme",
 		"clock-frequency", sysinfo.freq_pme, 1);
 #endif
 }
 #else
 #define ft_fixup_dpaa_clks(x)
 #endif
 #ifdef CONFIG_QE
 static void ft_fixup_qe_snum(void *blob)
 {
 	unsigned int svr;
 	svr = mfspr(SPRN_SVR);
 	if (SVR_SOC_VER(svr) == SVR_8569) {
 		if(IS_SVR_REV(svr, 1, 0))
 			do_fixup_by_compat_u32(blob, "fsl,qe",
 				"fsl,qe-num-snums", 46, 1);
 		else
 			do_fixup_by_compat_u32(blob, "fsl,qe",
 				"fsl,qe-num-snums", 76, 1);
 	}
 }
 #endif
 #if defined(CONFIG_ARCH_P4080)
 static void fdt_fixup_usb(void *fdt)
 {
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
 	int off;
 	off = fdt_node_offset_by_compatible(fdt, -1, "fsl,mpc85xx-usb2-mph");
 	if ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) !=
 				FSL_CORENET_RCWSR11_EC1_FM1_USB1)
 		fdt_status_disabled(fdt, off);
 	off = fdt_node_offset_by_compatible(fdt, -1, "fsl,mpc85xx-usb2-dr");
 	if ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) !=
 				FSL_CORENET_RCWSR11_EC2_USB2)
 		fdt_status_disabled(fdt, off);
 }
 #else
 #define fdt_fixup_usb(x)
 #endif
 #if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T4240) || \
 	defined(CONFIG_ARCH_T4160)
 void fdt_fixup_dma3(void *blob)
 {
 	/* the 3rd DMA is not functional if SRIO2 is chosen */
 	int nodeoff;
 	ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #define CONFIG_SYS_ELO3_DMA3 (0xffe000000 + 0x102300)
 #if defined(CONFIG_ARCH_T2080)
 	u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
 				    FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
 	srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 	switch (srds_prtcl_s2) {
 	case 0x29:
 	case 0x2d:
 	case 0x2e:
 #elif defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
 	u32 srds_prtcl_s4 = in_be32(&gur->rcwsr[4]) &
 				    FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
 	srds_prtcl_s4 >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
 	switch (srds_prtcl_s4) {
 	case 6:
 	case 8:
 	case 14:
 	case 16:
 #endif
 		nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,elo3-dma",
 							CONFIG_SYS_ELO3_DMA3);
 		if (nodeoff > 0)
 			fdt_status_disabled(blob, nodeoff);
 		else
 			printf("WARNING: unable to disable dma3\n");
 		break;
 	default:
 		break;
 	}
 }
 #else
 #define fdt_fixup_dma3(x)
 #endif
 #if defined(CONFIG_ARCH_T1040)
 static void fdt_fixup_l2_switch(void *blob)
 {
 	uchar l2swaddr[6];
 	int node;
 	/* The l2switch node from device-tree has
 	 * compatible string "vitesse-9953" */
 	node = fdt_node_offset_by_compatible(blob, -1, "vitesse-9953");
 	if (node == -FDT_ERR_NOTFOUND)
 		/* no l2switch node has been found */
 		return;
 	/* Get MAC address for the l2switch from "l2switchaddr"*/
 	if (!eth_env_get_enetaddr("l2switchaddr", l2swaddr)) {
 		printf("Warning: MAC address for l2switch not found\n");
 		memset(l2swaddr, 0, sizeof(l2swaddr));
 	}
 	/* Add MAC address to l2switch node */
 	fdt_setprop(blob, node, "local-mac-address", l2swaddr,
 		    sizeof(l2swaddr));
 }
 #else
 #define fdt_fixup_l2_switch(x)
 #endif
 void ft_cpu_setup(void *blob, bd_t *bd)
 {
 	int off;
 	int val;
 	int len;
 	sys_info_t sysinfo;
 	/* delete crypto node if not on an E-processor */
 	if (!IS_E_PROCESSOR(get_svr()))
 		fdt_fixup_crypto_node(blob, 0);
 #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
 	else {
 		ccsr_sec_t __iomem *sec;
 		sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
 		fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
 	}
 #endif
 	fdt_add_enet_stashing(blob);
 #ifndef CONFIG_FSL_TBCLK_EXTRA_DIV
 #define CONFIG_FSL_TBCLK_EXTRA_DIV 1
 #endif
 	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
 		"timebase-frequency", get_tbclk() / CONFIG_FSL_TBCLK_EXTRA_DIV,
 		1);
 	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
 		"bus-frequency", bd->bi_busfreq, 1);
 	get_sys_info(&sysinfo);
 	off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
 	while (off != -FDT_ERR_NOTFOUND) {
 		u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", &len);
 		val = cpu_to_fdt32(sysinfo.freq_processor[(*reg) / (len / 4)]);
 		fdt_setprop(blob, off, "clock-frequency", &val, 4);
 		off = fdt_node_offset_by_prop_value(blob, off, "device_type",
 							"cpu", 4);
 	}
 	do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
 		"bus-frequency", bd->bi_busfreq, 1);
 #ifdef CONFIG_QE
 	ft_qe_setup(blob);
 	ft_fixup_qe_snum(blob);
 #endif
 #ifdef CONFIG_SYS_DPAA_FMAN
 	fdt_fixup_fman_firmware(blob);
 #endif
 #ifdef CONFIG_SYS_NS16550
 	do_fixup_by_compat_u32(blob, "ns16550",
 		"clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
 #endif
 #ifdef CONFIG_CPM2
 	do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart",
 		"current-speed", gd->baudrate, 1);
 	do_fixup_by_compat_u32(blob, "fsl,cpm2-brg",
 		"clock-frequency", bd->bi_brgfreq, 1);
 #endif
 #ifdef CONFIG_FSL_CORENET
 	do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0",
 		"clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
 	do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-2.0",
 		"clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
 	do_fixup_by_compat_u32(blob, "fsl,mpic",
 		"clock-frequency", get_bus_freq(0)/2, 1);
 #else
 	do_fixup_by_compat_u32(blob, "fsl,mpic",
 		"clock-frequency", get_bus_freq(0), 1);
 #endif
 	fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
 #ifdef CONFIG_MP
 	ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize);
 	ft_fixup_num_cores(blob);
 #endif
 	ft_fixup_cache(blob);
 #if defined(CONFIG_FSL_ESDHC)
 	fdt_fixup_esdhc(blob, bd);
 #endif
 	ft_fixup_dpaa_clks(blob);
 #if defined(CONFIG_SYS_BMAN_MEM_PHYS)
 	fdt_portal(blob, "fsl,bman-portal", "bman-portals",
 			(u64)CONFIG_SYS_BMAN_MEM_PHYS,
 			CONFIG_SYS_BMAN_MEM_SIZE);
 	fdt_fixup_bportals(blob);
 #endif
 #if defined(CONFIG_SYS_QMAN_MEM_PHYS)
 	fdt_portal(blob, "fsl,qman-portal", "qman-portals",
 			(u64)CONFIG_SYS_QMAN_MEM_PHYS,
 			CONFIG_SYS_QMAN_MEM_SIZE);
 	fdt_fixup_qportals(blob);
 #endif
 #ifdef CONFIG_SYS_SRIO
 	ft_srio_setup(blob);
 #endif
 	/*
 	 * system-clock = CCB clock/2
 	 * Here gd->bus_clk = CCB clock
 	 * We are using the system clock as 1588 Timer reference
 	 * clock source select
 	 */
 	do_fixup_by_compat_u32(blob, "fsl,gianfar-ptp-timer",
 			"timer-frequency", gd->bus_clk/2, 1);
 	/*
 	 * clock-freq should change to clock-frequency and
 	 * flexcan-v1.0 should change to p1010-flexcan respectively
 	 * in the future.
 	 */
 	do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0",
 			"clock_freq", gd->bus_clk/2, 1);
 	do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0",
 			"clock-frequency", gd->bus_clk/2, 1);
 	do_fixup_by_compat_u32(blob, "fsl,p1010-flexcan",
 			"clock-frequency", gd->bus_clk/2, 1);
 	fdt_fixup_usb(blob);
 	fdt_fixup_l2_switch(blob);
 	fdt_fixup_dma3(blob);
 }
 /*
  * For some CCSR devices, we only have the virtual address, not the physical
  * address.  This is because we map CCSR as a whole, so we typically don't need
  * a macro for the physical address of any device within CCSR.  In this case,
  * we calculate the physical address of that device using it's the difference
  * between the virtual address of the device and the virtual address of the
  * beginning of CCSR.
  */
 #define CCSR_VIRT_TO_PHYS(x) \
 	(CONFIG_SYS_CCSRBAR_PHYS + ((x) - CONFIG_SYS_CCSRBAR))
 static void msg(const char *name, uint64_t uaddr, uint64_t daddr)
 {
 	printf("Warning: U-Boot configured %s at address %llx,\n"
 	       "but the device tree has it at %llx\n", name, uaddr, daddr);
 }
 /*
  * Verify the device tree
  *
  * This function compares several CONFIG_xxx macros that contain physical
  * addresses with the corresponding nodes in the device tree, to see if
  * the physical addresses are all correct.  For example, if
  * CONFIG_SYS_NS16550_COM1 is defined, then it contains the virtual address
  * of the first UART.  We convert this to a physical address and compare
  * that with the physical address of the first ns16550-compatible node
  * in the device tree.  If they don't match, then we display a warning.
  *
  * Returns 1 on success, 0 on failure
  */
 int ft_verify_fdt(void *fdt)
 {
 	uint64_t addr = 0;
 	int aliases;
 	int off;
 	/* First check the CCSR base address */
 	off = fdt_node_offset_by_prop_value(fdt, -1, "device_type", "soc", 4);
 	if (off > 0) {
 		int size;
 		u32 naddr;
 		const fdt32_t *prop;
 		naddr = fdt_address_cells(fdt, off);
 		prop = fdt_getprop(fdt, off, "ranges", &size);
 		addr = fdt_translate_address(fdt, off, prop + naddr);
 	}
 	if (!addr) {
 		printf("Warning: could not determine base CCSR address in "
 		       "device tree\n");
 		/* No point in checking anything else */
 		return 0;
 	}
 	if (addr != CONFIG_SYS_CCSRBAR_PHYS) {
 		msg("CCSR", CONFIG_SYS_CCSRBAR_PHYS, addr);
 		/* No point in checking anything else */
 		return 0;
 	}
 	/*
 	 * Check some nodes via aliases.  We assume that U-Boot and the device
 	 * tree enumerate the devices equally.  E.g. the first serial port in
 	 * U-Boot is the same as "serial0" in the device tree.
 	 */
 	aliases = fdt_path_offset(fdt, "/aliases");
 	if (aliases > 0) {
 #ifdef CONFIG_SYS_NS16550_COM1
 		if (!fdt_verify_alias_address(fdt, aliases, "serial0",
 			CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM1)))
 			return 0;
 #endif
 #ifdef CONFIG_SYS_NS16550_COM2
 		if (!fdt_verify_alias_address(fdt, aliases, "serial1",
 			CCSR_VIRT_TO_PHYS(CONFIG_SYS_NS16550_COM2)))
 			return 0;
 #endif
 	}
 	/*
 	 * The localbus node is typically a root node, even though the lbc
 	 * controller is part of CCSR.  If we were to put the lbc node under
 	 * the SOC node, then the 'ranges' property in the lbc node would
 	 * translate through the 'ranges' property of the parent SOC node, and
 	 * we don't want that.  Since it's a separate node, it's possible for
 	 * the 'reg' property to be wrong, so check it here.  For now, we
 	 * only check for "fsl,elbc" nodes.
 	 */
 #ifdef CONFIG_SYS_LBC_ADDR
 	off = fdt_node_offset_by_compatible(fdt, -1, "fsl,elbc");
 	if (off > 0) {
 		const fdt32_t *reg = fdt_getprop(fdt, off, "reg", NULL);
 		if (reg) {
 			uint64_t uaddr = CCSR_VIRT_TO_PHYS(CONFIG_SYS_LBC_ADDR);
 			addr = fdt_translate_address(fdt, off, reg);
 			if (uaddr != addr) {
 				msg("the localbus", uaddr, addr);
 				return 0;
 			}
 		}
 	}
 #endif
 	return 1;
 }
 void fdt_del_diu(void *blob)
 {
 	int nodeoff = 0;
 	while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 				"fsl,diu")) >= 0) {
 		fdt_del_node(blob, nodeoff);
 	}
 }

arch/powerpc/cpu/mpc85xx/portals.c

Diff comments View file @ 4426232

1	/*	1	/*
2	* Copyright 2008-2011 Freescale Semiconductor, Inc.	2	* Copyright 2008-2011 Freescale Semiconductor, Inc.
3	*	3	*
4	* SPDX-License-Identifier: GPL-2.0+	4	* SPDX-License-Identifier: GPL-2.0+
5	*/	5	*/
6		6
7	#include <common.h>	7	#include <common.h>
8	#include <libfdt.h>	8	#include <libfdt.h>
9	#include <fdt_support.h>	9	#include <fdt_support.h>
10		10
11	#include <asm/processor.h>	11	#include <asm/processor.h>
12	#include <asm/io.h>	12	#include <asm/io.h>
13		13
14	#include <asm/fsl_portals.h>	14	#include <asm/fsl_portals.h>
15	#include <asm/fsl_liodn.h>	15	#include <asm/fsl_liodn.h>
16		16
17	#define MAX_BPORTALS (CONFIG_SYS_BMAN_CINH_SIZE / CONFIG_SYS_BMAN_SP_CINH_SIZE)
18	#define MAX_QPORTALS (CONFIG_SYS_QMAN_CINH_SIZE / CONFIG_SYS_QMAN_SP_CINH_SIZE)
19	static void inhibit_portals(void __iomem *addr, int max_portals,
20	int arch_max_portals, int portal_cinh_size)
21	{
22	uint32_t val;
23	int i;
24
25	/* arch_max_portals is the maximum based on memory size. This includes
26	* the reserved memory in the SoC. max_portals the number of physical
27	* portals in the SoC */
28	if (max_portals > arch_max_portals) {
29	printf("ERROR: portal config error\n");
30	max_portals = arch_max_portals;
31	}
32
33	for (i = 0; i < max_portals; i++) {
34	out_be32(addr, -1);
35	val = in_be32(addr);
36	if (!val) {
37	printf("ERROR: Stopped after %d portals\n", i);
38	goto done;
39	}
40	addr += portal_cinh_size;
41	}
42	#ifdef DEBUG
43	printf("Cleared %d portals\n", i);
44	#endif
45	done:
46
47	return;
48	}
49
50	void setup_portals(void)
51	{
52	ccsr_qman_t qman = (void )CONFIG_SYS_FSL_QMAN_ADDR;
53	void __iomem bpaddr = (void )CONFIG_SYS_BMAN_CINH_BASE +
54	CONFIG_SYS_BMAN_SWP_ISDR_REG;
55	void __iomem qpaddr = (void )CONFIG_SYS_QMAN_CINH_BASE +
56	CONFIG_SYS_QMAN_SWP_ISDR_REG;
57	#ifdef CONFIG_FSL_CORENET
58	int i;
59
60	for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) {
61	u8 sdest = qp_info[i].sdest;
62	u16 fliodn = qp_info[i].fliodn;
63	u16 dliodn = qp_info[i].dliodn;
64	u16 liodn_off = qp_info[i].liodn_offset;
65
66	out_be32(&qman->qcsp[i].qcsp_lio_cfg, (liodn_off << 16) \|
67	dliodn);
68	/* set frame liodn */
69	out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) \| fliodn);
70	}
71	#endif
72
73	/* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */
74	#ifdef CONFIG_PHYS_64BIT
75	out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32));
76	#endif
77	out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS);
78
79	/* Change default state of BMan ISDR portals to all 1s */
80	inhibit_portals(bpaddr, CONFIG_SYS_BMAN_NUM_PORTALS, MAX_BPORTALS,
81	CONFIG_SYS_BMAN_SP_CINH_SIZE);
82	inhibit_portals(qpaddr, CONFIG_SYS_QMAN_NUM_PORTALS, MAX_QPORTALS,
83	CONFIG_SYS_QMAN_SP_CINH_SIZE);
84	}
85
86	/* Update portal containter to match LAW setup of portal in phy map */	17	/* Update portal containter to match LAW setup of portal in phy map */
87	void fdt_portal(void blob, const char compat, const char *container,	18	void fdt_portal(void blob, const char compat, const char *container,
88	u64 addr, u32 size)	19	u64 addr, u32 size)
89	{	20	{
90	int off;	21	int off;
91		22
92	off = fdt_node_offset_by_compatible(blob, -1, compat);	23	off = fdt_node_offset_by_compatible(blob, -1, compat);
93	if (off < 0)	24	if (off < 0)
94	return ;	25	return ;
95		26
96	off = fdt_parent_offset(blob, off);	27	off = fdt_parent_offset(blob, off);
97	/* if non-zero assume we have a container */	28	/* if non-zero assume we have a container */
98	if (off > 0) {	29	if (off > 0) {
99	char buf[60];	30	char buf[60];
100	const char p, name;	31	const char p, name;
101	u32 *range;	32	u32 *range;
102	int len;	33	int len;
103		34
104	/* fixup ranges */	35	/* fixup ranges */
105	range = fdt_getprop_w(blob, off, "ranges", &len);	36	range = fdt_getprop_w(blob, off, "ranges", &len);
106	if (range == NULL) {	37	if (range == NULL) {
107	printf("ERROR: container for %s has no ranges", compat);	38	printf("ERROR: container for %s has no ranges", compat);
108	return ;	39	return ;
109	}	40	}
110		41
111	range[0] = 0;	42	range[0] = 0;
112	if (len == 16) {	43	if (len == 16) {
113	range[1] = addr >> 32;	44	range[1] = addr >> 32;
114	range[2] = addr & 0xffffffff;	45	range[2] = addr & 0xffffffff;
115	range[3] = size;	46	range[3] = size;
116	} else {	47	} else {
117	range[1] = addr & 0xffffffff;	48	range[1] = addr & 0xffffffff;
118	range[2] = size;	49	range[2] = size;
119	}	50	}
120	fdt_setprop_inplace(blob, off, "ranges", range, len);	51	fdt_setprop_inplace(blob, off, "ranges", range, len);
121		52
122	/* fixup the name */	53	/* fixup the name */
123	name = fdt_get_name(blob, off, &len);	54	name = fdt_get_name(blob, off, &len);
124	p = memchr(name, '@', len);	55	p = memchr(name, '@', len);
125		56
126	if (p)	57	if (p)
127	len = p - name;	58	len = p - name;
128		59
129	/* if we are given a container name check it	60	/* if we are given a container name check it
130	* against what we found, if it doesnt match exit out */	61	* against what we found, if it doesnt match exit out */
131	if (container && (memcmp(container, name, len))) {	62	if (container && (memcmp(container, name, len))) {
132	printf("WARNING: container names didn't match %s %s\n",	63	printf("WARNING: container names didn't match %s %s\n",
133	container, name);	64	container, name);
134	return ;	65	return ;
135	}	66	}
136		67
137	memcpy(&buf, name, len);	68	memcpy(&buf, name, len);
138	len += sprintf(&buf[len], "@%llx", addr);	69	len += sprintf(&buf[len], "@%llx", addr);
139	fdt_set_name(blob, off, buf);	70	fdt_set_name(blob, off, buf);
140	return ;	71	return ;
141	}	72	}
142		73
143	printf("ERROR: %s isn't in a container. Not supported\n", compat);	74	printf("ERROR: %s isn't in a container. Not supported\n", compat);
144	}
145
146	static int fdt_qportal(void blob, int off, int id, char name,
147	enum fsl_dpaa_dev dev, int create)
148	{
149	int childoff, dev_off, ret = 0;
150	uint32_t dev_handle;
151	#ifdef CONFIG_FSL_CORENET
152	int num;
153	u32 liodns[2];
154	#endif
155
156	childoff = fdt_subnode_offset(blob, off, name);
157	if (create) {
158	char handle[64], *p;
159
160	strncpy(handle, name, sizeof(handle));
161	p = strchr(handle, '@');
162	if (!strncmp(name, "fman", 4)) {
163	p = (p + 1);
164	p++;
165	}
166	*p = '\0';
167
168	dev_off = fdt_path_offset(blob, handle);
169	/* skip this node if alias is not found */
170	if (dev_off == -FDT_ERR_BADPATH)
171	return 0;
172	if (dev_off < 0)
173	return dev_off;
174
175	if (childoff <= 0)
176	childoff = fdt_add_subnode(blob, off, name);
177
178	/* need to update the dev_off after adding a subnode */
179	dev_off = fdt_path_offset(blob, handle);
180	if (dev_off < 0)
181	return dev_off;
182
183	if (childoff > 0) {
184	dev_handle = fdt_get_phandle(blob, dev_off);
185	if (dev_handle <= 0) {
186	dev_handle = fdt_alloc_phandle(blob);
187	ret = fdt_set_phandle(blob, dev_off,
188	dev_handle);
189	if (ret < 0)
190	return ret;
191	}
192
193	ret = fdt_setprop(blob, childoff, "dev-handle",
194	&dev_handle, sizeof(dev_handle));
195	if (ret < 0)
196	return ret;
197
198	#ifdef CONFIG_FSL_CORENET
199	num = get_dpaa_liodn(dev, &liodns[0], id);
200	ret = fdt_setprop(blob, childoff, "fsl,liodn",
201	&liodns[0], sizeof(u32) * num);
202	if (!strncmp(name, "pme", 3)) {
203	u32 pme_rev1, pme_rev2;
204	ccsr_pme_t *pme_regs =
205	(void *)CONFIG_SYS_FSL_CORENET_PME_ADDR;
206
207	pme_rev1 = in_be32(&pme_regs->pm_ip_rev_1);
208	pme_rev2 = in_be32(&pme_regs->pm_ip_rev_2);
209	ret = fdt_setprop(blob, childoff,
210	"fsl,pme-rev1", &pme_rev1, sizeof(u32));
211	if (ret < 0)
212	return ret;
213	ret = fdt_setprop(blob, childoff,
214	"fsl,pme-rev2", &pme_rev2, sizeof(u32));
215	}
216	#endif
217	} else {
218	return childoff;
219	}
220	} else {
221	if (childoff > 0)
222	ret = fdt_del_node(blob, childoff);
223	}
224
225	return ret;
226	}
227
228	void fdt_fixup_qportals(void *blob)
229	{
230	int off, err;
231	unsigned int maj, min;
232	unsigned int ip_cfg;
233	ccsr_qman_t qman = (void )CONFIG_SYS_FSL_QMAN_ADDR;
234	u32 rev_1 = in_be32(&qman->ip_rev_1);
235	u32 rev_2 = in_be32(&qman->ip_rev_2);
236	char compat[64];
237	int compat_len;
238
239	maj = (rev_1 >> 8) & 0xff;
240	min = rev_1 & 0xff;
241	ip_cfg = rev_2 & 0xff;
242
243	compat_len = sprintf(compat, "fsl,qman-portal-%u.%u.%u",
244	maj, min, ip_cfg) + 1;
245	compat_len += sprintf(compat + compat_len, "fsl,qman-portal") + 1;
246
247	off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal");
248	while (off != -FDT_ERR_NOTFOUND) {
249	#ifdef CONFIG_FSL_CORENET
250	u32 liodns[2];
251	#endif
252	const int *ci = fdt_getprop(blob, off, "cell-index", &err);
253	int i;
254
255	if (!ci)
256	goto err;
257
258	i = *ci;
259	#ifdef CONFIG_SYS_DPAA_FMAN
260	int j;
261	#endif
262
263	err = fdt_setprop(blob, off, "compatible", compat, compat_len);
264	if (err < 0)
265	goto err;
266
267	#ifdef CONFIG_FSL_CORENET
268	liodns[0] = qp_info[i].dliodn;
269	liodns[1] = qp_info[i].fliodn;
270
271	err = fdt_setprop(blob, off, "fsl,liodn",
272	&liodns, sizeof(u32) * 2);
273	if (err < 0)
274	goto err;
275	#endif
276
277	i++;
278
279	err = fdt_qportal(blob, off, i, "crypto@0", FSL_HW_PORTAL_SEC,
280	IS_E_PROCESSOR(get_svr()));
281	if (err < 0)
282	goto err;
283
284	#ifdef CONFIG_FSL_CORENET
285	#ifdef CONFIG_SYS_DPAA_PME
286	err = fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 1);
287	if (err < 0)
288	goto err;
289	#else
290	fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 0);
291	#endif
292	#endif
293
294	#ifdef CONFIG_SYS_DPAA_FMAN
295	for (j = 0; j < CONFIG_SYS_NUM_FMAN; j++) {
296	char name[] = "fman@0";
297
298	name[sizeof(name) - 2] = '0' + j;
299	err = fdt_qportal(blob, off, i, name,
300	FSL_HW_PORTAL_FMAN1 + j, 1);
301	if (err < 0)
302	goto err;
303	}
304	#endif
305	#ifdef CONFIG_SYS_DPAA_RMAN
306	err = fdt_qportal(blob, off, i, "rman@0",
307	FSL_HW_PORTAL_RMAN, 1);
308	if (err < 0)
309	goto err;
310	#endif
311
312	err:
313	if (err < 0) {
314	printf("ERROR: unable to create props for %s: %s\n",
315	fdt_get_name(blob, off, NULL), fdt_strerror(err));
316	return;
317	}
318
319	off = fdt_node_offset_by_compatible(blob, off, "fsl,qman-portal");
320	}
321	}
322
323	void fdt_fixup_bportals(void *blob)
324	{
325	int off, err;
326	unsigned int maj, min;
327	unsigned int ip_cfg;
328	ccsr_bman_t bman = (void )CONFIG_SYS_FSL_BMAN_ADDR;
329	u32 rev_1 = in_be32(&bman->ip_rev_1);
330	u32 rev_2 = in_be32(&bman->ip_rev_2);
331	char compat[64];
332	int compat_len;
333
334	maj = (rev_1 >> 8) & 0xff;
335	min = rev_1 & 0xff;
336
337	ip_cfg = rev_2 & 0xff;
338
339	compat_len = sprintf(compat, "fsl,bman-portal-%u.%u.%u",
340	maj, min, ip_cfg) + 1;
341	compat_len += sprintf(compat + compat_len, "fsl,bman-portal") + 1;
342
343	off = fdt_node_offset_by_compatible(blob, -1, "fsl,bman-portal");
344	while (off != -FDT_ERR_NOTFOUND) {
345	err = fdt_setprop(blob, off, "compatible", compat, compat_len);
346	if (err < 0) {
347	printf("ERROR: unable to create props for %s: %s\n",
348	fdt_get_name(blob, off, NULL),
349	fdt_strerror(err));
350	return;
351	}
352
353	off = fdt_node_offset_by_compatible(blob, off, "fsl,bman-portal");
354	}
355
356	}	75	}
357		76

arch/powerpc/include/asm/fsl_liodn.h

Diff comments View file @ 4426232

 /*
  * Copyright 2009-2011 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef _FSL_LIODN_H_
 #define _FSL_LIODN_H_
 #include <asm/types.h>
+#include <fsl_qbman.h>
 struct srio_liodn_id_table {
 	u32 id[2];
 	unsigned long reg_offset[2];
 	u8 num_ids;
 	u8 portid;
 };
 #define SET_SRIO_LIODN_1(port, idA) \
 	{ .id = { idA }, .num_ids = 1, .portid = port, \
 	  .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \
 		+ CONFIG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
 	}
 #define SET_SRIO_LIODN_2(port, idA, idB) \
 	{ .id = { idA, idB }, .num_ids = 2, .portid = port, \
 	  .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \
 		+ CONFIG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
 	  .reg_offset[1] = offsetof(ccsr_gur_t, rio##port##maintliodnr) \
 		+ CONFIG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \
 	}
 #define SET_SRIO_LIODN_BASE(port, id_a) \
 	{ .id = { id_a }, .num_ids = 1, .portid = port, \
 	  .reg_offset[0] = offsetof(struct ccsr_rio, liodn) \
 		+ (port - 1) * 0x200 \
 		+ CONFIG_SYS_FSL_SRIO_ADDR, \
 	}
 struct liodn_id_table {
 	const char * compat;
 	u32 id[2];
 	u8 num_ids;
 	phys_addr_t compat_offset;
 	unsigned long reg_offset;
 };
 struct fman_liodn_id_table {
 	/* Freescale FMan Device Tree binding was updated for FMan.
 	 * We need to support both new and old compatibles in order not to
 	 * break backward compatibility.
 	 */
 	const char *compat[2];
 	u32 id[2];
 	u8 num_ids;
 	phys_addr_t compat_offset;
 	unsigned long reg_offset;
 };
 extern u32 get_ppid_liodn(int ppid_tbl_idx, int ppid);
 extern void set_liodns(void);
 extern void fdt_fixup_liodn(void *blob);
 #define SET_LIODN_BASE_1(idA) \
 	{ .id = { idA }, .num_ids = 1, }
 #define SET_LIODN_BASE_2(idA, idB) \
 	{ .id = { idA, idB }, .num_ids = 2 }
 #define SET_FMAN_LIODN_ENTRY(name1, name2, idA, off, compatoff)\
 	{ .compat[0] = name1, \
 	  .compat[1] = name2, \
 	  .id = { idA }, .num_ids = 1, \
 	  .reg_offset = off + CONFIG_SYS_CCSRBAR, \
 	  .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
 	}
 #define SET_LIODN_ENTRY_1(name, idA, off, compatoff) \
 	{ .compat = name, \
 	  .id = { idA }, .num_ids = 1, \
 	  .reg_offset = off + CONFIG_SYS_CCSRBAR, \
 	  .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
 	}
 #define SET_LIODN_ENTRY_2(name, idA, idB, off, compatoff) \
 	{ .compat = name, \
 	  .id = { idA, idB }, .num_ids = 2, \
 	  .reg_offset = off + CONFIG_SYS_CCSRBAR, \
 	  .compat_offset = compatoff + CONFIG_SYS_CCSRBAR_PHYS, \
 	}
 #define SET_GUTS_LIODN(compat, liodn, name, compatoff) \
 	SET_LIODN_ENTRY_1(compat, liodn, \
 		offsetof(ccsr_gur_t, name) + CONFIG_SYS_MPC85xx_GUTS_OFFSET, \
 		compatoff)
 #define SET_USB_LIODN(usbNum, compat, liodn) \
 	SET_GUTS_LIODN(compat, liodn, usb##usbNum##liodnr,\
 		CONFIG_SYS_MPC85xx_USB##usbNum##_OFFSET)
 #define SET_SATA_LIODN(sataNum, liodn) \
 	SET_GUTS_LIODN("fsl,pq-sata-v2", liodn, sata##sataNum##liodnr,\
 		CONFIG_SYS_MPC85xx_SATA##sataNum##_OFFSET)
 #define SET_PCI_LIODN(compat, pciNum, liodn) \
 	SET_GUTS_LIODN(compat, liodn, pex##pciNum##liodnr,\
 		CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
 #define SET_PCI_LIODN_BASE(compat, pciNum, liodn) \
 	SET_LIODN_ENTRY_1(compat, liodn,\
 		offsetof(ccsr_pcix_t, liodn_base) + CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET,\
 		CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
 /* reg nodes for DMA start @ 0x300 */
 #define SET_DMA_LIODN(dmaNum, compat, liodn) \
 	SET_GUTS_LIODN(compat, liodn, dma##dmaNum##liodnr,\
 		CONFIG_SYS_MPC85xx_DMA##dmaNum##_OFFSET + 0x300)
 #define SET_SDHC_LIODN(sdhcNum, liodn) \
 	SET_GUTS_LIODN("fsl,esdhc", liodn, sdmmc##sdhcNum##liodnr,\
 		CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
 #define SET_QE_LIODN(liodn) \
 	SET_GUTS_LIODN("fsl,qe", liodn, qeliodnr,\
 		CONFIG_SYS_MPC85xx_QE_OFFSET)
 #define SET_TDM_LIODN(liodn) \
 	SET_GUTS_LIODN("fsl,tdm1.0", liodn, tdmliodnr,\
 		CONFIG_SYS_MPC85xx_TDM_OFFSET)
 #define SET_QMAN_LIODN(liodn) \
-	SET_LIODN_ENTRY_1("fsl,qman", liodn, offsetof(ccsr_qman_t, liodnr) + \
+	SET_LIODN_ENTRY_1("fsl,qman", liodn, \
+		offsetof(struct ccsr_qman, liodnr) + \
 		CONFIG_SYS_FSL_QMAN_OFFSET, \
 		CONFIG_SYS_FSL_QMAN_OFFSET)
 #define SET_BMAN_LIODN(liodn) \
-	SET_LIODN_ENTRY_1("fsl,bman", liodn, offsetof(ccsr_bman_t, liodnr) + \
+	SET_LIODN_ENTRY_1("fsl,bman", liodn, \
+		offsetof(struct ccsr_bman, liodnr) + \
 		CONFIG_SYS_FSL_BMAN_OFFSET, \
 		CONFIG_SYS_FSL_BMAN_OFFSET)
 #define SET_PME_LIODN(liodn) \
 	SET_LIODN_ENTRY_1("fsl,pme", liodn, offsetof(ccsr_pme_t, liodnr) + \
 		CONFIG_SYS_FSL_CORENET_PME_OFFSET, \
 		CONFIG_SYS_FSL_CORENET_PME_OFFSET)
 #define SET_PMAN_LIODN(num, liodn) \
 	SET_LIODN_ENTRY_2("fsl,pman", liodn, 0, \
 		offsetof(struct ccsr_pman, ppa1) + \
 		CONFIG_SYS_FSL_CORENET_PMAN##num##_OFFSET, \
 		CONFIG_SYS_FSL_CORENET_PMAN##num##_OFFSET)
 /* -1 from portID due to how immap has the registers */
 #define FM_PPID_RX_PORT_OFFSET(fmNum, portID) \
 	CONFIG_SYS_FSL_FM##fmNum##_OFFSET + \
 	offsetof(struct ccsr_fman, fm_bmi_common.fmbm_ppid[portID - 1])
 #ifdef CONFIG_SYS_FMAN_V3
 /* enetNum is 0, 1, 2... so we + 8 for 1g to get to HW Port ID */
 #define SET_FMAN_RX_1G_LIODN(fmNum, enetNum, liodn) \
 	SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx", \
 		liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \
 		CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
 /* enetNum is 0, 1, 2... so we + 16 for 10g to get to HW Port ID */
 #define SET_FMAN_RX_10G_LIODN(fmNum, enetNum, liodn) \
 	SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx", \
 		liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \
 		CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET)
 /* enetNum is 0, 1, 2... so we + 8 for type-2 10g to get to HW Port ID */
 #define SET_FMAN_RX_10G_TYPE2_LIODN(fmNum, enetNum, liodn) \
 	SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx", \
 		liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \
 		CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
 #else
 /* enetNum is 0, 1, 2... so we + 8 for 1g to get to HW Port ID */
 #define SET_FMAN_RX_1G_LIODN(fmNum, enetNum, liodn) \
 	SET_FMAN_LIODN_ENTRY("fsl,fman-v2-port-rx", "fsl,fman-port-1g-rx", \
 		liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \
 		CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
 /* enetNum is 0, 1, 2... so we + 16 for 10g to get to HW Port ID */
 #define SET_FMAN_RX_10G_LIODN(fmNum, enetNum, liodn) \
 	SET_FMAN_LIODN_ENTRY("fsl,fman-v2-port-rx", "fsl,fman-port-10g-rx", \
 		liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \
 		CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET)
 #endif
 /*
  * handle both old and new versioned SEC properties:
  * "fsl,secX.Y" became "fsl,sec-vX.Y" during development
  */
 #define SET_SEC_JR_LIODN_ENTRY(jrNum, liodnA, liodnB) \
 	SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB,\
 		offsetof(ccsr_sec_t, jrliodnr[jrNum].ls) + \
 		CONFIG_SYS_FSL_SEC_OFFSET, \
 		CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum), \
 	SET_LIODN_ENTRY_2("fsl,sec-v4.0-job-ring", liodnA, liodnB,\
 		offsetof(ccsr_sec_t, jrliodnr[jrNum].ls) + \
 		CONFIG_SYS_FSL_SEC_OFFSET, \
 		CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum)
 /* This is a bit evil since we treat rtic param as both a string & hex value */
 #define SET_SEC_RTIC_LIODN_ENTRY(rtic, liodnA) \
 	SET_LIODN_ENTRY_1("fsl,sec4.0-rtic-memory", \
 		liodnA,	\
 		offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
 		CONFIG_SYS_FSL_SEC_OFFSET, \
 		CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \
 	SET_LIODN_ENTRY_1("fsl,sec-v4.0-rtic-memory", \
 		liodnA,	\
 		offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
 		CONFIG_SYS_FSL_SEC_OFFSET, \
 		CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa))
 #define SET_SEC_DECO_LIODN_ENTRY(num, liodnA, liodnB) \
 	SET_LIODN_ENTRY_2(NULL, liodnA, liodnB, \
 		offsetof(ccsr_sec_t, decoliodnr[num].ls) + \
 		CONFIG_SYS_FSL_SEC_OFFSET, 0)
 #define SET_RAID_ENGINE_JQ_LIODN_ENTRY(jqNum, rNum, liodnA) \
 	SET_LIODN_ENTRY_1("fsl,raideng-v1.0-job-ring", \
 	liodnA, \
 	offsetof(struct ccsr_raide, jq[jqNum].ring[rNum].cfg1) + \
 	CONFIG_SYS_FSL_RAID_ENGINE_OFFSET, \
 	offsetof(struct ccsr_raide, jq[jqNum].ring[rNum].cfg0) + \
 	CONFIG_SYS_FSL_RAID_ENGINE_OFFSET)
 #define SET_RMAN_LIODN(ibNum, liodn) \
 	SET_LIODN_ENTRY_1("fsl,rman-inbound-block", liodn, \
 		offsetof(struct ccsr_rman, mmitdr) + \
 		CONFIG_SYS_FSL_CORENET_RMAN_OFFSET, \
 		CONFIG_SYS_FSL_CORENET_RMAN_OFFSET + ibNum * 0x1000)
 extern struct liodn_id_table liodn_tbl[], liodn_bases[], sec_liodn_tbl[];
 extern struct liodn_id_table raide_liodn_tbl[];
 extern struct fman_liodn_id_table fman1_liodn_tbl[], fman2_liodn_tbl[];
 #ifdef CONFIG_SYS_SRIO
 extern struct srio_liodn_id_table srio_liodn_tbl[];
 extern int srio_liodn_tbl_sz;
 #endif
 extern struct liodn_id_table rman_liodn_tbl[];
 extern int liodn_tbl_sz, sec_liodn_tbl_sz, raide_liodn_tbl_sz;
 extern int fman1_liodn_tbl_sz, fman2_liodn_tbl_sz;
 extern int rman_liodn_tbl_sz;
 #endif

arch/powerpc/include/asm/fsl_portals.h

Diff comments View file @ 4426232

 /*
  * Copyright 2009-2011 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef _FSL_PORTALS_H_
 #define _FSL_PORTALS_H_
 /* entries must be in order and contiguous */
 enum fsl_dpaa_dev {
 	FSL_HW_PORTAL_SEC,
 #ifdef CONFIG_SYS_DPAA_FMAN
 	FSL_HW_PORTAL_FMAN1,
 #if (CONFIG_SYS_NUM_FMAN == 2)
 	FSL_HW_PORTAL_FMAN2,
 #endif
 #endif
 	FSL_HW_PORTAL_PME,
 #ifdef CONFIG_SYS_FSL_RAID_ENGINE
 	FSL_HW_PORTAL_RAID_ENGINE,
 #endif
 #ifdef CONFIG_SYS_DPAA_RMAN
 	FSL_HW_PORTAL_RMAN,
 #endif
 #ifdef CONFIG_SYS_DPAA_DCE
 	FSL_HW_PORTAL_DCE,
 #endif
 };
 struct qportal_info {
 	u16	dliodn;	/* DQRR LIODN */
 	u16	fliodn;	/* frame data LIODN */
 	u16	liodn_offset;
 	u8	sdest;
 };
 #define SET_QP_INFO(dqrr, fdata, off, dest) \
 	{ .dliodn = dqrr, .fliodn = fdata, .liodn_offset = off, .sdest = dest }
 extern int get_dpaa_liodn(enum fsl_dpaa_dev dpaa_dev,
 			  u32 *liodns, int liodn_offset);
-extern void setup_portals(void);
-extern void fdt_fixup_qportals(void *blob);
-extern void fdt_fixup_bportals(void *blob);
 extern struct qportal_info qp_info[];
 extern void fdt_portal(void *blob, const char *compat, const char *container,
 			u64 addr, u32 size);
 #endif

arch/powerpc/include/asm/immap_85xx.h

Diff comments View file @ 4426232

 /*
  * MPC85xx Internal Memory Map
  *
  * Copyright 2007-2012 Freescale Semiconductor, Inc.
  *
  * Copyright(c) 2002,2003 Motorola Inc.
  * Xianghua Xiao (x.xiao@motorola.com)
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef __IMMAP_85xx__
 #define __IMMAP_85xx__
 #include <asm/types.h>
 #include <asm/fsl_dma.h>
 #include <asm/fsl_i2c.h>
 #include <fsl_ifc.h>
 #include <fsl_sec.h>
 #include <fsl_sfp.h>
 #include <asm/fsl_lbc.h>
 #include <fsl_fman.h>
 #include <fsl_immap.h>
 typedef struct ccsr_local {
 	u32	ccsrbarh;	/* CCSR Base Addr High */
 	u32	ccsrbarl;	/* CCSR Base Addr Low */
 	u32	ccsrar;		/* CCSR Attr */
 #define CCSRAR_C	0x80000000	/* Commit */
 	u8	res1[4];
 	u32	altcbarh;	/* Alternate Configuration Base Addr High */
 	u32	altcbarl;	/* Alternate Configuration Base Addr Low */
 	u32	altcar;		/* Alternate Configuration Attr */
 	u8	res2[4];
 	u32	bstrh;		/* Boot space translation high */
 	u32	bstrl;		/* Boot space translation Low */
 	u32	bstrar;		/* Boot space translation attributes */
 	u8	res3[0xbd4];
 	struct {
 		u32	lawbarh;	/* LAWn base addr high */
 		u32	lawbarl;	/* LAWn base addr low */
 		u32	lawar;		/* LAWn attributes */
 		u8	res4[4];
 	} law[32];
 	u8	res35[0x204];
 } ccsr_local_t;
 /* Local-Access Registers & ECM Registers */
 typedef struct ccsr_local_ecm {
 	u32	ccsrbar;	/* CCSR Base Addr */
 	u8	res1[4];
 	u32	altcbar;	/* Alternate Configuration Base Addr */
 	u8	res2[4];
 	u32	altcar;		/* Alternate Configuration Attr */
 	u8	res3[12];
 	u32	bptr;		/* Boot Page Translation */
 	u8	res4[3044];
 	u32	lawbar0;	/* Local Access Window 0 Base Addr */
 	u8	res5[4];
 	u32	lawar0;		/* Local Access Window 0 Attrs */
 	u8	res6[20];
 	u32	lawbar1;	/* Local Access Window 1 Base Addr */
 	u8	res7[4];
 	u32	lawar1;		/* Local Access Window 1 Attrs */
 	u8	res8[20];
 	u32	lawbar2;	/* Local Access Window 2 Base Addr */
 	u8	res9[4];
 	u32	lawar2;		/* Local Access Window 2 Attrs */
 	u8	res10[20];
 	u32	lawbar3;	/* Local Access Window 3 Base Addr */
 	u8	res11[4];
 	u32	lawar3;		/* Local Access Window 3 Attrs */
 	u8	res12[20];
 	u32	lawbar4;	/* Local Access Window 4 Base Addr */
 	u8	res13[4];
 	u32	lawar4;		/* Local Access Window 4 Attrs */
 	u8	res14[20];
 	u32	lawbar5;	/* Local Access Window 5 Base Addr */
 	u8	res15[4];
 	u32	lawar5;		/* Local Access Window 5 Attrs */
 	u8	res16[20];
 	u32	lawbar6;	/* Local Access Window 6 Base Addr */
 	u8	res17[4];
 	u32	lawar6;		/* Local Access Window 6 Attrs */
 	u8	res18[20];
 	u32	lawbar7;	/* Local Access Window 7 Base Addr */
 	u8	res19[4];
 	u32	lawar7;		/* Local Access Window 7 Attrs */
 	u8	res19_8a[20];
 	u32	lawbar8;	/* Local Access Window 8 Base Addr */
 	u8	res19_8b[4];
 	u32	lawar8;		/* Local Access Window 8 Attrs */
 	u8	res19_9a[20];
 	u32	lawbar9;	/* Local Access Window 9 Base Addr */
 	u8	res19_9b[4];
 	u32	lawar9;		/* Local Access Window 9 Attrs */
 	u8	res19_10a[20];
 	u32	lawbar10;	/* Local Access Window 10 Base Addr */
 	u8	res19_10b[4];
 	u32	lawar10;	/* Local Access Window 10 Attrs */
 	u8	res19_11a[20];
 	u32	lawbar11;	/* Local Access Window 11 Base Addr */
 	u8	res19_11b[4];
 	u32	lawar11;	/* Local Access Window 11 Attrs */
 	u8	res20[652];
 	u32	eebacr;		/* ECM CCB Addr Configuration */
 	u8	res21[12];
 	u32	eebpcr;		/* ECM CCB Port Configuration */
 	u8	res22[3564];
 	u32	eedr;		/* ECM Error Detect */
 	u8	res23[4];
 	u32	eeer;		/* ECM Error Enable */
 	u32	eeatr;		/* ECM Error Attrs Capture */
 	u32	eeadr;		/* ECM Error Addr Capture */
 	u8	res24[492];
 } ccsr_local_ecm_t;
 #define DDR_EOR_RD_BDW_OPT_DIS	0x80000000 /* Read BDW Opt. disable */
 #define DDR_EOR_ADDR_HASH_EN	0x40000000 /* Address hash enabled */
 /* I2C Registers */
 typedef struct ccsr_i2c {
 	struct fsl_i2c_base	i2c[1];
 	u8	res[4096 - 1 * sizeof(struct fsl_i2c_base)];
 } ccsr_i2c_t;
 #if defined(CONFIG_ARCH_MPC8540) || \
 	defined(CONFIG_ARCH_MPC8541) || \
 	defined(CONFIG_ARCH_MPC8548) || \
 	defined(CONFIG_ARCH_MPC8555)
 /* DUART Registers */
 typedef struct ccsr_duart {
 	u8	res1[1280];
 /* URBR1, UTHR1, UDLB1 with the same addr */
 	u8	urbr1_uthr1_udlb1;
 /* UIER1, UDMB1 with the same addr01 */
 	u8	uier1_udmb1;
 /* UIIR1, UFCR1, UAFR1 with the same addr */
 	u8	uiir1_ufcr1_uafr1;
 	u8	ulcr1;		/* UART1 Line Control */
 	u8	umcr1;		/* UART1 Modem Control */
 	u8	ulsr1;		/* UART1 Line Status */
 	u8	umsr1;		/* UART1 Modem Status */
 	u8	uscr1;		/* UART1 Scratch */
 	u8	res2[8];
 	u8	udsr1;		/* UART1 DMA Status */
 	u8	res3[239];
 /* URBR2, UTHR2, UDLB2 with the same addr */
 	u8	urbr2_uthr2_udlb2;
 /* UIER2, UDMB2 with the same addr */
 	u8	uier2_udmb2;
 /* UIIR2, UFCR2, UAFR2 with the same addr */
 	u8	uiir2_ufcr2_uafr2;
 	u8	ulcr2;		/* UART2 Line Control */
 	u8	umcr2;		/* UART2 Modem Control */
 	u8	ulsr2;		/* UART2 Line Status */
 	u8	umsr2;		/* UART2 Modem Status */
 	u8	uscr2;		/* UART2 Scratch */
 	u8	res4[8];
 	u8	udsr2;		/* UART2 DMA Status */
 	u8	res5[2543];
 } ccsr_duart_t;
 #else /* MPC8560 uses UART on its CPM */
 typedef struct ccsr_duart {
 	u8 res[4096];
 } ccsr_duart_t;
 #endif
 /* eSPI Registers */
 typedef struct ccsr_espi {
 	u32	mode;		/* eSPI mode */
 	u32	event;		/* eSPI event */
 	u32	mask;		/* eSPI mask */
 	u32	com;		/* eSPI command */
 	u32	tx;		/* eSPI transmit FIFO access */
 	u32	rx;		/* eSPI receive FIFO access */
 	u8	res1[8];	/* reserved */
 	u32	csmode[4];	/* 0x2c: sSPI CS0/1/2/3 mode */
 	u8	res2[4048];	/* fill up to 0x1000 */
 } ccsr_espi_t;
 /* PCI Registers */
 typedef struct ccsr_pcix {
 	u32	cfg_addr;	/* PCIX Configuration Addr */
 	u32	cfg_data;	/* PCIX Configuration Data */
 	u32	int_ack;	/* PCIX IRQ Acknowledge */
 	u8	res000c[52];
 	u32	liodn_base;	/* PCIX LIODN base register */
 	u8	res0044[2996];
 	u32	ipver1;		/* PCIX IP block revision register 1 */
 	u32	ipver2;		/* PCIX IP block revision register 2 */
 	u32	potar0;		/* PCIX Outbound Transaction Addr 0 */
 	u32	potear0;	/* PCIX Outbound Translation Extended Addr 0 */
 	u32	powbar0;	/* PCIX Outbound Window Base Addr 0 */
 	u32	powbear0;	/* PCIX Outbound Window Base Extended Addr 0 */
 	u32	powar0;		/* PCIX Outbound Window Attrs 0 */
 	u8	res2[12];
 	u32	potar1;		/* PCIX Outbound Transaction Addr 1 */
 	u32	potear1;	/* PCIX Outbound Translation Extended Addr 1 */
 	u32	powbar1;	/* PCIX Outbound Window Base Addr 1 */
 	u32	powbear1;	/* PCIX Outbound Window Base Extended Addr 1 */
 	u32	powar1;		/* PCIX Outbound Window Attrs 1 */
 	u8	res3[12];
 	u32	potar2;		/* PCIX Outbound Transaction Addr 2 */
 	u32	potear2;	/* PCIX Outbound Translation Extended Addr 2 */
 	u32	powbar2;	/* PCIX Outbound Window Base Addr 2 */
 	u32	powbear2;	/* PCIX Outbound Window Base Extended Addr 2 */
 	u32	powar2;		/* PCIX Outbound Window Attrs 2 */
 	u8	res4[12];
 	u32	potar3;		/* PCIX Outbound Transaction Addr 3 */
 	u32	potear3;	/* PCIX Outbound Translation Extended Addr 3 */
 	u32	powbar3;	/* PCIX Outbound Window Base Addr 3 */
 	u32	powbear3;	/* PCIX Outbound Window Base Extended Addr 3 */
 	u32	powar3;		/* PCIX Outbound Window Attrs 3 */
 	u8	res5[12];
 	u32	potar4;		/* PCIX Outbound Transaction Addr 4 */
 	u32	potear4;	/* PCIX Outbound Translation Extended Addr 4 */
 	u32	powbar4;	/* PCIX Outbound Window Base Addr 4 */
 	u32	powbear4;	/* PCIX Outbound Window Base Extended Addr 4 */
 	u32	powar4;		/* PCIX Outbound Window Attrs 4 */
 	u8	res6[268];
 	u32	pitar3;		/* PCIX Inbound Translation Addr 3 */
 	u32	pitear3;	/* PCIX Inbound Translation Extended Addr 3 */
 	u32	piwbar3;	/* PCIX Inbound Window Base Addr 3 */
 	u32	piwbear3;	/* PCIX Inbound Window Base Extended Addr 3 */
 	u32	piwar3;		/* PCIX Inbound Window Attrs 3 */
 	u8	res7[12];
 	u32	pitar2;		/* PCIX Inbound Translation Addr 2 */
 	u32	pitear2;	/* PCIX Inbound Translation Extended Addr 2 */
 	u32	piwbar2;	/* PCIX Inbound Window Base Addr 2 */
 	u32	piwbear2;	/* PCIX Inbound Window Base Extended Addr 2 */
 	u32	piwar2;		/* PCIX Inbound Window Attrs 2 */
 	u8	res8[12];
 	u32	pitar1;		/* PCIX Inbound Translation Addr 1 */
 	u32	pitear1;	/* PCIX Inbound Translation Extended Addr 1 */
 	u32	piwbar1;	/* PCIX Inbound Window Base Addr 1 */
 	u8	res9[4];
 	u32	piwar1;		/* PCIX Inbound Window Attrs 1 */
 	u8	res10[12];
 	u32	pedr;		/* PCIX Error Detect */
 	u32	pecdr;		/* PCIX Error Capture Disable */
 	u32	peer;		/* PCIX Error Enable */
 	u32	peattrcr;	/* PCIX Error Attrs Capture */
 	u32	peaddrcr;	/* PCIX Error Addr Capture */
 	u32	peextaddrcr;	/* PCIX Error Extended Addr Capture */
 	u32	pedlcr;		/* PCIX Error Data Low Capture */
 	u32	pedhcr;		/* PCIX Error Error Data High Capture */
 	u32	gas_timr;	/* PCIX Gasket Timer */
 	u8	res11[476];
 } ccsr_pcix_t;
 #define PCIX_COMMAND	0x62
 #define POWAR_EN	0x80000000
 #define POWAR_IO_READ	0x00080000
 #define POWAR_MEM_READ	0x00040000
 #define POWAR_IO_WRITE	0x00008000
 #define POWAR_MEM_WRITE	0x00004000
 #define POWAR_MEM_512M	0x0000001c
 #define POWAR_IO_1M	0x00000013
 #define PIWAR_EN	0x80000000
 #define PIWAR_PF	0x20000000
 #define PIWAR_LOCAL	0x00f00000
 #define PIWAR_READ_SNOOP	0x00050000
 #define PIWAR_WRITE_SNOOP	0x00005000
 #define PIWAR_MEM_2G		0x0000001e
 #ifndef CONFIG_MPC85XX_GPIO
 typedef struct ccsr_gpio {
 	u32	gpdir;
 	u32	gpodr;
 	u32	gpdat;
 	u32	gpier;
 	u32	gpimr;
 	u32	gpicr;
 } ccsr_gpio_t;
 #endif
 /* L2 Cache Registers */
 typedef struct ccsr_l2cache {
 	u32	l2ctl;		/* L2 configuration 0 */
 	u8	res1[12];
 	u32	l2cewar0;	/* L2 cache external write addr 0 */
 	u8	res2[4];
 	u32	l2cewcr0;	/* L2 cache external write control 0 */
 	u8	res3[4];
 	u32	l2cewar1;	/* L2 cache external write addr 1 */
 	u8	res4[4];
 	u32	l2cewcr1;	/* L2 cache external write control 1 */
 	u8	res5[4];
 	u32	l2cewar2;	/* L2 cache external write addr 2 */
 	u8	res6[4];
 	u32	l2cewcr2;	/* L2 cache external write control 2 */
 	u8	res7[4];
 	u32	l2cewar3;	/* L2 cache external write addr 3 */
 	u8	res8[4];
 	u32	l2cewcr3;	/* L2 cache external write control 3 */
 	u8	res9[180];
 	u32	l2srbar0;	/* L2 memory-mapped SRAM base addr 0 */
 	u8	res10[4];
 	u32	l2srbar1;	/* L2 memory-mapped SRAM base addr 1 */
 	u8	res11[3316];
 	u32	l2errinjhi;	/* L2 error injection mask high */
 	u32	l2errinjlo;	/* L2 error injection mask low */
 	u32	l2errinjctl;	/* L2 error injection tag/ECC control */
 	u8	res12[20];
 	u32	l2captdatahi;	/* L2 error data high capture */
 	u32	l2captdatalo;	/* L2 error data low capture */
 	u32	l2captecc;	/* L2 error ECC capture */
 	u8	res13[20];
 	u32	l2errdet;	/* L2 error detect */
 	u32	l2errdis;	/* L2 error disable */
 	u32	l2errinten;	/* L2 error interrupt enable */
 	u32	l2errattr;	/* L2 error attributes capture */
 	u32	l2erraddr;	/* L2 error addr capture */
 	u8	res14[4];
 	u32	l2errctl;	/* L2 error control */
 	u8	res15[420];
 } ccsr_l2cache_t;
 #define MPC85xx_L2CTL_L2E			0x80000000
 #define MPC85xx_L2CTL_L2SRAM_ENTIRE		0x00010000
 #define MPC85xx_L2ERRDIS_MBECC			0x00000008
 #define MPC85xx_L2ERRDIS_SBECC			0x00000004
 /* DMA Registers */
 typedef struct ccsr_dma {
 	u8	res1[256];
 	struct fsl_dma dma[4];
 	u32	dgsr;		/* DMA General Status */
 	u8	res2[11516];
 } ccsr_dma_t;
 /* tsec */
 typedef struct ccsr_tsec {
 	u8	res1[16];
 	u32	ievent;		/* IRQ Event */
 	u32	imask;		/* IRQ Mask */
 	u32	edis;		/* Error Disabled */
 	u8	res2[4];
 	u32	ecntrl;		/* Ethernet Control */
 	u32	minflr;		/* Minimum Frame Len */
 	u32	ptv;		/* Pause Time Value */
 	u32	dmactrl;	/* DMA Control */
 	u32	tbipa;		/* TBI PHY Addr */
 	u8	res3[88];
 	u32	fifo_tx_thr;		/* FIFO transmit threshold */
 	u8	res4[8];
 	u32	fifo_tx_starve;		/* FIFO transmit starve */
 	u32	fifo_tx_starve_shutoff;	/* FIFO transmit starve shutoff */
 	u8	res5[96];
 	u32	tctrl;		/* TX Control */
 	u32	tstat;		/* TX Status */
 	u8	res6[4];
 	u32	tbdlen;		/* TX Buffer Desc Data Len */
 	u8	res7[16];
 	u32	ctbptrh;	/* Current TX Buffer Desc Ptr High */
 	u32	ctbptr;		/* Current TX Buffer Desc Ptr */
 	u8	res8[88];
 	u32	tbptrh;		/* TX Buffer Desc Ptr High */
 	u32	tbptr;		/* TX Buffer Desc Ptr Low */
 	u8	res9[120];
 	u32	tbaseh;		/* TX Desc Base Addr High */
 	u32	tbase;		/* TX Desc Base Addr */
 	u8	res10[168];
 	u32	ostbd;		/* Out-of-Sequence(OOS) TX Buffer Desc */
 	u32	ostbdp;		/* OOS TX Data Buffer Ptr */
 	u32	os32tbdp;	/* OOS 32 Bytes TX Data Buffer Ptr Low */
 	u32	os32iptrh;	/* OOS 32 Bytes TX Insert Ptr High */
 	u32	os32iptrl;	/* OOS 32 Bytes TX Insert Ptr Low */
 	u32	os32tbdr;	/* OOS 32 Bytes TX Reserved */
 	u32	os32iil;	/* OOS 32 Bytes TX Insert Idx/Len */
 	u8	res11[52];
 	u32	rctrl;		/* RX Control */
 	u32	rstat;		/* RX Status */
 	u8	res12[4];
 	u32	rbdlen;		/* RxBD Data Len */
 	u8	res13[16];
 	u32	crbptrh;	/* Current RX Buffer Desc Ptr High */
 	u32	crbptr;		/* Current RX Buffer Desc Ptr */
 	u8	res14[24];
 	u32	mrblr;		/* Maximum RX Buffer Len */
 	u32	mrblr2r3;	/* Maximum RX Buffer Len R2R3 */
 	u8	res15[56];
 	u32	rbptrh;		/* RX Buffer Desc Ptr High 0 */
 	u32	rbptr;		/* RX Buffer Desc Ptr */
 	u32	rbptrh1;	/* RX Buffer Desc Ptr High 1 */
 	u32	rbptrl1;	/* RX Buffer Desc Ptr Low 1 */
 	u32	rbptrh2;	/* RX Buffer Desc Ptr High 2 */
 	u32	rbptrl2;	/* RX Buffer Desc Ptr Low 2 */
 	u32	rbptrh3;	/* RX Buffer Desc Ptr High 3 */
 	u32	rbptrl3;	/* RX Buffer Desc Ptr Low 3 */
 	u8	res16[96];
 	u32	rbaseh;		/* RX Desc Base Addr High 0 */
 	u32	rbase;		/* RX Desc Base Addr */
 	u32	rbaseh1;	/* RX Desc Base Addr High 1 */
 	u32	rbasel1;	/* RX Desc Base Addr Low 1 */
 	u32	rbaseh2;	/* RX Desc Base Addr High 2 */
 	u32	rbasel2;	/* RX Desc Base Addr Low 2 */
 	u32	rbaseh3;	/* RX Desc Base Addr High 3 */
 	u32	rbasel3;	/* RX Desc Base Addr Low 3 */
 	u8	res17[224];
 	u32	maccfg1;	/* MAC Configuration 1 */
 	u32	maccfg2;	/* MAC Configuration 2 */
 	u32	ipgifg;		/* Inter Packet Gap/Inter Frame Gap */
 	u32	hafdup;		/* Half Duplex */
 	u32	maxfrm;		/* Maximum Frame Len */
 	u8	res18[12];
 	u32	miimcfg;	/* MII Management Configuration */
 	u32	miimcom;	/* MII Management Cmd */
 	u32	miimadd;	/* MII Management Addr */
 	u32	miimcon;	/* MII Management Control */
 	u32	miimstat;	/* MII Management Status */
 	u32	miimind;	/* MII Management Indicator */
 	u8	res19[4];
 	u32	ifstat;		/* Interface Status */
 	u32	macstnaddr1;	/* Station Addr Part 1 */
 	u32	macstnaddr2;	/* Station Addr Part 2 */
 	u8	res20[312];
 	u32	tr64;		/* TX & RX 64-byte Frame Counter */
 	u32	tr127;		/* TX & RX 65-127 byte Frame Counter */
 	u32	tr255;		/* TX & RX 128-255 byte Frame Counter */
 	u32	tr511;		/* TX & RX 256-511 byte Frame Counter */
 	u32	tr1k;		/* TX & RX 512-1023 byte Frame Counter */
 	u32	trmax;		/* TX & RX 1024-1518 byte Frame Counter */
 	u32	trmgv;		/* TX & RX 1519-1522 byte Good VLAN Frame */
 	u32	rbyt;		/* RX Byte Counter */
 	u32	rpkt;		/* RX Packet Counter */
 	u32	rfcs;		/* RX FCS Error Counter */
 	u32	rmca;		/* RX Multicast Packet Counter */
 	u32	rbca;		/* RX Broadcast Packet Counter */
 	u32	rxcf;		/* RX Control Frame Packet Counter */
 	u32	rxpf;		/* RX Pause Frame Packet Counter */
 	u32	rxuo;		/* RX Unknown OP Code Counter */
 	u32	raln;		/* RX Alignment Error Counter */
 	u32	rflr;		/* RX Frame Len Error Counter */
 	u32	rcde;		/* RX Code Error Counter */
 	u32	rcse;		/* RX Carrier Sense Error Counter */
 	u32	rund;		/* RX Undersize Packet Counter */
 	u32	rovr;		/* RX Oversize Packet Counter */
 	u32	rfrg;		/* RX Fragments Counter */
 	u32	rjbr;		/* RX Jabber Counter */
 	u32	rdrp;		/* RX Drop Counter */
 	u32	tbyt;		/* TX Byte Counter Counter */
 	u32	tpkt;		/* TX Packet Counter */
 	u32	tmca;		/* TX Multicast Packet Counter */
 	u32	tbca;		/* TX Broadcast Packet Counter */
 	u32	txpf;		/* TX Pause Control Frame Counter */
 	u32	tdfr;		/* TX Deferral Packet Counter */
 	u32	tedf;		/* TX Excessive Deferral Packet Counter */
 	u32	tscl;		/* TX Single Collision Packet Counter */
 	u32	tmcl;		/* TX Multiple Collision Packet Counter */
 	u32	tlcl;		/* TX Late Collision Packet Counter */
 	u32	txcl;		/* TX Excessive Collision Packet Counter */
 	u32	tncl;		/* TX Total Collision Counter */
 	u8	res21[4];
 	u32	tdrp;		/* TX Drop Frame Counter */
 	u32	tjbr;		/* TX Jabber Frame Counter */
 	u32	tfcs;		/* TX FCS Error Counter */
 	u32	txcf;		/* TX Control Frame Counter */
 	u32	tovr;		/* TX Oversize Frame Counter */
 	u32	tund;		/* TX Undersize Frame Counter */
 	u32	tfrg;		/* TX Fragments Frame Counter */
 	u32	car1;		/* Carry One */
 	u32	car2;		/* Carry Two */
 	u32	cam1;		/* Carry Mask One */
 	u32	cam2;		/* Carry Mask Two */
 	u8	res22[192];
 	u32	iaddr0;		/* Indivdual addr 0 */
 	u32	iaddr1;		/* Indivdual addr 1 */
 	u32	iaddr2;		/* Indivdual addr 2 */
 	u32	iaddr3;		/* Indivdual addr 3 */
 	u32	iaddr4;		/* Indivdual addr 4 */
 	u32	iaddr5;		/* Indivdual addr 5 */
 	u32	iaddr6;		/* Indivdual addr 6 */
 	u32	iaddr7;		/* Indivdual addr 7 */
 	u8	res23[96];
 	u32	gaddr0;		/* Global addr 0 */
 	u32	gaddr1;		/* Global addr 1 */
 	u32	gaddr2;		/* Global addr 2 */
 	u32	gaddr3;		/* Global addr 3 */
 	u32	gaddr4;		/* Global addr 4 */
 	u32	gaddr5;		/* Global addr 5 */
 	u32	gaddr6;		/* Global addr 6 */
 	u32	gaddr7;		/* Global addr 7 */
 	u8	res24[96];
 	u32	pmd0;		/* Pattern Match Data */
 	u8	res25[4];
 	u32	pmask0;		/* Pattern Mask */
 	u8	res26[4];
 	u32	pcntrl0;	/* Pattern Match Control */
 	u8	res27[4];
 	u32	pattrb0;	/* Pattern Match Attrs */
 	u32	pattrbeli0;	/* Pattern Match Attrs Extract Len & Idx */
 	u32	pmd1;		/* Pattern Match Data */
 	u8	res28[4];
 	u32	pmask1;		/* Pattern Mask */
 	u8	res29[4];
 	u32	pcntrl1;	/* Pattern Match Control */
 	u8	res30[4];
 	u32	pattrb1;	/* Pattern Match Attrs */
 	u32	pattrbeli1;	/* Pattern Match Attrs Extract Len & Idx */
 	u32	pmd2;		/* Pattern Match Data */
 	u8	res31[4];
 	u32	pmask2;		/* Pattern Mask */
 	u8	res32[4];
 	u32	pcntrl2;	/* Pattern Match Control */
 	u8	res33[4];
 	u32	pattrb2;	/* Pattern Match Attrs */
 	u32	pattrbeli2;	/* Pattern Match Attrs Extract Len & Idx */
 	u32	pmd3;		/* Pattern Match Data */
 	u8	res34[4];
 	u32	pmask3;		/* Pattern Mask */
 	u8	res35[4];
 	u32	pcntrl3;	/* Pattern Match Control */
 	u8	res36[4];
 	u32	pattrb3;	/* Pattern Match Attrs */
 	u32	pattrbeli3;	/* Pattern Match Attrs Extract Len & Idx */
 	u32	pmd4;		/* Pattern Match Data */
 	u8	res37[4];
 	u32	pmask4;		/* Pattern Mask */
 	u8	res38[4];
 	u32	pcntrl4;	/* Pattern Match Control */
 	u8	res39[4];
 	u32	pattrb4;	/* Pattern Match Attrs */
 	u32	pattrbeli4;	/* Pattern Match Attrs Extract Len & Idx */
 	u32	pmd5;		/* Pattern Match Data */
 	u8	res40[4];
 	u32	pmask5;		/* Pattern Mask */
 	u8	res41[4];
 	u32	pcntrl5;	/* Pattern Match Control */
 	u8	res42[4];
 	u32	pattrb5;	/* Pattern Match Attrs */
 	u32	pattrbeli5;	/* Pattern Match Attrs Extract Len & Idx */
 	u32	pmd6;		/* Pattern Match Data */
 	u8	res43[4];
 	u32	pmask6;		/* Pattern Mask */
 	u8	res44[4];
 	u32	pcntrl6;	/* Pattern Match Control */
 	u8	res45[4];
 	u32	pattrb6;	/* Pattern Match Attrs */
 	u32	pattrbeli6;	/* Pattern Match Attrs Extract Len & Idx */
 	u32	pmd7;		/* Pattern Match Data */
 	u8	res46[4];
 	u32	pmask7;		/* Pattern Mask */
 	u8	res47[4];
 	u32	pcntrl7;	/* Pattern Match Control */
 	u8	res48[4];
 	u32	pattrb7;	/* Pattern Match Attrs */
 	u32	pattrbeli7;	/* Pattern Match Attrs Extract Len & Idx */
 	u32	pmd8;		/* Pattern Match Data */
 	u8	res49[4];
 	u32	pmask8;		/* Pattern Mask */
 	u8	res50[4];
 	u32	pcntrl8;	/* Pattern Match Control */
 	u8	res51[4];
 	u32	pattrb8;	/* Pattern Match Attrs */
 	u32	pattrbeli8;	/* Pattern Match Attrs Extract Len & Idx */
 	u32	pmd9;		/* Pattern Match Data */
 	u8	res52[4];
 	u32	pmask9;		/* Pattern Mask */
 	u8	res53[4];
 	u32	pcntrl9;	/* Pattern Match Control */
 	u8	res54[4];
 	u32	pattrb9;	/* Pattern Match Attrs */
 	u32	pattrbeli9;	/* Pattern Match Attrs Extract Len & Idx */
 	u32	pmd10;		/* Pattern Match Data */
 	u8	res55[4];
 	u32	pmask10;	/* Pattern Mask */
 	u8	res56[4];
 	u32	pcntrl10;	/* Pattern Match Control */
 	u8	res57[4];
 	u32	pattrb10;	/* Pattern Match Attrs */
 	u32	pattrbeli10;	/* Pattern Match Attrs Extract Len & Idx */
 	u32	pmd11;		/* Pattern Match Data */
 	u8	res58[4];
 	u32	pmask11;	/* Pattern Mask */
 	u8	res59[4];
 	u32	pcntrl11;	/* Pattern Match Control */
 	u8	res60[4];
 	u32	pattrb11;	/* Pattern Match Attrs */
 	u32	pattrbeli11;	/* Pattern Match Attrs Extract Len & Idx */
 	u32	pmd12;		/* Pattern Match Data */
 	u8	res61[4];
 	u32	pmask12;	/* Pattern Mask */
 	u8	res62[4];
 	u32	pcntrl12;	/* Pattern Match Control */
 	u8	res63[4];
 	u32	pattrb12;	/* Pattern Match Attrs */
 	u32	pattrbeli12;	/* Pattern Match Attrs Extract Len & Idx */
 	u32	pmd13;		/* Pattern Match Data */
 	u8	res64[4];
 	u32	pmask13;	/* Pattern Mask */
 	u8	res65[4];
 	u32	pcntrl13;	/* Pattern Match Control */
 	u8	res66[4];
 	u32	pattrb13;	/* Pattern Match Attrs */
 	u32	pattrbeli13;	/* Pattern Match Attrs Extract Len & Idx */
 	u32	pmd14;		/* Pattern Match Data */
 	u8	res67[4];
 	u32	pmask14;	/* Pattern Mask */
 	u8	res68[4];
 	u32	pcntrl14;	/* Pattern Match Control */
 	u8	res69[4];
 	u32	pattrb14;	/* Pattern Match Attrs */
 	u32	pattrbeli14;	/* Pattern Match Attrs Extract Len & Idx */
 	u32	pmd15;		/* Pattern Match Data */
 	u8	res70[4];
 	u32	pmask15;	/* Pattern Mask */
 	u8	res71[4];
 	u32	pcntrl15;	/* Pattern Match Control */
 	u8	res72[4];
 	u32	pattrb15;	/* Pattern Match Attrs */
 	u32	pattrbeli15;	/* Pattern Match Attrs Extract Len & Idx */
 	u8	res73[248];
 	u32	attr;		/* Attrs */
 	u32	attreli;	/* Attrs Extract Len & Idx */
 	u8	res74[1024];
 } ccsr_tsec_t;
 /* PIC Registers */
 typedef struct ccsr_pic {
 	u8	res1[64];
 	u32	ipidr0;		/* Interprocessor IRQ Dispatch 0 */
 	u8	res2[12];
 	u32	ipidr1;		/* Interprocessor IRQ Dispatch 1 */
 	u8	res3[12];
 	u32	ipidr2;		/* Interprocessor IRQ Dispatch 2 */
 	u8	res4[12];
 	u32	ipidr3;		/* Interprocessor IRQ Dispatch 3 */
 	u8	res5[12];
 	u32	ctpr;		/* Current Task Priority */
 	u8	res6[12];
 	u32	whoami;		/* Who Am I */
 	u8	res7[12];
 	u32	iack;		/* IRQ Acknowledge */
 	u8	res8[12];
 	u32	eoi;		/* End Of IRQ */
 	u8	res9[3916];
 	u32	frr;		/* Feature Reporting */
 	u8	res10[28];
 	u32	gcr;		/* Global Configuration */
 #define MPC85xx_PICGCR_RST	0x80000000
 #define MPC85xx_PICGCR_M	0x20000000
 	u8	res11[92];
 	u32	vir;		/* Vendor Identification */
 	u8	res12[12];
 	u32	pir;		/* Processor Initialization */
 	u8	res13[12];
 	u32	ipivpr0;	/* IPI Vector/Priority 0 */
 	u8	res14[12];
 	u32	ipivpr1;	/* IPI Vector/Priority 1 */
 	u8	res15[12];
 	u32	ipivpr2;	/* IPI Vector/Priority 2 */
 	u8	res16[12];
 	u32	ipivpr3;	/* IPI Vector/Priority 3 */
 	u8	res17[12];
 	u32	svr;		/* Spurious Vector */
 	u8	res18[12];
 	u32	tfrr;		/* Timer Frequency Reporting */
 	u8	res19[12];
 	u32	gtccr0;		/* Global Timer Current Count 0 */
 	u8	res20[12];
 	u32	gtbcr0;		/* Global Timer Base Count 0 */
 	u8	res21[12];
 	u32	gtvpr0;		/* Global Timer Vector/Priority 0 */
 	u8	res22[12];
 	u32	gtdr0;		/* Global Timer Destination 0 */
 	u8	res23[12];
 	u32	gtccr1;		/* Global Timer Current Count 1 */
 	u8	res24[12];
 	u32	gtbcr1;		/* Global Timer Base Count 1 */
 	u8	res25[12];
 	u32	gtvpr1;		/* Global Timer Vector/Priority 1 */
 	u8	res26[12];
 	u32	gtdr1;		/* Global Timer Destination 1 */
 	u8	res27[12];
 	u32	gtccr2;		/* Global Timer Current Count 2 */
 	u8	res28[12];
 	u32	gtbcr2;		/* Global Timer Base Count 2 */
 	u8	res29[12];
 	u32	gtvpr2;		/* Global Timer Vector/Priority 2 */
 	u8	res30[12];
 	u32	gtdr2;		/* Global Timer Destination 2 */
 	u8	res31[12];
 	u32	gtccr3;		/* Global Timer Current Count 3 */
 	u8	res32[12];
 	u32	gtbcr3;		/* Global Timer Base Count 3 */
 	u8	res33[12];
 	u32	gtvpr3;		/* Global Timer Vector/Priority 3 */
 	u8	res34[12];
 	u32	gtdr3;		/* Global Timer Destination 3 */
 	u8	res35[268];
 	u32	tcr;		/* Timer Control */
 	u8	res36[12];
 	u32	irqsr0;		/* IRQ_OUT Summary 0 */
 	u8	res37[12];
 	u32	irqsr1;		/* IRQ_OUT Summary 1 */
 	u8	res38[12];
 	u32	cisr0;		/* Critical IRQ Summary 0 */
 	u8	res39[12];
 	u32	cisr1;		/* Critical IRQ Summary 1 */
 	u8	res40[188];
 	u32	msgr0;		/* Message 0 */
 	u8	res41[12];
 	u32	msgr1;		/* Message 1 */
 	u8	res42[12];
 	u32	msgr2;		/* Message 2 */
 	u8	res43[12];
 	u32	msgr3;		/* Message 3 */
 	u8	res44[204];
 	u32	mer;		/* Message Enable */
 	u8	res45[12];
 	u32	msr;		/* Message Status */
 	u8	res46[60140];
 	u32	eivpr0;		/* External IRQ Vector/Priority 0 */
 	u8	res47[12];
 	u32	eidr0;		/* External IRQ Destination 0 */
 	u8	res48[12];
 	u32	eivpr1;		/* External IRQ Vector/Priority 1 */
 	u8	res49[12];
 	u32	eidr1;		/* External IRQ Destination 1 */
 	u8	res50[12];
 	u32	eivpr2;		/* External IRQ Vector/Priority 2 */
 	u8	res51[12];
 	u32	eidr2;		/* External IRQ Destination 2 */
 	u8	res52[12];
 	u32	eivpr3;		/* External IRQ Vector/Priority 3 */
 	u8	res53[12];
 	u32	eidr3;		/* External IRQ Destination 3 */
 	u8	res54[12];
 	u32	eivpr4;		/* External IRQ Vector/Priority 4 */
 	u8	res55[12];
 	u32	eidr4;		/* External IRQ Destination 4 */
 	u8	res56[12];
 	u32	eivpr5;		/* External IRQ Vector/Priority 5 */
 	u8	res57[12];
 	u32	eidr5;		/* External IRQ Destination 5 */
 	u8	res58[12];
 	u32	eivpr6;		/* External IRQ Vector/Priority 6 */
 	u8	res59[12];
 	u32	eidr6;		/* External IRQ Destination 6 */
 	u8	res60[12];
 	u32	eivpr7;		/* External IRQ Vector/Priority 7 */
 	u8	res61[12];
 	u32	eidr7;		/* External IRQ Destination 7 */
 	u8	res62[12];
 	u32	eivpr8;		/* External IRQ Vector/Priority 8 */
 	u8	res63[12];
 	u32	eidr8;		/* External IRQ Destination 8 */
 	u8	res64[12];
 	u32	eivpr9;		/* External IRQ Vector/Priority 9 */
 	u8	res65[12];
 	u32	eidr9;		/* External IRQ Destination 9 */
 	u8	res66[12];
 	u32	eivpr10;	/* External IRQ Vector/Priority 10 */
 	u8	res67[12];
 	u32	eidr10;		/* External IRQ Destination 10 */
 	u8	res68[12];
 	u32	eivpr11;	/* External IRQ Vector/Priority 11 */
 	u8	res69[12];
 	u32	eidr11;		/* External IRQ Destination 11 */
 	u8	res70[140];
 	u32	iivpr0;		/* Internal IRQ Vector/Priority 0 */
 	u8	res71[12];
 	u32	iidr0;		/* Internal IRQ Destination 0 */
 	u8	res72[12];
 	u32	iivpr1;		/* Internal IRQ Vector/Priority 1 */
 	u8	res73[12];
 	u32	iidr1;		/* Internal IRQ Destination 1 */
 	u8	res74[12];
 	u32	iivpr2;		/* Internal IRQ Vector/Priority 2 */
 	u8	res75[12];
 	u32	iidr2;		/* Internal IRQ Destination 2 */
 	u8	res76[12];
 	u32	iivpr3;		/* Internal IRQ Vector/Priority 3 */
 	u8	res77[12];
 	u32	iidr3;		/* Internal IRQ Destination 3 */
 	u8	res78[12];
 	u32	iivpr4;		/* Internal IRQ Vector/Priority 4 */
 	u8	res79[12];
 	u32	iidr4;		/* Internal IRQ Destination 4 */
 	u8	res80[12];
 	u32	iivpr5;		/* Internal IRQ Vector/Priority 5 */
 	u8	res81[12];
 	u32	iidr5;		/* Internal IRQ Destination 5 */
 	u8	res82[12];
 	u32	iivpr6;		/* Internal IRQ Vector/Priority 6 */
 	u8	res83[12];
 	u32	iidr6;		/* Internal IRQ Destination 6 */
 	u8	res84[12];
 	u32	iivpr7;		/* Internal IRQ Vector/Priority 7 */
 	u8	res85[12];
 	u32	iidr7;		/* Internal IRQ Destination 7 */
 	u8	res86[12];
 	u32	iivpr8;		/* Internal IRQ Vector/Priority 8 */
 	u8	res87[12];
 	u32	iidr8;		/* Internal IRQ Destination 8 */
 	u8	res88[12];
 	u32	iivpr9;		/* Internal IRQ Vector/Priority 9 */
 	u8	res89[12];
 	u32	iidr9;		/* Internal IRQ Destination 9 */
 	u8	res90[12];
 	u32	iivpr10;	/* Internal IRQ Vector/Priority 10 */
 	u8	res91[12];
 	u32	iidr10;		/* Internal IRQ Destination 10 */
 	u8	res92[12];
 	u32	iivpr11;	/* Internal IRQ Vector/Priority 11 */
 	u8	res93[12];
 	u32	iidr11;		/* Internal IRQ Destination 11 */
 	u8	res94[12];
 	u32	iivpr12;	/* Internal IRQ Vector/Priority 12 */
 	u8	res95[12];
 	u32	iidr12;		/* Internal IRQ Destination 12 */
 	u8	res96[12];
 	u32	iivpr13;	/* Internal IRQ Vector/Priority 13 */
 	u8	res97[12];
 	u32	iidr13;		/* Internal IRQ Destination 13 */
 	u8	res98[12];
 	u32	iivpr14;	/* Internal IRQ Vector/Priority 14 */
 	u8	res99[12];
 	u32	iidr14;		/* Internal IRQ Destination 14 */
 	u8	res100[12];
 	u32	iivpr15;	/* Internal IRQ Vector/Priority 15 */
 	u8	res101[12];
 	u32	iidr15;		/* Internal IRQ Destination 15 */
 	u8	res102[12];
 	u32	iivpr16;	/* Internal IRQ Vector/Priority 16 */
 	u8	res103[12];
 	u32	iidr16;		/* Internal IRQ Destination 16 */
 	u8	res104[12];
 	u32	iivpr17;	/* Internal IRQ Vector/Priority 17 */
 	u8	res105[12];
 	u32	iidr17;		/* Internal IRQ Destination 17 */
 	u8	res106[12];
 	u32	iivpr18;	/* Internal IRQ Vector/Priority 18 */
 	u8	res107[12];
 	u32	iidr18;		/* Internal IRQ Destination 18 */
 	u8	res108[12];
 	u32	iivpr19;	/* Internal IRQ Vector/Priority 19 */
 	u8	res109[12];
 	u32	iidr19;		/* Internal IRQ Destination 19 */
 	u8	res110[12];
 	u32	iivpr20;	/* Internal IRQ Vector/Priority 20 */
 	u8	res111[12];
 	u32	iidr20;		/* Internal IRQ Destination 20 */
 	u8	res112[12];
 	u32	iivpr21;	/* Internal IRQ Vector/Priority 21 */
 	u8	res113[12];
 	u32	iidr21;		/* Internal IRQ Destination 21 */
 	u8	res114[12];
 	u32	iivpr22;	/* Internal IRQ Vector/Priority 22 */
 	u8	res115[12];
 	u32	iidr22;		/* Internal IRQ Destination 22 */
 	u8	res116[12];
 	u32	iivpr23;	/* Internal IRQ Vector/Priority 23 */
 	u8	res117[12];
 	u32	iidr23;		/* Internal IRQ Destination 23 */
 	u8	res118[12];
 	u32	iivpr24;	/* Internal IRQ Vector/Priority 24 */
 	u8	res119[12];
 	u32	iidr24;		/* Internal IRQ Destination 24 */
 	u8	res120[12];
 	u32	iivpr25;	/* Internal IRQ Vector/Priority 25 */
 	u8	res121[12];
 	u32	iidr25;		/* Internal IRQ Destination 25 */
 	u8	res122[12];
 	u32	iivpr26;	/* Internal IRQ Vector/Priority 26 */
 	u8	res123[12];
 	u32	iidr26;		/* Internal IRQ Destination 26 */
 	u8	res124[12];
 	u32	iivpr27;	/* Internal IRQ Vector/Priority 27 */
 	u8	res125[12];
 	u32	iidr27;		/* Internal IRQ Destination 27 */
 	u8	res126[12];
 	u32	iivpr28;	/* Internal IRQ Vector/Priority 28 */
 	u8	res127[12];
 	u32	iidr28;		/* Internal IRQ Destination 28 */
 	u8	res128[12];
 	u32	iivpr29;	/* Internal IRQ Vector/Priority 29 */
 	u8	res129[12];
 	u32	iidr29;		/* Internal IRQ Destination 29 */
 	u8	res130[12];
 	u32	iivpr30;	/* Internal IRQ Vector/Priority 30 */
 	u8	res131[12];
 	u32	iidr30;		/* Internal IRQ Destination 30 */
 	u8	res132[12];
 	u32	iivpr31;	/* Internal IRQ Vector/Priority 31 */
 	u8	res133[12];
 	u32	iidr31;		/* Internal IRQ Destination 31 */
 	u8	res134[4108];
 	u32	mivpr0;		/* Messaging IRQ Vector/Priority 0 */
 	u8	res135[12];
 	u32	midr0;		/* Messaging IRQ Destination 0 */
 	u8	res136[12];
 	u32	mivpr1;		/* Messaging IRQ Vector/Priority 1 */
 	u8	res137[12];
 	u32	midr1;		/* Messaging IRQ Destination 1 */
 	u8	res138[12];
 	u32	mivpr2;		/* Messaging IRQ Vector/Priority 2 */
 	u8	res139[12];
 	u32	midr2;		/* Messaging IRQ Destination 2 */
 	u8	res140[12];
 	u32	mivpr3;		/* Messaging IRQ Vector/Priority 3 */
 	u8	res141[12];
 	u32	midr3;		/* Messaging IRQ Destination 3 */
 	u8	res142[59852];
 	u32	ipi0dr0;	/* Processor 0 Interprocessor IRQ Dispatch 0 */
 	u8	res143[12];
 	u32	ipi0dr1;	/* Processor 0 Interprocessor IRQ Dispatch 1 */
 	u8	res144[12];
 	u32	ipi0dr2;	/* Processor 0 Interprocessor IRQ Dispatch 2 */
 	u8	res145[12];
 	u32	ipi0dr3;	/* Processor 0 Interprocessor IRQ Dispatch 3 */
 	u8	res146[12];
 	u32	ctpr0;		/* Current Task Priority for Processor 0 */
 	u8	res147[12];
 	u32	whoami0;	/* Who Am I for Processor 0 */
 	u8	res148[12];
 	u32	iack0;		/* IRQ Acknowledge for Processor 0 */
 	u8	res149[12];
 	u32	eoi0;		/* End Of IRQ for Processor 0 */
 	u8	res150[130892];
 } ccsr_pic_t;
 /* CPM Block */
 #ifndef CONFIG_CPM2
 typedef struct ccsr_cpm {
 	u8 res[262144];
 } ccsr_cpm_t;
 #else
 /*
  * DPARM
  * General SIU
  */
 typedef struct ccsr_cpm_siu {
 	u8	res1[80];
 	u32	smaer;
 	u32	smser;
 	u32	smevr;
 	u8	res2[4];
 	u32	lmaer;
 	u32	lmser;
 	u32	lmevr;
 	u8	res3[2964];
 } ccsr_cpm_siu_t;
 /* IRQ Controller */
 typedef struct ccsr_cpm_intctl {
 	u16	sicr;
 	u8	res1[2];
 	u32	sivec;
 	u32	sipnrh;
 	u32	sipnrl;
 	u32	siprr;
 	u32	scprrh;
 	u32	scprrl;
 	u32	simrh;
 	u32	simrl;
 	u32	siexr;
 	u8	res2[88];
 	u32	sccr;
 	u8	res3[124];
 } ccsr_cpm_intctl_t;
 /* input/output port */
 typedef struct ccsr_cpm_iop {
 	u32	pdira;
 	u32	ppara;
 	u32	psora;
 	u32	podra;
 	u32	pdata;
 	u8	res1[12];
 	u32	pdirb;
 	u32	pparb;
 	u32	psorb;
 	u32	podrb;
 	u32	pdatb;
 	u8	res2[12];
 	u32	pdirc;
 	u32	pparc;
 	u32	psorc;
 	u32	podrc;
 	u32	pdatc;
 	u8	res3[12];
 	u32	pdird;
 	u32	ppard;
 	u32	psord;
 	u32	podrd;
 	u32	pdatd;
 	u8	res4[12];
 } ccsr_cpm_iop_t;
 /* CPM timers */
 typedef struct ccsr_cpm_timer {
 	u8	tgcr1;
 	u8	res1[3];
 	u8	tgcr2;
 	u8	res2[11];
 	u16	tmr1;
 	u16	tmr2;
 	u16	trr1;
 	u16	trr2;
 	u16	tcr1;
 	u16	tcr2;
 	u16	tcn1;
 	u16	tcn2;
 	u16	tmr3;
 	u16	tmr4;
 	u16	trr3;
 	u16	trr4;
 	u16	tcr3;
 	u16	tcr4;
 	u16	tcn3;
 	u16	tcn4;
 	u16	ter1;
 	u16	ter2;
 	u16	ter3;
 	u16	ter4;
 	u8	res3[608];
 } ccsr_cpm_timer_t;
 /* SDMA */
 typedef struct ccsr_cpm_sdma {
 	u8	sdsr;
 	u8	res1[3];
 	u8	sdmr;
 	u8	res2[739];
 } ccsr_cpm_sdma_t;
 /* FCC1 */
 typedef struct ccsr_cpm_fcc1 {
 	u32	gfmr;
 	u32	fpsmr;
 	u16	ftodr;
 	u8	res1[2];
 	u16	fdsr;
 	u8	res2[2];
 	u16	fcce;
 	u8	res3[2];
 	u16	fccm;
 	u8	res4[2];
 	u8	fccs;
 	u8	res5[3];
 	u8	ftirr_phy[4];
 } ccsr_cpm_fcc1_t;
 /* FCC2 */
 typedef struct ccsr_cpm_fcc2 {
 	u32	gfmr;
 	u32	fpsmr;
 	u16	ftodr;
 	u8	res1[2];
 	u16	fdsr;
 	u8	res2[2];
 	u16	fcce;
 	u8	res3[2];
 	u16	fccm;
 	u8	res4[2];
 	u8	fccs;
 	u8	res5[3];
 	u8	ftirr_phy[4];
 } ccsr_cpm_fcc2_t;
 /* FCC3 */
 typedef struct ccsr_cpm_fcc3 {
 	u32	gfmr;
 	u32	fpsmr;
 	u16	ftodr;
 	u8	res1[2];
 	u16	fdsr;
 	u8	res2[2];
 	u16	fcce;
 	u8	res3[2];
 	u16	fccm;
 	u8	res4[2];
 	u8	fccs;
 	u8	res5[3];
 	u8	res[36];
 } ccsr_cpm_fcc3_t;
 /* FCC1 extended */
 typedef struct ccsr_cpm_fcc1_ext {
 	u32	firper;
 	u32	firer;
 	u32	firsr_h;
 	u32	firsr_l;
 	u8	gfemr;
 	u8	res[15];
 } ccsr_cpm_fcc1_ext_t;
 /* FCC2 extended */
 typedef struct ccsr_cpm_fcc2_ext {
 	u32	firper;
 	u32	firer;
 	u32	firsr_h;
 	u32	firsr_l;
 	u8	gfemr;
 	u8	res[31];
 } ccsr_cpm_fcc2_ext_t;
 /* FCC3 extended */
 typedef struct ccsr_cpm_fcc3_ext {
 	u8	gfemr;
 	u8	res[47];
 } ccsr_cpm_fcc3_ext_t;
 /* TC layers */
 typedef struct ccsr_cpm_tmp1 {
 	u8	res[496];
 } ccsr_cpm_tmp1_t;
 /* BRGs:5,6,7,8 */
 typedef struct ccsr_cpm_brg2 {
 	u32	brgc5;
 	u32	brgc6;
 	u32	brgc7;
 	u32	brgc8;
 	u8	res[608];
 } ccsr_cpm_brg2_t;
 /* I2C */
 typedef struct ccsr_cpm_i2c {
 	u8	i2mod;
 	u8	res1[3];
 	u8	i2add;
 	u8	res2[3];
 	u8	i2brg;
 	u8	res3[3];
 	u8	i2com;
 	u8	res4[3];
 	u8	i2cer;
 	u8	res5[3];
 	u8	i2cmr;
 	u8	res6[331];
 } ccsr_cpm_i2c_t;
 /* CPM core */
 typedef struct ccsr_cpm_cp {
 	u32	cpcr;
 	u32	rccr;
 	u8	res1[14];
 	u16	rter;
 	u8	res2[2];
 	u16	rtmr;
 	u16	rtscr;
 	u8	res3[2];
 	u32	rtsr;
 	u8	res4[12];
 } ccsr_cpm_cp_t;
 /* BRGs:1,2,3,4 */
 typedef struct ccsr_cpm_brg1 {
 	u32	brgc1;
 	u32	brgc2;
 	u32	brgc3;
 	u32	brgc4;
 } ccsr_cpm_brg1_t;
 /* SCC1-SCC4 */
 typedef struct ccsr_cpm_scc {
 	u32	gsmrl;
 	u32	gsmrh;
 	u16	psmr;
 	u8	res1[2];
 	u16	todr;
 	u16	dsr;
 	u16	scce;
 	u8	res2[2];
 	u16	sccm;
 	u8	res3;
 	u8	sccs;
 	u8	res4[8];
 } ccsr_cpm_scc_t;
 typedef struct ccsr_cpm_tmp2 {
 	u8	res[32];
 } ccsr_cpm_tmp2_t;
 /* SPI */
 typedef struct ccsr_cpm_spi {
 	u16	spmode;
 	u8	res1[4];
 	u8	spie;
 	u8	res2[3];
 	u8	spim;
 	u8	res3[2];
 	u8	spcom;
 	u8	res4[82];
 } ccsr_cpm_spi_t;
 /* CPM MUX */
 typedef struct ccsr_cpm_mux {
 	u8	cmxsi1cr;
 	u8	res1;
 	u8	cmxsi2cr;
 	u8	res2;
 	u32	cmxfcr;
 	u32	cmxscr;
 	u8	res3[2];
 	u16	cmxuar;
 	u8	res4[16];
 } ccsr_cpm_mux_t;
 /* SI,MCC,etc */
 typedef struct ccsr_cpm_tmp3 {
 	u8 res[58592];
 } ccsr_cpm_tmp3_t;
 typedef struct ccsr_cpm_iram {
 	u32	iram[8192];
 	u8	res[98304];
 } ccsr_cpm_iram_t;
 typedef struct ccsr_cpm {
 	/* Some references are into the unique & known dpram spaces,
 	 * others are from the generic base.
 	 */
 #define im_dprambase		im_dpram1
 	u8			im_dpram1[16*1024];
 	u8			res1[16*1024];
 	u8			im_dpram2[16*1024];
 	u8			res2[16*1024];
 	ccsr_cpm_siu_t		im_cpm_siu; /* SIU Configuration */
 	ccsr_cpm_intctl_t	im_cpm_intctl; /* IRQ Controller */
 	ccsr_cpm_iop_t		im_cpm_iop; /* IO Port control/status */
 	ccsr_cpm_timer_t	im_cpm_timer; /* CPM timers */
 	ccsr_cpm_sdma_t		im_cpm_sdma; /* SDMA control/status */
 	ccsr_cpm_fcc1_t		im_cpm_fcc1;
 	ccsr_cpm_fcc2_t		im_cpm_fcc2;
 	ccsr_cpm_fcc3_t		im_cpm_fcc3;
 	ccsr_cpm_fcc1_ext_t	im_cpm_fcc1_ext;
 	ccsr_cpm_fcc2_ext_t	im_cpm_fcc2_ext;
 	ccsr_cpm_fcc3_ext_t	im_cpm_fcc3_ext;
 	ccsr_cpm_tmp1_t		im_cpm_tmp1;
 	ccsr_cpm_brg2_t		im_cpm_brg2;
 	ccsr_cpm_i2c_t		im_cpm_i2c;
 	ccsr_cpm_cp_t		im_cpm_cp;
 	ccsr_cpm_brg1_t		im_cpm_brg1;
 	ccsr_cpm_scc_t		im_cpm_scc[4];
 	ccsr_cpm_tmp2_t		im_cpm_tmp2;
 	ccsr_cpm_spi_t		im_cpm_spi;
 	ccsr_cpm_mux_t		im_cpm_mux;
 	ccsr_cpm_tmp3_t		im_cpm_tmp3;
 	ccsr_cpm_iram_t		im_cpm_iram;
 } ccsr_cpm_t;
 #endif
 #ifdef CONFIG_SYS_SRIO
 /* Architectural regsiters */
 struct rio_arch {
 	u32	didcar;	/* Device Identity CAR */
 	u32	dicar;	/* Device Information CAR */
 	u32	aidcar;	/* Assembly Identity CAR */
 	u32	aicar;	/* Assembly Information CAR */
 	u32	pefcar;	/* Processing Element Features CAR */
 	u8	res0[4];
 	u32	socar;	/* Source Operations CAR */
 	u32	docar;	/* Destination Operations CAR */
 	u8	res1[32];
 	u32	mcsr;	/* Mailbox CSR */
 	u32	pwdcsr;	/* Port-Write and Doorbell CSR */
 	u8	res2[4];
 	u32	pellccsr;	/* Processing Element Logic Layer CCSR */
 	u8	res3[12];
 	u32	lcsbacsr;	/* Local Configuration Space BACSR */
 	u32	bdidcsr;	/* Base Device ID CSR */
 	u8	res4[4];
 	u32	hbdidlcsr;	/* Host Base Device ID Lock CSR */
 	u32	ctcsr;	/* Component Tag CSR */
 };
 /* Extended Features Space: 1x/4x LP-Serial Port registers */
 struct rio_lp_serial_port {
 	u32	plmreqcsr;	/* Port Link Maintenance Request CSR */
 	u32	plmrespcsr;	/* Port Link Maintenance Response CS */
 	u32	plascsr;	/* Port Local Ackid Status CSR */
 	u8	res0[12];
 	u32	pescsr;	/* Port Error and Status CSR */
 	u32	pccsr;	/* Port Control CSR */
 };
 /* Extended Features Space: 1x/4x LP-Serial registers */
 struct rio_lp_serial {
 	u32	pmbh0csr;	/* Port Maintenance Block Header 0 CSR */
 	u8	res0[28];
 	u32	pltoccsr;	/* Port Link Time-out CCSR */
 	u32	prtoccsr;	/* Port Response Time-out CCSR */
 	u8	res1[20];
 	u32	pgccsr;	/* Port General CSR */
 	struct rio_lp_serial_port	port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
 };
 /* Logical error reporting registers */
 struct rio_logical_err {
 	u32	erbh;	/* Error Reporting Block Header Register */
 	u8	res0[4];
 	u32	ltledcsr;	/* Logical/Transport layer error DCSR */
 	u32	ltleecsr;	/* Logical/Transport layer error ECSR */
 	u8	res1[4];
 	u32	ltlaccsr;	/* Logical/Transport layer ACCSR */
 	u32	ltldidccsr;	/* Logical/Transport layer DID CCSR */
 	u32	ltlcccsr;	/* Logical/Transport layer control CCSR */
 };
 /* Physical error reporting port registers */
 struct rio_phys_err_port {
 	u32	edcsr;	/* Port error detect CSR */
 	u32	erecsr;	/* Port error rate enable CSR */
 	u32	ecacsr;	/* Port error capture attributes CSR */
 	u32	pcseccsr0;	/* Port packet/control symbol ECCSR 0 */
 	u32	peccsr[3];	/* Port error capture CSR */
 	u8	res0[12];
 	u32	ercsr;	/* Port error rate CSR */
 	u32	ertcsr;	/* Port error rate threshold CSR */
 	u8	res1[16];
 };
 /* Physical error reporting registers */
 struct rio_phys_err {
 	struct rio_phys_err_port	port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
 };
 /* Implementation Space: General Port-Common */
 struct rio_impl_common {
 	u8	res0[4];
 	u32	llcr;	/* Logical Layer Configuration Register */
 	u8	res1[8];
 	u32	epwisr;	/* Error / Port-Write Interrupt SR */
 	u8	res2[12];
 	u32	lretcr;	/* Logical Retry Error Threshold CR */
 	u8	res3[92];
 	u32	pretcr;	/* Physical Retry Erorr Threshold CR */
 	u8	res4[124];
 };
 /* Implementation Space: Port Specific */
 struct rio_impl_port_spec {
 	u32	adidcsr;	/* Port Alt. Device ID CSR */
 	u8	res0[28];
 	u32	ptaacr;	/* Port Pass-Through/Accept-All CR */
 	u32	lopttlcr;
 	u8	res1[8];
 	u32	iecsr;	/* Port Implementation Error CSR */
 	u8	res2[12];
 	u32	pcr;		/* Port Phsyical Configuration Register */
 	u8	res3[20];
 	u32	slcsr;	/* Port Serial Link CSR */
 	u8	res4[4];
 	u32	sleicr;	/* Port Serial Link Error Injection */
 	u32	a0txcr;	/* Port Arbitration 0 Tx CR */
 	u32	a1txcr;	/* Port Arbitration 1 Tx CR */
 	u32	a2txcr;	/* Port Arbitration 2 Tx CR */
 	u32	mreqtxbacr[3];	/* Port Request Tx Buffer ACR */
 	u32	mrspfctxbacr;	/* Port Response/Flow Control Tx Buffer ACR */
 };
 /* Implementation Space: register */
 struct rio_implement {
 	struct rio_impl_common	com;
 	struct rio_impl_port_spec	port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
 };
 /* Revision Control Register */
 struct rio_rev_ctrl {
 	u32	ipbrr[2];	/* IP Block Revision Register */
 };
 struct rio_atmu_row {
 	u32	rowtar; /* RapidIO Outbound Window TAR */
 	u32	rowtear; /* RapidIO Outbound Window TEAR */
 	u32	rowbar;
 	u8	res0[4];
 	u32	rowar; /* RapidIO Outbound Attributes Register */
 	u32	rowsr[3]; /* Port RapidIO outbound window segment register */
 };
 struct rio_atmu_riw {
 	u32	riwtar; /* RapidIO Inbound Window Translation AR */
 	u8	res0[4];
 	u32	riwbar; /* RapidIO Inbound Window Base AR */
 	u8	res1[4];
 	u32	riwar; /* RapidIO Inbound Attributes Register */
 	u8	res2[12];
 };
 /* ATMU window registers */
 struct rio_atmu_win {
 	struct rio_atmu_row	outbw[CONFIG_SYS_FSL_SRIO_OB_WIN_NUM];
 	u8	res0[64];
 	struct rio_atmu_riw	inbw[CONFIG_SYS_FSL_SRIO_IB_WIN_NUM];
 };
 struct rio_atmu {
 	struct rio_atmu_win	port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
 };
 #ifdef CONFIG_SYS_FSL_RMU
 struct rio_msg {
 	u32	omr; /* Outbound Mode Register */
 	u32	osr; /* Outbound Status Register */
 	u32	eodqdpar; /* Extended Outbound DQ DPAR */
 	u32	odqdpar; /* Outbound Descriptor Queue DPAR */
 	u32	eosar; /* Extended Outbound Unit Source AR */
 	u32	osar; /* Outbound Unit Source AR */
 	u32	odpr; /* Outbound Destination Port Register */
 	u32	odatr; /* Outbound Destination Attributes Register */
 	u32	odcr; /* Outbound Doubleword Count Register */
 	u32	eodqepar; /* Extended Outbound DQ EPAR */
 	u32	odqepar; /* Outbound Descriptor Queue EPAR */
 	u32	oretr; /* Outbound Retry Error Threshold Register */
 	u32	omgr; /* Outbound Multicast Group Register */
 	u32	omlr; /* Outbound Multicast List Register */
 	u8	res0[40];
 	u32	imr;	 /* Outbound Mode Register */
 	u32	isr; /* Inbound Status Register */
 	u32	eidqdpar; /* Extended Inbound Descriptor Queue DPAR */
 	u32	idqdpar; /* Inbound Descriptor Queue DPAR */
 	u32	eifqepar; /* Extended Inbound Frame Queue EPAR */
 	u32	ifqepar; /* Inbound Frame Queue EPAR */
 	u32	imirir; /* Inbound Maximum Interrutp RIR */
 	u8	res1[4];
 	u32 eihqepar; /* Extended inbound message header queue EPAR */
 	u32 ihqepar; /* Inbound message header queue EPAR */
 	u8	res2[120];
 };
 struct rio_dbell {
 	u32	odmr; /* Outbound Doorbell Mode Register */
 	u32	odsr; /* Outbound Doorbell Status Register */
 	u8	res0[16];
 	u32	oddpr; /* Outbound Doorbell Destination Port */
 	u32	oddatr; /* Outbound Doorbell Destination AR */
 	u8	res1[12];
 	u32	oddretr; /* Outbound Doorbell Retry Threshold CR */
 	u8	res2[48];
 	u32	idmr; /* Inbound Doorbell Mode Register */
 	u32	idsr;	 /* Inbound Doorbell Status Register */
 	u32	iedqdpar; /* Extended Inbound Doorbell Queue DPAR */
 	u32	iqdpar; /* Inbound Doorbell Queue DPAR */
 	u32	iedqepar; /* Extended Inbound Doorbell Queue EPAR */
 	u32	idqepar; /* Inbound Doorbell Queue EPAR */
 	u32	idmirir; /* Inbound Doorbell Max Interrupt RIR */
 };
 struct rio_pw {
 	u32	pwmr; /* Port-Write Mode Register */
 	u32	pwsr; /* Port-Write Status Register */
 	u32	epwqbar; /* Extended Port-Write Queue BAR */
 	u32	pwqbar; /* Port-Write Queue Base Address Register */
 };
 #endif
 #ifdef CONFIG_SYS_FSL_SRIO_LIODN
 struct rio_liodn {
 	u32	plbr;
 	u8	res0[28];
 	u32	plaor;
 	u8	res1[12];
 	u32	pludr;
 	u32	plldr;
 	u8	res2[456];
 };
 #endif
 /* RapidIO Registers */
 struct ccsr_rio {
 	struct rio_arch	arch;
 	u8	res0[144];
 	struct rio_lp_serial	lp_serial;
 	u8	res1[1152];
 	struct rio_logical_err	logical_err;
 	u8	res2[32];
 	struct rio_phys_err	phys_err;
 	u8	res3[63808];
 	struct rio_implement	impl;
 	u8	res4[2552];
 	struct rio_rev_ctrl	rev;
 	struct rio_atmu	atmu;
 #ifdef CONFIG_SYS_FSL_RMU
 	u8	res5[8192];
 	struct rio_msg	msg[CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM];
 	u8	res6[512];
 	struct rio_dbell	dbell;
 	u8	res7[100];
 	struct rio_pw	pw;
 #endif
 #ifdef CONFIG_SYS_FSL_SRIO_LIODN
 	u8	res5[8192];
 	struct rio_liodn liodn[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
 #endif
 };
 #endif
 /* Quick Engine Block Pin Muxing Registers */
 typedef struct par_io {
 	u32	cpodr;
 	u32	cpdat;
 	u32	cpdir1;
 	u32	cpdir2;
 	u32	cppar1;
 	u32	cppar2;
 	u8	res[8];
 } par_io_t;
 #ifdef CONFIG_SYS_FSL_CPC
 /*
  * Define a single offset that is the start of all the CPC register
  * blocks - if there is more than one CPC, we expect these to be
  * contiguous 4k regions
  */
 typedef struct cpc_corenet {
 	u32 	cpccsr0;	/* Config/status reg */
 	u32	res1;
 	u32	cpccfg0;	/* Configuration register */
 	u32	res2;
 	u32	cpcewcr0;	/* External Write reg 0 */
 	u32	cpcewabr0;	/* External write base reg 0 */
 	u32	res3[2];
 	u32	cpcewcr1;	/* External Write reg 1 */
 	u32	cpcewabr1;	/* External write base reg 1 */
 	u32	res4[54];
 	u32	cpcsrcr1;	/* SRAM control reg 1 */
 	u32	cpcsrcr0;	/* SRAM control reg 0 */
 	u32	res5[62];
 	struct {
 		u32	id;	/* partition ID */
 		u32	res;
 		u32	alloc;	/* partition allocation */
 		u32	way;	/* partition way */
 	} partition_regs[16];
 	u32	res6[704];
 	u32	cpcerrinjhi;	/* Error injection high */
 	u32	cpcerrinjlo;	/* Error injection lo */
 	u32	cpcerrinjctl;	/* Error injection control */
 	u32	res7[5];
 	u32	cpccaptdatahi;	/* capture data high */
 	u32	cpccaptdatalo;	/* capture data low */
 	u32	cpcaptecc;	/* capture ECC */
 	u32	res8[5];
 	u32	cpcerrdet;	/* error detect */
 	u32	cpcerrdis;	/* error disable */
 	u32	cpcerrinten;	/* errir interrupt enable */
 	u32	cpcerrattr;	/* error attribute */
 	u32	cpcerreaddr;	/* error extended address */
 	u32	cpcerraddr;	/* error address */
 	u32	cpcerrctl;	/* error control */
 	u32	res9[41];	/* pad out to 4k */
 	u32	cpchdbcr0;	/* hardware debug control register 0 */
 	u32	res10[63];	/* pad out to 4k */
 } cpc_corenet_t;
 #define CPC_CSR0_CE	0x80000000	/* Cache Enable */
 #define CPC_CSR0_PE	0x40000000	/* Enable ECC */
 #define CPC_CSR0_FI	0x00200000	/* Cache Flash Invalidate */
 #define CPC_CSR0_WT	0x00080000	/* Write-through mode */
 #define CPC_CSR0_FL	0x00000800	/* Hardware cache flush */
 #define CPC_CSR0_LFC	0x00000400	/* Cache Lock Flash Clear */
 #define CPC_CFG0_SZ_MASK	0x00003fff
 #define CPC_CFG0_SZ_K(x)	((x & CPC_CFG0_SZ_MASK) << 6)
 #define CPC_CFG0_NUM_WAYS(x)	(((x >> 14) & 0x1f) + 1)
 #define CPC_CFG0_LINE_SZ(x)	((((x >> 23) & 0x3) + 1) * 32)
 #define CPC_SRCR1_SRBARU_MASK	0x0000ffff
 #define CPC_SRCR1_SRBARU(x)	(((unsigned long long)x >> 32) \
 				 & CPC_SRCR1_SRBARU_MASK)
 #define	CPC_SRCR0_SRBARL_MASK	0xffff8000
 #define CPC_SRCR0_SRBARL(x)	(x & CPC_SRCR0_SRBARL_MASK)
 #define CPC_SRCR0_INTLVEN	0x00000100
 #define CPC_SRCR0_SRAMSZ_1_WAY	0x00000000
 #define CPC_SRCR0_SRAMSZ_2_WAY	0x00000002
 #define CPC_SRCR0_SRAMSZ_4_WAY	0x00000004
 #define CPC_SRCR0_SRAMSZ_8_WAY	0x00000006
 #define CPC_SRCR0_SRAMSZ_16_WAY	0x00000008
 #define CPC_SRCR0_SRAMSZ_32_WAY	0x0000000a
 #define CPC_SRCR0_SRAMEN	0x00000001
 #define	CPC_ERRDIS_TMHITDIS  	0x00000080	/* multi-way hit disable */
 #define CPC_HDBCR0_CDQ_SPEC_DIS	0x08000000
 #define CPC_HDBCR0_TAG_ECC_SCRUB_DIS	0x01000000
 #define CPC_HDBCR0_DATA_ECC_SCRUB_DIS	0x00400000
 #define CPC_HDBCR0_SPLRU_LEVEL_EN	0x001e0000
 #endif /* CONFIG_SYS_FSL_CPC */
 /* Global Utilities Block */
 #ifdef CONFIG_FSL_CORENET
 typedef struct ccsr_gur {
 	u32	porsr1;		/* POR status 1 */
 	u32	porsr2;		/* POR status 2 */
 #ifdef	CONFIG_SYS_FSL_SINGLE_SOURCE_CLK
 #define	FSL_DCFG_PORSR1_SYSCLK_SHIFT	15
 #define	FSL_DCFG_PORSR1_SYSCLK_MASK	0x1
 #define	FSL_DCFG_PORSR1_SYSCLK_SINGLE_ENDED	0x1
 #define	FSL_DCFG_PORSR1_SYSCLK_DIFF	0x0
 #endif
 	u8	res_008[0x20-0x8];
 	u32	gpporcr1;	/* General-purpose POR configuration */
 	u32	gpporcr2;	/* General-purpose POR configuration 2 */
 	u32	dcfg_fusesr;	/* Fuse status register */
 #define FSL_CORENET_DCFG_FUSESR_VID_SHIFT	25
 #define FSL_CORENET_DCFG_FUSESR_VID_MASK	0x1F
 #define FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT	20
 #define FSL_CORENET_DCFG_FUSESR_ALTVID_MASK	0x1F
 	u8	res_02c[0x70-0x2c];
 	u32	devdisr;	/* Device disable control */
 	u32	devdisr2;	/* Device disable control 2 */
 	u32	devdisr3;	/* Device disable control 3 */
 	u32	devdisr4;	/* Device disable control 4 */
 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
 	u32	devdisr5;	/* Device disable control 5 */
 #define FSL_CORENET_DEVDISR_PBL	0x80000000
 #define FSL_CORENET_DEVDISR_PMAN	0x40000000
 #define FSL_CORENET_DEVDISR_ESDHC	0x20000000
 #define FSL_CORENET_DEVDISR_DMA1	0x00800000
 #define FSL_CORENET_DEVDISR_DMA2	0x00400000
 #define FSL_CORENET_DEVDISR_USB1	0x00080000
 #define FSL_CORENET_DEVDISR_USB2	0x00040000
 #define FSL_CORENET_DEVDISR_SATA1	0x00008000
 #define FSL_CORENET_DEVDISR_SATA2	0x00004000
 #define FSL_CORENET_DEVDISR_PME	0x00000800
 #define FSL_CORENET_DEVDISR_SEC	0x00000200
 #define FSL_CORENET_DEVDISR_RMU	0x00000080
 #define FSL_CORENET_DEVDISR_DCE	0x00000040
 #define FSL_CORENET_DEVDISR2_DTSEC1_1	0x80000000
 #define FSL_CORENET_DEVDISR2_DTSEC1_2	0x40000000
 #define FSL_CORENET_DEVDISR2_DTSEC1_3	0x20000000
 #define FSL_CORENET_DEVDISR2_DTSEC1_4	0x10000000
 #define FSL_CORENET_DEVDISR2_DTSEC1_5	0x08000000
 #define FSL_CORENET_DEVDISR2_DTSEC1_6	0x04000000
 #define FSL_CORENET_DEVDISR2_DTSEC1_9	0x00800000
 #define FSL_CORENET_DEVDISR2_DTSEC1_10	0x00400000
 #ifdef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
 #define FSL_CORENET_DEVDISR2_10GEC1_1   0x80000000
 #define FSL_CORENET_DEVDISR2_10GEC1_2   0x40000000
 #else
 #define FSL_CORENET_DEVDISR2_10GEC1_1	0x00800000
 #define FSL_CORENET_DEVDISR2_10GEC1_2	0x00400000
 #define FSL_CORENET_DEVDISR2_10GEC1_3	0x80000000
 #define FSL_CORENET_DEVDISR2_10GEC1_4	0x40000000
 #endif
 #define FSL_CORENET_DEVDISR2_DTSEC2_1	0x00080000
 #define FSL_CORENET_DEVDISR2_DTSEC2_2	0x00040000
 #define FSL_CORENET_DEVDISR2_DTSEC2_3	0x00020000
 #define FSL_CORENET_DEVDISR2_DTSEC2_4	0x00010000
 #define FSL_CORENET_DEVDISR2_DTSEC2_5	0x00008000
 #define FSL_CORENET_DEVDISR2_DTSEC2_6	0x00004000
 #define FSL_CORENET_DEVDISR2_DTSEC2_9	0x00000800
 #define FSL_CORENET_DEVDISR2_DTSEC2_10	0x00000400
 #define FSL_CORENET_DEVDISR2_10GEC2_1	0x00000800
 #define FSL_CORENET_DEVDISR2_10GEC2_2	0x00000400
 #define FSL_CORENET_DEVDISR2_FM1	0x00000080
 #define FSL_CORENET_DEVDISR2_FM2	0x00000040
 #define FSL_CORENET_DEVDISR2_CPRI	0x00000008
 #define FSL_CORENET_DEVDISR3_PCIE1	0x80000000
 #define FSL_CORENET_DEVDISR3_PCIE2	0x40000000
 #define FSL_CORENET_DEVDISR3_PCIE3	0x20000000
 #define FSL_CORENET_DEVDISR3_PCIE4	0x10000000
 #define FSL_CORENET_DEVDISR3_SRIO1	0x08000000
 #define FSL_CORENET_DEVDISR3_SRIO2	0x04000000
 #define FSL_CORENET_DEVDISR3_QMAN	0x00080000
 #define FSL_CORENET_DEVDISR3_BMAN	0x00040000
 #define FSL_CORENET_DEVDISR3_LA1	0x00008000
 #define FSL_CORENET_DEVDISR3_MAPLE1	0x00000800
 #define FSL_CORENET_DEVDISR3_MAPLE2	0x00000400
 #define FSL_CORENET_DEVDISR3_MAPLE3	0x00000200
 #define FSL_CORENET_DEVDISR4_I2C1	0x80000000
 #define FSL_CORENET_DEVDISR4_I2C2	0x40000000
 #define FSL_CORENET_DEVDISR4_DUART1	0x20000000
 #define FSL_CORENET_DEVDISR4_DUART2	0x10000000
 #define FSL_CORENET_DEVDISR4_ESPI	0x08000000
 #define FSL_CORENET_DEVDISR5_DDR1	0x80000000
 #define FSL_CORENET_DEVDISR5_DDR2	0x40000000
 #define FSL_CORENET_DEVDISR5_DDR3	0x20000000
 #define FSL_CORENET_DEVDISR5_CPC1	0x08000000
 #define FSL_CORENET_DEVDISR5_CPC2	0x04000000
 #define FSL_CORENET_DEVDISR5_CPC3	0x02000000
 #define FSL_CORENET_DEVDISR5_IFC	0x00800000
 #define FSL_CORENET_DEVDISR5_GPIO	0x00400000
 #define FSL_CORENET_DEVDISR5_DBG	0x00200000
 #define FSL_CORENET_DEVDISR5_NAL	0x00100000
 #define FSL_CORENET_DEVDISR5_TIMERS	0x00020000
 #define FSL_CORENET_NUM_DEVDISR		5
 #else
 #define FSL_CORENET_DEVDISR_PCIE1	0x80000000
 #define FSL_CORENET_DEVDISR_PCIE2	0x40000000
 #define FSL_CORENET_DEVDISR_PCIE3	0x20000000
 #define FSL_CORENET_DEVDISR_PCIE4	0x10000000
 #define FSL_CORENET_DEVDISR_RMU		0x08000000
 #define FSL_CORENET_DEVDISR_SRIO1	0x04000000
 #define FSL_CORENET_DEVDISR_SRIO2	0x02000000
 #define FSL_CORENET_DEVDISR_DMA1	0x00400000
 #define FSL_CORENET_DEVDISR_DMA2	0x00200000
 #define FSL_CORENET_DEVDISR_DDR1	0x00100000
 #define FSL_CORENET_DEVDISR_DDR2	0x00080000
 #define FSL_CORENET_DEVDISR_DBG		0x00010000
 #define FSL_CORENET_DEVDISR_NAL		0x00008000
 #define FSL_CORENET_DEVDISR_SATA1	0x00004000
 #define FSL_CORENET_DEVDISR_SATA2	0x00002000
 #define FSL_CORENET_DEVDISR_ELBC	0x00001000
 #define FSL_CORENET_DEVDISR_USB1	0x00000800
 #define FSL_CORENET_DEVDISR_USB2	0x00000400
 #define FSL_CORENET_DEVDISR_ESDHC	0x00000100
 #define FSL_CORENET_DEVDISR_GPIO	0x00000080
 #define FSL_CORENET_DEVDISR_ESPI	0x00000040
 #define FSL_CORENET_DEVDISR_I2C1	0x00000020
 #define FSL_CORENET_DEVDISR_I2C2	0x00000010
 #define FSL_CORENET_DEVDISR_DUART1	0x00000002
 #define FSL_CORENET_DEVDISR_DUART2	0x00000001
 #define FSL_CORENET_DEVDISR2_PME	0x80000000
 #define FSL_CORENET_DEVDISR2_SEC	0x40000000
 #define FSL_CORENET_DEVDISR2_QMBM	0x08000000
 #define FSL_CORENET_DEVDISR2_FM1	0x02000000
 #define FSL_CORENET_DEVDISR2_10GEC1	0x01000000
 #define FSL_CORENET_DEVDISR2_DTSEC1_1	0x00800000
 #define FSL_CORENET_DEVDISR2_DTSEC1_2	0x00400000
 #define FSL_CORENET_DEVDISR2_DTSEC1_3	0x00200000
 #define FSL_CORENET_DEVDISR2_DTSEC1_4	0x00100000
 #define FSL_CORENET_DEVDISR2_DTSEC1_5	0x00080000
 #define FSL_CORENET_DEVDISR2_FM2	0x00020000
 #define FSL_CORENET_DEVDISR2_10GEC2	0x00010000
 #define FSL_CORENET_DEVDISR2_DTSEC2_1	0x00008000
 #define FSL_CORENET_DEVDISR2_DTSEC2_2	0x00004000
 #define FSL_CORENET_DEVDISR2_DTSEC2_3	0x00002000
 #define FSL_CORENET_DEVDISR2_DTSEC2_4	0x00001000
 #define FSL_CORENET_DEVDISR2_DTSEC2_5	0x00000800
 #define FSL_CORENET_NUM_DEVDISR		2
 	u32	powmgtcsr;	/* Power management status & control */
 #endif
 	u8	res8[12];
 	u32	coredisru;	/* uppper portion for support of 64 cores */
 	u32	coredisrl;	/* lower portion for support of 64 cores */
 	u8	res9[8];
 	u32	pvr;		/* Processor version */
 	u32	svr;		/* System version */
 	u8	res10[8];
 	u32	rstcr;		/* Reset control */
 	u32	rstrqpblsr;	/* Reset request preboot loader status */
 	u8	res11[8];
 	u32	rstrqmr1;	/* Reset request mask */
 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
 #define FSL_CORENET_RSTRQMR1_SRDS_RST_MSK      0x00000800
 #endif
 	u8	res12[4];
 	u32	rstrqsr1;	/* Reset request status */
 	u8	res13[4];
 	u8	res14[4];
 	u32	rstrqwdtmrl;	/* Reset request WDT mask */
 	u8	res15[4];
 	u32	rstrqwdtsrl;	/* Reset request WDT status */
 	u8	res16[4];
 	u32	brrl;		/* Boot release */
 	u8	res17[24];
 	u32	rcwsr[16];	/* Reset control word status */
 #define RCW_SB_EN_REG_INDEX	7
 #define RCW_SB_EN_MASK		0x00200000
 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT	16
 /* use reserved bits 18~23 as scratch space to host DDR PLL ratio */
 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_RESV_SHIFT	8
 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK	0x3f
 #if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL		0xfc000000
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT	26
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL		0x00fe0000
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT	17
 #define FSL_CORENET2_RCWSR4_SRDS3_PRTCL		0x0000f800
 #define FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT	11
 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL		0x000000f8
 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT	3
 #define FSL_CORENET_RCWSR6_BOOT_LOC	0x0f800000
 #elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL	0xfe000000
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT	25
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL	0x00ff0000
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT	16
 #define FSL_CORENET_RCWSR6_BOOT_LOC	0x0f800000
 #elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL	0xff000000
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT	24
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL	0x00fe0000
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT	17
 #define FSL_CORENET_RCWSR13_EC1	0x30000000 /* bits 418..419 */
 #define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII	0x00000000
 #define FSL_CORENET_RCWSR13_EC1_FM1_GPIO	0x10000000
 #define FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII	0x20000000
 #define FSL_CORENET_RCWSR13_EC2	0x0c000000 /* bits 420..421 */
 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII	0x00000000
 #define FSL_CORENET_RCWSR13_EC2_FM1_GPIO	0x10000000
 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII	0x20000000
 #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL	0x00000080
 #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH	0x00000000
 #define FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT	0x80000000
 #define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET	0x28
 #define PXCKEN_MASK	0x80000000
 #define PXCK_MASK	0x00FF0000
 #define PXCK_BITS_START	16
 #elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL		0xff800000
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT	23
 #define FSL_CORENET_RCWSR6_BOOT_LOC		0x0f800000
 #define FSL_CORENET_RCWSR13_EC1			0x30000000 /* bits 418..419 */
 #define FSL_CORENET_RCWSR13_EC1_RGMII		0x00000000
 #define FSL_CORENET_RCWSR13_EC1_GPIO		0x10000000
 #define FSL_CORENET_RCWSR13_EC2			0x0c000000
 #define FSL_CORENET_RCWSR13_EC2_RGMII		0x08000000
 #define CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET	0x28
 #define CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET	0xd00
 #define PXCKEN_MASK				0x80000000
 #define PXCK_MASK				0x00FF0000
 #define PXCK_BITS_START				16
 #elif defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL		0xff000000
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT	24
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL		0x00ff0000
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT	16
 #define FSL_CORENET_RCWSR6_BOOT_LOC		0x0f800000
 #endif
 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL1	0x00800000
 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S1_PLL2	0x00400000
 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL1	0x00200000
 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S2_PLL2	0x00100000
 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL1	0x00080000
 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S3_PLL2	0x00040000
 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL1	0x00020000
 #define FSL_CORENET2_RCWSR5_SRDS_PLL_PD_S4_PLL2	0x00010000
 #define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_SHIFT 4
 #define FSL_CORENET2_RCWSR5_DDR_REFCLK_SEL_MASK	0x00000011
 #define FSL_CORENET2_RCWSR5_DDR_REFCLK_SINGLE_CLK	1
 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_SHIFT	17
 #define FSL_CORENET_RCWSR0_MEM_PLL_RAT_MASK	0x1f
 #define FSL_CORENET_RCWSR4_SRDS_PRTCL		0xfc000000
 #define FSL_CORENET_RCWSR5_DDR_SYNC		0x00000080
 #define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT		 7
 #define FSL_CORENET_RCWSR5_SRDS_EN		0x00002000
 #define FSL_CORENET_RCWSR5_SRDS2_EN		0x00001000
 #define FSL_CORENET_RCWSR6_BOOT_LOC	0x0f800000
 #define FSL_CORENET_RCWSRn_SRDS_LPD_B2		0x3c000000 /* bits 162..165 */
 #define FSL_CORENET_RCWSRn_SRDS_LPD_B3		0x003c0000 /* bits 170..173 */
 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 #define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT	0x00400000
 #define FSL_CORENET_RCWSR8_HOST_AGT_B1		0x00e00000
 #define FSL_CORENET_RCWSR8_HOST_AGT_B2		0x00100000
 #define FSL_CORENET_RCWSR11_EC1			0x00c00000 /* bits 360..361 */
 #ifdef CONFIG_ARCH_P4080
 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1		0x00000000
 #define FSL_CORENET_RCWSR11_EC1_FM1_USB1		0x00800000
 #define FSL_CORENET_RCWSR11_EC2			0x001c0000 /* bits 363..365 */
 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC1		0x00000000
 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2		0x00080000
 #define FSL_CORENET_RCWSR11_EC2_USB2			0x00100000
 #endif
 #if defined(CONFIG_ARCH_P2041) || \
 	defined(CONFIG_ARCH_P3041) || defined(CONFIG_ARCH_P5020)
 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII	0x00000000
 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII		0x00800000
 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_NONE		0x00c00000
 #define FSL_CORENET_RCWSR11_EC2			0x00180000 /* bits 363..364 */
 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_RGMII	0x00000000
 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII		0x00100000
 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_NONE		0x00180000
 #endif
 #if defined(CONFIG_ARCH_P5040)
 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII        0x00000000
 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII          0x00800000
 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_NONE         0x00c00000
 #define FSL_CORENET_RCWSR11_EC2                 0x00180000 /* bits 363..364 */
 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_RGMII        0x00000000
 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII          0x00100000
 #define FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_NONE         0x00180000
 #endif
 #if defined(CONFIG_ARCH_T4240) || defined(CONFIG_ARCH_T4160)
 #define FSL_CORENET_RCWSR13_EC1			0x60000000 /* bits 417..418 */
 #define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII	0x00000000
 #define FSL_CORENET_RCWSR13_EC1_FM2_GPIO		0x40000000
 #define FSL_CORENET_RCWSR13_EC2			0x18000000 /* bits 419..420 */
 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII	0x00000000
 #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC6_RGMII	0x08000000
 #define FSL_CORENET_RCWSR13_EC2_FM1_GPIO		0x10000000
 #endif
 #if defined(CONFIG_ARCH_T2080) || defined(CONFIG_ARCH_T2081)
 #define FSL_CORENET_RCWSR13_EC1			0x60000000 /* bits 417..418 */
 #define FSL_CORENET_RCWSR13_EC1_DTSEC3_RGMII	0x00000000
 #define FSL_CORENET_RCWSR13_EC1_GPIO		0x40000000
 #define FSL_CORENET_RCWSR13_EC2			0x18000000 /* bits 419..420 */
 #define FSL_CORENET_RCWSR13_EC2_DTSEC4_RGMII	0x00000000
 #define FSL_CORENET_RCWSR13_EC2_DTSEC10_RGMII	0x08000000
 #define FSL_CORENET_RCWSR13_EC2_GPIO		0x10000000
 #endif
 	u8	res18[192];
 	u32	scratchrw[4];	/* Scratch Read/Write */
 	u8	res19[240];
 	u32	scratchw1r[4];	/* Scratch Read (Write once) */
 	u8	res20[240];
 	u32	scrtsr[8];	/* Core reset status */
 	u8	res21[224];
 	u32	pex1liodnr;	/* PCI Express 1 LIODN */
 	u32	pex2liodnr;	/* PCI Express 2 LIODN */
 	u32	pex3liodnr;	/* PCI Express 3 LIODN */
 	u32	pex4liodnr;	/* PCI Express 4 LIODN */
 	u32	rio1liodnr;	/* RIO 1 LIODN */
 	u32	rio2liodnr;	/* RIO 2 LIODN */
 	u32	rio3liodnr;	/* RIO 3 LIODN */
 	u32	rio4liodnr;	/* RIO 4 LIODN */
 	u32	usb1liodnr;	/* USB 1 LIODN */
 	u32	usb2liodnr;	/* USB 2 LIODN */
 	u32	usb3liodnr;	/* USB 3 LIODN */
 	u32	usb4liodnr;	/* USB 4 LIODN */
 	u32	sdmmc1liodnr;	/* SD/MMC 1 LIODN */
 	u32	sdmmc2liodnr;	/* SD/MMC 2 LIODN */
 	u32	sdmmc3liodnr;	/* SD/MMC 3 LIODN */
 	u32	sdmmc4liodnr;	/* SD/MMC 4 LIODN */
 	u32	rio1maintliodnr;/* RIO 1 Maintenance LIODN */
 	u32	rio2maintliodnr;/* RIO 2 Maintenance LIODN */
 	u32	rio3maintliodnr;/* RIO 3 Maintenance LIODN */
 	u32	rio4maintliodnr;/* RIO 4 Maintenance LIODN */
 	u32	sata1liodnr;	/* SATA 1 LIODN */
 	u32	sata2liodnr;	/* SATA 2 LIODN */
 	u32	sata3liodnr;	/* SATA 3 LIODN */
 	u32	sata4liodnr;	/* SATA 4 LIODN */
 	u8	res22[20];
 	u32	tdmliodnr;	/* TDM LIODN */
 	u32     qeliodnr;       /* QE LIODN */
 	u8      res_57c[4];
 	u32	dma1liodnr;	/* DMA 1 LIODN */
 	u32	dma2liodnr;	/* DMA 2 LIODN */
 	u32	dma3liodnr;	/* DMA 3 LIODN */
 	u32	dma4liodnr;	/* DMA 4 LIODN */
 	u8	res23[48];
 	u8	res24[64];
 	u32	pblsr;		/* Preboot loader status */
 	u32	pamubypenr;	/* PAMU bypass enable */
 	u32	dmacr1;		/* DMA control */
 	u8	res25[4];
 	u32	gensr1;		/* General status */
 	u8	res26[12];
 	u32	gencr1;		/* General control */
 	u8	res27[12];
 	u8	res28[4];
 	u32	cgensrl;	/* Core general status */
 	u8	res29[8];
 	u8	res30[4];
 	u32	cgencrl;	/* Core general control */
 	u8	res31[184];
 	u32	sriopstecr;	/* SRIO prescaler timer enable control */
 	u32	dcsrcr;		/* DCSR Control register */
 	u8	res31a[56];
 	u32	tp_ityp[64];	/* Topology Initiator Type Register */
 	struct {
 		u32	upper;
 		u32	lower;
 	} tp_cluster[16];	/* Core Cluster n Topology Register */
 	u8	res32[1344];
 	u32	pmuxcr;		/* Pin multiplexing control */
 	u8	res33[60];
 	u32	iovselsr;	/* I/O voltage selection status */
 	u8	res34[28];
 	u32	ddrclkdr;	/* DDR clock disable */
 	u8	res35;
 	u32	elbcclkdr;	/* eLBC clock disable */
 	u8	res36[20];
 	u32	sdhcpcr;	/* eSDHC polarity configuration */
 	u8	res37[380];
 } ccsr_gur_t;
 #define TP_ITYP_AV	0x00000001		/* Initiator available */
 #define TP_ITYP_TYPE(x)	(((x) & 0x6) >> 1)	/* Initiator Type */
 #define TP_ITYP_TYPE_OTHER	0x0
 #define TP_ITYP_TYPE_PPC	0x1	/* PowerPC */
 #define TP_ITYP_TYPE_SC		0x2	/* StarCore DSP */
 #define TP_ITYP_TYPE_HA		0x3	/* HW Accelerator */
 #define TP_ITYP_THDS(x)	(((x) & 0x18) >> 3)	/* # threads */
 #define TP_ITYP_VER(x)	(((x) & 0xe0) >> 5)	/* Initiator Version */
 #define TP_CLUSTER_EOC		0x80000000	/* end of clusters */
 #define TP_CLUSTER_INIT_MASK	0x0000003f	/* initiator mask */
 #define TP_INIT_PER_CLUSTER	4
 #define FSL_CORENET_DCSR_SZ_MASK	0x00000003
 #define FSL_CORENET_DCSR_SZ_4M		0x0
 #define FSL_CORENET_DCSR_SZ_1G		0x3
 /*
  * On p4080 we have an LIODN for msg unit (rmu) but not maintenance
  * everything after has RMan thus msg unit LIODN is used for maintenance
  */
 #define rmuliodnr rio1maintliodnr
 typedef struct ccsr_clk {
 	struct {
 		u32 clkcncsr;	/* core cluster n clock control status */
 		u8  res_004[0x0c];
 		u32 clkcgnhwacsr;/* clock generator n hardware accelerator */
 		u8  res_014[0x0c];
 	} clkcsr[12];
 	u8	res_100[0x680]; /* 0x100 */
 	struct {
 		u32 pllcngsr;
 		u8 res10[0x1c];
 	} pllcgsr[12];
 	u8	res21[0x280];
 	u32	pllpgsr;	/* 0xc00 Platform PLL General Status */
 	u8	res16[0x1c];
 	u32	plldgsr;	/* 0xc20 DDR PLL General Status */
 	u8	res17[0x3dc];
 } ccsr_clk_t;
 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
 typedef struct ccsr_rcpm {
 	u8	res_00[12];
 	u32	tph10sr0;	/* Thread PH10 Status Register */
 	u8	res_10[12];
 	u32	tph10setr0;	/* Thread PH10 Set Control Register */
 	u8	res_20[12];
 	u32	tph10clrr0;	/* Thread PH10 Clear Control Register */
 	u8	res_30[12];
 	u32	tph10psr0;	/* Thread PH10 Previous Status Register */
 	u8	res_40[12];
 	u32	twaitsr0;	/* Thread Wait Status Register */
 	u8	res_50[96];
 	u32	pcph15sr;	/* Physical Core PH15 Status Register */
 	u32	pcph15setr;	/* Physical Core PH15 Set Control Register */
 	u32	pcph15clrr;	/* Physical Core PH15 Clear Control Register */
 	u32	pcph15psr;	/* Physical Core PH15 Prev Status Register */
 	u8	res_c0[16];
 	u32	pcph20sr;	/* Physical Core PH20 Status Register */
 	u32	pcph20setr;	/* Physical Core PH20 Set Control Register */
 	u32	pcph20clrr;	/* Physical Core PH20 Clear Control Register */
 	u32	pcph20psr;	/* Physical Core PH20 Prev Status Register */
 	u32	pcpw20sr;	/* Physical Core PW20 Status Register */
 	u8	res_e0[12];
 	u32	pcph30sr;	/* Physical Core PH30 Status Register */
 	u32	pcph30setr;	/* Physical Core PH30 Set Control Register */
 	u32	pcph30clrr;	/* Physical Core PH30 Clear Control Register */
 	u32	pcph30psr;	/* Physical Core PH30 Prev Status Register */
 	u8	res_100[32];
 	u32	ippwrgatecr;	/* IP Power Gating Control Register */
 	u8	res_124[12];
 	u32	powmgtcsr;	/* Power Management Control & Status Reg */
 	u8	res_134[12];
 	u32	ippdexpcr[4];	/* IP Powerdown Exception Control Reg */
 	u8	res_150[12];
 	u32	tpmimr0;	/* Thread PM Interrupt Mask Reg */
 	u8	res_160[12];
 	u32	tpmcimr0;	/* Thread PM Crit Interrupt Mask Reg */
 	u8	res_170[12];
 	u32	tpmmcmr0;	/* Thread PM Machine Check Interrupt Mask Reg */
 	u8	res_180[12];
 	u32	tpmnmimr0;	/* Thread PM NMI Mask Reg */
 	u8	res_190[12];
 	u32	tmcpmaskcr0;	/* Thread Machine Check Mask Control Reg */
 	u32	pctbenr;	/* Physical Core Time Base Enable Reg */
 	u32	pctbclkselr;	/* Physical Core Time Base Clock Select */
 	u32	tbclkdivr;	/* Time Base Clock Divider Register */
 	u8	res_1ac[4];
 	u32	ttbhltcr[4];	/* Thread Time Base Halt Control Register */
 	u32	clpcl10sr;	/* Cluster PCL10 Status Register */
 	u32	clpcl10setr;	/* Cluster PCL30 Set Control Register */
 	u32	clpcl10clrr;	/* Cluster PCL30 Clear Control Register */
 	u32	clpcl10psr;	/* Cluster PCL30 Prev Status Register */
 	u32	cddslpsetr;	/* Core Domain Deep Sleep Set Register */
 	u32	cddslpclrr;	/* Core Domain Deep Sleep Clear Register */
 	u32	cdpwroksetr;	/* Core Domain Power OK Set Register */
 	u32	cdpwrokclrr;	/* Core Domain Power OK Clear Register */
 	u32	cdpwrensr;	/* Core Domain Power Enable Status Register */
 	u32	cddslsr;	/* Core Domain Deep Sleep Status Register */
 	u8	res_1e8[8];
 	u32	dslpcntcr[8];	/* Deep Sleep Counter Cfg Register */
 	u8	res_300[3568];
 } ccsr_rcpm_t;
 #define ctbenrl pctbenr
 #else
 typedef struct ccsr_rcpm {
 	u8	res1[4];
 	u32	cdozsrl;	/* Core Doze Status */
 	u8	res2[4];
 	u32	cdozcrl;	/* Core Doze Control */
 	u8	res3[4];
 	u32	cnapsrl;	/* Core Nap Status */
 	u8	res4[4];
 	u32	cnapcrl;	/* Core Nap Control */
 	u8	res5[4];
 	u32	cdozpsrl;	/* Core Doze Previous Status */
 	u8	res6[4];
 	u32	cdozpcrl;	/* Core Doze Previous Control */
 	u8	res7[4];
 	u32	cwaitsrl;	/* Core Wait Status */
 	u8	res8[8];
 	u32	powmgtcsr;	/* Power Mangement Control & Status */
 	u8	res9[12];
 	u32	ippdexpcr0;	/* IP Powerdown Exception Control 0 */
 	u8	res10[12];
 	u8	res11[4];
 	u32	cpmimrl;	/* Core PM IRQ Masking */
 	u8	res12[4];
 	u32	cpmcimrl;	/* Core PM Critical IRQ Masking */
 	u8	res13[4];
 	u32	cpmmcimrl;	/* Core PM Machine Check IRQ Masking */
 	u8	res14[4];
 	u32	cpmnmimrl;	/* Core PM NMI Masking */
 	u8	res15[4];
 	u32	ctbenrl;	/* Core Time Base Enable */
 	u8	res16[4];
 	u32	ctbclkselrl;	/* Core Time Base Clock Select */
 	u8	res17[4];
 	u32	ctbhltcrl;	/* Core Time Base Halt Control */
 	u8	res18[0xf68];
 } ccsr_rcpm_t;
 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 #else
 typedef struct ccsr_gur {
 	u32	porpllsr;	/* POR PLL ratio status */
 #ifdef CONFIG_ARCH_MPC8536
 #define MPC85xx_PORPLLSR_DDR_RATIO	0x3e000000
 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT	25
 #elif defined(CONFIG_ARCH_C29X)
 #define MPC85xx_PORPLLSR_DDR_RATIO	0x00003f00
 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT	(9 - ((gur->pordevsr2 \
 					& MPC85xx_PORDEVSR2_DDR_SPD_0) \
 					>> MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT))
 #else
 #if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
 #define MPC85xx_PORPLLSR_DDR_RATIO	0x00003f00
 #else
 #define MPC85xx_PORPLLSR_DDR_RATIO	0x00003e00
 #endif
 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT	9
 #endif
 #define MPC85xx_PORPLLSR_QE_RATIO	0x3e000000
 #define MPC85xx_PORPLLSR_QE_RATIO_SHIFT		25
 #define MPC85xx_PORPLLSR_PLAT_RATIO	0x0000003e
 #define MPC85xx_PORPLLSR_PLAT_RATIO_SHIFT	1
 	u32	porbmsr;	/* POR boot mode status */
 #define MPC85xx_PORBMSR_HA		0x00070000
 #define MPC85xx_PORBMSR_HA_SHIFT	16
 #define MPC85xx_PORBMSR_ROMLOC_SHIFT	24
 #define PORBMSR_ROMLOC_SPI	0x6
 #define PORBMSR_ROMLOC_SDHC	0x7
 #define PORBMSR_ROMLOC_NAND_2K	0x9
 #define PORBMSR_ROMLOC_NOR	0xf
 	u32	porimpscr;	/* POR I/O impedance status & control */
 	u32	pordevsr;	/* POR I/O device status regsiter */
 #if defined(CONFIG_ARCH_P1023)
 #define MPC85xx_PORDEVSR_SGMII1_DIS	0x10000000
 #define MPC85xx_PORDEVSR_SGMII2_DIS	0x08000000
 #define MPC85xx_PORDEVSR_TSEC1_PRTC	0x02000000
 #else
 #define MPC85xx_PORDEVSR_SGMII1_DIS	0x20000000
 #define MPC85xx_PORDEVSR_SGMII2_DIS	0x10000000
 #endif
 #define MPC85xx_PORDEVSR_SGMII3_DIS	0x08000000
 #define MPC85xx_PORDEVSR_SGMII4_DIS	0x04000000
 #define MPC85xx_PORDEVSR_SRDS2_IO_SEL	0x38000000
 #define MPC85xx_PORDEVSR_PCI1		0x00800000
 #if defined(CONFIG_ARCH_P1022)
 #define MPC85xx_PORDEVSR_IO_SEL		0x007c0000
 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT	18
 #elif defined(CONFIG_ARCH_P1023)
 #define MPC85xx_PORDEVSR_IO_SEL		0x00600000
 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT	21
 #else
 #if defined(CONFIG_ARCH_P1010)
 #define MPC85xx_PORDEVSR_IO_SEL		0x00600000
 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT	21
 #elif defined(CONFIG_ARCH_BSC9132)
 #define MPC85xx_PORDEVSR_IO_SEL		0x00FE0000
 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT	17
 #elif defined(CONFIG_ARCH_C29X)
 #define MPC85xx_PORDEVSR_IO_SEL		0x00e00000
 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT	21
 #else
 #define MPC85xx_PORDEVSR_IO_SEL		0x00780000
 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT	19
 #endif /* if defined(CONFIG_ARCH_P1010) */
 #endif
 #define MPC85xx_PORDEVSR_PCI2_ARB	0x00040000
 #define MPC85xx_PORDEVSR_PCI1_ARB	0x00020000
 #define MPC85xx_PORDEVSR_PCI1_PCI32	0x00010000
 #define MPC85xx_PORDEVSR_PCI1_SPD	0x00008000
 #define MPC85xx_PORDEVSR_PCI2_SPD	0x00004000
 #define MPC85xx_PORDEVSR_DRAM_RTYPE	0x00000060
 #define MPC85xx_PORDEVSR_RIO_CTLS	0x00000008
 #define MPC85xx_PORDEVSR_RIO_DEV_ID	0x00000007
 	u32	pordbgmsr;	/* POR debug mode status */
 	u32	pordevsr2;	/* POR I/O device status 2 */
 #if defined(CONFIG_ARCH_C29X)
 #define MPC85xx_PORDEVSR2_DDR_SPD_0	0x00000008
 #define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT	3
 #endif
 #define MPC85xx_PORDEVSR2_SBC_MASK	0x10000000
 /* The 8544 RM says this is bit 26, but it's really bit 24 */
 #define MPC85xx_PORDEVSR2_SEC_CFG	0x00000080
 	u8	res1[8];
 	u32	gpporcr;	/* General-purpose POR configuration */
 	u8	res2[12];
 #if defined(CONFIG_ARCH_MPC8536)
 	u32	gencfgr;	/* General Configuration Register */
 #define MPC85xx_GENCFGR_SDHC_WP_INV	0x20000000
 #else
 	u32	gpiocr;		/* GPIO control */
 #endif
 	u8	res3[12];
 #if defined(CONFIG_ARCH_MPC8569)
 	u32	plppar1;	/* Platform port pin assignment 1 */
 	u32	plppar2;	/* Platform port pin assignment 2 */
 	u32	plpdir1;	/* Platform port pin direction 1 */
 	u32	plpdir2;	/* Platform port pin direction 2 */
 #else
 	u32	gpoutdr;	/* General-purpose output data */
 	u8	res4[12];
 #endif
 	u32	gpindr;		/* General-purpose input data */
 	u8	res5[12];
 	u32	pmuxcr;		/* Alt. function signal multiplex control */
 #if defined(CONFIG_ARCH_P1010)
 #define MPC85xx_PMUXCR_TSEC1_0_1588		0x40000000
 #define MPC85xx_PMUXCR_TSEC1_0_RES		0xC0000000
 #define MPC85xx_PMUXCR_TSEC1_1_1588_TRIG	0x10000000
 #define MPC85xx_PMUXCR_TSEC1_1_GPIO_12		0x20000000
 #define MPC85xx_PMUXCR_TSEC1_1_RES		0x30000000
 #define MPC85xx_PMUXCR_TSEC1_2_DMA		0x04000000
 #define MPC85xx_PMUXCR_TSEC1_2_GPIO		0x08000000
 #define MPC85xx_PMUXCR_TSEC1_2_RES		0x0C000000
 #define MPC85xx_PMUXCR_TSEC1_3_RES		0x01000000
 #define MPC85xx_PMUXCR_TSEC1_3_GPIO_15		0x02000000
 #define MPC85xx_PMUXCR_IFC_ADDR16_SDHC		0x00400000
 #define MPC85xx_PMUXCR_IFC_ADDR16_USB		0x00800000
 #define MPC85xx_PMUXCR_IFC_ADDR16_IFC_CS2	0x00C00000
 #define MPC85xx_PMUXCR_IFC_ADDR17_18_SDHC	0x00100000
 #define MPC85xx_PMUXCR_IFC_ADDR17_18_USB	0x00200000
 #define MPC85xx_PMUXCR_IFC_ADDR17_18_DMA	0x00300000
 #define MPC85xx_PMUXCR_IFC_ADDR19_SDHC_DATA	0x00040000
 #define MPC85xx_PMUXCR_IFC_ADDR19_USB		0x00080000
 #define MPC85xx_PMUXCR_IFC_ADDR19_DMA		0x000C0000
 #define MPC85xx_PMUXCR_IFC_ADDR20_21_SDHC_DATA	0x00010000
 #define MPC85xx_PMUXCR_IFC_ADDR20_21_USB	0x00020000
 #define MPC85xx_PMUXCR_IFC_ADDR20_21_RES	0x00030000
 #define MPC85xx_PMUXCR_IFC_ADDR22_SDHC		0x00004000
 #define MPC85xx_PMUXCR_IFC_ADDR22_USB		0x00008000
 #define MPC85xx_PMUXCR_IFC_ADDR22_RES		0x0000C000
 #define MPC85xx_PMUXCR_IFC_ADDR23_SDHC		0x00001000
 #define MPC85xx_PMUXCR_IFC_ADDR23_USB		0x00002000
 #define MPC85xx_PMUXCR_IFC_ADDR23_RES		0x00003000
 #define MPC85xx_PMUXCR_IFC_ADDR24_SDHC		0x00000400
 #define MPC85xx_PMUXCR_IFC_ADDR24_USB		0x00000800
 #define MPC85xx_PMUXCR_IFC_ADDR24_RES		0x00000C00
 #define MPC85xx_PMUXCR_IFC_PAR_PERR_RES		0x00000300
 #define MPC85xx_PMUXCR_IFC_PAR_PERR_USB		0x00000200
 #define MPC85xx_PMUXCR_LCLK_RES			0x00000040
 #define MPC85xx_PMUXCR_LCLK_USB			0x00000080
 #define MPC85xx_PMUXCR_LCLK_IFC_CS3		0x000000C0
 #define MPC85xx_PMUXCR_SPI_RES			0x00000030
 #define MPC85xx_PMUXCR_SPI_GPIO			0x00000020
 #define MPC85xx_PMUXCR_CAN1_UART		0x00000004
 #define MPC85xx_PMUXCR_CAN1_TDM			0x00000008
 #define MPC85xx_PMUXCR_CAN1_RES			0x0000000C
 #define MPC85xx_PMUXCR_CAN2_UART		0x00000001
 #define MPC85xx_PMUXCR_CAN2_TDM			0x00000002
 #define MPC85xx_PMUXCR_CAN2_RES			0x00000003
 #endif
 #if defined(CONFIG_ARCH_P1023)
 #define MPC85xx_PMUXCR_TSEC1_1		0x10000000
 #else
 #define MPC85xx_PMUXCR_SD_DATA		0x80000000
 #define MPC85xx_PMUXCR_SDHC_CD		0x40000000
 #define MPC85xx_PMUXCR_SDHC_WP		0x20000000
 #define MPC85xx_PMUXCR_ELBC_OFF_USB2_ON	0x01000000
 #define MPC85xx_PMUXCR_TDM_ENA		0x00800000
 #define MPC85xx_PMUXCR_QE0		0x00008000
 #define MPC85xx_PMUXCR_QE1		0x00004000
 #define MPC85xx_PMUXCR_QE2		0x00002000
 #define MPC85xx_PMUXCR_QE3		0x00001000
 #define MPC85xx_PMUXCR_QE4		0x00000800
 #define MPC85xx_PMUXCR_QE5		0x00000400
 #define MPC85xx_PMUXCR_QE6		0x00000200
 #define MPC85xx_PMUXCR_QE7		0x00000100
 #define MPC85xx_PMUXCR_QE8		0x00000080
 #define MPC85xx_PMUXCR_QE9		0x00000040
 #define MPC85xx_PMUXCR_QE10		0x00000020
 #define MPC85xx_PMUXCR_QE11		0x00000010
 #define MPC85xx_PMUXCR_QE12		0x00000008
 #endif
 #if defined(CONFIG_ARCH_P1022)
 #define MPC85xx_PMUXCR_TDM_MASK		0x0001cc00
 #define MPC85xx_PMUXCR_TDM		0x00014800
 #define MPC85xx_PMUXCR_SPI_MASK		0x00600000
 #define MPC85xx_PMUXCR_SPI		0x00000000
 #endif
 #if defined(CONFIG_ARCH_BSC9131)
 #define MPC85xx_PMUXCR_TSEC2_DMA_GPIO_IRQ	0x40000000
 #define MPC85xx_PMUXCR_TSEC2_USB		0xC0000000
 #define MPC85xx_PMUXCR_TSEC2_1588_PPS		0x10000000
 #define MPC85xx_PMUXCR_TSEC2_1588_RSVD		0x30000000
 #define MPC85xx_PMUXCR_IFC_AD_GPIO		0x04000000
 #define MPC85xx_PMUXCR_IFC_AD_GPIO_MASK		0x0C000000
 #define MPC85xx_PMUXCR_IFC_AD15_GPIO		0x01000000
 #define MPC85xx_PMUXCR_IFC_AD15_TIMER2		0x02000000
 #define MPC85xx_PMUXCR_IFC_AD16_GPO8		0x00400000
 #define MPC85xx_PMUXCR_IFC_AD16_MSRCID0		0x00800000
 #define MPC85xx_PMUXCR_IFC_AD17_GPO		0x00100000
 #define MPC85xx_PMUXCR_IFC_AD17_GPO_MASK	0x00300000
 #define MPC85xx_PMUXCR_IFC_AD17_MSRCID_DSP	0x00200000
 #define MPC85xx_PMUXCR_IFC_CS2_GPO65		0x00040000
 #define MPC85xx_PMUXCR_IFC_CS2_DSP_TDI		0x00080000
 #define MPC85xx_PMUXCR_SDHC_USIM		0x00010000
 #define MPC85xx_PMUXCR_SDHC_TDM_RFS_RCK		0x00020000
 #define MPC85xx_PMUXCR_SDHC_GPIO77		0x00030000
 #define MPC85xx_PMUXCR_SDHC_RESV		0x00004000
 #define MPC85xx_PMUXCR_SDHC_TDM_TXD_RXD		0x00008000
 #define MPC85xx_PMUXCR_SDHC_GPIO_TIMER4		0x0000C000
 #define MPC85xx_PMUXCR_USB_CLK_UART_SIN		0x00001000
 #define MPC85xx_PMUXCR_USB_CLK_GPIO69		0x00002000
 #define MPC85xx_PMUXCR_USB_CLK_TIMER3		0x00003000
 #define MPC85xx_PMUXCR_USB_UART_GPIO0		0x00000400
 #define MPC85xx_PMUXCR_USB_RSVD			0x00000C00
 #define MPC85xx_PMUXCR_USB_GPIO62_TRIG_IN	0x00000800
 #define MPC85xx_PMUXCR_USB_D1_2_IIC2_SDA_SCL	0x00000100
 #define MPC85xx_PMUXCR_USB_D1_2_GPIO71_72	0x00000200
 #define MPC85xx_PMUXCR_USB_D1_2_RSVD		0x00000300
 #define MPC85xx_PMUXCR_USB_DIR_GPIO2		0x00000040
 #define MPC85xx_PMUXCR_USB_DIR_TIMER1		0x00000080
 #define MPC85xx_PMUXCR_USB_DIR_MCP_B		0x000000C0
 #define MPC85xx_PMUXCR_SPI1_UART3		0x00000010
 #define MPC85xx_PMUXCR_SPI1_SIM			0x00000020
 #define MPC85xx_PMUXCR_SPI1_CKSTP_IN_GPO74	0x00000030
 #define MPC85xx_PMUXCR_SPI1_CS2_CKSTP_OUT_B	0x00000004
 #define MPC85xx_PMUXCR_SPI1_CS2_dbg_adi1_rxen	0x00000008
 #define MPC85xx_PMUXCR_SPI1_CS2_GPO75		0x0000000C
 #define MPC85xx_PMUXCR_SPI1_CS3_ANT_TCXO_PWM	0x00000001
 #define MPC85xx_PMUXCR_SPI1_CS3_dbg_adi2_rxen	0x00000002
 #define MPC85xx_PMUXCR_SPI1_CS3_GPO76		0x00000003
 #endif
 #ifdef CONFIG_ARCH_BSC9132
 #define MPC85xx_PMUXCR0_SIM_SEL_MASK	0x0003b000
 #define MPC85xx_PMUXCR0_SIM_SEL		0x00014000
 #endif
 #if defined(CONFIG_ARCH_C29X)
 #define MPC85xx_PMUXCR_SPI_MASK			0x00000300
 #define MPC85xx_PMUXCR_SPI			0x00000000
 #define MPC85xx_PMUXCR_SPI_GPIO			0x00000100
 #endif
 	u32	pmuxcr2;	/* Alt. function signal multiplex control 2 */
 #if defined(CONFIG_ARCH_P1010)
 #define MPC85xx_PMUXCR2_UART_GPIO		0x40000000
 #define MPC85xx_PMUXCR2_UART_TDM		0x80000000
 #define MPC85xx_PMUXCR2_UART_RES		0xC0000000
 #define MPC85xx_PMUXCR2_IRQ2_TRIG_IN		0x10000000
 #define MPC85xx_PMUXCR2_IRQ2_RES		0x30000000
 #define MPC85xx_PMUXCR2_IRQ3_SRESET		0x04000000
 #define MPC85xx_PMUXCR2_IRQ3_RES		0x0C000000
 #define MPC85xx_PMUXCR2_GPIO01_DRVVBUS		0x01000000
 #define MPC85xx_PMUXCR2_GPIO01_RES		0x03000000
 #define MPC85xx_PMUXCR2_GPIO23_CKSTP		0x00400000
 #define MPC85xx_PMUXCR2_GPIO23_RES		0x00800000
 #define MPC85xx_PMUXCR2_GPIO23_USB		0x00C00000
 #define MPC85xx_PMUXCR2_GPIO4_MCP		0x00100000
 #define MPC85xx_PMUXCR2_GPIO4_RES		0x00200000
 #define MPC85xx_PMUXCR2_GPIO4_CLK_OUT		0x00300000
 #define MPC85xx_PMUXCR2_GPIO5_UDE		0x00040000
 #define MPC85xx_PMUXCR2_GPIO5_RES		0x00080000
 #define MPC85xx_PMUXCR2_READY_ASLEEP		0x00020000
 #define MPC85xx_PMUXCR2_DDR_ECC_MUX		0x00010000
 #define MPC85xx_PMUXCR2_DEBUG_PORT_EXPOSE	0x00008000
 #define MPC85xx_PMUXCR2_POST_EXPOSE		0x00004000
 #define MPC85xx_PMUXCR2_DEBUG_MUX_SEL_USBPHY	0x00002000
 #define MPC85xx_PMUXCR2_PLL_LKDT_EXPOSE		0x00001000
 #endif
 #if defined(CONFIG_ARCH_P1022)
 #define MPC85xx_PMUXCR2_ETSECUSB_MASK	0x001f8000
 #define MPC85xx_PMUXCR2_USB		0x00150000
 #endif
 #if defined(CONFIG_ARCH_BSC9131) || defined(CONFIG_ARCH_BSC9132)
 #if defined(CONFIG_ARCH_BSC9131)
 #define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD		0X40000000
 #define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS		0X80000000
 #define MPC85xx_PMUXCR2_UART_CTS_B0_GPIO42		0xC0000000
 #define MPC85xx_PMUXCR2_UART_RTS_B0_PWM2		0x10000000
 #define MPC85xx_PMUXCR2_UART_RTS_B0_DSP_TCK		0x20000000
 #define MPC85xx_PMUXCR2_UART_RTS_B0_GPIO43		0x30000000
 #define MPC85xx_PMUXCR2_UART_CTS_B1_SIM_PD		0x04000000
 #define MPC85xx_PMUXCR2_UART_CTS_B1_SRESET_B		0x08000000
 #define MPC85xx_PMUXCR2_UART_CTS_B1_GPIO44		0x0C000000
 #define MPC85xx_PMUXCR2_UART_RTS_B1_PPS_LED		0x01000000
 #define MPC85xx_PMUXCR2_UART_RTS_B1_RSVD		0x02000000
 #define MPC85xx_PMUXCR2_UART_RTS_B1_GPIO45		0x03000000
 #define MPC85xx_PMUXCR2_TRIG_OUT_ASLEEP			0x00400000
 #define MPC85xx_PMUXCR2_TRIG_OUT_DSP_TRST_B		0x00800000
 #define MPC85xx_PMUXCR2_ANT1_TIMER5			0x00100000
 #define MPC85xx_PMUXCR2_ANT1_TSEC_1588			0x00200000
 #define MPC85xx_PMUXCR2_ANT1_GPIO95_19			0x00300000
 #define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_MAX3_LOCK	0x00040000
 #define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_RSVD		0x00080000
 #define MPC85xx_PMUXCR2_ANT1_TX_RX_FRAME_GPIO80_20	0x000C0000
 #define MPC85xx_PMUXCR2_ANT1_DIO0_3_SPI3_CS0		0x00010000
 #define MPC85xx_PMUXCR2_ANT1_DIO0_3_ANT2_DO_3		0x00020000
 #define MPC85xx_PMUXCR2_ANT1_DIO0_3_GPIO81_84		0x00030000
 #define MPC85xx_PMUXCR2_ANT1_DIO4_7_SPI4		0x00004000
 #define MPC85xx_PMUXCR2_ANT1_DIO4_7_ANT2_DO4_7		0x00008000
 #define MPC85xx_PMUXCR2_ANT1_DIO4_7_GPIO85_88		0x0000C000
 #define MPC85xx_PMUXCR2_ANT1_DIO8_9_MAX2_1_LOCK		0x00001000
 #define MPC85xx_PMUXCR2_ANT1_DIO8_9_ANT2_DO8_9		0x00002000
 #define MPC85xx_PMUXCR2_ANT1_DIO8_9_GPIO21_22		0x00003000
 #define MPC85xx_PMUXCR2_ANT1_DIO10_11_TIMER6_7		0x00000400
 #define MPC85xx_PMUXCR2_ANT1_DIO10_11_ANT2_DO10_11	0x00000800
 #define MPC85xx_PMUXCR2_ANT1_DIO10_11_GPIO23_24		0x00000C00
 #define MPC85xx_PMUXCR2_ANT2_RSVD			0x00000100
 #define MPC85xx_PMUXCR2_ANT2_GPO90_91_DMA		0x00000300
 #define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_USB		0x00000040
 #define MPC85xx_PMUXCR2_ANT2_ENABLE_DIO0_10_GPIO	0x000000C0
 #define MPC85xx_PMUXCR2_ANT2_DIO11_RSVD			0x00000010
 #define MPC85xx_PMUXCR2_ANT2_DIO11_TIMER8		0x00000020
 #define MPC85xx_PMUXCR2_ANT2_DIO11_GPIO61		0x00000030
 #define MPC85xx_PMUXCR2_ANT3_AGC_GPO53			0x00000004
 #define MPC85xx_PMUXCR2_ANT3_DO_TDM			0x00000001
 #define MPC85xx_PMUXCR2_ANT3_DO_GPIO46_49		0x00000002
 #endif
 	u32	pmuxcr3;
 #if defined(CONFIG_ARCH_BSC9131)
 #define MPC85xx_PMUXCR3_ANT3_DO4_5_TDM			0x40000000
 #define MPC85xx_PMUXCR3_ANT3_DO4_5_GPIO_50_51		0x80000000
 #define MPC85xx_PMUXCR3_ANT3_DO6_7_TRIG_IN_SRESET_B	0x10000000
 #define MPC85xx_PMUXCR3_ANT3_DO6_7_GPIO_52_53		0x20000000
 #define MPC85xx_PMUXCR3_ANT3_DO8_MCP_B			0x04000000
 #define MPC85xx_PMUXCR3_ANT3_DO8_GPIO54			0x08000000
 #define MPC85xx_PMUXCR3_ANT3_DO9_10_CKSTP_IN_OUT	0x01000000
 #define MPC85xx_PMUXCR3_ANT3_DO9_10_GPIO55_56		0x02000000
 #define MPC85xx_PMUXCR3_ANT3_DO11_IRQ_OUT		0x00400000
 #define MPC85xx_PMUXCR3_ANT3_DO11_GPIO57		0x00800000
 #define MPC85xx_PMUXCR3_SPI2_CS2_GPO93			0x00100000
 #define MPC85xx_PMUXCR3_SPI2_CS3_GPO94			0x00040000
 #define MPC85xx_PMUXCR3_ANT2_AGC_RSVD			0x00010000
 #define MPC85xx_PMUXCR3_ANT2_GPO89			0x00030000
 #endif
 #ifdef CONFIG_ARCH_BSC9132
 #define MPC85xx_PMUXCR3_USB_SEL_MASK	0x0000ff00
 #define MPC85xx_PMUXCR3_UART2_SEL	0x00005000
 #define MPC85xx_PMUXCR3_UART3_SEL_MASK	0xc0000000
 #define MPC85xx_PMUXCR3_UART3_SEL	0x40000000
 #endif
 	u32 pmuxcr4;
 #else
 	u8	res6[8];
 #endif
 	u32	devdisr;	/* Device disable control */
 #define MPC85xx_DEVDISR_PCI1		0x80000000
 #define MPC85xx_DEVDISR_PCI2		0x40000000
 #define MPC85xx_DEVDISR_PCIE		0x20000000
 #define MPC85xx_DEVDISR_LBC		0x08000000
 #define MPC85xx_DEVDISR_PCIE2		0x04000000
 #define MPC85xx_DEVDISR_PCIE3		0x02000000
 #define MPC85xx_DEVDISR_SEC		0x01000000
 #define MPC85xx_DEVDISR_SRIO		0x00080000
 #define MPC85xx_DEVDISR_RMSG		0x00040000
 #define MPC85xx_DEVDISR_DDR		0x00010000
 #define MPC85xx_DEVDISR_CPU		0x00008000
 #define MPC85xx_DEVDISR_CPU0		MPC85xx_DEVDISR_CPU
 #define MPC85xx_DEVDISR_TB		0x00004000
 #define MPC85xx_DEVDISR_TB0		MPC85xx_DEVDISR_TB
 #define MPC85xx_DEVDISR_CPU1		0x00002000
 #define MPC85xx_DEVDISR_TB1		0x00001000
 #define MPC85xx_DEVDISR_DMA		0x00000400
 #define MPC85xx_DEVDISR_TSEC1		0x00000080
 #define MPC85xx_DEVDISR_TSEC2		0x00000040
 #define MPC85xx_DEVDISR_TSEC3		0x00000020
 #define MPC85xx_DEVDISR_TSEC4		0x00000010
 #define MPC85xx_DEVDISR_I2C		0x00000004
 #define MPC85xx_DEVDISR_DUART		0x00000002
 	u8	res7[12];
 	u32	powmgtcsr;	/* Power management status & control */
 	u8	res8[12];
 	u32	mcpsumr;	/* Machine check summary */
 	u8	res9[12];
 	u32	pvr;		/* Processor version */
 	u32	svr;		/* System version */
 	u8	res10[8];
 	u32	rstcr;		/* Reset control */
 #if defined(CONFIG_ARCH_MPC8568) || defined(CONFIG_ARCH_MPC8569)
 	u8	res11a[76];
 	par_io_t qe_par_io[7];
 	u8	res11b[1600];
 #elif defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025)
 	u8      res11a[12];
 	u32     iovselsr;
 	u8      res11b[60];
 	par_io_t qe_par_io[3];
 	u8      res11c[1496];
 #else
 	u8	res11a[1868];
 #endif
 	u32	clkdvdr;	/* Clock Divide register */
 	u8	res12[1532];
 	u32	clkocr;		/* Clock out select */
 	u8	res13[12];
 	u32	ddrdllcr;	/* DDR DLL control */
 	u8	res14[12];
 	u32	lbcdllcr;	/* LBC DLL control */
 #if defined(CONFIG_ARCH_BSC9131)
 	u8	res15[12];
 	u32	halt_req_mask;
 #define HALTED_TO_HALT_REQ_MASK_0	0x80000000
 	u8	res18[232];
 #else
 	u8	res15[248];
 #endif
 	u32	lbiuiplldcr0;	/* LBIU PLL Debug Reg 0 */
 	u32	lbiuiplldcr1;	/* LBIU PLL Debug Reg 1 */
 	u32	ddrioovcr;	/* DDR IO Override Control */
 	u32	tsec12ioovcr;	/* eTSEC 1/2 IO override control */
 	u32	tsec34ioovcr;	/* eTSEC 3/4 IO override control */
 	u8      res16[52];
 	u32	sdhcdcr;	/* SDHC debug control register */
 	u8      res17[61592];
 } ccsr_gur_t;
 #endif
 #define SDHCDCR_CD_INV		0x80000000 /* invert SDHC card detect */
 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
 #define MAX_SERDES 4
 #if defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
 #define SRDS_MAX_LANES 4
 #else
 #define SRDS_MAX_LANES 8
 #endif
 #define SRDS_MAX_BANK 2
 typedef struct serdes_corenet {
 	struct {
 		u32	rstctl;	/* Reset Control Register */
 #define SRDS_RSTCTL_RST		0x80000000
 #define SRDS_RSTCTL_RSTDONE	0x40000000
 #define SRDS_RSTCTL_RSTERR	0x20000000
 #define SRDS_RSTCTL_SWRST	0x10000000
 #define SRDS_RSTCTL_SDEN	0x00000020
 #define SRDS_RSTCTL_SDRST_B	0x00000040
 #define SRDS_RSTCTL_PLLRST_B	0x00000080
 #define SRDS_RSTCTL_RSTERR_SHIFT  29
 		u32	pllcr0; /* PLL Control Register 0 */
 #define SRDS_PLLCR0_POFF		0x80000000
 #define SRDS_PLLCR0_RFCK_SEL_MASK	0x70000000
 #define SRDS_PLLCR0_RFCK_SEL_100	0x00000000
 #define SRDS_PLLCR0_RFCK_SEL_125	0x10000000
 #define SRDS_PLLCR0_RFCK_SEL_156_25	0x20000000
 #define SRDS_PLLCR0_RFCK_SEL_150	0x30000000
 #define SRDS_PLLCR0_RFCK_SEL_161_13	0x40000000
 #define SRDS_PLLCR0_RFCK_SEL_122_88	0x50000000
 #define SRDS_PLLCR0_PLL_LCK		0x00800000
 #define SRDS_PLLCR0_DCBIAS_OUT_EN      0x02000000
 #define SRDS_PLLCR0_FRATE_SEL_MASK	0x000f0000
 #define SRDS_PLLCR0_FRATE_SEL_5		0x00000000
 #define SRDS_PLLCR0_FRATE_SEL_4_9152	0x00030000
 #define SRDS_PLLCR0_FRATE_SEL_3_75	0x00050000
 #define SRDS_PLLCR0_FRATE_SEL_5_15	0x00060000
 #define SRDS_PLLCR0_FRATE_SEL_4		0x00070000
 #define SRDS_PLLCR0_FRATE_SEL_3_125	0x00090000
 #define SRDS_PLLCR0_FRATE_SEL_3_0	0x000a0000
 #define SRDS_PLLCR0_FRATE_SEL_3_072	0x000c0000
 #define SRDS_PLLCR0_DCBIAS_OVRD		0x000000F0
 #define SRDS_PLLCR0_DCBIAS_OVRD_SHIFT	4
 		u32	pllcr1; /* PLL Control Register 1 */
 #define SRDS_PLLCR1_BCAP_EN		0x20000000
 #define SRDS_PLLCR1_BCAP_OVD		0x10000000
 #define SRDS_PLLCR1_PLL_FCAP		0x001F8000
 #define SRDS_PLLCR1_PLL_FCAP_SHIFT	15
 #define SRDS_PLLCR1_PLL_BWSEL		0x08000000
 #define SRDS_PLLCR1_BYP_CAL		0x02000000
 		u32	pllsr2;	/* At 0x00c, PLL Status Register 2 */
 #define SRDS_PLLSR2_BCAP_EN		0x00800000
 #define SRDS_PLLSR2_BCAP_EN_SHIFT	23
 #define SRDS_PLLSR2_FCAP		0x003F0000
 #define SRDS_PLLSR2_FCAP_SHIFT		16
 #define SRDS_PLLSR2_DCBIAS		0x000F0000
 #define SRDS_PLLSR2_DCBIAS_SHIFT	16
 		u32	pllcr3;
 		u32	pllcr4;
 		u8	res_18[0x20-0x18];
 	} bank[2];
 	u8	res_40[0x90-0x40];
 	u32	srdstcalcr;	/* 0x90 TX Calibration Control */
 	u8	res_94[0xa0-0x94];
 	u32	srdsrcalcr;	/* 0xa0 RX Calibration Control */
 	u8	res_a4[0xb0-0xa4];
 	u32	srdsgr0;	/* 0xb0 General Register 0 */
 	u8	res_b4[0xe0-0xb4];
 	u32	srdspccr0;	/* 0xe0 Protocol Converter Config 0 */
 	u32	srdspccr1;	/* 0xe4 Protocol Converter Config 1 */
 	u32	srdspccr2;	/* 0xe8 Protocol Converter Config 2 */
 	u32	srdspccr3;	/* 0xec Protocol Converter Config 3 */
 	u32	srdspccr4;	/* 0xf0 Protocol Converter Config 4 */
 	u8	res_f4[0x100-0xf4];
 	struct {
 		u32	lnpssr;	/* 0x100, 0x120, ..., 0x1e0 */
 		u8	res_104[0x120-0x104];
 	} srdslnpssr[8];
 	u8	res_200[0x800-0x200];
 	struct {
 		u32	gcr0;	/* 0x800 General Control Register 0 */
 		u32	gcr1;	/* 0x804 General Control Register 1 */
 		u32	gcr2;	/* 0x808 General Control Register 2 */
 		u32	res_80c;
 		u32	recr0;	/* 0x810 Receive Equalization Control */
 		u32	res_814;
 		u32	tecr0;	/* 0x818 Transmit Equalization Control */
 		u32	res_81c;
 		u32	ttlcr0;	/* 0x820 Transition Tracking Loop Ctrl 0 */
 		u8	res_824[0x840-0x824];
 	} lane[8];	/* Lane A, B, C, D, E, F, G, H */
 	u8	res_a00[0x1000-0xa00];	/* from 0xa00 to 0xfff */
 } serdes_corenet_t;
 #else /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 #define SRDS_MAX_LANES		18
 #define SRDS_MAX_BANK		3
 typedef struct serdes_corenet {
 	struct {
 		u32	rstctl;	/* Reset Control Register */
 #define SRDS_RSTCTL_RST		0x80000000
 #define SRDS_RSTCTL_RSTDONE	0x40000000
 #define SRDS_RSTCTL_RSTERR	0x20000000
 #define SRDS_RSTCTL_SDPD	0x00000020
 		u32	pllcr0; /* PLL Control Register 0 */
 #define SRDS_PLLCR0_RFCK_SEL_MASK	0x70000000
 #define SRDS_PLLCR0_PVCOCNT_EN		0x02000000
 #define SRDS_PLLCR0_RFCK_SEL_100	0x00000000
 #define SRDS_PLLCR0_RFCK_SEL_125	0x10000000
 #define SRDS_PLLCR0_RFCK_SEL_156_25	0x20000000
 #define SRDS_PLLCR0_RFCK_SEL_150	0x30000000
 #define SRDS_PLLCR0_RFCK_SEL_161_13	0x40000000
 #define SRDS_PLLCR0_FRATE_SEL_MASK	0x00030000
 #define SRDS_PLLCR0_FRATE_SEL_5		0x00000000
 #define SRDS_PLLCR0_FRATE_SEL_6_25	0x00010000
 		u32	pllcr1; /* PLL Control Register 1 */
 #define SRDS_PLLCR1_PLL_BWSEL	0x08000000
 		u32	res[5];
 	} bank[3];
 	u32	res1[12];
 	u32	srdstcalcr;	/* TX Calibration Control */
 	u32	res2[3];
 	u32	srdsrcalcr;	/* RX Calibration Control */
 	u32	res3[3];
 	u32	srdsgr0;	/* General Register 0 */
 	u32	res4[11];
 	u32	srdspccr0;	/* Protocol Converter Config 0 */
 	u32	srdspccr1;	/* Protocol Converter Config 1 */
 	u32	srdspccr2;	/* Protocol Converter Config 2 */
 #define SRDS_PCCR2_RST_XGMII1		0x00800000
 #define SRDS_PCCR2_RST_XGMII2		0x00400000
 	u32	res5[197];
 	struct serdes_lane {
 		u32	gcr0;	/* General Control Register 0 */
 #define SRDS_GCR0_RRST			0x00400000
 #define SRDS_GCR0_1STLANE		0x00010000
 #define SRDS_GCR0_UOTHL			0x00100000
 		u32	gcr1;	/* General Control Register 1 */
 #define SRDS_GCR1_REIDL_CTL_MASK	0x001f0000
 #define SRDS_GCR1_REIDL_CTL_PCIE	0x00100000
 #define SRDS_GCR1_REIDL_CTL_SRIO	0x00000000
 #define SRDS_GCR1_REIDL_CTL_SGMII	0x00040000
 #define SRDS_GCR1_OPAD_CTL		0x04000000
 		u32	res1[4];
 		u32	tecr0;	/* TX Equalization Control Reg 0 */
 #define SRDS_TECR0_TEQ_TYPE_MASK	0x30000000
 #define SRDS_TECR0_TEQ_TYPE_2LVL	0x10000000
 		u32	res3;
 		u32	ttlcr0;	/* Transition Tracking Loop Ctrl 0 */
 #define SRDS_TTLCR0_FLT_SEL_MASK	0x3f000000
 #define SRDS_TTLCR0_FLT_SEL_KFR_26	0x10000000
 #define SRDS_TTLCR0_FLT_SEL_KPH_28	0x08000000
 #define SRDS_TTLCR0_FLT_SEL_750PPM	0x03000000
 #define SRDS_TTLCR0_PM_DIS		0x00004000
 #define SRDS_TTLCR0_FREQOVD_EN		0x00000001
 		u32	res4[7];
 	} lane[24];
 	u32 res6[384];
 } serdes_corenet_t;
 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 enum {
 	FSL_SRDS_B1_LANE_A = 0,
 	FSL_SRDS_B1_LANE_B = 1,
 	FSL_SRDS_B1_LANE_C = 2,
 	FSL_SRDS_B1_LANE_D = 3,
 	FSL_SRDS_B1_LANE_E = 4,
 	FSL_SRDS_B1_LANE_F = 5,
 	FSL_SRDS_B1_LANE_G = 6,
 	FSL_SRDS_B1_LANE_H = 7,
 	FSL_SRDS_B1_LANE_I = 8,
 	FSL_SRDS_B1_LANE_J = 9,
 	FSL_SRDS_B2_LANE_A = 16,
 	FSL_SRDS_B2_LANE_B = 17,
 	FSL_SRDS_B2_LANE_C = 18,
 	FSL_SRDS_B2_LANE_D = 19,
 	FSL_SRDS_B3_LANE_A = 20,
 	FSL_SRDS_B3_LANE_B = 21,
 	FSL_SRDS_B3_LANE_C = 22,
 	FSL_SRDS_B3_LANE_D = 23,
 };
-typedef struct ccsr_qman {
-#ifdef CONFIG_SYS_FSL_QMAN_V3
-	u8	res0[0x200];
-#else
-	struct {
-		u32	qcsp_lio_cfg;	/* 0x0 - SW Portal n LIO cfg */
-		u32	qcsp_io_cfg;	/* 0x4 - SW Portal n IO cfg */
-		u32	res;
-		u32	qcsp_dd_cfg;	/* 0xc - SW Portal n Dynamic Debug cfg */
-	} qcsp[32];
-#endif
-	/* Not actually reserved, but irrelevant to u-boot */
-	u8	res[0xbf8 - 0x200];
-	u32	ip_rev_1;
-	u32	ip_rev_2;
-	u32	fqd_bare;	/* FQD Extended Base Addr Register */
-	u32	fqd_bar;	/* FQD Base Addr Register */
-	u8	res1[0x8];
-	u32	fqd_ar;		/* FQD Attributes Register */
-	u8	res2[0xc];
-	u32	pfdr_bare;	/* PFDR Extended Base Addr Register */
-	u32	pfdr_bar;	/* PFDR Base Addr Register */
-	u8	res3[0x8];
-	u32	pfdr_ar;	/* PFDR Attributes Register */
-	u8	res4[0x4c];
-	u32	qcsp_bare;	/* QCSP Extended Base Addr Register */
-	u32	qcsp_bar;	/* QCSP Base Addr Register */
-	u8	res5[0x78];
-	u32	ci_sched_cfg;	/* Initiator Scheduling Configuration */
-	u32	srcidr;		/* Source ID Register */
-	u32	liodnr;		/* LIODN Register */
-	u8	res6[4];
-	u32	ci_rlm_cfg;	/* Initiator Read Latency Monitor Cfg */
-	u32	ci_rlm_avg;	/* Initiator Read Latency Monitor Avg */
-	u8	res7[0x2e8];
-#ifdef CONFIG_SYS_FSL_QMAN_V3
-	struct {
-		u32	qcsp_lio_cfg;	/* 0x0 - SW Portal n LIO cfg */
-		u32	qcsp_io_cfg;	/* 0x4 - SW Portal n IO cfg */
-		u32	res;
-		u32	qcsp_dd_cfg;	/* 0xc - SW Portal n Dynamic Debug cfg*/
-	} qcsp[50];
-#endif
-} ccsr_qman_t;
-typedef struct ccsr_bman {
-	/* Not actually reserved, but irrelevant to u-boot */
-	u8	res[0xbf8];
-	u32	ip_rev_1;
-	u32	ip_rev_2;
-	u32	fbpr_bare;	/* FBPR Extended Base Addr Register */
-	u32	fbpr_bar;	/* FBPR Base Addr Register */
-	u8	res1[0x8];
-	u32	fbpr_ar;	/* FBPR Attributes Register */
-	u8	res2[0xf0];
-	u32	srcidr;		/* Source ID Register */
-	u32	liodnr;		/* LIODN Register */
-	u8	res7[0x2f4];
-} ccsr_bman_t;
 typedef struct ccsr_pme {
 	u8	res0[0x804];
 	u32	liodnbr;	/* LIODN Base Register */
 	u8	res1[0x1f8];
 	u32	srcidr;		/* Source ID Register */
 	u8	res2[8];
 	u32	liodnr;		/* LIODN Register */
 	u8	res3[0x1e8];
 	u32	pm_ip_rev_1;	/* PME IP Block Revision Reg 1*/
 	u32	pm_ip_rev_2;	/* PME IP Block Revision Reg 1*/
 	u8	res4[0x400];
 } ccsr_pme_t;
 struct ccsr_pamu {
 	u32 ppbah;
 	u32 ppbal;
 	u32 pplah;
 	u32 pplal;
 	u32 spbah;
 	u32 spbal;
 	u32 splah;
 	u32 splal;
 	u32 obah;
 	u32 obal;
 	u32 olah;
 	u32 olal;
 };
 #ifdef CONFIG_SYS_FSL_RAID_ENGINE
 struct ccsr_raide {
 	u8	res0[0x543];
 	u32	liodnbr;			/* LIODN Base Register */
 	u8	res1[0xab8];
 	struct {
 		struct {
 			u32	cfg0;		/* cfg register 0 */
 			u32	cfg1;		/* cfg register 1 */
 			u8	res1[0x3f8];
 		} ring[2];
 		u8	res[0x800];
 	} jq[2];
 };
 #endif
 #ifdef CONFIG_SYS_DPAA_RMAN
 struct ccsr_rman {
 	u8	res0[0xf64];
 	u32	mmliodnbr;	/* Message Manager LIODN Base Register */
 	u32	mmitar;		/* RMAN Inbound Translation Address Register */
 	u32	mmitdr;		/* RMAN Inbound Translation Data Register */
 	u8	res4[0x1f090];
 };
 #endif
 #ifdef CONFIG_SYS_PMAN
 struct ccsr_pman {
 	u8	res_00[0x40];
 	u32	poes1;		/* PMAN Operation Error Status Register 1 */
 	u32	poes2;		/* PMAN Operation Error Status Register 2 */
 	u32	poeah;		/* PMAN Operation Error Address High */
 	u32	poeal;		/* PMAN Operation Error Address Low */
 	u8	res_50[0x50];
 	u32	pr1;		/* PMAN Revision Register 1 */
 	u32	pr2;		/* PMAN Revision Register 2 */
 	u8	res_a8[0x8];
 	u32	pcap;		/* PMAN Capabilities Register */
 	u8	res_b4[0xc];
 	u32	pc1;		/* PMAN Control Register 1 */
 	u32	pc2;		/* PMAN Control Register 2 */
 	u32	pc3;		/* PMAN Control Register 3 */
 	u32	pc4;		/* PMAN Control Register 4 */
 	u32	pc5;		/* PMAN Control Register 5 */
 	u32	pc6;		/* PMAN Control Register 6 */
 	u8	res_d8[0x8];
 	u32	ppa1;		/* PMAN Prefetch Attributes Register 1 */
 	u32	ppa2;		/* PMAN Prefetch Attributes Register 2 */
 	u8	res_e8[0x8];
 	u32	pics;		/* PMAN Interrupt Control and Status */
 	u8	res_f4[0xf0c];
 };
 #endif
 #ifdef CONFIG_FSL_CORENET
 #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET	0x0000
 #ifdef CONFIG_SYS_PMAN
 #define CONFIG_SYS_FSL_CORENET_PMAN1_OFFSET	0x4000
 #define CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET	0x5000
 #define CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET	0x6000
 #endif
 #define CONFIG_SYS_MPC8xxx_DDR_OFFSET		0x8000
 #define CONFIG_SYS_MPC8xxx_DDR2_OFFSET		0x9000
 #define CONFIG_SYS_MPC8xxx_DDR3_OFFSET		0xA000
 #define CONFIG_SYS_FSL_CORENET_CLK_OFFSET	0xE1000
 #define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET	0xE2000
 #ifdef CONFIG_SYS_FSL_SFP_VER_3_0
 /* In SFPv3, OSPR register is now at offset 0x200.
  *  * So directly mapping sfp register map to this address */
 #define CONFIG_SYS_OSPR_OFFSET                  0x200
 #define CONFIG_SYS_SFP_OFFSET            (0xE8000 + CONFIG_SYS_OSPR_OFFSET)
 #else
 #define CONFIG_SYS_SFP_OFFSET                   0xE8000
 #endif
 #define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET	0xEA000
 #define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET	0xEB000
 #define CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET	0xEC000
 #define CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET	0xED000
 #define CONFIG_SYS_FSL_CPC_OFFSET		0x10000
 #define CONFIG_SYS_FSL_SCFG_OFFSET		0xFC000
 #define CONFIG_SYS_FSL_PAMU_OFFSET		0x20000
 #define CONFIG_SYS_MPC85xx_DMA1_OFFSET		0x100000
 #define CONFIG_SYS_MPC85xx_DMA2_OFFSET		0x101000
 #define CONFIG_SYS_MPC85xx_DMA3_OFFSET		0x102000
 #define CONFIG_SYS_MPC85xx_DMA_OFFSET		CONFIG_SYS_MPC85xx_DMA1_OFFSET
 #define CONFIG_SYS_MPC85xx_ESPI_OFFSET		0x110000
 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET		0x114000
 #define CONFIG_SYS_MPC85xx_LBC_OFFSET		0x124000
 #define CONFIG_SYS_MPC85xx_IFC_OFFSET		0x124000
 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET		0x130000
 #define CONFIG_SYS_MPC85xx_TDM_OFFSET		0x185000
 #define CONFIG_SYS_MPC85xx_QE_OFFSET		0x140000
 #define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET	0x1e0000
 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_ARCH_B4860) && \
 	!defined(CONFIG_ARCH_B4420)
 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET		0x240000
 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET		0x250000
 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET		0x260000
 #define CONFIG_SYS_MPC85xx_PCIE4_OFFSET		0x270000
 #else
 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET		0x200000
 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET		0x201000
 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET		0x202000
 #define CONFIG_SYS_MPC85xx_PCIE4_OFFSET		0x203000
 #endif
 #define CONFIG_SYS_MPC85xx_USB1_OFFSET		0x210000
 #define CONFIG_SYS_MPC85xx_USB2_OFFSET		0x211000
 #define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000
 #define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100
 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET		0x220000
 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET		0x221000
 #define CONFIG_SYS_FSL_SEC_OFFSET		0x300000
 #define CONFIG_SYS_FSL_JR0_OFFSET		0x301000
 #define CONFIG_SYS_SEC_MON_OFFSET		0x314000
 #define CONFIG_SYS_FSL_CORENET_PME_OFFSET	0x316000
 #define CONFIG_SYS_FSL_QMAN_OFFSET		0x318000
 #define CONFIG_SYS_FSL_BMAN_OFFSET		0x31a000
 #define CONFIG_SYS_FSL_RAID_ENGINE_OFFSET	0x320000
 #define CONFIG_SYS_FSL_FM1_OFFSET		0x400000
 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET	0x488000
 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET	0x489000
 #define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET	0x48a000
 #define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET	0x48b000
 #define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET	0x48c000
 #define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET	0x48d000
 #define CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET	0x490000
 #define CONFIG_SYS_FSL_FM1_RX1_10G_OFFSET	0x491000
 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET	0x4e0000
 #define CONFIG_SYS_FSL_FM2_OFFSET		0x500000
 #define CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET	0x588000
 #define CONFIG_SYS_FSL_FM2_RX1_1G_OFFSET	0x589000
 #define CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET	0x58a000
 #define CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET	0x58b000
 #define CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET	0x58c000
 #define CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET	0x58d000
 #define CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET	0x590000
 #define CONFIG_SYS_FSL_FM2_RX1_10G_OFFSET	0x591000
 #define CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET	0xC20000
 #else
 #define CONFIG_SYS_MPC85xx_ECM_OFFSET		0x0000
 #define CONFIG_SYS_MPC8xxx_DDR_OFFSET		0x2000
 #define CONFIG_SYS_MPC85xx_LBC_OFFSET		0x5000
 #define CONFIG_SYS_MPC8xxx_DDR2_OFFSET		0x6000
 #define CONFIG_SYS_MPC85xx_ESPI_OFFSET		0x7000
 #define CONFIG_SYS_MPC85xx_PCI1_OFFSET		0x8000
 #define CONFIG_SYS_MPC85xx_PCIX_OFFSET		0x8000
 #define CONFIG_SYS_MPC85xx_PCI2_OFFSET		0x9000
 #define CONFIG_SYS_MPC85xx_PCIX2_OFFSET		0x9000
 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET         0xa000
 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET         0x9000
 #if defined(CONFIG_ARCH_MPC8572) || defined(CONFIG_ARCH_P2020)
 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET         0x8000
 #else
 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET         0xb000
 #endif
 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET		0xF000
 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET		0x18000
 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET		0x19000
 #define CONFIG_SYS_MPC85xx_IFC_OFFSET		0x1e000
 #define CONFIG_SYS_MPC85xx_L2_OFFSET		0x20000
 #define CONFIG_SYS_MPC85xx_DMA_OFFSET		0x21000
 #define CONFIG_SYS_MPC85xx_USB1_OFFSET		0x22000
 #define CONFIG_SYS_MPC85xx_USB2_OFFSET		0x23000
 #define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET	0xE5000
 #define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET	0xE5100
 #ifdef CONFIG_TSECV2
 #define CONFIG_SYS_TSEC1_OFFSET			0xB0000
 #elif defined(CONFIG_TSECV2_1)
 #define CONFIG_SYS_TSEC1_OFFSET			0x10000
 #else
 #define CONFIG_SYS_TSEC1_OFFSET			0x24000
 #endif
 #define CONFIG_SYS_MDIO1_OFFSET			0x24000
 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET		0x2e000
 #if defined(CONFIG_ARCH_C29X)
 #define CONFIG_SYS_FSL_SEC_OFFSET		0x80000
 #define CONFIG_SYS_FSL_JR0_OFFSET               0x81000
 #else
 #define CONFIG_SYS_FSL_SEC_OFFSET		0x30000
 #define CONFIG_SYS_FSL_JR0_OFFSET               0x31000
 #endif
 #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET	0xE3100
 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET	0xE3000
 #define CONFIG_SYS_SEC_MON_OFFSET		0xE6000
 #define CONFIG_SYS_SFP_OFFSET			0xE7000
 #define CONFIG_SYS_MPC85xx_CPM_OFFSET		0x80000
 #define CONFIG_SYS_FSL_QMAN_OFFSET		0x88000
 #define CONFIG_SYS_FSL_BMAN_OFFSET		0x8a000
 #define CONFIG_SYS_FSL_FM1_OFFSET		0x100000
 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET	0x188000
 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET	0x189000
 #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET	0x1e0000
 #endif
 #define CONFIG_SYS_MPC85xx_PIC_OFFSET		0x40000
 #define CONFIG_SYS_MPC85xx_GUTS_OFFSET		0xE0000
 #define CONFIG_SYS_FSL_SRIO_OFFSET		0xC0000
 #if defined(CONFIG_ARCH_BSC9132)
 #define CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET	0x10000
 #define CONFIG_SYS_FSL_DSP_CCSR_DDR_ADDR \
 	(CONFIG_SYS_FSL_DSP_CCSRBAR + CONFIG_SYS_FSL_DSP_CCSR_DDR_OFFSET)
 #endif
 #define CONFIG_SYS_FSL_CPC_ADDR	\
 	(CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
 #define CONFIG_SYS_FSL_SCFG_ADDR	\
 	(CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_SCFG_OFFSET)
 #define CONFIG_SYS_FSL_SCFG_PIXCLK_ADDR	\
 	(CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_PIXCLKCR_OFFSET)
 #define CONFIG_SYS_FSL_SCFG_IODSECR1_ADDR \
 	(CONFIG_SYS_FSL_SCFG_ADDR + CONFIG_SYS_FSL_SCFG_IODSECR1_OFFSET)
 #define CONFIG_SYS_FSL_QMAN_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
 #define CONFIG_SYS_FSL_BMAN_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_PME_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET)
 #define CONFIG_SYS_FSL_RAID_ENGINE_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_RMAN_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RMAN_OFFSET)
 #define CONFIG_SYS_MPC85xx_GUTS_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_CCM_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_CLK_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_RCPM_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET)
 #define CONFIG_SYS_MPC85xx_ECM_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET)
 #define CONFIG_SYS_FSL_DDR_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
 #define CONFIG_SYS_FSL_DDR2_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
 #define CONFIG_SYS_FSL_DDR3_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR3_OFFSET)
 #define CONFIG_SYS_LBC_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
 #define CONFIG_SYS_IFC_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_IFC_OFFSET)
 #define CONFIG_SYS_MPC85xx_ESPI_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET)
 #define CONFIG_SYS_MPC85xx_PCIX_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET)
 #define CONFIG_SYS_MPC85xx_PCIX2_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET)
 #define CONFIG_SYS_MPC85xx_GPIO_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET)
 #define CONFIG_SYS_MPC85xx_SATA1_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET)
 #define CONFIG_SYS_MPC85xx_SATA2_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET)
 #define CONFIG_SYS_MPC85xx_L2_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET)
 #define CONFIG_SYS_MPC85xx_DMA_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET)
 #define CONFIG_SYS_MPC85xx_ESDHC_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
 #define CONFIG_SYS_MPC8xxx_PIC_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET)
 #define CONFIG_SYS_MPC85xx_CPM_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET)
 #define CONFIG_SYS_MPC85xx_SERDES1_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET)
 #define CONFIG_SYS_MPC85xx_SERDES2_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_SERDES3_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_SERDES4_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET)
 #define CONFIG_SYS_MPC85xx_USB1_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_OFFSET)
 #define CONFIG_SYS_MPC85xx_USB2_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_OFFSET)
 #define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET)
 #define CONFIG_SYS_MPC85xx_USB2_PHY_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET)
 #define CONFIG_SYS_FSL_SEC_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
 #define CONFIG_SYS_FSL_JR0_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
 #define CONFIG_SYS_FSL_FM1_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
 #define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
 #define CONFIG_SYS_FSL_FM2_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET)
 #define CONFIG_SYS_FSL_SRIO_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SRIO_OFFSET)
 #define CONFIG_SYS_PAMU_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_PAMU_OFFSET)
 #define CONFIG_SYS_PCI1_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET)
 #define CONFIG_SYS_PCI2_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI2_OFFSET)
 #define CONFIG_SYS_PCIE1_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE1_OFFSET)
 #define CONFIG_SYS_PCIE2_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE2_OFFSET)
 #define CONFIG_SYS_PCIE3_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE3_OFFSET)
 #define CONFIG_SYS_PCIE4_ADDR \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE4_OFFSET)
 #define CONFIG_SYS_SFP_ADDR  \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_SFP_OFFSET)
 #define CONFIG_SYS_SEC_MON_ADDR  \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_SEC_MON_OFFSET)
 #define TSEC_BASE_ADDR		(CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
 #define MDIO_BASE_ADDR		(CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
 struct ccsr_cluster_l2 {
 	u32 l2csr0;	/* 0x000 L2 cache control and status register 0 */
 	u32 l2csr1;	/* 0x004 L2 cache control and status register 1 */
 	u32 l2cfg0;	/* 0x008 L2 cache configuration register 0 */
 	u8  res_0c[500];/* 0x00c - 0x1ff */
 	u32 l2pir0;	/* 0x200 L2 cache partitioning ID register 0 */
 	u8  res_204[4];
 	u32 l2par0;	/* 0x208 L2 cache partitioning allocation register 0 */
 	u32 l2pwr0;	/* 0x20c L2 cache partitioning way register 0 */
 	u32 l2pir1;	/* 0x210 L2 cache partitioning ID register 1 */
 	u8  res_214[4];
 	u32 l2par1;	/* 0x218 L2 cache partitioning allocation register 1 */
 	u32 l2pwr1;	/* 0x21c L2 cache partitioning way register 1 */
 	u32 u2pir2;	/* 0x220 L2 cache partitioning ID register 2 */
 	u8  res_224[4];
 	u32 l2par2;	/* 0x228 L2 cache partitioning allocation register 2 */
 	u32 l2pwr2;	/* 0x22c L2 cache partitioning way register 2 */
 	u32 l2pir3;	/* 0x230 L2 cache partitioning ID register 3 */
 	u8  res_234[4];
 	u32 l2par3;	/* 0x238 L2 cache partitining allocation register 3 */
 	u32 l2pwr3;	/* 0x23c L2 cache partitining way register 3 */
 	u32 l2pir4;	/* 0x240 L2 cache partitioning ID register 3 */
 	u8  res244[4];
 	u32 l2par4;	/* 0x248 L2 cache partitioning allocation register 3 */
 	u32 l2pwr4;	/* 0x24c L2 cache partitioning way register 3 */
 	u32 l2pir5;	/* 0x250 L2 cache partitioning ID register 3 */
 	u8  res_254[4];
 	u32 l2par5;	/* 0x258 L2 cache partitioning allocation register 3 */
 	u32 l2pwr5;	/* 0x25c L2 cache partitioning way register 3 */
 	u32 l2pir6;	/* 0x260 L2 cache partitioning ID register 3 */
 	u8  res_264[4];
 	u32 l2par6;	/* 0x268 L2 cache partitioning allocation register 3 */
 	u32 l2pwr6;	/* 0x26c L2 cache partitioning way register 3 */
 	u32 l2pir7;	/* 0x270 L2 cache partitioning ID register 3 */
 	u8  res274[4];
 	u32 l2par7;	/* 0x278 L2 cache partitioning allocation register 3 */
 	u32 l2pwr7;	/* 0x27c L2 cache partitioning way register 3 */
 	u8  res_280[0xb80]; /* 0x280 - 0xdff */
 	u32 l2errinjhi;	/* 0xe00 L2 cache error injection mask high */
 	u32 l2errinjlo;	/* 0xe04 L2 cache error injection mask low */
 	u32 l2errinjctl;/* 0xe08 L2 cache error injection control */
 	u8  res_e0c[20];	/* 0xe0c - 0x01f */
 	u32 l2captdatahi; /* 0xe20 L2 cache error capture data high */
 	u32 l2captdatalo; /* 0xe24 L2 cache error capture data low */
 	u32 l2captecc;	/* 0xe28 L2 cache error capture ECC syndrome */
 	u8  res_e2c[20];	/* 0xe2c - 0xe3f */
 	u32 l2errdet;	/* 0xe40 L2 cache error detect */
 	u32 l2errdis;	/* 0xe44 L2 cache error disable */
 	u32 l2errinten;	/* 0xe48 L2 cache error interrupt enable */
 	u32 l2errattr;	/* 0xe4c L2 cache error attribute */
 	u32 l2erreaddr;	/* 0xe50 L2 cache error extended address */
 	u32 l2erraddr;	/* 0xe54 L2 cache error address */
 	u32 l2errctl;	/* 0xe58 L2 cache error control */
 };
 #define CONFIG_SYS_FSL_CLUSTER_1_L2 \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET)
 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
 #define	CONFIG_SYS_DCSR_DCFG_OFFSET	0X20000
 struct dcsr_dcfg_regs {
 	u8  res_0[0x520];
 	u32 ecccr1;
 #define	DCSR_DCFG_ECC_DISABLE_USB1	0x00008000
 #define	DCSR_DCFG_ECC_DISABLE_USB2	0x00004000
 	u8  res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */
 };
 #define CONFIG_SYS_MPC85xx_SCFG \
 	(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SCFG_OFFSET)
 #define CONFIG_SYS_MPC85xx_SCFG_OFFSET	0xfc000
 /* The supplement configuration unit register */
 struct ccsr_scfg {
 	u32 dpslpcr;	/* 0x000 Deep Sleep Control register */
 	u32 usb1dpslpcsr;/* 0x004 USB1 Deep Sleep Control Status register */
 	u32 usb2dpslpcsr;/* 0x008 USB2 Deep Sleep Control Status register */
 	u32 fmclkdpslpcr;/* 0x00c FM Clock Deep Sleep Control register */
 	u32 res1[4];
 	u32 esgmiiselcr;/* 0x020 Ethernet Switch SGMII Select Control reg */
 	u32 res2;
 	u32 pixclkcr;	/* 0x028 Pixel Clock Control register */
 	u32 res3[245];
 	u32 qeioclkcr;	/* 0x400 QUICC Engine IO Clock Control register */
 	u32 emiiocr;	/* 0x404 EMI MDIO Control Register */
 	u32 sdhciovselcr;/* 0x408 SDHC IO VSEL Control register */
 	u32 qmifrstcr;	/* 0x40c QMAN Interface Reset Control register */
 	u32 res4[60];
 	u32 sparecr[8];	/* 0x500 Spare Control register(0-7) */
 };
 #endif /*__IMMAP_85xx__*/

board/freescale/p1023rdb/p1023rdb.c

Diff comments View file @ 4426232

 /*
  * Copyright 2013 Freescale Semiconductor, Inc.
  *
  * Authors:  Roy Zang <tie-fei.zang@freescale.com>
  *           Chunhe Lan <Chunhe.Lan@freescale.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
 #include <command.h>
 #include <pci.h>
 #include <asm/io.h>
 #include <asm/cache.h>
 #include <asm/processor.h>
 #include <asm/mmu.h>
 #include <asm/immap_85xx.h>
 #include <asm/fsl_pci.h>
 #include <fsl_ddr_sdram.h>
 #include <asm/fsl_portals.h>
+#include <fsl_qbman.h>
 #include <libfdt.h>
 #include <fdt_support.h>
 #include <netdev.h>
 #include <malloc.h>
 #include <fm_eth.h>
 #include <fsl_mdio.h>
 #include <miiphy.h>
 #include <phy.h>
 #include <fsl_dtsec.h>
 DECLARE_GLOBAL_DATA_PTR;
 int board_early_init_f(void)
 {
 	fsl_lbc_t *lbc = LBC_BASE_ADDR;
 	/* Set ABSWP to implement conversion of addresses in the LBC */
 	setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
 	return 0;
 }
 int checkboard(void)
 {
 	printf("Board: P1023 RDB\n");
 	return 0;
 }
 #ifdef CONFIG_PCI
 void pci_init_board(void)
 {
 	fsl_pcie_init_board(0);
 }
 #endif
 int board_early_init_r(void)
 {
 	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 	int flash_esel = find_tlb_idx((void *)flashbase, 1);
 	/*
 	 * Remap Boot flash + PROMJET region to caching-inhibited
 	 * so that flash can be erased properly.
 	 */
 	/* Flush d-cache and invalidate i-cache of any FLASH data */
 	flush_dcache();
 	invalidate_icache();
 	if (flash_esel == -1) {
 		/* very unlikely unless something is messed up */
 		puts("Error: Could not find TLB for FLASH BASE\n");
 		flash_esel = 2;	/* give our best effort to continue */
 	} else {
 		/* invalidate existing TLB entry for flash + promjet */
 		disable_tlb(flash_esel);
 	}
 	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
 		MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		0, flash_esel, BOOKE_PAGESZ_256M, 1);
-	setup_portals();
+	setup_qbman_portals();
 	return 0;
 }
 unsigned long get_board_sys_clk(ulong dummy)
 {
 	return gd->bus_clk;
 }
 unsigned long get_board_ddr_clk(ulong dummy)
 {
 	return gd->mem_clk;
 }
 int board_eth_init(bd_t *bis)
 {
 	ccsr_gur_t *gur = (ccsr_gur_t *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
 	struct fsl_pq_mdio_info dtsec_mdio_info;
 	/*
 	 * Need to set dTSEC 1 pin multiplexing to TSEC. The default setting
 	 * is not correct.
 	 */
 	setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TSEC1_1);
 	dtsec_mdio_info.regs =
 		(struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
 	dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
 	/* Register the 1G MDIO bus */
 	fsl_pq_mdio_init(bis, &dtsec_mdio_info);
 	fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
 	fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
 	fm_info_set_mdio(FM1_DTSEC1,
 			 miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
 	fm_info_set_mdio(FM1_DTSEC2,
 			 miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
 #ifdef CONFIG_FMAN_ENET
 	cpu_eth_init(bis);
 #endif
 	return pci_eth_init(bis);
 }
 #if defined(CONFIG_OF_BOARD_SETUP)
 int ft_board_setup(void *blob, bd_t *bd)
 {
 	phys_addr_t base;
 	phys_size_t size;
 	ft_cpu_setup(blob, bd);
 	base = env_get_bootm_low();
 	size = env_get_bootm_size();
 	fdt_fixup_memory(blob, (u64)base, (u64)size);
 #ifdef CONFIG_HAS_FSL_DR_USB
 	fsl_fdt_fixup_dr_usb(blob, bd);
 #endif
 	fdt_fixup_fman_ethernet(blob);
 	return 0;
 }
 #endif

board/keymile/kmp204x/kmp204x.c

Diff comments View file @ 4426232

1	/*	1	/*
2	* (C) Copyright 2013 Keymile AG	2	* (C) Copyright 2013 Keymile AG
3	* Valentin Longchamp <valentin.longchamp@keymile.com>	3	* Valentin Longchamp <valentin.longchamp@keymile.com>
4	*	4	*
5	* Copyright 2011,2012 Freescale Semiconductor, Inc.	5	* Copyright 2011,2012 Freescale Semiconductor, Inc.
6	*	6	*
7	* SPDX-License-Identifier: GPL-2.0+	7	* SPDX-License-Identifier: GPL-2.0+
8	*/	8	*/
9		9
10	#include <common.h>	10	#include <common.h>
11	#include <command.h>	11	#include <command.h>
12	#include <netdev.h>	12	#include <netdev.h>
13	#include <linux/compiler.h>	13	#include <linux/compiler.h>
14	#include <asm/mmu.h>	14	#include <asm/mmu.h>
15	#include <asm/processor.h>	15	#include <asm/processor.h>
16	#include <asm/cache.h>	16	#include <asm/cache.h>
17	#include <asm/immap_85xx.h>	17	#include <asm/immap_85xx.h>
18	#include <asm/fsl_law.h>	18	#include <asm/fsl_law.h>
19	#include <asm/fsl_serdes.h>	19	#include <asm/fsl_serdes.h>
20	#include <asm/fsl_portals.h>	20	#include <asm/fsl_portals.h>
21	#include <asm/fsl_liodn.h>	21	#include <asm/fsl_liodn.h>
22	#include <fm_eth.h>	22	#include <fm_eth.h>
23		23
24	#include "../common/common.h"	24	#include "../common/common.h"
25	#include "kmp204x.h"	25	#include "kmp204x.h"
26		26
27	DECLARE_GLOBAL_DATA_PTR;	27	DECLARE_GLOBAL_DATA_PTR;
28		28
29	static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];	29	static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
30		30
31	int checkboard(void)	31	int checkboard(void)
32	{	32	{
33	printf("Board: Keymile %s\n", CONFIG_KM_BOARD_NAME);	33	printf("Board: Keymile %s\n", CONFIG_KM_BOARD_NAME);
34		34
35	return 0;	35	return 0;
36	}	36	}
37		37
38	/* I2C deblocking uses the algorithm defined in board/keymile/common/common.c	38	/* I2C deblocking uses the algorithm defined in board/keymile/common/common.c
39	* 2 dedicated QRIO GPIOs externally pull the SCL and SDA lines	39	* 2 dedicated QRIO GPIOs externally pull the SCL and SDA lines
40	* For I2C only the low state is activly driven and high state is pulled-up	40	* For I2C only the low state is activly driven and high state is pulled-up
41	* by a resistor. Therefore the deblock GPIOs are used	41	* by a resistor. Therefore the deblock GPIOs are used
42	* -> as an active output to drive a low state	42	* -> as an active output to drive a low state
43	* -> as an open-drain input to have a pulled-up high state	43	* -> as an open-drain input to have a pulled-up high state
44	*/	44	*/
45		45
46	/* QRIO GPIOs used for deblocking */	46	/* QRIO GPIOs used for deblocking */
47	#define DEBLOCK_PORT1 GPIO_A	47	#define DEBLOCK_PORT1 GPIO_A
48	#define DEBLOCK_SCL1 20	48	#define DEBLOCK_SCL1 20
49	#define DEBLOCK_SDA1 21	49	#define DEBLOCK_SDA1 21
50		50
51	/* By default deblock GPIOs are floating */	51	/* By default deblock GPIOs are floating */
52	static void i2c_deblock_gpio_cfg(void)	52	static void i2c_deblock_gpio_cfg(void)
53	{	53	{
54	/* set I2C bus 1 deblocking GPIOs input, but 0 value for open drain */	54	/* set I2C bus 1 deblocking GPIOs input, but 0 value for open drain */
55	qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SCL1);	55	qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SCL1);
56	qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SDA1);	56	qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SDA1);
57		57
58	qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, 0);	58	qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, 0);
59	qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, 0);	59	qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, 0);
60	}	60	}
61		61
62	void set_sda(int state)	62	void set_sda(int state)
63	{	63	{
64	qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, state);	64	qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, state);
65	}	65	}
66		66
67	void set_scl(int state)	67	void set_scl(int state)
68	{	68	{
69	qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, state);	69	qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, state);
70	}	70	}
71		71
72	int get_sda(void)	72	int get_sda(void)
73	{	73	{
74	return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1);	74	return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1);
75	}	75	}
76		76
77	int get_scl(void)	77	int get_scl(void)
78	{	78	{
79	return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1);	79	return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1);
80	}	80	}
81		81
82		82
83	#define ZL30158_RST 8	83	#define ZL30158_RST 8
84	#define BFTIC4_RST 0	84	#define BFTIC4_RST 0
85	#define RSTRQSR1_WDT_RR 0x00200000	85	#define RSTRQSR1_WDT_RR 0x00200000
86	#define RSTRQSR1_SW_RR 0x00100000	86	#define RSTRQSR1_SW_RR 0x00100000
87		87
88	int board_early_init_f(void)	88	int board_early_init_f(void)
89	{	89	{
90	ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);	90	ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
91	bool cpuwd_flag = false;	91	bool cpuwd_flag = false;
92		92
93	/* configure mode for uP reset request */	93	/* configure mode for uP reset request */
94	qrio_uprstreq(UPREQ_CORE_RST);	94	qrio_uprstreq(UPREQ_CORE_RST);
95		95
96	/* board only uses the DDR_MCK0, so disable the DDR_MCK1/2/3 */	96	/* board only uses the DDR_MCK0, so disable the DDR_MCK1/2/3 */
97	setbits_be32(&gur->ddrclkdr, 0x001f000f);	97	setbits_be32(&gur->ddrclkdr, 0x001f000f);
98		98
99	/* set reset reason according CPU register */	99	/* set reset reason according CPU register */
100	if ((gur->rstrqsr1 & (RSTRQSR1_WDT_RR \| RSTRQSR1_SW_RR)) ==	100	if ((gur->rstrqsr1 & (RSTRQSR1_WDT_RR \| RSTRQSR1_SW_RR)) ==
101	RSTRQSR1_WDT_RR)	101	RSTRQSR1_WDT_RR)
102	cpuwd_flag = true;	102	cpuwd_flag = true;
103		103
104	qrio_cpuwd_flag(cpuwd_flag);	104	qrio_cpuwd_flag(cpuwd_flag);
105	/* clear CPU bits by writing 1 */	105	/* clear CPU bits by writing 1 */
106	setbits_be32(&gur->rstrqsr1, RSTRQSR1_WDT_RR \| RSTRQSR1_SW_RR);	106	setbits_be32(&gur->rstrqsr1, RSTRQSR1_WDT_RR \| RSTRQSR1_SW_RR);
107		107
108	/* set the BFTIC's prstcfg to reset at power-up and unit reset only */	108	/* set the BFTIC's prstcfg to reset at power-up and unit reset only */
109	qrio_prstcfg(BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST);	109	qrio_prstcfg(BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST);
110	/* and enable WD on it */	110	/* and enable WD on it */
111	qrio_wdmask(BFTIC4_RST, true);	111	qrio_wdmask(BFTIC4_RST, true);
112		112
113	/* set the ZL30138's prstcfg to reset at power-up only */	113	/* set the ZL30138's prstcfg to reset at power-up only */
114	qrio_prstcfg(ZL30158_RST, PRSTCFG_POWUP_RST);	114	qrio_prstcfg(ZL30158_RST, PRSTCFG_POWUP_RST);
115	/* and take it out of reset as soon as possible (needed for Hooper) */	115	/* and take it out of reset as soon as possible (needed for Hooper) */
116	qrio_prst(ZL30158_RST, false, false);	116	qrio_prst(ZL30158_RST, false, false);
117		117
118	return 0;	118	return 0;
119	}	119	}
120		120
121	int board_early_init_r(void)	121	int board_early_init_r(void)
122	{	122	{
123	int ret = 0;	123	int ret = 0;
124	/* Flush d-cache and invalidate i-cache of any FLASH data */	124	/* Flush d-cache and invalidate i-cache of any FLASH data */
125	flush_dcache();	125	flush_dcache();
126	invalidate_icache();	126	invalidate_icache();
127		127
128	set_liodns();	128	set_liodns();
129	setup_portals();	129	setup_qbman_portals();
130		130
131	ret = trigger_fpga_config();	131	ret = trigger_fpga_config();
132	if (ret)	132	if (ret)
133	printf("error triggering PCIe FPGA config\n");	133	printf("error triggering PCIe FPGA config\n");
134		134
135	/* enable the Unit LED (red) & Boot LED (on) */	135	/* enable the Unit LED (red) & Boot LED (on) */
136	qrio_set_leds();	136	qrio_set_leds();
137		137
138	/* enable Application Buffer */	138	/* enable Application Buffer */
139	qrio_enable_app_buffer();	139	qrio_enable_app_buffer();
140		140
141	return ret;	141	return ret;
142	}	142	}
143		143
144	unsigned long get_board_sys_clk(unsigned long dummy)	144	unsigned long get_board_sys_clk(unsigned long dummy)
145	{	145	{
146	return 66666666;	146	return 66666666;
147	}	147	}
148		148
149	#define ETH_FRONT_PHY_RST 15	149	#define ETH_FRONT_PHY_RST 15
150	#define QSFP2_RST 11	150	#define QSFP2_RST 11
151	#define QSFP1_RST 10	151	#define QSFP1_RST 10
152	#define ZL30343_RST 9	152	#define ZL30343_RST 9
153		153
154	int misc_init_f(void)	154	int misc_init_f(void)
155	{	155	{
156	/* configure QRIO pis for i2c deblocking */	156	/* configure QRIO pis for i2c deblocking */
157	i2c_deblock_gpio_cfg();	157	i2c_deblock_gpio_cfg();
158		158
159	/* configure the front phy's prstcfg and take it out of reset */	159	/* configure the front phy's prstcfg and take it out of reset */
160	qrio_prstcfg(ETH_FRONT_PHY_RST, PRSTCFG_POWUP_UNIT_CORE_RST);	160	qrio_prstcfg(ETH_FRONT_PHY_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
161	qrio_prst(ETH_FRONT_PHY_RST, false, false);	161	qrio_prst(ETH_FRONT_PHY_RST, false, false);
162		162
163	/* set the ZL30343 prstcfg to reset at power-up only */	163	/* set the ZL30343 prstcfg to reset at power-up only */
164	qrio_prstcfg(ZL30343_RST, PRSTCFG_POWUP_RST);	164	qrio_prstcfg(ZL30343_RST, PRSTCFG_POWUP_RST);
165	/* and enable the WD on it */	165	/* and enable the WD on it */
166	qrio_wdmask(ZL30343_RST, true);	166	qrio_wdmask(ZL30343_RST, true);
167		167
168	/* set the QSFPs' prstcfg to reset at power-up and unit rst only */	168	/* set the QSFPs' prstcfg to reset at power-up and unit rst only */
169	qrio_prstcfg(QSFP1_RST, PRSTCFG_POWUP_UNIT_RST);	169	qrio_prstcfg(QSFP1_RST, PRSTCFG_POWUP_UNIT_RST);
170	qrio_prstcfg(QSFP2_RST, PRSTCFG_POWUP_UNIT_RST);	170	qrio_prstcfg(QSFP2_RST, PRSTCFG_POWUP_UNIT_RST);
171		171
172	/* and enable the WD on them */	172	/* and enable the WD on them */
173	qrio_wdmask(QSFP1_RST, true);	173	qrio_wdmask(QSFP1_RST, true);
174	qrio_wdmask(QSFP2_RST, true);	174	qrio_wdmask(QSFP2_RST, true);
175		175
176	return 0;	176	return 0;
177	}	177	}
178		178
179	#define NUM_SRDS_BANKS 2	179	#define NUM_SRDS_BANKS 2
180		180
181	int misc_init_r(void)	181	int misc_init_r(void)
182	{	182	{
183	serdes_corenet_t regs = (void )CONFIG_SYS_FSL_CORENET_SERDES_ADDR;	183	serdes_corenet_t regs = (void )CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
184	u32 expected[NUM_SRDS_BANKS] = {SRDS_PLLCR0_RFCK_SEL_100,	184	u32 expected[NUM_SRDS_BANKS] = {SRDS_PLLCR0_RFCK_SEL_100,
185	SRDS_PLLCR0_RFCK_SEL_125};	185	SRDS_PLLCR0_RFCK_SEL_125};
186	unsigned int i;	186	unsigned int i;
187		187
188	/* check SERDES reference clocks */	188	/* check SERDES reference clocks */
189	for (i = 0; i < NUM_SRDS_BANKS; i++) {	189	for (i = 0; i < NUM_SRDS_BANKS; i++) {
190	u32 actual = in_be32(&regs->bank[i].pllcr0);	190	u32 actual = in_be32(&regs->bank[i].pllcr0);
191	actual &= SRDS_PLLCR0_RFCK_SEL_MASK;	191	actual &= SRDS_PLLCR0_RFCK_SEL_MASK;
192	if (actual != expected[i]) {	192	if (actual != expected[i]) {
193	printf("Warning: SERDES bank %u expects reference \	193	printf("Warning: SERDES bank %u expects reference \
194	clock %sMHz, but actual is %sMHz\n", i + 1,	194	clock %sMHz, but actual is %sMHz\n", i + 1,
195	serdes_clock_to_string(expected[i]),	195	serdes_clock_to_string(expected[i]),
196	serdes_clock_to_string(actual));	196	serdes_clock_to_string(actual));
197	}	197	}
198	}	198	}
199		199
200	ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);	200	ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
201	return 0;	201	return 0;
202	}	202	}
203		203
204	#if defined(CONFIG_HUSH_INIT_VAR)	204	#if defined(CONFIG_HUSH_INIT_VAR)
205	int hush_init_var(void)	205	int hush_init_var(void)
206	{	206	{
207	ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);	207	ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
208	return 0;	208	return 0;
209	}	209	}
210	#endif	210	#endif
211		211
212	#if defined(CONFIG_LAST_STAGE_INIT)	212	#if defined(CONFIG_LAST_STAGE_INIT)
213		213
214	int last_stage_init(void)	214	int last_stage_init(void)
215	{	215	{
216	#if defined(CONFIG_KMCOGE4)	216	#if defined(CONFIG_KMCOGE4)
217	/* on KMCOGE4, the BFTIC4 is on the LBAPP2 */	217	/* on KMCOGE4, the BFTIC4 is on the LBAPP2 */
218	struct bfticu_iomap *bftic4 =	218	struct bfticu_iomap *bftic4 =
219	(struct bfticu_iomap *)CONFIG_SYS_LBAPP2_BASE;	219	(struct bfticu_iomap *)CONFIG_SYS_LBAPP2_BASE;
220	u8 dip_switch = in_8((u8 *)&(bftic4->mswitch)) & BFTICU_DIPSWITCH_MASK;	220	u8 dip_switch = in_8((u8 *)&(bftic4->mswitch)) & BFTICU_DIPSWITCH_MASK;
221		221
222	if (dip_switch != 0) {	222	if (dip_switch != 0) {
223	/* start bootloader */	223	/* start bootloader */
224	puts("DIP: Enabled\n");	224	puts("DIP: Enabled\n");
225	env_set("actual_bank", "0");	225	env_set("actual_bank", "0");
226	}	226	}
227	#endif	227	#endif
228	set_km_env();	228	set_km_env();
229		229
230	return 0;	230	return 0;
231	}	231	}
232	#endif	232	#endif
233		233
234	#ifdef CONFIG_SYS_DPAA_FMAN	234	#ifdef CONFIG_SYS_DPAA_FMAN
235	void fdt_fixup_fman_mac_addresses(void *blob)	235	void fdt_fixup_fman_mac_addresses(void *blob)
236	{	236	{
237	int node, i, ret;	237	int node, i, ret;
238	char tmp, end;	238	char tmp, end;
239	unsigned char mac_addr[6];	239	unsigned char mac_addr[6];
240		240
241	/* get the mac addr from env */	241	/* get the mac addr from env */
242	tmp = env_get("ethaddr");	242	tmp = env_get("ethaddr");
243	if (!tmp) {	243	if (!tmp) {
244	printf("ethaddr env variable not defined\n");	244	printf("ethaddr env variable not defined\n");
245	return;	245	return;
246	}	246	}
247	for (i = 0; i < 6; i++) {	247	for (i = 0; i < 6; i++) {
248	mac_addr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;	248	mac_addr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
249	if (tmp)	249	if (tmp)
250	tmp = (*end) ? end+1 : end;	250	tmp = (*end) ? end+1 : end;
251	}	251	}
252		252
253	/* find the correct fdt ethernet path and correct it */	253	/* find the correct fdt ethernet path and correct it */
254	node = fdt_path_offset(blob, "/soc/fman/ethernet@e8000");	254	node = fdt_path_offset(blob, "/soc/fman/ethernet@e8000");
255	if (node < 0) {	255	if (node < 0) {
256	printf("no /soc/fman/ethernet path offset\n");	256	printf("no /soc/fman/ethernet path offset\n");
257	return;	257	return;
258	}	258	}
259	ret = fdt_setprop(blob, node, "local-mac-address", &mac_addr, 6);	259	ret = fdt_setprop(blob, node, "local-mac-address", &mac_addr, 6);
260	if (ret) {	260	if (ret) {
261	printf("error setting local-mac-address property\n");	261	printf("error setting local-mac-address property\n");
262	return;	262	return;
263	}	263	}
264	}	264	}
265	#endif	265	#endif
266		266
267	int ft_board_setup(void blob, bd_t bd)	267	int ft_board_setup(void blob, bd_t bd)
268	{	268	{
269	phys_addr_t base;	269	phys_addr_t base;
270	phys_size_t size;	270	phys_size_t size;
271		271
272	ft_cpu_setup(blob, bd);	272	ft_cpu_setup(blob, bd);
273		273
274	base = env_get_bootm_low();	274	base = env_get_bootm_low();
275	size = env_get_bootm_size();	275	size = env_get_bootm_size();
276		276
277	fdt_fixup_memory(blob, (u64)base, (u64)size);	277	fdt_fixup_memory(blob, (u64)base, (u64)size);
278		278
279	#if defined(CONFIG_HAS_FSL_DR_USB) \|\| defined(CONFIG_HAS_FSL_MPH_USB)	279	#if defined(CONFIG_HAS_FSL_DR_USB) \|\| defined(CONFIG_HAS_FSL_MPH_USB)
280	fsl_fdt_fixup_dr_usb(blob, bd);	280	fsl_fdt_fixup_dr_usb(blob, bd);
281	#endif	281	#endif
282		282
283	#ifdef CONFIG_PCI	283	#ifdef CONFIG_PCI
284	pci_of_setup(blob, bd);	284	pci_of_setup(blob, bd);
285	#endif	285	#endif
286		286
287	fdt_fixup_liodn(blob);	287	fdt_fixup_liodn(blob);
288	#ifdef CONFIG_SYS_DPAA_FMAN	288	#ifdef CONFIG_SYS_DPAA_FMAN
289	fdt_fixup_fman_ethernet(blob);	289	fdt_fixup_fman_ethernet(blob);
290	fdt_fixup_fman_mac_addresses(blob);	290	fdt_fixup_fman_mac_addresses(blob);
291	#endif	291	#endif
292		292
293	return 0;	293	return 0;
294	}	294	}
295		295
296	#if defined(CONFIG_POST)	296	#if defined(CONFIG_POST)
297		297
298	/* DIC26_SELFTEST GPIO used to start factory test sw */	298	/* DIC26_SELFTEST GPIO used to start factory test sw */
299	#define SELFTEST_PORT GPIO_A	299	#define SELFTEST_PORT GPIO_A
300	#define SELFTEST_PIN 31	300	#define SELFTEST_PIN 31
301		301
302	int post_hotkeys_pressed(void)	302	int post_hotkeys_pressed(void)
303	{	303	{
304	qrio_gpio_direction_input(SELFTEST_PORT, SELFTEST_PIN);	304	qrio_gpio_direction_input(SELFTEST_PORT, SELFTEST_PIN);
305	return qrio_get_gpio(SELFTEST_PORT, SELFTEST_PIN);	305	return qrio_get_gpio(SELFTEST_PORT, SELFTEST_PIN);
306	}	306	}
307	#endif	307	#endif
308		308

board/varisys/cyrus/cyrus.c

Diff comments View file @ 4426232

1	/*	1	/*
2	* Based on corenet_ds.c	2	* Based on corenet_ds.c
3	*	3	*
4	* SPDX-License-Identifier: GPL-2.0+	4	* SPDX-License-Identifier: GPL-2.0+
5	*/	5	*/
6		6
7	#include <common.h>	7	#include <common.h>
8	#include <command.h>	8	#include <command.h>
9	#include <netdev.h>	9	#include <netdev.h>
10	#include <linux/compiler.h>	10	#include <linux/compiler.h>
11	#include <asm/mmu.h>	11	#include <asm/mmu.h>
12	#include <asm/processor.h>	12	#include <asm/processor.h>
13	#include <asm/cache.h>	13	#include <asm/cache.h>
14	#include <asm/immap_85xx.h>	14	#include <asm/immap_85xx.h>
15	#include <asm/fsl_law.h>	15	#include <asm/fsl_law.h>
16	#include <asm/fsl_serdes.h>	16	#include <asm/fsl_serdes.h>
17	#include <asm/fsl_portals.h>	17	#include <asm/fsl_portals.h>
18	#include <asm/fsl_liodn.h>	18	#include <asm/fsl_liodn.h>
19	#include <fm_eth.h>	19	#include <fm_eth.h>
20	#include <pci.h>	20	#include <pci.h>
21		21
22	#include "cyrus.h"	22	#include "cyrus.h"
23	#include "../common/eeprom.h"	23	#include "../common/eeprom.h"
24		24
25	DECLARE_GLOBAL_DATA_PTR;	25	DECLARE_GLOBAL_DATA_PTR;
26		26
27	#define GPIO_OPENDRAIN 0x30000000	27	#define GPIO_OPENDRAIN 0x30000000
28	#define GPIO_DIR 0x3c000004	28	#define GPIO_DIR 0x3c000004
29	#define GPIO_INITIAL 0x30000000	29	#define GPIO_INITIAL 0x30000000
30	#define GPIO_VGA_SWITCH 0x00001000	30	#define GPIO_VGA_SWITCH 0x00001000
31		31
32	int checkboard(void)	32	int checkboard(void)
33	{	33	{
34	printf("Board: CYRUS\n");	34	printf("Board: CYRUS\n");
35		35
36	return 0;	36	return 0;
37	}	37	}
38		38
39	int board_early_init_f(void)	39	int board_early_init_f(void)
40	{	40	{
41	ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);	41	ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
42	ccsr_gpio_t pgpio = (void )(CONFIG_SYS_MPC85xx_GPIO_ADDR);	42	ccsr_gpio_t pgpio = (void )(CONFIG_SYS_MPC85xx_GPIO_ADDR);
43		43
44	/*	44	/*
45	* Only use DDR1_MCK0/3 and DDR2_MCK0/3	45	* Only use DDR1_MCK0/3 and DDR2_MCK0/3
46	* disable DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce	46	* disable DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce
47	* the noise introduced by these unterminated and unused clock pairs.	47	* the noise introduced by these unterminated and unused clock pairs.
48	*/	48	*/
49	setbits_be32(&gur->ddrclkdr, 0x001B001B);	49	setbits_be32(&gur->ddrclkdr, 0x001B001B);
50		50
51	/* Set GPIO reset lines to open-drain, tristate */	51	/* Set GPIO reset lines to open-drain, tristate */
52	setbits_be32(&pgpio->gpdat, GPIO_INITIAL);	52	setbits_be32(&pgpio->gpdat, GPIO_INITIAL);
53	setbits_be32(&pgpio->gpodr, GPIO_OPENDRAIN);	53	setbits_be32(&pgpio->gpodr, GPIO_OPENDRAIN);
54		54
55	/* Set GPIO Direction */	55	/* Set GPIO Direction */
56	setbits_be32(&pgpio->gpdir, GPIO_DIR);	56	setbits_be32(&pgpio->gpdir, GPIO_DIR);
57		57
58	return 0;	58	return 0;
59	}	59	}
60		60
61	int board_early_init_r(void)	61	int board_early_init_r(void)
62	{	62	{
63	fsl_lbc_t *lbc = LBC_BASE_ADDR;	63	fsl_lbc_t *lbc = LBC_BASE_ADDR;
64		64
65	out_be32(&lbc->lbcr, 0);	65	out_be32(&lbc->lbcr, 0);
66	/* 1 clock LALE cycle */	66	/* 1 clock LALE cycle */
67	out_be32(&lbc->lcrr, 0x80000000 \| CONFIG_SYS_LBC_LCRR);	67	out_be32(&lbc->lcrr, 0x80000000 \| CONFIG_SYS_LBC_LCRR);
68		68
69	set_liodns();	69	set_liodns();
70		70
71	#ifdef CONFIG_SYS_DPAA_QBMAN	71	#ifdef CONFIG_SYS_DPAA_QBMAN
72	setup_portals();	72	setup_qbman_portals();
73	#endif	73	#endif
74	print_lbc_regs();	74	print_lbc_regs();
75	return 0;	75	return 0;
76	}	76	}
77		77
78	int misc_init_r(void)	78	int misc_init_r(void)
79	{	79	{
80	return 0;	80	return 0;
81	}	81	}
82		82
83	int ft_board_setup(void blob, bd_t bd)	83	int ft_board_setup(void blob, bd_t bd)
84	{	84	{
85	phys_addr_t base;	85	phys_addr_t base;
86	phys_size_t size;	86	phys_size_t size;
87		87
88	ft_cpu_setup(blob, bd);	88	ft_cpu_setup(blob, bd);
89		89
90	base = env_get_bootm_low();	90	base = env_get_bootm_low();
91	size = env_get_bootm_size();	91	size = env_get_bootm_size();
92		92
93	fdt_fixup_memory(blob, (u64)base, (u64)size);	93	fdt_fixup_memory(blob, (u64)base, (u64)size);
94		94
95	#ifdef CONFIG_PCI	95	#ifdef CONFIG_PCI
96	pci_of_setup(blob, bd);	96	pci_of_setup(blob, bd);
97	#endif	97	#endif
98		98
99	fdt_fixup_liodn(blob);	99	fdt_fixup_liodn(blob);
100	fsl_fdt_fixup_dr_usb(blob, bd);	100	fsl_fdt_fixup_dr_usb(blob, bd);
101		101
102	#ifdef CONFIG_SYS_DPAA_FMAN	102	#ifdef CONFIG_SYS_DPAA_FMAN
103	fdt_fixup_fman_ethernet(blob);	103	fdt_fixup_fman_ethernet(blob);
104	#endif	104	#endif
105		105
106	return 0;	106	return 0;
107	}	107	}
108		108
109	int mac_read_from_eeprom(void)	109	int mac_read_from_eeprom(void)
110	{	110	{
111	init_eeprom(CONFIG_SYS_EEPROM_BUS_NUM,	111	init_eeprom(CONFIG_SYS_EEPROM_BUS_NUM,
112	CONFIG_SYS_I2C_EEPROM_ADDR,	112	CONFIG_SYS_I2C_EEPROM_ADDR,
113	CONFIG_SYS_I2C_EEPROM_ADDR_LEN);	113	CONFIG_SYS_I2C_EEPROM_ADDR_LEN);
114		114
115	return mac_read_from_eeprom_common();	115	return mac_read_from_eeprom_common();
116	}	116	}
117		117

drivers/misc/Makefile

Diff comments View file @ 4426232

 #
 # (C) Copyright 2000-2007
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # SPDX-License-Identifier:	GPL-2.0+
 #
 obj-$(CONFIG_MISC) += misc-uclass.o
 obj-$(CONFIG_ALI152X) += ali512x.o
 obj-$(CONFIG_ALTERA_SYSID) += altera_sysid.o
 obj-$(CONFIG_ATSHA204A) += atsha204a-i2c.o
 obj-$(CONFIG_DS4510)  += ds4510.o
 obj-$(CONFIG_CBMEM_CONSOLE) += cbmem_console.o
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_CROS_EC) += cros_ec.o
 obj-$(CONFIG_CROS_EC_LPC) += cros_ec_lpc.o
 obj-$(CONFIG_CROS_EC_I2C) += cros_ec_i2c.o
 obj-$(CONFIG_CROS_EC_SANDBOX) += cros_ec_sandbox.o
 obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o
 endif
 obj-$(CONFIG_FSL_IIM) += fsl_iim.o
 obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o
 obj-$(CONFIG_$(SPL_)I2C_EEPROM) += i2c_eeprom.o
 obj-$(CONFIG_FSL_MC9SDZ60) += mc9sdz60.o
 obj-$(CONFIG_MXC_OCOTP) += mxc_ocotp.o
 obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o
 obj-$(CONFIG_NUVOTON_NCT6102D) += nuvoton_nct6102d.o
 obj-$(CONFIG_NS87308) += ns87308.o
 obj-$(CONFIG_$(SPL_)PWRSEQ) += pwrseq-uclass.o
 ifdef CONFIG_DM_I2C
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_SANDBOX) += i2c_eeprom_emul.o
 endif
 endif
 obj-$(CONFIG_SMSC_LPC47M) += smsc_lpc47m.o
 obj-$(CONFIG_SMSC_SIO1007) += smsc_sio1007.o
 obj-$(CONFIG_LED_STATUS) += status_led.o
 obj-$(CONFIG_SANDBOX) += swap_case.o
 ifdef CONFIG_SPL_OF_PLATDATA
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_SANDBOX) += spltest_sandbox.o
 endif
 endif
 obj-$(CONFIG_SANDBOX) += syscon_sandbox.o
 obj-$(CONFIG_TEGRA_CAR) += tegra_car.o
 obj-$(CONFIG_TEGRA186_BPMP) += tegra186_bpmp.o
 obj-$(CONFIG_TWL4030_LED) += twl4030_led.o
 obj-$(CONFIG_FSL_IFC) += fsl_ifc.o
 obj-$(CONFIG_FSL_SEC_MON) += fsl_sec_mon.o
 obj-$(CONFIG_PCA9551_LED) += pca9551_led.o
 obj-$(CONFIG_FSL_DEVICE_DISABLE) += fsl_devdis.o
 obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o
 obj-$(CONFIG_QFW) += qfw.o
 obj-$(CONFIG_ROCKCHIP_EFUSE) += rockchip-efuse.o
 obj-$(CONFIG_STM32_RCC) += stm32_rcc.o
+obj-$(CONFIG_SYS_DPAA_QBMAN) += fsl_portals.o

drivers/misc/fsl_portals.c

Diff comments View file @ 4426232

File was created	1	/*
	2	* Copyright 2008-2011 Freescale Semiconductor, Inc.
	3	* Copyright 2017 NXP
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#include <common.h>
	9	#include <libfdt.h>
	10	#include <fdt_support.h>
	11
	12	#include <asm/processor.h>
	13	#include <asm/io.h>
	14	#ifdef CONFIG_PPC
	15	#include <asm/fsl_portals.h>
	16	#include <asm/fsl_liodn.h>
	17	#endif
	18	#include <fsl_qbman.h>
	19
	20	#define MAX_BPORTALS (CONFIG_SYS_BMAN_CINH_SIZE / CONFIG_SYS_BMAN_SP_CINH_SIZE)
	21	#define MAX_QPORTALS (CONFIG_SYS_QMAN_CINH_SIZE / CONFIG_SYS_QMAN_SP_CINH_SIZE)
	22	void setup_qbman_portals(void)
	23	{
	24	void __iomem bpaddr = (void )CONFIG_SYS_BMAN_CINH_BASE +
	25	CONFIG_SYS_BMAN_SWP_ISDR_REG;
	26	void __iomem qpaddr = (void )CONFIG_SYS_QMAN_CINH_BASE +
	27	CONFIG_SYS_QMAN_SWP_ISDR_REG;
	28	#ifdef CONFIG_PPC
	29	struct ccsr_qman qman = (void )CONFIG_SYS_FSL_QMAN_ADDR;
	30
	31	/* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */
	32	#ifdef CONFIG_PHYS_64BIT
	33	out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32));
	34	#endif
	35	out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS);
	36	#endif
	37	#ifdef CONFIG_FSL_CORENET
	38	int i;
	39
	40	for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) {
	41	u8 sdest = qp_info[i].sdest;
	42	u16 fliodn = qp_info[i].fliodn;
	43	u16 dliodn = qp_info[i].dliodn;
	44	u16 liodn_off = qp_info[i].liodn_offset;
	45
	46	out_be32(&qman->qcsp[i].qcsp_lio_cfg, (liodn_off << 16) \|
	47	dliodn);
	48	/* set frame liodn */
	49	out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) \| fliodn);
	50	}
	51	#endif
	52
	53	/* Change default state of BMan ISDR portals to all 1s */
	54	inhibit_portals(bpaddr, CONFIG_SYS_BMAN_NUM_PORTALS, MAX_BPORTALS,
	55	CONFIG_SYS_BMAN_SP_CINH_SIZE);
	56	inhibit_portals(qpaddr, CONFIG_SYS_QMAN_NUM_PORTALS, MAX_QPORTALS,
	57	CONFIG_SYS_QMAN_SP_CINH_SIZE);
	58	}
	59
	60	void inhibit_portals(void __iomem *addr, int max_portals,
	61	int arch_max_portals, int portal_cinh_size)
	62	{
	63	u32 val;
	64	int i;
	65
	66	/* arch_max_portals is the maximum based on memory size. This includes
	67	* the reserved memory in the SoC. max_portals the number of physical
	68	* portals in the SoC
	69	*/
	70	if (max_portals > arch_max_portals) {
	71	printf("ERROR: portal config error\n");
	72	max_portals = arch_max_portals;
	73	}
	74
	75	for (i = 0; i < max_portals; i++) {
	76	out_be32(addr, -1);
	77	val = in_be32(addr);
	78	if (!val) {
	79	printf("ERROR: Stopped after %d portals\n", i);
	80	return;
	81	}
	82	addr += portal_cinh_size;
	83	}
	84	debug("Cleared %d portals\n", i);
	85	}
	86
	87	#ifdef CONFIG_PPC
	88	static int fdt_qportal(void blob, int off, int id, char name,
	89	enum fsl_dpaa_dev dev, int create)
	90	{
	91	int childoff, dev_off, ret = 0;
	92	u32 dev_handle;
	93	#ifdef CONFIG_FSL_CORENET
	94	int num;
	95	u32 liodns[2];
	96	#endif
	97
	98	childoff = fdt_subnode_offset(blob, off, name);
	99	if (create) {
	100	char handle[64], *p;
	101
	102	strncpy(handle, name, sizeof(handle));
	103	p = strchr(handle, '@');
	104	if (!strncmp(name, "fman", 4)) {
	105	p = (p + 1);
	106	p++;
	107	}
	108	*p = '\0';
	109
	110	dev_off = fdt_path_offset(blob, handle);
	111	/* skip this node if alias is not found */
	112	if (dev_off == -FDT_ERR_BADPATH)
	113	return 0;
	114	if (dev_off < 0)
	115	return dev_off;
	116
	117	if (childoff <= 0)
	118	childoff = fdt_add_subnode(blob, off, name);
	119
	120	/* need to update the dev_off after adding a subnode */
	121	dev_off = fdt_path_offset(blob, handle);
	122	if (dev_off < 0)
	123	return dev_off;
	124
	125	if (childoff > 0) {
	126	dev_handle = fdt_get_phandle(blob, dev_off);
	127	if (dev_handle <= 0) {
	128	dev_handle = fdt_alloc_phandle(blob);
	129	ret = fdt_set_phandle(blob, dev_off,
	130	dev_handle);
	131	if (ret < 0)
	132	return ret;
	133	}
	134
	135	ret = fdt_setprop(blob, childoff, "dev-handle",
	136	&dev_handle, sizeof(dev_handle));
	137	if (ret < 0)
	138	return ret;
	139
	140	#ifdef CONFIG_FSL_CORENET
	141	num = get_dpaa_liodn(dev, &liodns[0], id);
	142	ret = fdt_setprop(blob, childoff, "fsl,liodn",
	143	&liodns[0], sizeof(u32) * num);
	144	if (!strncmp(name, "pme", 3)) {
	145	u32 pme_rev1, pme_rev2;
	146	ccsr_pme_t *pme_regs =
	147	(void *)CONFIG_SYS_FSL_CORENET_PME_ADDR;
	148
	149	pme_rev1 = in_be32(&pme_regs->pm_ip_rev_1);
	150	pme_rev2 = in_be32(&pme_regs->pm_ip_rev_2);
	151	ret = fdt_setprop(blob, childoff,
	152	"fsl,pme-rev1", &pme_rev1,
	153	sizeof(u32));
	154	if (ret < 0)
	155	return ret;
	156	ret = fdt_setprop(blob, childoff,
	157	"fsl,pme-rev2", &pme_rev2,
	158	sizeof(u32));
	159	}
	160	#endif
	161	} else {
	162	return childoff;
	163	}
	164	} else {
	165	if (childoff > 0)
	166	ret = fdt_del_node(blob, childoff);
	167	}
	168
	169	return ret;
	170	}
	171	#endif /* CONFIG_PPC */
	172
	173	void fdt_fixup_qportals(void *blob)
	174	{
	175	int off, err;
	176	unsigned int maj, min;
	177	unsigned int ip_cfg;
	178	struct ccsr_qman qman = (void )CONFIG_SYS_FSL_QMAN_ADDR;
	179	u32 rev_1 = in_be32(&qman->ip_rev_1);
	180	u32 rev_2 = in_be32(&qman->ip_rev_2);
	181	char compat[64];
	182	int compat_len;
	183
	184	maj = (rev_1 >> 8) & 0xff;
	185	min = rev_1 & 0xff;
	186	ip_cfg = rev_2 & 0xff;
	187
	188	compat_len = sprintf(compat, "fsl,qman-portal-%u.%u.%u",
	189	maj, min, ip_cfg) + 1;
	190	compat_len += sprintf(compat + compat_len, "fsl,qman-portal") + 1;
	191
	192	off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal");
	193	while (off != -FDT_ERR_NOTFOUND) {
	194	#ifdef CONFIG_PPC
	195	#ifdef CONFIG_FSL_CORENET
	196	u32 liodns[2];
	197	#endif
	198	const int *ci = fdt_getprop(blob, off, "cell-index", &err);
	199	int i;
	200
	201	if (!ci)
	202	goto err;
	203
	204	i = *ci;
	205	#ifdef CONFIG_SYS_DPAA_FMAN
	206	int j;
	207	#endif
	208
	209	#endif /* CONFIG_PPC */
	210	err = fdt_setprop(blob, off, "compatible", compat, compat_len);
	211	if (err < 0)
	212	goto err;
	213	#ifdef CONFIG_PPC
	214	#ifdef CONFIG_FSL_CORENET
	215	liodns[0] = qp_info[i].dliodn;
	216	liodns[1] = qp_info[i].fliodn;
	217	err = fdt_setprop(blob, off, "fsl,liodn",
	218	&liodns, sizeof(u32) * 2);
	219	if (err < 0)
	220	goto err;
	221	#endif
	222
	223	i++;
	224
	225	err = fdt_qportal(blob, off, i, "crypto@0", FSL_HW_PORTAL_SEC,
	226	IS_E_PROCESSOR(get_svr()));
	227	if (err < 0)
	228	goto err;
	229
	230	#ifdef CONFIG_FSL_CORENET
	231	#ifdef CONFIG_SYS_DPAA_PME
	232	err = fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 1);
	233	if (err < 0)
	234	goto err;
	235	#else
	236	fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 0);
	237	#endif
	238	#endif
	239
	240	#ifdef CONFIG_SYS_DPAA_FMAN
	241	for (j = 0; j < CONFIG_SYS_NUM_FMAN; j++) {
	242	char name[] = "fman@0";
	243
	244	name[sizeof(name) - 2] = '0' + j;
	245	err = fdt_qportal(blob, off, i, name,
	246	FSL_HW_PORTAL_FMAN1 + j, 1);
	247	if (err < 0)
	248	goto err;
	249	}
	250	#endif
	251	#ifdef CONFIG_SYS_DPAA_RMAN
	252	err = fdt_qportal(blob, off, i, "rman@0",
	253	FSL_HW_PORTAL_RMAN, 1);
	254	if (err < 0)
	255	goto err;
	256	#endif
	257	#endif /* CONFIG_PPC */
	258
	259	err:
	260	if (err < 0) {
	261	printf("ERROR: unable to create props for %s: %s\n",
	262	fdt_get_name(blob, off, NULL),
	263	fdt_strerror(err));
	264	return;
	265	}
	266
	267	off = fdt_node_offset_by_compatible(blob, off,
	268	"fsl,qman-portal");
	269	}
	270	}
	271
	272	void fdt_fixup_bportals(void *blob)
	273	{
	274	int off, err;
	275	unsigned int maj, min;
	276	unsigned int ip_cfg;
	277	struct ccsr_bman bman = (void )CONFIG_SYS_FSL_BMAN_ADDR;
	278	u32 rev_1 = in_be32(&bman->ip_rev_1);
	279	u32 rev_2 = in_be32(&bman->ip_rev_2);
	280	char compat[64];
	281	int compat_len;
	282
	283	maj = (rev_1 >> 8) & 0xff;
	284	min = rev_1 & 0xff;
	285
	286	ip_cfg = rev_2 & 0xff;
	287
	288	compat_len = sprintf(compat, "fsl,bman-portal-%u.%u.%u",
	289	maj, min, ip_cfg) + 1;
	290	compat_len += sprintf(compat + compat_len, "fsl,bman-portal") + 1;
	291
	292	off = fdt_node_offset_by_compatible(blob, -1, "fsl,bman-portal");
	293	while (off != -FDT_ERR_NOTFOUND) {
	294	err = fdt_setprop(blob, off, "compatible", compat, compat_len);
	295	if (err < 0) {
	296	printf("ERROR: unable to create props for %s: %s\n",
	297	fdt_get_name(blob, off, NULL),
	298	fdt_strerror(err));
	299	return;
	300	}
	301
	302	off = fdt_node_offset_by_compatible(blob, off,
	303	"fsl,bman-portal");
	304	}
	305	}
	306

include/configs/ls1043a_common.h

Diff comments View file @ 4426232

 /*
  * Copyright (C) 2015 Freescale Semiconductor
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef __LS1043A_COMMON_H
 #define __LS1043A_COMMON_H
 /* SPL build */
 #ifdef CONFIG_SPL_BUILD
 #define SPL_NO_FMAN
 #define SPL_NO_DSPI
 #define SPL_NO_PCIE
 #define SPL_NO_ENV
 #define SPL_NO_MISC
 #define SPL_NO_USB
 #define SPL_NO_SATA
 #define SPL_NO_QE
 #define SPL_NO_EEPROM
 #endif
 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
 #define SPL_NO_MMC
 #endif
 #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT_QSPI))
 #define SPL_NO_IFC
 #endif
 #define CONFIG_REMAKE_ELF
 #define CONFIG_FSL_LAYERSCAPE
 #define CONFIG_MP
 #define CONFIG_GICV2
 #include <asm/arch/stream_id_lsch2.h>
 #include <asm/arch/config.h>
 /* Link Definitions */
 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
 #define CONFIG_SUPPORT_RAW_INITRD
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_VERY_BIG_RAM
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY	0
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
 #define CONFIG_SYS_DDR_BLOCK2_BASE      0x880000000ULL
 #define CPU_RELEASE_ADDR               secondary_boot_func
 /* Generic Timer Definitions */
 #define COUNTER_FREQUENCY		25000000	/* 25MHz */
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 1024 * 1024)
 /* Serial Port */
 #define CONFIG_CONS_INDEX		1
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK          (get_serial_clock())
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 /* SD boot SPL */
 #ifdef CONFIG_SD_BOOT
 #define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
 #define CONFIG_SPL_TEXT_BASE		0x10000000
 #define CONFIG_SPL_MAX_SIZE		0x17000
 #define CONFIG_SPL_STACK		0x1001e000
 #define CONFIG_SPL_PAD_TO		0x1d000
 #define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_BSS_START_ADDR + \
 					CONFIG_SPL_BSS_MAX_SIZE)
 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
 #define CONFIG_SPL_BSS_START_ADDR	0x8f000000
 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000
 #ifdef CONFIG_SECURE_BOOT
 #define CONFIG_U_BOOT_HDR_SIZE				(16 << 10)
 /*
  * HDR would be appended at end of image and copied to DDR along
  * with U-Boot image. Here u-boot max. size is 512K. So if binary
  * size increases then increase this size in case of secure boot as
  * it uses raw u-boot image instead of fit image.
  */
 #define CONFIG_SYS_MONITOR_LEN		(0x100000 + CONFIG_U_BOOT_HDR_SIZE)
 #else
 #define CONFIG_SYS_MONITOR_LEN		0x100000
 #endif /* ifdef CONFIG_SECURE_BOOT */
 #endif
 /* NAND SPL */
 #ifdef CONFIG_NAND_BOOT
 #define CONFIG_SPL_PBL_PAD
 #define CONFIG_SPL_FRAMEWORK
 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
 #define CONFIG_SPL_TEXT_BASE		0x10000000
 #define CONFIG_SPL_MAX_SIZE		0x1a000
 #define CONFIG_SPL_STACK		0x1001d000
 #define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_SPL_MALLOC_START	0x80200000
 #define CONFIG_SPL_BSS_START_ADDR	0x80100000
 #define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000
 #define CONFIG_SPL_BSS_MAX_SIZE		0x80000
 #ifdef CONFIG_SECURE_BOOT
 #define CONFIG_U_BOOT_HDR_SIZE				(16 << 10)
 #endif /* ifdef CONFIG_SECURE_BOOT */
 #ifdef CONFIG_U_BOOT_HDR_SIZE
 /*
  * HDR would be appended at end of image and copied to DDR along
  * with U-Boot image. Here u-boot max. size is 512K. So if binary
  * size increases then increase this size in case of secure boot as
  * it uses raw u-boot image instead of fit image.
  */
 #define CONFIG_SYS_MONITOR_LEN		(0x100000 + CONFIG_U_BOOT_HDR_SIZE)
 #else
 #define CONFIG_SYS_MONITOR_LEN		0x100000
 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
 #endif
 /* IFC */
 #ifndef SPL_NO_IFC
 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 #define CONFIG_FSL_IFC
 /*
  * CONFIG_SYS_FLASH_BASE has the final address (core view)
  * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
  * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
  * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
  */
 #define CONFIG_SYS_FLASH_BASE			0x60000000
 #define CONFIG_SYS_FLASH_BASE_PHYS		CONFIG_SYS_FLASH_BASE
 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY	0x00000000
 #ifdef CONFIG_MTD_NOR_FLASH
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 #define CONFIG_SYS_FLASH_QUIET_TEST
 #define CONFIG_FLASH_SHOW_PROGRESS	45	/* count down from 45/5: 9..1 */
 #endif
 #endif
 #endif
 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_MXC
 #define CONFIG_SYS_I2C_MXC_I2C1
 #define CONFIG_SYS_I2C_MXC_I2C2
 #define CONFIG_SYS_I2C_MXC_I2C3
 #define CONFIG_SYS_I2C_MXC_I2C4
 /* PCIe */
 #ifndef SPL_NO_PCIE
 #define CONFIG_PCIE1		/* PCIE controller 1 */
 #define CONFIG_PCIE2		/* PCIE controller 2 */
 #define CONFIG_PCIE3		/* PCIE controller 3 */
 #ifdef CONFIG_PCI
 #define CONFIG_PCI_SCAN_SHOW
 #endif
 #endif
 /* Command line configuration */
 /*  MMC  */
 #ifndef SPL_NO_MMC
 #ifdef CONFIG_MMC
 #define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
 #endif
 #endif
 /*  DSPI  */
 #ifndef SPL_NO_DSPI
 #define CONFIG_FSL_DSPI
 #ifdef CONFIG_FSL_DSPI
 #define CONFIG_DM_SPI_FLASH
 #define CONFIG_SPI_FLASH_STMICRO	/* cs0 */
 #define CONFIG_SPI_FLASH_SST		/* cs1 */
 #define CONFIG_SPI_FLASH_EON		/* cs2 */
 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 #define CONFIG_SF_DEFAULT_BUS		1
 #define CONFIG_SF_DEFAULT_CS		0
 #endif
 #endif
 #endif
+#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
 /* FMan ucode */
 #ifndef SPL_NO_FMAN
 #define CONFIG_SYS_DPAA_FMAN
 #ifdef CONFIG_SYS_DPAA_FMAN
 #define CONFIG_SYS_FM_MURAM_SIZE	0x60000
 #ifdef CONFIG_NAND_BOOT
 /* Store Fman ucode at offeset 0x900000(72 blocks). */
 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 #define CONFIG_SYS_FMAN_FW_ADDR		(72 * CONFIG_SYS_NAND_BLOCK_SIZE)
 #elif defined(CONFIG_SD_BOOT)
 /*
  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  * about 1MB (2040 blocks), Env is stored after the image, and the env size is
  * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 18432(0x4800).
  */
 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 #define CONFIG_SYS_FMAN_FW_ADDR		(512 * 0x4800)
 #define CONFIG_SYS_QE_FW_ADDR		(512 * 0x4a08)
 #elif defined(CONFIG_QSPI_BOOT)
 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 #define CONFIG_SYS_FMAN_FW_ADDR		0x40900000
 #define CONFIG_ENV_SPI_BUS		0
 #define CONFIG_ENV_SPI_CS		0
 #define CONFIG_ENV_SPI_MAX_HZ		1000000
 #define CONFIG_ENV_SPI_MODE		0x03
 #else
 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 /* FMan fireware Pre-load address */
 #define CONFIG_SYS_FMAN_FW_ADDR		0x60900000
 #define CONFIG_SYS_QE_FW_ADDR		0x60940000
 #endif
 #define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
 #define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 #endif
 #endif
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
 #define CONFIG_HWCONFIG
 #define HWCONFIG_BUFFER_SIZE		128
 #ifndef SPL_NO_MISC
 #include <config_distro_defaults.h>
 #ifndef CONFIG_SPL_BUILD
 #define BOOT_TARGET_DEVICES(func) \
 	func(MMC, mmc, 0) \
 	func(USB, usb, 0)
 #include <config_distro_bootcmd.h>
 #endif
 /* Initial environment variables */
 #define CONFIG_EXTRA_ENV_SETTINGS		\
 	"hwconfig=fsl_ddr:bank_intlv=auto\0"	\
 	"fdt_high=0xffffffffffffffff\0"		\
 	"initrd_high=0xffffffffffffffff\0"	\
 	"fdt_addr=0x64f00000\0"		 	\
 	"kernel_addr=0x61000000\0"		\
 	"scriptaddr=0x80000000\0"		\
 	"scripthdraddr=0x80080000\0"		\
 	"fdtheader_addr_r=0x80100000\0"		\
 	"kernelheader_addr_r=0x80200000\0"	\
 	"kernel_addr_r=0x81000000\0"		\
 	"fdt_addr_r=0x90000000\0"		\
 	"load_addr=0xa0000000\0"		\
 	"kernelheader_addr=0x60800000\0"	\
 	"kernel_size=0x2800000\0"		\
 	"kernelheader_size=0x40000\0"		\
 	"kernel_addr_sd=0x8000\0"		\
 	"kernel_size_sd=0x14000\0"		\
 	"kernelhdr_addr_sd=0x4000\0"		\
 	"kernelhdr_size_sd=0x10\0"		\
 	"console=ttyS0,115200\0"		\
 	"boot_os=y\0"				\
 	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0"	\
 	BOOTENV					\
 	"boot_scripts=ls1043ardb_boot.scr\0"	\
 	"boot_script_hdr=hdr_ls1043ardb_bs.out\0"	\
 	"scan_dev_for_boot_part="		\
 		"part list ${devtype} ${devnum} devplist; "	\
 		"env exists devplist || setenv devplist 1; "	\
 		"for distro_bootpart in ${devplist}; do "	\
 			"if fstype ${devtype} "			\
 				"${devnum}:${distro_bootpart} "	\
 				"bootfstype; then "		\
 				"run scan_dev_for_boot; "	\
 			"fi; "					\
 		"done\0"			\
 	"scan_dev_for_boot="					\
 		"echo Scanning ${devtype} "			\
 			"${devnum}:${distro_bootpart}...; "	\
 		"for prefix in ${boot_prefixes}; do "		\
 			"run scan_dev_for_scripts; "		\
 		"done;\0"					\
 	"boot_a_script="					\
 		"load ${devtype} ${devnum}:${distro_bootpart} "	\
 			"${scriptaddr} ${prefix}${script}; "	\
 		"env exists secureboot && load ${devtype} "	\
 			"${devnum}:${distro_bootpart} "		\
 			"${scripthdraddr} ${prefix}${boot_script_hdr} "	\
 			"&& esbc_validate ${scripthdraddr};"	\
 		"source ${scriptaddr}\0"			\
 	"qspi_bootcmd=echo Trying load from qspi..;"	\
 		"sf probe && sf read $load_addr "	\
 		"$kernel_addr $kernel_size; env exists secureboot "	\
 		"&& sf read $kernelheader_addr_r $kernelheader_addr "	\
 		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
 		"bootm $load_addr#$board\0"	\
 	"nor_bootcmd=echo Trying load from nor..;"	\
 		"cp.b $kernel_addr $load_addr "	\
 		"$kernel_size; env exists secureboot "	\
 		"&& cp.b $kernelheader_addr $kernelheader_addr_r "	\
 		"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
 		"bootm $load_addr#$board\0"	    \
 	"sd_bootcmd=echo Trying load from SD ..;"       \
 		"mmcinfo; mmc read $load_addr "         \
 		"$kernel_addr_sd $kernel_size_sd && "     \
 		"env exists secureboot && mmc read $kernelheader_addr_r "		\
 		"$kernelhdr_addr_sd $kernelhdr_size_sd "		\
 		" && esbc_validate ${kernelheader_addr_r};"	\
 		"bootm $load_addr#$board\0"
 #undef CONFIG_BOOTCOMMAND
 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; "	\
 			   "env exists secureboot && esbc_halt;"
 #elif defined(CONFIG_SD_BOOT)
 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "  \
 			   "env exists secureboot && esbc_halt;"
 #else
 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; "	\
 			   "env exists secureboot && esbc_halt;"
 #endif
 #endif
 /* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
 #define CONFIG_SYS_LONGHELP
 #ifndef SPL_NO_MISC
 #ifndef CONFIG_CMDLINE_EDITING
 #define CONFIG_CMDLINE_EDITING		1
 #endif
 #endif
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_MAXARGS		64	/* max command args */
 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
 #include <asm/arch/soc.h>
 #endif /* __LS1043A_COMMON_H */

include/fsl_qbman.h

Diff comments View file @ 4426232

File was created	1	/*
	2	* Copyright 2017 NXP
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef __FSL_QBMAN_H__
	8	#define __FSL_QBMAN_H__
	9	void fdt_fixup_qportals(void *blob);
	10	void fdt_fixup_bportals(void *blob);
	11	void inhibit_portals(void __iomem *addr, int max_portals,
	12	int arch_max_portals, int portal_cinh_size);
	13	void setup_qbman_portals(void);
	14
	15	struct ccsr_qman {
	16	#ifdef CONFIG_SYS_FSL_QMAN_V3
	17	u8 res0[0x200];
	18	#else
	19	struct {
	20	u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */
	21	u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */
	22	u32 res;
	23	u32 qcsp_dd_cfg; /* 0xc - SW Portal Dynamic Debug cfg */
	24	} qcsp[32];
	25	#endif
	26	/* Not actually reserved, but irrelevant to u-boot */
	27	u8 res[0xbf8 - 0x200];
	28	u32 ip_rev_1;
	29	u32 ip_rev_2;
	30	u32 fqd_bare; /* FQD Extended Base Addr Register */
	31	u32 fqd_bar; /* FQD Base Addr Register */
	32	u8 res1[0x8];
	33	u32 fqd_ar; /* FQD Attributes Register */
	34	u8 res2[0xc];
	35	u32 pfdr_bare; /* PFDR Extended Base Addr Register */
	36	u32 pfdr_bar; /* PFDR Base Addr Register */
	37	u8 res3[0x8];
	38	u32 pfdr_ar; /* PFDR Attributes Register */
	39	u8 res4[0x4c];
	40	u32 qcsp_bare; /* QCSP Extended Base Addr Register */
	41	u32 qcsp_bar; /* QCSP Base Addr Register */
	42	u8 res5[0x78];
	43	u32 ci_sched_cfg; /* Initiator Scheduling Configuration */
	44	u32 srcidr; /* Source ID Register */
	45	u32 liodnr; /* LIODN Register */
	46	u8 res6[4];
	47	u32 ci_rlm_cfg; /* Initiator Read Latency Monitor Cfg */
	48	u32 ci_rlm_avg; /* Initiator Read Latency Monitor Avg */
	49	u8 res7[0x2e8];
	50	#ifdef CONFIG_SYS_FSL_QMAN_V3
	51	struct {
	52	u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */
	53	u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */
	54	u32 res;
	55	u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg*/
	56	} qcsp[50];
	57	#endif
	58	};
	59
	60	struct ccsr_bman {
	61	/* Not actually reserved, but irrelevant to u-boot */
	62	u8 res[0xbf8];
	63	u32 ip_rev_1;
	64	u32 ip_rev_2;
	65	u32 fbpr_bare; /* FBPR Extended Base Addr Register */
	66	u32 fbpr_bar; /* FBPR Base Addr Register */
	67	u8 res1[0x8];
	68	u32 fbpr_ar; /* FBPR Attributes Register */
	69	u8 res2[0xf0];
	70	u32 srcidr; /* Source ID Register */
	71	u32 liodnr; /* LIODN Register */
	72	u8 res7[0x2f4];
	73	};
	74
	75	#endif /* __FSL_QBMAN_H__ */
	76