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Commit 44262327aa288b111a41ce067bed235759db4c1c

Authored by Ahmed Mansour
Committed by York Sun
1 parent 1b76f3b8ab
Exists in smarc_8mq_lf_v2020.04 and in 17 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

drivers/misc: Share qbman init between archs 

This patch adds changes necessary to move functionality present in
PowerPC folders with ARM architectures that have DPAA1 QBMan hardware

- Create new board/freescale/common/fsl_portals.c to house shared
  device tree fixups for DPAA1 devices with ARM and PowerPC cores
- Add new header file to top includes directory to allow files in
  both architectures to grab the function prototypes
- Port inhibit_portals() from PowerPC to ARM. This function is used in
  setup to disable interrupts on all QMan and BMan portals. It is
  needed because the interrupts are enabled by default for all portals
  including unused/uninitialised portals. When the kernel attempts to
  go to deep sleep the unused portals prevent it from doing so

Signed-off-by: Ahmed Mansour <ahmed.mansour@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

Showing 18 changed files with 454 additions and 351 deletions Side-by-side Diff

arch/arm/cpu/armv8/fsl-layerscape/cpu.c
Diff comments   View file @ 4426232
... ... @@ -30,6 +30,7 @@
30 30 #endif
31 31 #include <asm/arch/clock.h>
32 32 #include <hwconfig.h>
  33 +#include <fsl_qbman.h>
33 34  
34 35 DECLARE_GLOBAL_DATA_PTR;
35 36  
... ... @@ -564,6 +565,9 @@
564 565 #endif
565 566 #ifdef CONFIG_FMAN_ENET
566 567 fman_enet_init();
  568 +#endif
  569 +#ifdef CONFIG_SYS_DPAA_QBMAN
  570 + setup_qbman_portals();
567 571 #endif
568 572 return 0;
569 573 }
arch/arm/cpu/armv8/fsl-layerscape/fdt.c
Diff comments   View file @ 4426232
... ... @@ -26,6 +26,8 @@
26 26 #ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
27 27 #include <asm/armv8/sec_firmware.h>
28 28 #endif
  29 +#include <asm/arch/speed.h>
  30 +#include <fsl_qbman.h>
29 31  
30 32 int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
31 33 {
... ... @@ -440,6 +442,13 @@
440 442  
441 443 #ifdef CONFIG_FSL_ESDHC
442 444 fdt_fixup_esdhc(blob, bd);
  445 +#endif
  446 +
  447 +#ifdef CONFIG_SYS_DPAA_QBMAN
  448 + fdt_fixup_bportals(blob);
  449 + fdt_fixup_qportals(blob);
  450 + do_fixup_by_compat_u32(blob, "fsl,qman",
  451 + "clock-frequency", get_qman_freq(), 1);
443 452 #endif
444 453  
445 454 #ifdef CONFIG_SYS_DPAA_FMAN
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
Diff comments   View file @ 4426232
... ... @@ -155,7 +155,21 @@
155 155 sys_info->freq_localbus = sys_info->freq_systembus /
156 156 CONFIG_SYS_FSL_IFC_CLK_DIV;
157 157 #endif
  158 +#ifdef CONFIG_SYS_DPAA_QBMAN
  159 + sys_info->freq_qman = sys_info->freq_systembus;
  160 +#endif
158 161 }
  162 +
  163 +#ifdef CONFIG_SYS_DPAA_QBMAN
  164 +unsigned long get_qman_freq(void)
  165 +{
  166 + struct sys_info sys_info;
  167 +
  168 + get_sys_info(&sys_info);
  169 +
  170 + return sys_info.freq_qman;
  171 +}
  172 +#endif
159 173  
160 174 int get_clocks(void)
161 175 {
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
Diff comments   View file @ 4426232
... ... @@ -23,6 +23,8 @@
23 23 #define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
24 24 #define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00ee00b0)
25 25 #define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
  26 +#define CONFIG_SYS_FSL_BMAN_ADDR (CONFIG_SYS_IMMR + 0x00890000)
  27 +#define CONFIG_SYS_FSL_QMAN_ADDR (CONFIG_SYS_IMMR + 0x00880000)
26 28 #define CONFIG_SYS_FSL_FMAN_ADDR (CONFIG_SYS_IMMR + 0x00a00000)
27 29 #define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
28 30 #define CONFIG_SYS_FSL_DCFG_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
... ... @@ -40,6 +42,33 @@
40 42 #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
41 43 #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0xe90000)
42 44 #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0xe80200)
  45 +
  46 +#define CONFIG_SYS_BMAN_NUM_PORTALS 10
  47 +#define CONFIG_SYS_BMAN_MEM_BASE 0x508000000
  48 +#define CONFIG_SYS_BMAN_MEM_PHYS (0xf00000000ull + \
  49 + CONFIG_SYS_BMAN_MEM_BASE)
  50 +#define CONFIG_SYS_BMAN_MEM_SIZE 0x08000000
  51 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x10000
  52 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x10000
  53 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
  54 +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  55 +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
  56 + CONFIG_SYS_BMAN_CENA_SIZE)
  57 +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  58 +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0x3E80
  59 +#define CONFIG_SYS_QMAN_NUM_PORTALS 10
  60 +#define CONFIG_SYS_QMAN_MEM_BASE 0x500000000
  61 +#define CONFIG_SYS_QMAN_MEM_PHYS (0xf00000000ull + \
  62 + CONFIG_SYS_QMAN_MEM_BASE)
  63 +#define CONFIG_SYS_QMAN_MEM_SIZE 0x08000000
  64 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x10000
  65 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x10000
  66 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
  67 +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  68 +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
  69 + CONFIG_SYS_QMAN_CENA_SIZE)
  70 +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  71 +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0x3680
43 72  
44 73 #define CONFIG_SYS_FSL_TIMER_ADDR 0x02b00000
45 74  
arch/arm/include/asm/arch-fsl-layerscape/speed.h
Diff comments   View file @ 4426232
... ... @@ -7,5 +7,8 @@
7 7 #ifndef _FSL_LAYERSCAPE_SPEED_H
8 8 #define _FSL_LAYERSCAPE_SPEED_H
9 9 void get_sys_info(struct sys_info *sys_info);
  10 +#ifdef CONFIG_SYS_DPAA_QBMAN
  11 +unsigned long get_qman_freq(void);
  12 +#endif
10 13 #endif /* _FSL_LAYERSCAPE_SPEED_H */
arch/powerpc/cpu/mpc85xx/cpu_init.c
Diff comments   View file @ 4426232
... ... @@ -26,6 +26,7 @@
26 26 #ifdef CONFIG_FSL_CORENET
27 27 #include <asm/fsl_portals.h>
28 28 #include <asm/fsl_liodn.h>
  29 +#include <fsl_qbman.h>
29 30 #endif
30 31 #include <fsl_usb.h>
31 32 #include <hwconfig.h>
... ... @@ -804,7 +805,7 @@
804 805 #ifdef CONFIG_FSL_CORENET
805 806 set_liodns();
806 807 #ifdef CONFIG_SYS_DPAA_QBMAN
807   - setup_portals();
  808 + setup_qbman_portals();
808 809 #endif
809 810 #endif
810 811  
arch/powerpc/cpu/mpc85xx/fdt.c
Diff comments   View file @ 4426232
... ... @@ -15,6 +15,7 @@
15 15 #include <asm/io.h>
16 16 #include <asm/fsl_fdt.h>
17 17 #include <asm/fsl_portals.h>
  18 +#include <fsl_qbman.h>
18 19 #include <hwconfig.h>
19 20 #ifdef CONFIG_FSL_ESDHC
20 21 #include <fsl_esdhc.h>
arch/powerpc/cpu/mpc85xx/portals.c
Diff comments   View file @ 4426232
... ... @@ -14,75 +14,6 @@
14 14 #include <asm/fsl_portals.h>
15 15 #include <asm/fsl_liodn.h>
16 16  
17   -#define MAX_BPORTALS (CONFIG_SYS_BMAN_CINH_SIZE / CONFIG_SYS_BMAN_SP_CINH_SIZE)
18   -#define MAX_QPORTALS (CONFIG_SYS_QMAN_CINH_SIZE / CONFIG_SYS_QMAN_SP_CINH_SIZE)
19   -static void inhibit_portals(void __iomem *addr, int max_portals,
20   - int arch_max_portals, int portal_cinh_size)
21   -{
22   - uint32_t val;
23   - int i;
24   -
25   - /* arch_max_portals is the maximum based on memory size. This includes
26   - * the reserved memory in the SoC. max_portals the number of physical
27   - * portals in the SoC */
28   - if (max_portals > arch_max_portals) {
29   - printf("ERROR: portal config error\n");
30   - max_portals = arch_max_portals;
31   - }
32   -
33   - for (i = 0; i < max_portals; i++) {
34   - out_be32(addr, -1);
35   - val = in_be32(addr);
36   - if (!val) {
37   - printf("ERROR: Stopped after %d portals\n", i);
38   - goto done;
39   - }
40   - addr += portal_cinh_size;
41   - }
42   -#ifdef DEBUG
43   - printf("Cleared %d portals\n", i);
44   -#endif
45   -done:
46   -
47   - return;
48   -}
49   -
50   -void setup_portals(void)
51   -{
52   - ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
53   - void __iomem *bpaddr = (void *)CONFIG_SYS_BMAN_CINH_BASE +
54   - CONFIG_SYS_BMAN_SWP_ISDR_REG;
55   - void __iomem *qpaddr = (void *)CONFIG_SYS_QMAN_CINH_BASE +
56   - CONFIG_SYS_QMAN_SWP_ISDR_REG;
57   -#ifdef CONFIG_FSL_CORENET
58   - int i;
59   -
60   - for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) {
61   - u8 sdest = qp_info[i].sdest;
62   - u16 fliodn = qp_info[i].fliodn;
63   - u16 dliodn = qp_info[i].dliodn;
64   - u16 liodn_off = qp_info[i].liodn_offset;
65   -
66   - out_be32(&qman->qcsp[i].qcsp_lio_cfg, (liodn_off << 16) |
67   - dliodn);
68   - /* set frame liodn */
69   - out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) | fliodn);
70   - }
71   -#endif
72   -
73   - /* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */
74   -#ifdef CONFIG_PHYS_64BIT
75   - out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32));
76   -#endif
77   - out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS);
78   -
79   - /* Change default state of BMan ISDR portals to all 1s */
80   - inhibit_portals(bpaddr, CONFIG_SYS_BMAN_NUM_PORTALS, MAX_BPORTALS,
81   - CONFIG_SYS_BMAN_SP_CINH_SIZE);
82   - inhibit_portals(qpaddr, CONFIG_SYS_QMAN_NUM_PORTALS, MAX_QPORTALS,
83   - CONFIG_SYS_QMAN_SP_CINH_SIZE);
84   -}
85   -
86 17 /* Update portal containter to match LAW setup of portal in phy map */
87 18 void fdt_portal(void *blob, const char *compat, const char *container,
88 19 u64 addr, u32 size)
... ... @@ -141,217 +72,5 @@
141 72 }
142 73  
143 74 printf("ERROR: %s isn't in a container. Not supported\n", compat);
144   -}
145   -
146   -static int fdt_qportal(void *blob, int off, int id, char *name,
147   - enum fsl_dpaa_dev dev, int create)
148   -{
149   - int childoff, dev_off, ret = 0;
150   - uint32_t dev_handle;
151   -#ifdef CONFIG_FSL_CORENET
152   - int num;
153   - u32 liodns[2];
154   -#endif
155   -
156   - childoff = fdt_subnode_offset(blob, off, name);
157   - if (create) {
158   - char handle[64], *p;
159   -
160   - strncpy(handle, name, sizeof(handle));
161   - p = strchr(handle, '@');
162   - if (!strncmp(name, "fman", 4)) {
163   - *p = *(p + 1);
164   - p++;
165   - }
166   - *p = '\0';
167   -
168   - dev_off = fdt_path_offset(blob, handle);
169   - /* skip this node if alias is not found */
170   - if (dev_off == -FDT_ERR_BADPATH)
171   - return 0;
172   - if (dev_off < 0)
173   - return dev_off;
174   -
175   - if (childoff <= 0)
176   - childoff = fdt_add_subnode(blob, off, name);
177   -
178   - /* need to update the dev_off after adding a subnode */
179   - dev_off = fdt_path_offset(blob, handle);
180   - if (dev_off < 0)
181   - return dev_off;
182   -
183   - if (childoff > 0) {
184   - dev_handle = fdt_get_phandle(blob, dev_off);
185   - if (dev_handle <= 0) {
186   - dev_handle = fdt_alloc_phandle(blob);
187   - ret = fdt_set_phandle(blob, dev_off,
188   - dev_handle);
189   - if (ret < 0)
190   - return ret;
191   - }
192   -
193   - ret = fdt_setprop(blob, childoff, "dev-handle",
194   - &dev_handle, sizeof(dev_handle));
195   - if (ret < 0)
196   - return ret;
197   -
198   -#ifdef CONFIG_FSL_CORENET
199   - num = get_dpaa_liodn(dev, &liodns[0], id);
200   - ret = fdt_setprop(blob, childoff, "fsl,liodn",
201   - &liodns[0], sizeof(u32) * num);
202   - if (!strncmp(name, "pme", 3)) {
203   - u32 pme_rev1, pme_rev2;
204   - ccsr_pme_t *pme_regs =
205   - (void *)CONFIG_SYS_FSL_CORENET_PME_ADDR;
206   -
207   - pme_rev1 = in_be32(&pme_regs->pm_ip_rev_1);
208   - pme_rev2 = in_be32(&pme_regs->pm_ip_rev_2);
209   - ret = fdt_setprop(blob, childoff,
210   - "fsl,pme-rev1", &pme_rev1, sizeof(u32));
211   - if (ret < 0)
212   - return ret;
213   - ret = fdt_setprop(blob, childoff,
214   - "fsl,pme-rev2", &pme_rev2, sizeof(u32));
215   - }
216   -#endif
217   - } else {
218   - return childoff;
219   - }
220   - } else {
221   - if (childoff > 0)
222   - ret = fdt_del_node(blob, childoff);
223   - }
224   -
225   - return ret;
226   -}
227   -
228   -void fdt_fixup_qportals(void *blob)
229   -{
230   - int off, err;
231   - unsigned int maj, min;
232   - unsigned int ip_cfg;
233   - ccsr_qman_t *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
234   - u32 rev_1 = in_be32(&qman->ip_rev_1);
235   - u32 rev_2 = in_be32(&qman->ip_rev_2);
236   - char compat[64];
237   - int compat_len;
238   -
239   - maj = (rev_1 >> 8) & 0xff;
240   - min = rev_1 & 0xff;
241   - ip_cfg = rev_2 & 0xff;
242   -
243   - compat_len = sprintf(compat, "fsl,qman-portal-%u.%u.%u",
244   - maj, min, ip_cfg) + 1;
245   - compat_len += sprintf(compat + compat_len, "fsl,qman-portal") + 1;
246   -
247   - off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal");
248   - while (off != -FDT_ERR_NOTFOUND) {
249   -#ifdef CONFIG_FSL_CORENET
250   - u32 liodns[2];
251   -#endif
252   - const int *ci = fdt_getprop(blob, off, "cell-index", &err);
253   - int i;
254   -
255   - if (!ci)
256   - goto err;
257   -
258   - i = *ci;
259   -#ifdef CONFIG_SYS_DPAA_FMAN
260   - int j;
261   -#endif
262   -
263   - err = fdt_setprop(blob, off, "compatible", compat, compat_len);
264   - if (err < 0)
265   - goto err;
266   -
267   -#ifdef CONFIG_FSL_CORENET
268   - liodns[0] = qp_info[i].dliodn;
269   - liodns[1] = qp_info[i].fliodn;
270   -
271   - err = fdt_setprop(blob, off, "fsl,liodn",
272   - &liodns, sizeof(u32) * 2);
273   - if (err < 0)
274   - goto err;
275   -#endif
276   -
277   - i++;
278   -
279   - err = fdt_qportal(blob, off, i, "crypto@0", FSL_HW_PORTAL_SEC,
280   - IS_E_PROCESSOR(get_svr()));
281   - if (err < 0)
282   - goto err;
283   -
284   -#ifdef CONFIG_FSL_CORENET
285   -#ifdef CONFIG_SYS_DPAA_PME
286   - err = fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 1);
287   - if (err < 0)
288   - goto err;
289   -#else
290   - fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 0);
291   -#endif
292   -#endif
293   -
294   -#ifdef CONFIG_SYS_DPAA_FMAN
295   - for (j = 0; j < CONFIG_SYS_NUM_FMAN; j++) {
296   - char name[] = "fman@0";
297   -
298   - name[sizeof(name) - 2] = '0' + j;
299   - err = fdt_qportal(blob, off, i, name,
300   - FSL_HW_PORTAL_FMAN1 + j, 1);
301   - if (err < 0)
302   - goto err;
303   - }
304   -#endif
305   -#ifdef CONFIG_SYS_DPAA_RMAN
306   - err = fdt_qportal(blob, off, i, "rman@0",
307   - FSL_HW_PORTAL_RMAN, 1);
308   - if (err < 0)
309   - goto err;
310   -#endif
311   -
312   -err:
313   - if (err < 0) {
314   - printf("ERROR: unable to create props for %s: %s\n",
315   - fdt_get_name(blob, off, NULL), fdt_strerror(err));
316   - return;
317   - }
318   -
319   - off = fdt_node_offset_by_compatible(blob, off, "fsl,qman-portal");
320   - }
321   -}
322   -
323   -void fdt_fixup_bportals(void *blob)
324   -{
325   - int off, err;
326   - unsigned int maj, min;
327   - unsigned int ip_cfg;
328   - ccsr_bman_t *bman = (void *)CONFIG_SYS_FSL_BMAN_ADDR;
329   - u32 rev_1 = in_be32(&bman->ip_rev_1);
330   - u32 rev_2 = in_be32(&bman->ip_rev_2);
331   - char compat[64];
332   - int compat_len;
333   -
334   - maj = (rev_1 >> 8) & 0xff;
335   - min = rev_1 & 0xff;
336   -
337   - ip_cfg = rev_2 & 0xff;
338   -
339   - compat_len = sprintf(compat, "fsl,bman-portal-%u.%u.%u",
340   - maj, min, ip_cfg) + 1;
341   - compat_len += sprintf(compat + compat_len, "fsl,bman-portal") + 1;
342   -
343   - off = fdt_node_offset_by_compatible(blob, -1, "fsl,bman-portal");
344   - while (off != -FDT_ERR_NOTFOUND) {
345   - err = fdt_setprop(blob, off, "compatible", compat, compat_len);
346   - if (err < 0) {
347   - printf("ERROR: unable to create props for %s: %s\n",
348   - fdt_get_name(blob, off, NULL),
349   - fdt_strerror(err));
350   - return;
351   - }
352   -
353   - off = fdt_node_offset_by_compatible(blob, off, "fsl,bman-portal");
354   - }
355   -
356 75 }
arch/powerpc/include/asm/fsl_liodn.h
Diff comments   View file @ 4426232
... ... @@ -8,6 +8,7 @@
8 8 #define _FSL_LIODN_H_
9 9  
10 10 #include <asm/types.h>
  11 +#include <fsl_qbman.h>
11 12  
12 13 struct srio_liodn_id_table {
13 14 u32 id[2];
14 15  
... ... @@ -128,12 +129,14 @@
128 129 CONFIG_SYS_MPC85xx_TDM_OFFSET)
129 130  
130 131 #define SET_QMAN_LIODN(liodn) \
131   - SET_LIODN_ENTRY_1("fsl,qman", liodn, offsetof(ccsr_qman_t, liodnr) + \
  132 + SET_LIODN_ENTRY_1("fsl,qman", liodn, \
  133 + offsetof(struct ccsr_qman, liodnr) + \
132 134 CONFIG_SYS_FSL_QMAN_OFFSET, \
133 135 CONFIG_SYS_FSL_QMAN_OFFSET)
134 136  
135 137 #define SET_BMAN_LIODN(liodn) \
136   - SET_LIODN_ENTRY_1("fsl,bman", liodn, offsetof(ccsr_bman_t, liodnr) + \
  138 + SET_LIODN_ENTRY_1("fsl,bman", liodn, \
  139 + offsetof(struct ccsr_bman, liodnr) + \
137 140 CONFIG_SYS_FSL_BMAN_OFFSET, \
138 141 CONFIG_SYS_FSL_BMAN_OFFSET)
139 142  
arch/powerpc/include/asm/fsl_portals.h
Diff comments   View file @ 4426232
... ... @@ -41,10 +41,6 @@
41 41  
42 42 extern int get_dpaa_liodn(enum fsl_dpaa_dev dpaa_dev,
43 43 u32 *liodns, int liodn_offset);
44   -extern void setup_portals(void);
45   -extern void fdt_fixup_qportals(void *blob);
46   -extern void fdt_fixup_bportals(void *blob);
47   -
48 44 extern struct qportal_info qp_info[];
49 45 extern void fdt_portal(void *blob, const char *compat, const char *container,
50 46 u64 addr, u32 size);
arch/powerpc/include/asm/immap_85xx.h
Diff comments   View file @ 4426232
... ... @@ -2702,66 +2702,6 @@
2702 2702 FSL_SRDS_B3_LANE_D = 23,
2703 2703 };
2704 2704  
2705   -typedef struct ccsr_qman {
2706   -#ifdef CONFIG_SYS_FSL_QMAN_V3
2707   - u8 res0[0x200];
2708   -#else
2709   - struct {
2710   - u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */
2711   - u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */
2712   - u32 res;
2713   - u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg */
2714   - } qcsp[32];
2715   -#endif
2716   - /* Not actually reserved, but irrelevant to u-boot */
2717   - u8 res[0xbf8 - 0x200];
2718   - u32 ip_rev_1;
2719   - u32 ip_rev_2;
2720   - u32 fqd_bare; /* FQD Extended Base Addr Register */
2721   - u32 fqd_bar; /* FQD Base Addr Register */
2722   - u8 res1[0x8];
2723   - u32 fqd_ar; /* FQD Attributes Register */
2724   - u8 res2[0xc];
2725   - u32 pfdr_bare; /* PFDR Extended Base Addr Register */
2726   - u32 pfdr_bar; /* PFDR Base Addr Register */
2727   - u8 res3[0x8];
2728   - u32 pfdr_ar; /* PFDR Attributes Register */
2729   - u8 res4[0x4c];
2730   - u32 qcsp_bare; /* QCSP Extended Base Addr Register */
2731   - u32 qcsp_bar; /* QCSP Base Addr Register */
2732   - u8 res5[0x78];
2733   - u32 ci_sched_cfg; /* Initiator Scheduling Configuration */
2734   - u32 srcidr; /* Source ID Register */
2735   - u32 liodnr; /* LIODN Register */
2736   - u8 res6[4];
2737   - u32 ci_rlm_cfg; /* Initiator Read Latency Monitor Cfg */
2738   - u32 ci_rlm_avg; /* Initiator Read Latency Monitor Avg */
2739   - u8 res7[0x2e8];
2740   -#ifdef CONFIG_SYS_FSL_QMAN_V3
2741   - struct {
2742   - u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */
2743   - u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */
2744   - u32 res;
2745   - u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg*/
2746   - } qcsp[50];
2747   -#endif
2748   -} ccsr_qman_t;
2749   -
2750   -typedef struct ccsr_bman {
2751   - /* Not actually reserved, but irrelevant to u-boot */
2752   - u8 res[0xbf8];
2753   - u32 ip_rev_1;
2754   - u32 ip_rev_2;
2755   - u32 fbpr_bare; /* FBPR Extended Base Addr Register */
2756   - u32 fbpr_bar; /* FBPR Base Addr Register */
2757   - u8 res1[0x8];
2758   - u32 fbpr_ar; /* FBPR Attributes Register */
2759   - u8 res2[0xf0];
2760   - u32 srcidr; /* Source ID Register */
2761   - u32 liodnr; /* LIODN Register */
2762   - u8 res7[0x2f4];
2763   -} ccsr_bman_t;
2764   -
2765 2705 typedef struct ccsr_pme {
2766 2706 u8 res0[0x804];
2767 2707 u32 liodnbr; /* LIODN Base Register */
board/freescale/p1023rdb/p1023rdb.c
Diff comments   View file @ 4426232
... ... @@ -18,6 +18,7 @@
18 18 #include <asm/fsl_pci.h>
19 19 #include <fsl_ddr_sdram.h>
20 20 #include <asm/fsl_portals.h>
  21 +#include <fsl_qbman.h>
21 22 #include <libfdt.h>
22 23 #include <fdt_support.h>
23 24 #include <netdev.h>
... ... @@ -81,7 +82,7 @@
81 82 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
82 83 0, flash_esel, BOOKE_PAGESZ_256M, 1);
83 84  
84   - setup_portals();
  85 + setup_qbman_portals();
85 86  
86 87 return 0;
87 88 }
board/keymile/kmp204x/kmp204x.c
Diff comments   View file @ 4426232
... ... @@ -126,7 +126,7 @@
126 126 invalidate_icache();
127 127  
128 128 set_liodns();
129   - setup_portals();
  129 + setup_qbman_portals();
130 130  
131 131 ret = trigger_fpga_config();
132 132 if (ret)
board/varisys/cyrus/cyrus.c
Diff comments   View file @ 4426232
... ... @@ -69,7 +69,7 @@
69 69 set_liodns();
70 70  
71 71 #ifdef CONFIG_SYS_DPAA_QBMAN
72   - setup_portals();
  72 + setup_qbman_portals();
73 73 #endif
74 74 print_lbc_regs();
75 75 return 0;
drivers/misc/Makefile
Diff comments   View file @ 4426232
... ... @@ -53,4 +53,5 @@
53 53 obj-$(CONFIG_QFW) += qfw.o
54 54 obj-$(CONFIG_ROCKCHIP_EFUSE) += rockchip-efuse.o
55 55 obj-$(CONFIG_STM32_RCC) += stm32_rcc.o
  56 +obj-$(CONFIG_SYS_DPAA_QBMAN) += fsl_portals.o
drivers/misc/fsl_portals.c
Diff comments   View file @ 4426232
  1 +/*
  2 + * Copyright 2008-2011 Freescale Semiconductor, Inc.
  3 + * Copyright 2017 NXP
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#include <common.h>
  9 +#include <libfdt.h>
  10 +#include <fdt_support.h>
  11 +
  12 +#include <asm/processor.h>
  13 +#include <asm/io.h>
  14 +#ifdef CONFIG_PPC
  15 +#include <asm/fsl_portals.h>
  16 +#include <asm/fsl_liodn.h>
  17 +#endif
  18 +#include <fsl_qbman.h>
  19 +
  20 +#define MAX_BPORTALS (CONFIG_SYS_BMAN_CINH_SIZE / CONFIG_SYS_BMAN_SP_CINH_SIZE)
  21 +#define MAX_QPORTALS (CONFIG_SYS_QMAN_CINH_SIZE / CONFIG_SYS_QMAN_SP_CINH_SIZE)
  22 +void setup_qbman_portals(void)
  23 +{
  24 + void __iomem *bpaddr = (void *)CONFIG_SYS_BMAN_CINH_BASE +
  25 + CONFIG_SYS_BMAN_SWP_ISDR_REG;
  26 + void __iomem *qpaddr = (void *)CONFIG_SYS_QMAN_CINH_BASE +
  27 + CONFIG_SYS_QMAN_SWP_ISDR_REG;
  28 +#ifdef CONFIG_PPC
  29 + struct ccsr_qman *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
  30 +
  31 + /* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */
  32 +#ifdef CONFIG_PHYS_64BIT
  33 + out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32));
  34 +#endif
  35 + out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS);
  36 +#endif
  37 +#ifdef CONFIG_FSL_CORENET
  38 + int i;
  39 +
  40 + for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) {
  41 + u8 sdest = qp_info[i].sdest;
  42 + u16 fliodn = qp_info[i].fliodn;
  43 + u16 dliodn = qp_info[i].dliodn;
  44 + u16 liodn_off = qp_info[i].liodn_offset;
  45 +
  46 + out_be32(&qman->qcsp[i].qcsp_lio_cfg, (liodn_off << 16) |
  47 + dliodn);
  48 + /* set frame liodn */
  49 + out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) | fliodn);
  50 + }
  51 +#endif
  52 +
  53 + /* Change default state of BMan ISDR portals to all 1s */
  54 + inhibit_portals(bpaddr, CONFIG_SYS_BMAN_NUM_PORTALS, MAX_BPORTALS,
  55 + CONFIG_SYS_BMAN_SP_CINH_SIZE);
  56 + inhibit_portals(qpaddr, CONFIG_SYS_QMAN_NUM_PORTALS, MAX_QPORTALS,
  57 + CONFIG_SYS_QMAN_SP_CINH_SIZE);
  58 +}
  59 +
  60 +void inhibit_portals(void __iomem *addr, int max_portals,
  61 + int arch_max_portals, int portal_cinh_size)
  62 +{
  63 + u32 val;
  64 + int i;
  65 +
  66 + /* arch_max_portals is the maximum based on memory size. This includes
  67 + * the reserved memory in the SoC. max_portals the number of physical
  68 + * portals in the SoC
  69 + */
  70 + if (max_portals > arch_max_portals) {
  71 + printf("ERROR: portal config error\n");
  72 + max_portals = arch_max_portals;
  73 + }
  74 +
  75 + for (i = 0; i < max_portals; i++) {
  76 + out_be32(addr, -1);
  77 + val = in_be32(addr);
  78 + if (!val) {
  79 + printf("ERROR: Stopped after %d portals\n", i);
  80 + return;
  81 + }
  82 + addr += portal_cinh_size;
  83 + }
  84 + debug("Cleared %d portals\n", i);
  85 +}
  86 +
  87 +#ifdef CONFIG_PPC
  88 +static int fdt_qportal(void *blob, int off, int id, char *name,
  89 + enum fsl_dpaa_dev dev, int create)
  90 +{
  91 + int childoff, dev_off, ret = 0;
  92 + u32 dev_handle;
  93 +#ifdef CONFIG_FSL_CORENET
  94 + int num;
  95 + u32 liodns[2];
  96 +#endif
  97 +
  98 + childoff = fdt_subnode_offset(blob, off, name);
  99 + if (create) {
  100 + char handle[64], *p;
  101 +
  102 + strncpy(handle, name, sizeof(handle));
  103 + p = strchr(handle, '@');
  104 + if (!strncmp(name, "fman", 4)) {
  105 + *p = *(p + 1);
  106 + p++;
  107 + }
  108 + *p = '\0';
  109 +
  110 + dev_off = fdt_path_offset(blob, handle);
  111 + /* skip this node if alias is not found */
  112 + if (dev_off == -FDT_ERR_BADPATH)
  113 + return 0;
  114 + if (dev_off < 0)
  115 + return dev_off;
  116 +
  117 + if (childoff <= 0)
  118 + childoff = fdt_add_subnode(blob, off, name);
  119 +
  120 + /* need to update the dev_off after adding a subnode */
  121 + dev_off = fdt_path_offset(blob, handle);
  122 + if (dev_off < 0)
  123 + return dev_off;
  124 +
  125 + if (childoff > 0) {
  126 + dev_handle = fdt_get_phandle(blob, dev_off);
  127 + if (dev_handle <= 0) {
  128 + dev_handle = fdt_alloc_phandle(blob);
  129 + ret = fdt_set_phandle(blob, dev_off,
  130 + dev_handle);
  131 + if (ret < 0)
  132 + return ret;
  133 + }
  134 +
  135 + ret = fdt_setprop(blob, childoff, "dev-handle",
  136 + &dev_handle, sizeof(dev_handle));
  137 + if (ret < 0)
  138 + return ret;
  139 +
  140 +#ifdef CONFIG_FSL_CORENET
  141 + num = get_dpaa_liodn(dev, &liodns[0], id);
  142 + ret = fdt_setprop(blob, childoff, "fsl,liodn",
  143 + &liodns[0], sizeof(u32) * num);
  144 + if (!strncmp(name, "pme", 3)) {
  145 + u32 pme_rev1, pme_rev2;
  146 + ccsr_pme_t *pme_regs =
  147 + (void *)CONFIG_SYS_FSL_CORENET_PME_ADDR;
  148 +
  149 + pme_rev1 = in_be32(&pme_regs->pm_ip_rev_1);
  150 + pme_rev2 = in_be32(&pme_regs->pm_ip_rev_2);
  151 + ret = fdt_setprop(blob, childoff,
  152 + "fsl,pme-rev1", &pme_rev1,
  153 + sizeof(u32));
  154 + if (ret < 0)
  155 + return ret;
  156 + ret = fdt_setprop(blob, childoff,
  157 + "fsl,pme-rev2", &pme_rev2,
  158 + sizeof(u32));
  159 + }
  160 +#endif
  161 + } else {
  162 + return childoff;
  163 + }
  164 + } else {
  165 + if (childoff > 0)
  166 + ret = fdt_del_node(blob, childoff);
  167 + }
  168 +
  169 + return ret;
  170 +}
  171 +#endif /* CONFIG_PPC */
  172 +
  173 +void fdt_fixup_qportals(void *blob)
  174 +{
  175 + int off, err;
  176 + unsigned int maj, min;
  177 + unsigned int ip_cfg;
  178 + struct ccsr_qman *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
  179 + u32 rev_1 = in_be32(&qman->ip_rev_1);
  180 + u32 rev_2 = in_be32(&qman->ip_rev_2);
  181 + char compat[64];
  182 + int compat_len;
  183 +
  184 + maj = (rev_1 >> 8) & 0xff;
  185 + min = rev_1 & 0xff;
  186 + ip_cfg = rev_2 & 0xff;
  187 +
  188 + compat_len = sprintf(compat, "fsl,qman-portal-%u.%u.%u",
  189 + maj, min, ip_cfg) + 1;
  190 + compat_len += sprintf(compat + compat_len, "fsl,qman-portal") + 1;
  191 +
  192 + off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal");
  193 + while (off != -FDT_ERR_NOTFOUND) {
  194 +#ifdef CONFIG_PPC
  195 +#ifdef CONFIG_FSL_CORENET
  196 + u32 liodns[2];
  197 +#endif
  198 + const int *ci = fdt_getprop(blob, off, "cell-index", &err);
  199 + int i;
  200 +
  201 + if (!ci)
  202 + goto err;
  203 +
  204 + i = *ci;
  205 +#ifdef CONFIG_SYS_DPAA_FMAN
  206 + int j;
  207 +#endif
  208 +
  209 +#endif /* CONFIG_PPC */
  210 + err = fdt_setprop(blob, off, "compatible", compat, compat_len);
  211 + if (err < 0)
  212 + goto err;
  213 +#ifdef CONFIG_PPC
  214 +#ifdef CONFIG_FSL_CORENET
  215 + liodns[0] = qp_info[i].dliodn;
  216 + liodns[1] = qp_info[i].fliodn;
  217 + err = fdt_setprop(blob, off, "fsl,liodn",
  218 + &liodns, sizeof(u32) * 2);
  219 + if (err < 0)
  220 + goto err;
  221 +#endif
  222 +
  223 + i++;
  224 +
  225 + err = fdt_qportal(blob, off, i, "crypto@0", FSL_HW_PORTAL_SEC,
  226 + IS_E_PROCESSOR(get_svr()));
  227 + if (err < 0)
  228 + goto err;
  229 +
  230 +#ifdef CONFIG_FSL_CORENET
  231 +#ifdef CONFIG_SYS_DPAA_PME
  232 + err = fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 1);
  233 + if (err < 0)
  234 + goto err;
  235 +#else
  236 + fdt_qportal(blob, off, i, "pme@0", FSL_HW_PORTAL_PME, 0);
  237 +#endif
  238 +#endif
  239 +
  240 +#ifdef CONFIG_SYS_DPAA_FMAN
  241 + for (j = 0; j < CONFIG_SYS_NUM_FMAN; j++) {
  242 + char name[] = "fman@0";
  243 +
  244 + name[sizeof(name) - 2] = '0' + j;
  245 + err = fdt_qportal(blob, off, i, name,
  246 + FSL_HW_PORTAL_FMAN1 + j, 1);
  247 + if (err < 0)
  248 + goto err;
  249 + }
  250 +#endif
  251 +#ifdef CONFIG_SYS_DPAA_RMAN
  252 + err = fdt_qportal(blob, off, i, "rman@0",
  253 + FSL_HW_PORTAL_RMAN, 1);
  254 + if (err < 0)
  255 + goto err;
  256 +#endif
  257 +#endif /* CONFIG_PPC */
  258 +
  259 +err:
  260 + if (err < 0) {
  261 + printf("ERROR: unable to create props for %s: %s\n",
  262 + fdt_get_name(blob, off, NULL),
  263 + fdt_strerror(err));
  264 + return;
  265 + }
  266 +
  267 + off = fdt_node_offset_by_compatible(blob, off,
  268 + "fsl,qman-portal");
  269 + }
  270 +}
  271 +
  272 +void fdt_fixup_bportals(void *blob)
  273 +{
  274 + int off, err;
  275 + unsigned int maj, min;
  276 + unsigned int ip_cfg;
  277 + struct ccsr_bman *bman = (void *)CONFIG_SYS_FSL_BMAN_ADDR;
  278 + u32 rev_1 = in_be32(&bman->ip_rev_1);
  279 + u32 rev_2 = in_be32(&bman->ip_rev_2);
  280 + char compat[64];
  281 + int compat_len;
  282 +
  283 + maj = (rev_1 >> 8) & 0xff;
  284 + min = rev_1 & 0xff;
  285 +
  286 + ip_cfg = rev_2 & 0xff;
  287 +
  288 + compat_len = sprintf(compat, "fsl,bman-portal-%u.%u.%u",
  289 + maj, min, ip_cfg) + 1;
  290 + compat_len += sprintf(compat + compat_len, "fsl,bman-portal") + 1;
  291 +
  292 + off = fdt_node_offset_by_compatible(blob, -1, "fsl,bman-portal");
  293 + while (off != -FDT_ERR_NOTFOUND) {
  294 + err = fdt_setprop(blob, off, "compatible", compat, compat_len);
  295 + if (err < 0) {
  296 + printf("ERROR: unable to create props for %s: %s\n",
  297 + fdt_get_name(blob, off, NULL),
  298 + fdt_strerror(err));
  299 + return;
  300 + }
  301 +
  302 + off = fdt_node_offset_by_compatible(blob, off,
  303 + "fsl,bman-portal");
  304 + }
  305 +}
include/configs/ls1043a_common.h
Diff comments   View file @ 4426232
... ... @@ -194,6 +194,8 @@
194 194 #endif
195 195 #endif
196 196  
  197 +#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
  198 +
197 199 /* FMan ucode */
198 200 #ifndef SPL_NO_FMAN
199 201 #define CONFIG_SYS_DPAA_FMAN
  1 +/*
  2 + * Copyright 2017 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef __FSL_QBMAN_H__
  8 +#define __FSL_QBMAN_H__
  9 +void fdt_fixup_qportals(void *blob);
  10 +void fdt_fixup_bportals(void *blob);
  11 +void inhibit_portals(void __iomem *addr, int max_portals,
  12 + int arch_max_portals, int portal_cinh_size);
  13 +void setup_qbman_portals(void);
  14 +
  15 +struct ccsr_qman {
  16 +#ifdef CONFIG_SYS_FSL_QMAN_V3
  17 + u8 res0[0x200];
  18 +#else
  19 + struct {
  20 + u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */
  21 + u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */
  22 + u32 res;
  23 + u32 qcsp_dd_cfg; /* 0xc - SW Portal Dynamic Debug cfg */
  24 + } qcsp[32];
  25 +#endif
  26 + /* Not actually reserved, but irrelevant to u-boot */
  27 + u8 res[0xbf8 - 0x200];
  28 + u32 ip_rev_1;
  29 + u32 ip_rev_2;
  30 + u32 fqd_bare; /* FQD Extended Base Addr Register */
  31 + u32 fqd_bar; /* FQD Base Addr Register */
  32 + u8 res1[0x8];
  33 + u32 fqd_ar; /* FQD Attributes Register */
  34 + u8 res2[0xc];
  35 + u32 pfdr_bare; /* PFDR Extended Base Addr Register */
  36 + u32 pfdr_bar; /* PFDR Base Addr Register */
  37 + u8 res3[0x8];
  38 + u32 pfdr_ar; /* PFDR Attributes Register */
  39 + u8 res4[0x4c];
  40 + u32 qcsp_bare; /* QCSP Extended Base Addr Register */
  41 + u32 qcsp_bar; /* QCSP Base Addr Register */
  42 + u8 res5[0x78];
  43 + u32 ci_sched_cfg; /* Initiator Scheduling Configuration */
  44 + u32 srcidr; /* Source ID Register */
  45 + u32 liodnr; /* LIODN Register */
  46 + u8 res6[4];
  47 + u32 ci_rlm_cfg; /* Initiator Read Latency Monitor Cfg */
  48 + u32 ci_rlm_avg; /* Initiator Read Latency Monitor Avg */
  49 + u8 res7[0x2e8];
  50 +#ifdef CONFIG_SYS_FSL_QMAN_V3
  51 + struct {
  52 + u32 qcsp_lio_cfg; /* 0x0 - SW Portal n LIO cfg */
  53 + u32 qcsp_io_cfg; /* 0x4 - SW Portal n IO cfg */
  54 + u32 res;
  55 + u32 qcsp_dd_cfg; /* 0xc - SW Portal n Dynamic Debug cfg*/
  56 + } qcsp[50];
  57 +#endif
  58 +};
  59 +
  60 +struct ccsr_bman {
  61 + /* Not actually reserved, but irrelevant to u-boot */
  62 + u8 res[0xbf8];
  63 + u32 ip_rev_1;
  64 + u32 ip_rev_2;
  65 + u32 fbpr_bare; /* FBPR Extended Base Addr Register */
  66 + u32 fbpr_bar; /* FBPR Base Addr Register */
  67 + u8 res1[0x8];
  68 + u32 fbpr_ar; /* FBPR Attributes Register */
  69 + u8 res2[0xf0];
  70 + u32 srcidr; /* Source ID Register */
  71 + u32 liodnr; /* LIODN Register */
  72 + u8 res7[0x2f4];
  73 +};
  74 +
  75 +#endif /* __FSL_QBMAN_H__ */