x86: serial: Add a coreboot serial driver

Coreboot can provide information about the serial device in use on a platform. Add a driver that uses this information to produce a working UART. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

x86: serial: Add a coreboot serial driver
Coreboot can provide information about the serial device in use on a platform. Add a driver that uses this information to produce a working UART. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass · Bin Meng
1 parent 8c3ccb3f6d
Showing 3 changed files with 58 additions and 0 deletions Side-by-side Diff
drivers/serial/Kconfig
drivers/serial/Makefile
drivers/serial/serial_coreboot.c
@@ -542,6 +542,17 @@
 	help
 	  Select this to enable UART on BCM6345 SoCs.
  
+config COREBOOT_SERIAL
+	bool "Coreboot UART support"
+	depends on DM_SERIAL
+	default y if SYS_COREBOOT
+	select SYS_NS16550
+	help
+	  Select this to enable a ns16550-style UART where the platform data
+	  comes from the coreboot 'sysinfo' tables. This allows U-Boot to have
+	  a serial console on any platform without needing to change the
+	  device tree, etc.
+
 config FSL_LINFLEXUART
 	bool "Freescale Linflex UART support"
 	depends on DM_SERIAL
@@ -35,6 +35,7 @@
 obj-$(CONFIG_ARM_DCC) += arm_dcc.o
 obj-$(CONFIG_ATMEL_USART) += atmel_usart.o
 obj-$(CONFIG_BCM6345_SERIAL) += serial_bcm6345.o
+obj-$(CONFIG_COREBOOT_SERIAL) += serial_coreboot.o
 obj-$(CONFIG_EFI_APP) += serial_efi.o
 obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o
 obj-$(CONFIG_MCFUART) += mcfuart.o
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * UART support for U-Boot when launched from Coreboot
+ *
+ * Copyright 2019 Google LLC
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <ns16550.h>
+#include <serial.h>
+#include <asm/arch/sysinfo.h>
+
+static int coreboot_ofdata_to_platdata(struct udevice *dev)
+{
+	struct ns16550_platdata *plat = dev_get_platdata(dev);
+	struct cb_serial *cb_info = lib_sysinfo.serial;
+
+	plat->base = cb_info->baseaddr;
+	plat->reg_shift = cb_info->regwidth == 4 ? 2 : 0;
+	plat->reg_width = cb_info->regwidth;
+	plat->clock = cb_info->input_hertz;
+	plat->fcr = UART_FCR_DEFVAL;
+	plat->flags = 0;
+	if (cb_info->type == CB_SERIAL_TYPE_IO_MAPPED)
+		plat->flags |= NS16550_FLAG_IO;
+
+	return 0;
+}
+
+static const struct udevice_id coreboot_serial_ids[] = {
+	{ .compatible = "coreboot-serial" },
+	{ },
+};
+
+U_BOOT_DRIVER(coreboot_uart) = {
+	.name	= "coreboot_uart",
+	.id	= UCLASS_SERIAL,
+	.of_match	= coreboot_serial_ids,
+	.priv_auto_alloc_size = sizeof(struct NS16550),
+	.platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
+	.ofdata_to_platdata  = coreboot_ofdata_to_platdata,
+	.probe	= ns16550_serial_probe,
+	.ops	= &ns16550_serial_ops,
+	.flags	= DM_FLAG_PRE_RELOC,
+};
...	...	@@ -542,6 +542,17 @@
542	542	help
543	543	Select this to enable UART on BCM6345 SoCs.
544	544
	545	+config COREBOOT_SERIAL
	546	+ bool "Coreboot UART support"
	547	+ depends on DM_SERIAL
	548	+ default y if SYS_COREBOOT
	549	+ select SYS_NS16550
	550	+ help
	551	+ Select this to enable a ns16550-style UART where the platform data
	552	+ comes from the coreboot 'sysinfo' tables. This allows U-Boot to have
	553	+ a serial console on any platform without needing to change the
	554	+ device tree, etc.
	555	+
545	556	config FSL_LINFLEXUART
546	557	bool "Freescale Linflex UART support"
547	558	depends on DM_SERIAL
...	...	@@ -35,6 +35,7 @@
35	35	obj-$(CONFIG_ARM_DCC) += arm_dcc.o
36	36	obj-$(CONFIG_ATMEL_USART) += atmel_usart.o
37	37	obj-$(CONFIG_BCM6345_SERIAL) += serial_bcm6345.o
	38	+obj-$(CONFIG_COREBOOT_SERIAL) += serial_coreboot.o
38	39	obj-$(CONFIG_EFI_APP) += serial_efi.o
39	40	obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o
40	41	obj-$(CONFIG_MCFUART) += mcfuart.o
	1	+// SPDX-License-Identifier: GPL-2.0+
	2	+/*
	3	+ * UART support for U-Boot when launched from Coreboot
	4	+ *
	5	+ * Copyright 2019 Google LLC
	6	+ */
	7	+
	8	+#include <common.h>
	9	+#include <dm.h>
	10	+#include <ns16550.h>
	11	+#include <serial.h>
	12	+#include <asm/arch/sysinfo.h>
	13	+
	14	+static int coreboot_ofdata_to_platdata(struct udevice *dev)
	15	+{
	16	+ struct ns16550_platdata *plat = dev_get_platdata(dev);
	17	+ struct cb_serial *cb_info = lib_sysinfo.serial;
	18	+
	19	+ plat->base = cb_info->baseaddr;
	20	+ plat->reg_shift = cb_info->regwidth == 4 ? 2 : 0;
	21	+ plat->reg_width = cb_info->regwidth;
	22	+ plat->clock = cb_info->input_hertz;
	23	+ plat->fcr = UART_FCR_DEFVAL;
	24	+ plat->flags = 0;
	25	+ if (cb_info->type == CB_SERIAL_TYPE_IO_MAPPED)
	26	+ plat->flags \|= NS16550_FLAG_IO;
	27	+
	28	+ return 0;
	29	+}
	30	+
	31	+static const struct udevice_id coreboot_serial_ids[] = {
	32	+ { .compatible = "coreboot-serial" },
	33	+ { },
	34	+};
	35	+
	36	+U_BOOT_DRIVER(coreboot_uart) = {
	37	+ .name = "coreboot_uart",
	38	+ .id = UCLASS_SERIAL,
	39	+ .of_match = coreboot_serial_ids,
	40	+ .priv_auto_alloc_size = sizeof(struct NS16550),
	41	+ .platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
	42	+ .ofdata_to_platdata = coreboot_ofdata_to_platdata,
	43	+ .probe = ns16550_serial_probe,
	44	+ .ops = &ns16550_serial_ops,
	45	+ .flags = DM_FLAG_PRE_RELOC,
	46	+};