Eric Lee / smarc-uboot

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Commit 44cfc3a83f2a62963af2de8d983daf4c77e1db0c

Authored by Albert ARIBAUD
2 parents 9f5f51540d 2364e151e4
Exists in v2017.01-smarct4x and in 40 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master'

Showing 19 changed files Side-by-side Diff

arch/arm/cpu/arm720t/tegra-common/cpu.c
Diff comments   View file @ 44cfc3a
... ... @@ -82,7 +82,7 @@
82 82 { .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
83 83 },
84 84 /*
85   - * T30: 1.4 GHz
  85 + * T30: 600 MHz
86 86 *
87 87 * Register Field Bits Width
88 88 * ------------------------------
... ... @@ -92,10 +92,10 @@
92 92 * PLLX_MISC cpcon 11: 8 4
93 93 */
94 94 {
95   - { .n = 862, .m = 8, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */
96   - { .n = 583, .m = 8, .p = 0, .cpcon = 4 }, /* OSC: 19.2 MHz */
97   - { .n = 700, .m = 6, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */
98   - { .n = 700, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */
  95 + { .n = 600, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */
  96 + { .n = 500, .m = 16, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
  97 + { .n = 600, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */
  98 + { .n = 600, .m = 26, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */
99 99 },
100 100 /*
101 101 * T114: 700 MHz
arch/arm/cpu/arm720t/tegra30/cpu.c
Diff comments   View file @ 44cfc3a
... ... @@ -41,10 +41,18 @@
41 41 writel(config, &reg->cnfg);
42 42 }
43 43  
  44 +#define TPS62366A_I2C_ADDR 0xC0
  45 +#define TPS62366A_SET1_REG 0x01
  46 +#define TPS62366A_SET1_DATA (0x4600 | TPS62366A_SET1_REG)
  47 +
  48 +#define TPS62361B_I2C_ADDR 0xC0
  49 +#define TPS62361B_SET3_REG 0x03
  50 +#define TPS62361B_SET3_DATA (0x4600 | TPS62361B_SET3_REG)
  51 +
44 52 #define TPS65911_I2C_ADDR 0x5A
45 53 #define TPS65911_VDDCTRL_OP_REG 0x28
46 54 #define TPS65911_VDDCTRL_SR_REG 0x27
47   -#define TPS65911_VDDCTRL_OP_DATA (0x2300 | TPS65911_VDDCTRL_OP_REG)
  55 +#define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG)
48 56 #define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG)
49 57 #define I2C_SEND_2_BYTES 0x0A02
50 58  
51 59  
... ... @@ -58,9 +66,20 @@
58 66 reg |= CPUPWRREQ_OE;
59 67 writel(reg, &pmc->pmc_cntrl);
60 68  
  69 + /* Set VDD_CORE to 1.200V. */
  70 +#ifdef CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1
  71 + tegra_i2c_ll_write_addr(TPS62366A_I2C_ADDR, 2);
  72 + tegra_i2c_ll_write_data(TPS62366A_SET1_DATA, I2C_SEND_2_BYTES);
  73 +#endif
  74 +#ifdef CONFIG_TEGRA_VDD_CORE_TPS62361B_SET3
  75 + tegra_i2c_ll_write_addr(TPS62361B_I2C_ADDR, 2);
  76 + tegra_i2c_ll_write_data(TPS62361B_SET3_DATA, I2C_SEND_2_BYTES);
  77 +#endif
  78 + udelay(1000);
  79 +
61 80 /*
62 81 * Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
63   - * First set VDD to 1.4V, then enable the VDD regulator.
  82 + * First set VDD to 1.0125V, then enable the VDD regulator.
64 83 */
65 84 tegra_i2c_ll_write_addr(TPS65911_I2C_ADDR, 2);
66 85 tegra_i2c_ll_write_data(TPS65911_VDDCTRL_OP_DATA, I2C_SEND_2_BYTES);
arch/arm/cpu/tegra-common/pinmux-common.c
Diff comments   View file @ 44cfc3a
... ... @@ -86,11 +86,30 @@
86 86 #define IO_RESET_SHIFT 8
87 87 #define RCV_SEL_SHIFT 9
88 88  
  89 +#if !defined(CONFIG_TEGRA20) && !defined(CONFIG_TEGRA30)
  90 +/* This register/field only exists on Tegra114 and later */
  91 +#define APB_MISC_PP_PINMUX_GLOBAL_0 0x40
  92 +#define CLAMP_INPUTS_WHEN_TRISTATED 1
  93 +
  94 +void pinmux_set_tristate_input_clamping(void)
  95 +{
  96 + u32 *reg = _R(APB_MISC_PP_PINMUX_GLOBAL_0);
  97 + u32 val;
  98 +
  99 + val = readl(reg);
  100 + val |= CLAMP_INPUTS_WHEN_TRISTATED;
  101 + writel(val, reg);
  102 +}
  103 +#endif
  104 +
89 105 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
90 106 {
91 107 u32 *reg = MUX_REG(pin);
92 108 int i, mux = -1;
93 109 u32 val;
  110 +
  111 + if (func == PMUX_FUNC_DEFAULT)
  112 + return;
94 113  
95 114 /* Error check on pin and func */
96 115 assert(pmux_pingrp_isvalid(pin));
arch/arm/include/asm/arch-tegra/gpio.h
Diff comments   View file @ 44cfc3a
... ... @@ -14,12 +14,32 @@
14 14 #define GPIO_FULLPORT(x) ((x) >> 3)
15 15 #define GPIO_BIT(x) ((x) & 0x7)
16 16  
  17 +enum tegra_gpio_init {
  18 + TEGRA_GPIO_INIT_IN,
  19 + TEGRA_GPIO_INIT_OUT0,
  20 + TEGRA_GPIO_INIT_OUT1,
  21 +};
  22 +
  23 +struct tegra_gpio_config {
  24 + u32 gpio:16;
  25 + u32 init:2;
  26 +};
  27 +
17 28 /*
18 29 * Tegra-specific GPIO API
19 30 */
20 31  
  32 +/**
  33 + * Configure a list of GPIOs
  34 + *
  35 + * @param config List of GPIO configurations
  36 + * @param len Number of config items in list
  37 + */
  38 +void gpio_config_table(const struct tegra_gpio_config *config, int len);
  39 +
21 40 void gpio_info(void);
22 41  
23 42 #define gpio_status() gpio_info()
  43 +
24 44 #endif /* TEGRA_GPIO_H_ */
arch/arm/include/asm/arch-tegra/pinmux.h
Diff comments   View file @ 44cfc3a
... ... @@ -80,6 +80,11 @@
80 80 #endif
81 81 };
82 82  
  83 +#if !defined(CONFIG_TEGRA20) && !defined(CONFIG_TEGRA30)
  84 +/* Set the pinmux CLAMP_INPUTS_WHEN_TRISTATED bit */
  85 +void pinmux_set_tristate_input_clamping(void);
  86 +#endif
  87 +
83 88 /* Set the mux function for a pin group */
84 89 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func);
85 90  
arch/arm/include/asm/arch-tegra/tegra_mmc.h
Diff comments   View file @ 44cfc3a
... ... @@ -14,8 +14,6 @@
14 14 /* for mmc_config definition */
15 15 #include <mmc.h>
16 16  
17   -#define MAX_HOSTS 4 /* Max number of 'hosts'/controllers */
18   -
19 17 #ifndef __ASSEMBLY__
20 18 struct tegra_mmc {
21 19 unsigned int sysad; /* _SYSTEM_ADDRESS_0 */
arch/arm/include/asm/arch-tegra114/pinmux.h
Diff comments   View file @ 44cfc3a
... ... @@ -231,6 +231,7 @@
231 231 };
232 232  
233 233 enum pmux_func {
  234 + PMUX_FUNC_DEFAULT,
234 235 PMUX_FUNC_BLINK,
235 236 PMUX_FUNC_CEC,
236 237 PMUX_FUNC_CLDVFS,
arch/arm/include/asm/arch-tegra124/pinmux.h
Diff comments   View file @ 44cfc3a
... ... @@ -247,6 +247,7 @@
247 247 };
248 248  
249 249 enum pmux_func {
  250 + PMUX_FUNC_DEFAULT,
250 251 PMUX_FUNC_BLINK,
251 252 PMUX_FUNC_CCLA,
252 253 PMUX_FUNC_CEC,
arch/arm/include/asm/arch-tegra20/pinmux.h
Diff comments   View file @ 44cfc3a
... ... @@ -166,6 +166,7 @@
166 166 * purely a convenience. The translation is done through a table search.
167 167 */
168 168 enum pmux_func {
  169 + PMUX_FUNC_DEFAULT,
169 170 PMUX_FUNC_AHB_CLK,
170 171 PMUX_FUNC_APB_CLK,
171 172 PMUX_FUNC_AUDIO_SYNC,
arch/arm/include/asm/arch-tegra30/pinmux.h
Diff comments   View file @ 44cfc3a
... ... @@ -306,6 +306,7 @@
306 306 };
307 307  
308 308 enum pmux_func {
  309 + PMUX_FUNC_DEFAULT,
309 310 PMUX_FUNC_BLINK,
310 311 PMUX_FUNC_CEC,
311 312 PMUX_FUNC_CLK_12M_OUT,
board/nvidia/jetson-tk1/jetson-tk1.c
Diff comments   View file @ 44cfc3a
... ... @@ -6,6 +6,7 @@
6 6 */
7 7  
8 8 #include <common.h>
  9 +#include <asm/arch/gpio.h>
9 10 #include <asm/arch/pinmux.h>
10 11 #include "pinmux-config-jetson-tk1.h"
11 12  
... ... @@ -15,6 +16,11 @@
15 16 */
16 17 void pinmux_init(void)
17 18 {
  19 + pinmux_set_tristate_input_clamping();
  20 +
  21 + gpio_config_table(jetson_tk1_gpio_inits,
  22 + ARRAY_SIZE(jetson_tk1_gpio_inits));
  23 +
18 24 pinmux_config_pingrp_table(jetson_tk1_pingrps,
19 25 ARRAY_SIZE(jetson_tk1_pingrps));
20 26  
board/nvidia/jetson-tk1/pinmux-config-jetson-tk1.h
Diff comments   View file @ 44cfc3a
... ... @@ -7,6 +7,98 @@
7 7 #ifndef _PINMUX_CONFIG_JETSON_TK1_H_
8 8 #define _PINMUX_CONFIG_JETSON_TK1_H_
9 9  
  10 +#define GPIO_INIT(_gpio, _init) \
  11 + { \
  12 + .gpio = GPIO_P##_gpio, \
  13 + .init = TEGRA_GPIO_INIT_##_init, \
  14 + }
  15 +
  16 +static const struct tegra_gpio_config jetson_tk1_gpio_inits[] = {
  17 + /* gpio, init_val */
  18 + GPIO_INIT(C7, IN),
  19 + GPIO_INIT(G0, OUT0),
  20 + GPIO_INIT(G1, OUT0),
  21 + GPIO_INIT(G2, IN),
  22 + GPIO_INIT(G3, IN),
  23 + GPIO_INIT(H2, OUT0),
  24 + GPIO_INIT(H3, OUT0),
  25 + GPIO_INIT(H4, IN),
  26 + GPIO_INIT(H5, OUT0),
  27 + GPIO_INIT(H6, IN),
  28 + GPIO_INIT(H7, OUT0),
  29 + GPIO_INIT(I0, OUT0),
  30 + GPIO_INIT(I2, OUT0),
  31 + GPIO_INIT(I4, OUT0),
  32 + GPIO_INIT(I5, IN),
  33 + GPIO_INIT(I6, IN),
  34 + GPIO_INIT(J0, IN),
  35 + GPIO_INIT(J2, IN),
  36 + GPIO_INIT(K1, OUT0),
  37 + GPIO_INIT(K2, IN),
  38 + GPIO_INIT(K3, IN),
  39 + GPIO_INIT(K4, OUT0),
  40 + GPIO_INIT(K5, OUT0),
  41 + GPIO_INIT(K6, OUT0),
  42 + GPIO_INIT(N7, IN),
  43 + GPIO_INIT(O0, IN),
  44 + GPIO_INIT(O1, IN),
  45 + GPIO_INIT(O2, IN),
  46 + GPIO_INIT(O3, IN),
  47 + GPIO_INIT(O4, IN),
  48 + GPIO_INIT(O5, IN),
  49 + GPIO_INIT(O6, OUT0),
  50 + GPIO_INIT(O7, IN),
  51 + GPIO_INIT(P0, OUT0),
  52 + GPIO_INIT(P1, OUT0),
  53 + GPIO_INIT(P2, OUT0),
  54 + GPIO_INIT(Q0, IN),
  55 + GPIO_INIT(Q1, IN),
  56 + GPIO_INIT(Q2, IN),
  57 + GPIO_INIT(Q5, IN),
  58 + GPIO_INIT(Q6, IN),
  59 + GPIO_INIT(Q7, IN),
  60 + GPIO_INIT(R0, OUT0),
  61 + GPIO_INIT(R1, OUT0),
  62 + GPIO_INIT(R2, OUT0),
  63 + GPIO_INIT(R4, IN),
  64 + GPIO_INIT(R5, OUT0),
  65 + GPIO_INIT(R7, IN),
  66 + GPIO_INIT(S0, IN),
  67 + GPIO_INIT(S3, OUT0),
  68 + GPIO_INIT(S4, OUT0),
  69 + GPIO_INIT(S5, IN),
  70 + GPIO_INIT(S6, OUT0),
  71 + GPIO_INIT(T0, OUT0),
  72 + GPIO_INIT(T1, OUT0),
  73 + GPIO_INIT(U0, OUT0),
  74 + GPIO_INIT(U1, IN),
  75 + GPIO_INIT(U2, IN),
  76 + GPIO_INIT(U3, OUT0),
  77 + GPIO_INIT(U4, OUT0),
  78 + GPIO_INIT(U5, IN),
  79 + GPIO_INIT(U6, IN),
  80 + GPIO_INIT(V0, IN),
  81 + GPIO_INIT(V1, IN),
  82 + GPIO_INIT(W2, IN),
  83 + GPIO_INIT(W3, IN),
  84 + GPIO_INIT(X1, OUT0),
  85 + GPIO_INIT(X3, IN),
  86 + GPIO_INIT(X4, OUT0),
  87 + GPIO_INIT(X5, IN),
  88 + GPIO_INIT(X6, IN),
  89 + GPIO_INIT(X7, OUT0),
  90 + GPIO_INIT(BB3, OUT0),
  91 + GPIO_INIT(BB5, OUT0),
  92 + GPIO_INIT(BB6, OUT0),
  93 + GPIO_INIT(BB7, OUT0),
  94 + GPIO_INIT(CC1, IN),
  95 + GPIO_INIT(CC2, IN),
  96 + GPIO_INIT(CC5, OUT0),
  97 + GPIO_INIT(EE1, OUT0),
  98 + GPIO_INIT(FF1, OUT0),
  99 + GPIO_INIT(FF2, IN),
  100 +};
  101 +
10 102 #define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \
11 103 { \
12 104 .pingrp = PMUX_PINGRP_##_pingrp, \
13 105  
14 106  
15 107  
16 108  
17 109  
... ... @@ -41,43 +133,43 @@
41 133 PINCFG(UART2_RXD_PC3, IRDA, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
42 134 PINCFG(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
43 135 PINCFG(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
44   - PINCFG(PC7, RSVD1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
45   - PINCFG(PG0, RSVD1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
46   - PINCFG(PG1, RSVD1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
47   - PINCFG(PG2, RSVD1, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
48   - PINCFG(PG3, RSVD1, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
  136 + PINCFG(PC7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  137 + PINCFG(PG0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  138 + PINCFG(PG1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  139 + PINCFG(PG2, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
  140 + PINCFG(PG3, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
49 141 PINCFG(PG4, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
50 142 PINCFG(PG5, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
51 143 PINCFG(PG6, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
52 144 PINCFG(PG7, SPI4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
53 145 PINCFG(PH0, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
54 146 PINCFG(PH1, PWM1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
55   - PINCFG(PH2, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
56   - PINCFG(PH3, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
57   - PINCFG(PH4, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
58   - PINCFG(PH5, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
59   - PINCFG(PH6, GMI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
60   - PINCFG(PH7, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
61   - PINCFG(PI0, RSVD1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  147 + PINCFG(PH2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  148 + PINCFG(PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  149 + PINCFG(PH4, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  150 + PINCFG(PH5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  151 + PINCFG(PH6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  152 + PINCFG(PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  153 + PINCFG(PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
62 154 PINCFG(PI1, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
63   - PINCFG(PI2, RSVD4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  155 + PINCFG(PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
64 156 PINCFG(PI3, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
65   - PINCFG(PI4, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
66   - PINCFG(PI5, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
67   - PINCFG(PI6, RSVD1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  157 + PINCFG(PI4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  158 + PINCFG(PI5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  159 + PINCFG(PI6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
68 160 PINCFG(PI7, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
69   - PINCFG(PJ0, RSVD1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
70   - PINCFG(PJ2, RSVD1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  161 + PINCFG(PJ0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  162 + PINCFG(PJ2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
71 163 PINCFG(UART2_CTS_N_PJ5, UARTB, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
72 164 PINCFG(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
73 165 PINCFG(PJ7, UARTD, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
74 166 PINCFG(PK0, SOC, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
75   - PINCFG(PK1, RSVD4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
76   - PINCFG(PK2, RSVD1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
77   - PINCFG(PK3, GMI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
78   - PINCFG(PK4, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
79   - PINCFG(SPDIF_OUT_PK5, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
80   - PINCFG(SPDIF_IN_PK6, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  167 + PINCFG(PK1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  168 + PINCFG(PK2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  169 + PINCFG(PK3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  170 + PINCFG(PK4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  171 + PINCFG(SPDIF_OUT_PK5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  172 + PINCFG(SPDIF_IN_PK6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
81 173 PINCFG(PK7, UARTD, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
82 174 PINCFG(DAP1_FS_PN0, I2S0, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
83 175 PINCFG(DAP1_DIN_PN1, I2S0, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
84 176  
85 177  
86 178  
87 179  
88 180  
89 181  
90 182  
91 183  
92 184  
93 185  
... ... @@ -85,79 +177,79 @@
85 177 PINCFG(DAP1_SCLK_PN3, I2S0, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
86 178 PINCFG(USB_VBUS_EN0_PN4, USB, UP, NORMAL, INPUT, ENABLE, DEFAULT),
87 179 PINCFG(USB_VBUS_EN1_PN5, USB, UP, NORMAL, INPUT, ENABLE, DEFAULT),
88   - PINCFG(HDMI_INT_PN7, RSVD1, DOWN, NORMAL, INPUT, DEFAULT, NORMAL),
89   - PINCFG(ULPI_DATA7_PO0, ULPI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
90   - PINCFG(ULPI_DATA0_PO1, ULPI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
91   - PINCFG(ULPI_DATA1_PO2, ULPI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
92   - PINCFG(ULPI_DATA2_PO3, ULPI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
93   - PINCFG(ULPI_DATA3_PO4, ULPI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
94   - PINCFG(ULPI_DATA4_PO5, ULPI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
95   - PINCFG(ULPI_DATA5_PO6, ULPI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
96   - PINCFG(ULPI_DATA6_PO7, ULPI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
97   - PINCFG(DAP3_FS_PP0, I2S2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
98   - PINCFG(DAP3_DIN_PP1, I2S2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
99   - PINCFG(DAP3_DOUT_PP2, RSVD4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  180 + PINCFG(HDMI_INT_PN7, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, NORMAL),
  181 + PINCFG(ULPI_DATA7_PO0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  182 + PINCFG(ULPI_DATA0_PO1, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  183 + PINCFG(ULPI_DATA1_PO2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  184 + PINCFG(ULPI_DATA2_PO3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  185 + PINCFG(ULPI_DATA3_PO4, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  186 + PINCFG(ULPI_DATA4_PO5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  187 + PINCFG(ULPI_DATA5_PO6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  188 + PINCFG(ULPI_DATA6_PO7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  189 + PINCFG(DAP3_FS_PP0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  190 + PINCFG(DAP3_DIN_PP1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  191 + PINCFG(DAP3_DOUT_PP2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
100 192 PINCFG(DAP3_SCLK_PP3, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
101 193 PINCFG(DAP4_FS_PP4, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
102 194 PINCFG(DAP4_DIN_PP5, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
103 195 PINCFG(DAP4_DOUT_PP6, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
104 196 PINCFG(DAP4_SCLK_PP7, I2S3, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
105   - PINCFG(KB_COL0_PQ0, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
106   - PINCFG(KB_COL1_PQ1, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
107   - PINCFG(KB_COL2_PQ2, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  197 + PINCFG(KB_COL0_PQ0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  198 + PINCFG(KB_COL1_PQ1, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  199 + PINCFG(KB_COL2_PQ2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
108 200 PINCFG(KB_COL3_PQ3, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
109 201 PINCFG(KB_COL4_PQ4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
110   - PINCFG(KB_COL5_PQ5, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
111   - PINCFG(KB_COL6_PQ6, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
112   - PINCFG(KB_COL7_PQ7, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
113   - PINCFG(KB_ROW0_PR0, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
114   - PINCFG(KB_ROW1_PR1, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
115   - PINCFG(KB_ROW2_PR2, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  202 + PINCFG(KB_COL5_PQ5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  203 + PINCFG(KB_COL6_PQ6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  204 + PINCFG(KB_COL7_PQ7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  205 + PINCFG(KB_ROW0_PR0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  206 + PINCFG(KB_ROW1_PR1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  207 + PINCFG(KB_ROW2_PR2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
116 208 PINCFG(KB_ROW3_PR3, SYS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
117   - PINCFG(KB_ROW4_PR4, RSVD3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
118   - PINCFG(KB_ROW5_PR5, RSVD3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  209 + PINCFG(KB_ROW4_PR4, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  210 + PINCFG(KB_ROW5_PR5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
119 211 PINCFG(KB_ROW6_PR6, DISPLAYA_ALT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
120   - PINCFG(KB_ROW7_PR7, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
121   - PINCFG(KB_ROW8_PS0, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  212 + PINCFG(KB_ROW7_PR7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  213 + PINCFG(KB_ROW8_PS0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
122 214 PINCFG(KB_ROW9_PS1, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
123 215 PINCFG(KB_ROW10_PS2, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
124   - PINCFG(KB_ROW11_PS3, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
125   - PINCFG(KB_ROW12_PS4, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
126   - PINCFG(KB_ROW13_PS5, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
127   - PINCFG(KB_ROW14_PS6, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  216 + PINCFG(KB_ROW11_PS3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  217 + PINCFG(KB_ROW12_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  218 + PINCFG(KB_ROW13_PS5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  219 + PINCFG(KB_ROW14_PS6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
128 220 PINCFG(KB_ROW15_PS7, SOC, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
129   - PINCFG(KB_ROW16_PT0, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
130   - PINCFG(KB_ROW17_PT1, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  221 + PINCFG(KB_ROW16_PT0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  222 + PINCFG(KB_ROW17_PT1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
131 223 PINCFG(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
132 224 PINCFG(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
133 225 PINCFG(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
134   - PINCFG(PU0, RSVD4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
135   - PINCFG(PU1, RSVD1, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
136   - PINCFG(PU2, RSVD1, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
137   - PINCFG(PU3, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
138   - PINCFG(PU4, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
139   - PINCFG(PU5, GMI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
140   - PINCFG(PU6, RSVD3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
141   - PINCFG(PV0, RSVD1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
142   - PINCFG(PV1, RSVD1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  226 + PINCFG(PU0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  227 + PINCFG(PU1, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
  228 + PINCFG(PU2, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
  229 + PINCFG(PU3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  230 + PINCFG(PU4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  231 + PINCFG(PU5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  232 + PINCFG(PU6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  233 + PINCFG(PV0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  234 + PINCFG(PV1, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
143 235 PINCFG(SDMMC3_CD_N_PV2, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
144 236 PINCFG(SDMMC1_WP_N_PV3, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
145 237 PINCFG(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
146 238 PINCFG(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
147   - PINCFG(GPIO_W2_AUD_PW2, RSVD2, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
148   - PINCFG(GPIO_W3_AUD_PW3, SPI6, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  239 + PINCFG(GPIO_W2_AUD_PW2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  240 + PINCFG(GPIO_W3_AUD_PW3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
149 241 PINCFG(DAP_MCLK1_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
150 242 PINCFG(CLK2_OUT_PW5, EXTPERIPH2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
151 243 PINCFG(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
152 244 PINCFG(UART3_RXD_PW7, UARTC, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
153 245 PINCFG(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
154   - PINCFG(GPIO_X1_AUD_PX1, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  246 + PINCFG(GPIO_X1_AUD_PX1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
155 247 PINCFG(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
156   - PINCFG(GPIO_X3_AUD_PX3, RSVD4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
157   - PINCFG(GPIO_X4_AUD_PX4, GMI, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
158   - PINCFG(GPIO_X5_AUD_PX5, RSVD4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
159   - PINCFG(GPIO_X6_AUD_PX6, GMI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
160   - PINCFG(GPIO_X7_AUD_PX7, RSVD1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  248 + PINCFG(GPIO_X3_AUD_PX3, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  249 + PINCFG(GPIO_X4_AUD_PX4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  250 + PINCFG(GPIO_X5_AUD_PX5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  251 + PINCFG(GPIO_X6_AUD_PX6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  252 + PINCFG(GPIO_X7_AUD_PX7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
161 253 PINCFG(ULPI_CLK_PY0, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
162 254 PINCFG(ULPI_DIR_PY1, SPI1, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
163 255 PINCFG(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
164 256  
165 257  
166 258  
167 259  
168 260  
... ... @@ -181,25 +273,25 @@
181 273 PINCFG(PBB0, VIMCLK2_ALT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
182 274 PINCFG(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
183 275 PINCFG(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
184   - PINCFG(PBB3, VGP3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  276 + PINCFG(PBB3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
185 277 PINCFG(PBB4, VGP4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
186   - PINCFG(PBB5, RSVD3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
187   - PINCFG(PBB6, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
188   - PINCFG(PBB7, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  278 + PINCFG(PBB5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  279 + PINCFG(PBB6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  280 + PINCFG(PBB7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
189 281 PINCFG(CAM_MCLK_PCC0, VI_ALT3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
190   - PINCFG(PCC1, RSVD2, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
191   - PINCFG(PCC2, RSVD2, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
  282 + PINCFG(PCC1, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
  283 + PINCFG(PCC2, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, DEFAULT),
192 284 PINCFG(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
193   - PINCFG(CLK2_REQ_PCC5, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  285 + PINCFG(CLK2_REQ_PCC5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
194 286 PINCFG(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
195   - PINCFG(CLK3_REQ_PEE1, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  287 + PINCFG(CLK3_REQ_PEE1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
196 288 PINCFG(DAP_MCLK1_REQ_PEE2, SATA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
197 289 PINCFG(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
198 290 PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
199 291 PINCFG(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
200 292 PINCFG(DP_HPD_PFF0, DP, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
201   - PINCFG(USB_VBUS_EN2_PFF1, RSVD2, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
202   - PINCFG(PFF2, RSVD2, UP, NORMAL, INPUT, DISABLE, DEFAULT),
  293 + PINCFG(USB_VBUS_EN2_PFF1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
  294 + PINCFG(PFF2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
203 295 PINCFG(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
204 296 PINCFG(CPU_PWR_REQ, RSVD2, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
205 297 PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
board/nvidia/venice2/pinmux-config-venice2.h
Diff comments   View file @ 44cfc3a
1 1 /*
2   - * (C) Copyright 2013
3   - * NVIDIA Corporation <www.nvidia.com>
  2 + * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
4 3 *
5   - * SPDX-License-Identifier: GPL-2.0+
  4 + * SPDX-License-Identifier: GPL-2.0+
6 5 */
7 6  
8 7 #ifndef _PINMUX_CONFIG_VENICE2_H_
9 8 #define _PINMUX_CONFIG_VENICE2_H_
10 9  
11   -#define DEFAULT_PINMUX(_pingrp, _mux, _pull, _tri, _io) \
12   - { \
13   - .pingrp = PMUX_PINGRP_##_pingrp, \
14   - .func = PMUX_FUNC_##_mux, \
15   - .pull = PMUX_PULL_##_pull, \
16   - .tristate = PMUX_TRI_##_tri, \
17   - .io = PMUX_PIN_##_io, \
18   - .lock = PMUX_PIN_LOCK_DEFAULT, \
19   - .od = PMUX_PIN_OD_DEFAULT, \
20   - .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
  10 +#define GPIO_INIT(_gpio, _init) \
  11 + { \
  12 + .gpio = GPIO_P##_gpio, \
  13 + .init = TEGRA_GPIO_INIT_##_init, \
21 14 }
22 15  
23   -#define I2C_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
24   - { \
25   - .pingrp = PMUX_PINGRP_##_pingrp, \
26   - .func = PMUX_FUNC_##_mux, \
27   - .pull = PMUX_PULL_##_pull, \
28   - .tristate = PMUX_TRI_##_tri, \
29   - .io = PMUX_PIN_##_io, \
30   - .lock = PMUX_PIN_LOCK_##_lock, \
31   - .od = PMUX_PIN_OD_##_od, \
32   - .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
33   - }
  16 +static const struct tegra_gpio_config venice2_gpio_inits[] = {
  17 + /* gpio, init_val */
  18 + GPIO_INIT(A0, IN),
  19 + GPIO_INIT(C7, IN),
  20 + GPIO_INIT(G0, IN),
  21 + GPIO_INIT(G1, IN),
  22 + GPIO_INIT(G2, IN),
  23 + GPIO_INIT(G3, IN),
  24 + GPIO_INIT(H2, IN),
  25 + GPIO_INIT(H4, IN),
  26 + GPIO_INIT(H5, OUT0),
  27 + GPIO_INIT(H6, IN),
  28 + GPIO_INIT(H7, OUT1),
  29 + GPIO_INIT(I0, IN),
  30 + GPIO_INIT(I1, IN),
  31 + GPIO_INIT(I2, OUT0),
  32 + GPIO_INIT(I4, OUT0),
  33 + GPIO_INIT(I5, OUT1),
  34 + GPIO_INIT(I6, IN),
  35 + GPIO_INIT(J0, IN),
  36 + GPIO_INIT(J7, IN),
  37 + GPIO_INIT(K0, IN),
  38 + GPIO_INIT(K1, OUT0),
  39 + GPIO_INIT(K2, IN),
  40 + GPIO_INIT(K3, IN),
  41 + GPIO_INIT(K4, OUT0),
  42 + GPIO_INIT(K6, OUT0),
  43 + GPIO_INIT(K7, IN),
  44 + GPIO_INIT(N7, IN),
  45 + GPIO_INIT(O2, IN),
  46 + GPIO_INIT(O5, IN),
  47 + GPIO_INIT(O6, OUT0),
  48 + GPIO_INIT(O7, IN),
  49 + GPIO_INIT(P2, OUT0),
  50 + GPIO_INIT(Q0, IN),
  51 + GPIO_INIT(Q2, IN),
  52 + GPIO_INIT(Q3, IN),
  53 + GPIO_INIT(Q6, IN),
  54 + GPIO_INIT(Q7, IN),
  55 + GPIO_INIT(R0, OUT0),
  56 + GPIO_INIT(R1, IN),
  57 + GPIO_INIT(R4, IN),
  58 + GPIO_INIT(S0, IN),
  59 + GPIO_INIT(S3, OUT0),
  60 + GPIO_INIT(S4, OUT0),
  61 + GPIO_INIT(S7, IN),
  62 + GPIO_INIT(T1, IN),
  63 + GPIO_INIT(U4, IN),
  64 + GPIO_INIT(U5, IN),
  65 + GPIO_INIT(U6, IN),
  66 + GPIO_INIT(V0, IN),
  67 + GPIO_INIT(V1, IN),
  68 + GPIO_INIT(W3, IN),
  69 + GPIO_INIT(X1, IN),
  70 + GPIO_INIT(X3, IN),
  71 + GPIO_INIT(X4, IN),
  72 + GPIO_INIT(X7, OUT0),
  73 + GPIO_INIT(CC5, OUT0),
  74 +};
34 75  
35   -#define DDC_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _rcv_sel) \
  76 +#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _rcv_sel) \
36 77 { \
37 78 .pingrp = PMUX_PINGRP_##_pingrp, \
38 79 .func = PMUX_FUNC_##_mux, \
39 80 .pull = PMUX_PULL_##_pull, \
40 81 .tristate = PMUX_TRI_##_tri, \
41 82 .io = PMUX_PIN_##_io, \
42   - .lock = PMUX_PIN_LOCK_##_lock, \
  83 + .od = PMUX_PIN_OD_##_od, \
43 84 .rcv_sel = PMUX_PIN_RCV_SEL_##_rcv_sel, \
  85 + .lock = PMUX_PIN_LOCK_DEFAULT, \
44 86 .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
45 87 }
46 88  
47   -#define VI_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _ioreset) \
48   - { \
49   - .pingrp = PMUX_PINGRP_##_pingrp, \
50   - .func = PMUX_FUNC_##_mux, \
51   - .pull = PMUX_PULL_##_pull, \
52   - .tristate = PMUX_TRI_##_tri, \
53   - .io = PMUX_PIN_##_io, \
54   - .lock = PMUX_PIN_LOCK_##_lock, \
55   - .od = PMUX_PIN_OD_DEFAULT, \
56   - .ioreset = PMUX_PIN_IO_RESET_##_ioreset \
57   - }
  89 +static const struct pmux_pingrp_config venice2_pingrps[] = {
  90 + /* pingrp, mux, pull, tri, e_input, od, rcv_sel */
  91 + PINCFG(CLK_32K_OUT_PA0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  92 + PINCFG(UART3_CTS_N_PA1, UARTC, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  93 + PINCFG(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  94 + PINCFG(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  95 + PINCFG(DAP2_DIN_PA4, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  96 + PINCFG(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  97 + PINCFG(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  98 + PINCFG(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  99 + PINCFG(PB0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  100 + PINCFG(PB1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  101 + PINCFG(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  102 + PINCFG(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  103 + PINCFG(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  104 + PINCFG(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  105 + PINCFG(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  106 + PINCFG(UART2_TXD_PC2, IRDA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  107 + PINCFG(UART2_RXD_PC3, IRDA, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  108 + PINCFG(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
  109 + PINCFG(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
  110 + PINCFG(PC7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  111 + PINCFG(PG0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  112 + PINCFG(PG1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  113 + PINCFG(PG2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  114 + PINCFG(PG3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  115 + PINCFG(PG4, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  116 + PINCFG(PG5, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  117 + PINCFG(PG6, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  118 + PINCFG(PG7, SPI4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  119 + PINCFG(PH0, PWM0, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  120 + PINCFG(PH1, PWM1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  121 + PINCFG(PH2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  122 + PINCFG(PH3, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  123 + PINCFG(PH4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  124 + PINCFG(PH5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  125 + PINCFG(PH6, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  126 + PINCFG(PH7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  127 + PINCFG(PI0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  128 + PINCFG(PI1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  129 + PINCFG(PI2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  130 + PINCFG(PI3, SPI4, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  131 + PINCFG(PI4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  132 + PINCFG(PI5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  133 + PINCFG(PI6, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  134 + PINCFG(PI7, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  135 + PINCFG(PJ0, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  136 + PINCFG(PJ2, RSVD1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  137 + PINCFG(UART2_CTS_N_PJ5, UARTB, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  138 + PINCFG(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  139 + PINCFG(PJ7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  140 + PINCFG(PK0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  141 + PINCFG(PK1, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  142 + PINCFG(PK2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  143 + PINCFG(PK3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  144 + PINCFG(PK4, DEFAULT, UP, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  145 + PINCFG(SPDIF_OUT_PK5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  146 + PINCFG(SPDIF_IN_PK6, DEFAULT, DOWN, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  147 + PINCFG(PK7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  148 + PINCFG(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  149 + PINCFG(DAP1_DIN_PN1, I2S0, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  150 + PINCFG(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  151 + PINCFG(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  152 + PINCFG(USB_VBUS_EN0_PN4, USB, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
  153 + PINCFG(USB_VBUS_EN1_PN5, USB, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
  154 + PINCFG(HDMI_INT_PN7, DEFAULT, DOWN, NORMAL, INPUT, DEFAULT, NORMAL),
  155 + PINCFG(ULPI_DATA7_PO0, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  156 + PINCFG(ULPI_DATA0_PO1, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  157 + PINCFG(ULPI_DATA1_PO2, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  158 + PINCFG(ULPI_DATA2_PO3, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  159 + PINCFG(ULPI_DATA3_PO4, ULPI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  160 + PINCFG(ULPI_DATA4_PO5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  161 + PINCFG(ULPI_DATA5_PO6, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  162 + PINCFG(ULPI_DATA6_PO7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  163 + PINCFG(DAP3_FS_PP0, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  164 + PINCFG(DAP3_DIN_PP1, I2S2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  165 + PINCFG(DAP3_DOUT_PP2, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  166 + PINCFG(DAP3_SCLK_PP3, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  167 + PINCFG(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  168 + PINCFG(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  169 + PINCFG(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  170 + PINCFG(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  171 + PINCFG(KB_COL0_PQ0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  172 + PINCFG(KB_COL1_PQ1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  173 + PINCFG(KB_COL2_PQ2, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  174 + PINCFG(KB_COL3_PQ3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  175 + PINCFG(KB_COL4_PQ4, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  176 + PINCFG(KB_COL5_PQ5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  177 + PINCFG(KB_COL6_PQ6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  178 + PINCFG(KB_COL7_PQ7, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  179 + PINCFG(KB_ROW0_PR0, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  180 + PINCFG(KB_ROW1_PR1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  181 + PINCFG(KB_ROW2_PR2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  182 + PINCFG(KB_ROW3_PR3, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  183 + PINCFG(KB_ROW4_PR4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  184 + PINCFG(KB_ROW5_PR5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  185 + PINCFG(KB_ROW6_PR6, KBC, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  186 + PINCFG(KB_ROW7_PR7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  187 + PINCFG(KB_ROW8_PS0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  188 + PINCFG(KB_ROW9_PS1, UARTA, DOWN, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  189 + PINCFG(KB_ROW10_PS2, UARTA, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  190 + PINCFG(KB_ROW11_PS3, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  191 + PINCFG(KB_ROW12_PS4, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  192 + PINCFG(KB_ROW13_PS5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  193 + PINCFG(KB_ROW14_PS6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  194 + PINCFG(KB_ROW15_PS7, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  195 + PINCFG(KB_ROW16_PT0, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  196 + PINCFG(KB_ROW17_PT1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  197 + PINCFG(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
  198 + PINCFG(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
  199 + PINCFG(SDMMC4_CMD_PT7, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  200 + PINCFG(PU0, UARTA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  201 + PINCFG(PU1, UARTA, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  202 + PINCFG(PU2, UARTA, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  203 + PINCFG(PU3, UARTA, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  204 + PINCFG(PU4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  205 + PINCFG(PU5, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  206 + PINCFG(PU6, DEFAULT, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  207 + PINCFG(PV0, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  208 + PINCFG(PV1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  209 + PINCFG(SDMMC3_CD_N_PV2, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  210 + PINCFG(SDMMC1_WP_N_PV3, SDMMC1, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  211 + PINCFG(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
  212 + PINCFG(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, NORMAL),
  213 + PINCFG(GPIO_W2_AUD_PW2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  214 + PINCFG(GPIO_W3_AUD_PW3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  215 + PINCFG(DAP_MCLK1_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  216 + PINCFG(CLK2_OUT_PW5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  217 + PINCFG(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  218 + PINCFG(UART3_RXD_PW7, UARTC, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  219 + PINCFG(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  220 + PINCFG(GPIO_X1_AUD_PX1, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  221 + PINCFG(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  222 + PINCFG(GPIO_X3_AUD_PX3, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  223 + PINCFG(GPIO_X4_AUD_PX4, DEFAULT, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  224 + PINCFG(GPIO_X5_AUD_PX5, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  225 + PINCFG(GPIO_X6_AUD_PX6, GMI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  226 + PINCFG(GPIO_X7_AUD_PX7, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  227 + PINCFG(ULPI_CLK_PY0, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  228 + PINCFG(ULPI_DIR_PY1, SPI1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  229 + PINCFG(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  230 + PINCFG(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  231 + PINCFG(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  232 + PINCFG(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  233 + PINCFG(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  234 + PINCFG(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  235 + PINCFG(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  236 + PINCFG(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  237 + PINCFG(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
  238 + PINCFG(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
  239 + PINCFG(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  240 + PINCFG(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  241 + PINCFG(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  242 + PINCFG(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  243 + PINCFG(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  244 + PINCFG(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  245 + PINCFG(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  246 + PINCFG(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  247 + PINCFG(PBB0, VGP6, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  248 + PINCFG(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
  249 + PINCFG(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
  250 + PINCFG(PBB3, VGP3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  251 + PINCFG(PBB4, VGP4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  252 + PINCFG(PBB5, RSVD3, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  253 + PINCFG(PBB6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  254 + PINCFG(PBB7, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  255 + PINCFG(CAM_MCLK_PCC0, VI, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  256 + PINCFG(PCC1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  257 + PINCFG(PCC2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  258 + PINCFG(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  259 + PINCFG(CLK2_REQ_PCC5, DEFAULT, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  260 + PINCFG(PEX_L0_RST_N_PDD1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  261 + PINCFG(PEX_L0_CLKREQ_N_PDD2, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  262 + PINCFG(PEX_WAKE_N_PDD3, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  263 + PINCFG(PEX_L1_RST_N_PDD5, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  264 + PINCFG(PEX_L1_CLKREQ_N_PDD6, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  265 + PINCFG(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  266 + PINCFG(CLK3_REQ_PEE1, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  267 + PINCFG(DAP_MCLK1_REQ_PEE2, RSVD4, DOWN, TRISTATE, OUTPUT, DEFAULT, DEFAULT),
  268 + PINCFG(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, ENABLE, DEFAULT),
  269 + PINCFG(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  270 + PINCFG(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  271 + PINCFG(DP_HPD_PFF0, DP, UP, NORMAL, INPUT, DEFAULT, DEFAULT),
  272 + PINCFG(USB_VBUS_EN2_PFF1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  273 + PINCFG(PFF2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  274 + PINCFG(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  275 + PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  276 + PINCFG(PWR_INT_N, PMI, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  277 + PINCFG(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  278 + PINCFG(OWR, RSVD2, DOWN, TRISTATE, OUTPUT, DEFAULT, NORMAL),
  279 + PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DEFAULT, DEFAULT),
  280 + PINCFG(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT, DEFAULT, DEFAULT),
  281 +};
58 282  
59   -#define CEC_PINMUX(_pingrp, _mux, _pull, _tri, _io, _lock, _od) \
60   - { \
61   - .pingrp = PMUX_PINGRP_##_pingrp, \
62   - .func = PMUX_FUNC_##_mux, \
63   - .pull = PMUX_PULL_##_pull, \
64   - .tristate = PMUX_TRI_##_tri, \
65   - .io = PMUX_PIN_##_io, \
66   - .lock = PMUX_PIN_LOCK_##_lock, \
67   - .od = PMUX_PIN_OD_##_od, \
68   - .ioreset = PMUX_PIN_IO_RESET_DEFAULT, \
69   - }
70   -
71   -#define USB_PINMUX CEC_PINMUX
72   -
73   -#define DEFAULT_PADCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
  283 +#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
74 284 { \
75 285 .drvgrp = PMUX_DRVGRP_##_drvgrp, \
76 286 .slwf = _slwf, \
77 287  
... ... @@ -82,259 +292,8 @@
82 292 .hsm = PMUX_HSM_##_hsm, \
83 293 }
84 294  
85   -static struct pmux_pingrp_config tegra124_pinmux_common[] = {
86   - /* EXTPERIPH1 pinmux */
87   - DEFAULT_PINMUX(DAP_MCLK1_PW4, EXTPERIPH1, NORMAL, NORMAL, OUTPUT),
88   -
89   - /* I2S0 pinmux */
90   - DEFAULT_PINMUX(DAP1_DIN_PN1, I2S0, NORMAL, TRISTATE, INPUT),
91   - DEFAULT_PINMUX(DAP1_DOUT_PN2, I2S0, NORMAL, NORMAL, INPUT),
92   - DEFAULT_PINMUX(DAP1_FS_PN0, I2S0, NORMAL, NORMAL, INPUT),
93   - DEFAULT_PINMUX(DAP1_SCLK_PN3, I2S0, NORMAL, NORMAL, INPUT),
94   -
95   - /* I2S1 pinmux */
96   - DEFAULT_PINMUX(DAP2_DIN_PA4, I2S1, NORMAL, TRISTATE, INPUT),
97   - DEFAULT_PINMUX(DAP2_DOUT_PA5, I2S1, NORMAL, NORMAL, INPUT),
98   - DEFAULT_PINMUX(DAP2_FS_PA2, I2S1, NORMAL, NORMAL, INPUT),
99   - DEFAULT_PINMUX(DAP2_SCLK_PA3, I2S1, NORMAL, NORMAL, INPUT),
100   -
101   - /* I2S3 pinmux */
102   - DEFAULT_PINMUX(DAP4_DIN_PP5, I2S3, NORMAL, NORMAL, INPUT),
103   - DEFAULT_PINMUX(DAP4_DOUT_PP6, I2S3, NORMAL, NORMAL, INPUT),
104   - DEFAULT_PINMUX(DAP4_FS_PP4, I2S3, NORMAL, NORMAL, INPUT),
105   - DEFAULT_PINMUX(DAP4_SCLK_PP7, I2S3, NORMAL, NORMAL, INPUT),
106   -
107   - /* CLDVFS pinmux */
108   - DEFAULT_PINMUX(DVFS_PWM_PX0, CLDVFS, NORMAL, NORMAL, OUTPUT),
109   - DEFAULT_PINMUX(DVFS_CLK_PX2, CLDVFS, NORMAL, NORMAL, OUTPUT),
110   -
111   - /* ULPI pinmux */
112   - DEFAULT_PINMUX(ULPI_DATA0_PO1, ULPI, NORMAL, NORMAL, INPUT),
113   - DEFAULT_PINMUX(ULPI_DATA1_PO2, ULPI, NORMAL, NORMAL, INPUT),
114   - DEFAULT_PINMUX(ULPI_DATA2_PO3, ULPI, NORMAL, NORMAL, INPUT),
115   - DEFAULT_PINMUX(ULPI_DATA3_PO4, ULPI, NORMAL, NORMAL, INPUT),
116   - DEFAULT_PINMUX(ULPI_DATA4_PO5, ULPI, UP, NORMAL, INPUT),
117   - DEFAULT_PINMUX(ULPI_DATA5_PO6, ULPI, UP, NORMAL, INPUT),
118   - DEFAULT_PINMUX(ULPI_DATA6_PO7, ULPI, NORMAL, NORMAL, INPUT),
119   -
120   - /* EC KBC/SPI */
121   - DEFAULT_PINMUX(ULPI_CLK_PY0, SPI1, UP, NORMAL, INPUT),
122   - DEFAULT_PINMUX(ULPI_DIR_PY1, SPI1, UP, NORMAL, INPUT),
123   - DEFAULT_PINMUX(ULPI_NXT_PY2, SPI1, NORMAL, NORMAL, INPUT),
124   - DEFAULT_PINMUX(ULPI_STP_PY3, SPI1, NORMAL, NORMAL, INPUT),
125   -
126   - /* I2C3 (TPM) pinmux */
127   - I2C_PINMUX(CAM_I2C_SCL_PBB1, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
128   - I2C_PINMUX(CAM_I2C_SDA_PBB2, I2C3, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
129   -
130   - /* I2C2 pinmux */
131   - I2C_PINMUX(GEN2_I2C_SCL_PT5, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
132   - I2C_PINMUX(GEN2_I2C_SDA_PT6, I2C2, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
133   -
134   - /* UARTD pinmux (UART4 on Servo board, unused) */
135   - DEFAULT_PINMUX(PJ7, UARTD, NORMAL, NORMAL, OUTPUT),
136   - DEFAULT_PINMUX(PB0, UARTD, NORMAL, TRISTATE, INPUT),
137   - DEFAULT_PINMUX(PB1, UARTD, NORMAL, TRISTATE, INPUT),
138   - DEFAULT_PINMUX(PK7, UARTD, NORMAL, NORMAL, OUTPUT),
139   -
140   - /* SPI4 (Winbond 'boot ROM') */
141   - DEFAULT_PINMUX(PG5, SPI4, NORMAL, NORMAL, INPUT),
142   - DEFAULT_PINMUX(PG6, SPI4, UP, NORMAL, INPUT),
143   - DEFAULT_PINMUX(PG7, SPI4, UP, NORMAL, INPUT),
144   - DEFAULT_PINMUX(PI3, SPI4, NORMAL, NORMAL, INPUT),
145   -
146   - /* Touch IRQ */
147   - DEFAULT_PINMUX(GPIO_W3_AUD_PW3, RSVD1, NORMAL, NORMAL, INPUT),
148   -
149   - /* PWM1 pinmux */
150   - DEFAULT_PINMUX(PH1, PWM1, NORMAL, NORMAL, OUTPUT),
151   -
152   - /* SDMMC1 pinmux */
153   - DEFAULT_PINMUX(SDMMC1_CLK_PZ0, SDMMC1, NORMAL, NORMAL, INPUT),
154   - DEFAULT_PINMUX(SDMMC1_CMD_PZ1, SDMMC1, UP, NORMAL, INPUT),
155   - DEFAULT_PINMUX(SDMMC1_DAT0_PY7, SDMMC1, UP, NORMAL, INPUT),
156   - DEFAULT_PINMUX(SDMMC1_DAT1_PY6, SDMMC1, UP, NORMAL, INPUT),
157   - DEFAULT_PINMUX(SDMMC1_DAT2_PY5, SDMMC1, UP, NORMAL, INPUT),
158   - DEFAULT_PINMUX(SDMMC1_DAT3_PY4, SDMMC1, UP, NORMAL, INPUT),
159   -
160   - /* SDMMC3 pinmux */
161   - DEFAULT_PINMUX(SDMMC3_CLK_PA6, SDMMC3, NORMAL, NORMAL, INPUT),
162   - DEFAULT_PINMUX(SDMMC3_CMD_PA7, SDMMC3, UP, NORMAL, INPUT),
163   - DEFAULT_PINMUX(SDMMC3_DAT0_PB7, SDMMC3, UP, NORMAL, INPUT),
164   - DEFAULT_PINMUX(SDMMC3_DAT1_PB6, SDMMC3, UP, NORMAL, INPUT),
165   - DEFAULT_PINMUX(SDMMC3_DAT2_PB5, SDMMC3, UP, NORMAL, INPUT),
166   - DEFAULT_PINMUX(SDMMC3_DAT3_PB4, SDMMC3, UP, NORMAL, INPUT),
167   - DEFAULT_PINMUX(SDMMC3_CLK_LB_IN_PEE5, SDMMC3, UP, TRISTATE, INPUT),
168   - DEFAULT_PINMUX(SDMMC3_CLK_LB_OUT_PEE4, SDMMC3, DOWN, NORMAL, INPUT),
169   -
170   - /* SDMMC4 pinmux */
171   - DEFAULT_PINMUX(SDMMC4_CLK_PCC4, SDMMC4, NORMAL, NORMAL, INPUT),
172   - DEFAULT_PINMUX(SDMMC4_CMD_PT7, SDMMC4, UP, NORMAL, INPUT),
173   - DEFAULT_PINMUX(SDMMC4_DAT0_PAA0, SDMMC4, UP, NORMAL, INPUT),
174   - DEFAULT_PINMUX(SDMMC4_DAT1_PAA1, SDMMC4, UP, NORMAL, INPUT),
175   - DEFAULT_PINMUX(SDMMC4_DAT2_PAA2, SDMMC4, UP, NORMAL, INPUT),
176   - DEFAULT_PINMUX(SDMMC4_DAT3_PAA3, SDMMC4, UP, NORMAL, INPUT),
177   - DEFAULT_PINMUX(SDMMC4_DAT4_PAA4, SDMMC4, UP, NORMAL, INPUT),
178   - DEFAULT_PINMUX(SDMMC4_DAT5_PAA5, SDMMC4, UP, NORMAL, INPUT),
179   - DEFAULT_PINMUX(SDMMC4_DAT6_PAA6, SDMMC4, UP, NORMAL, INPUT),
180   - DEFAULT_PINMUX(SDMMC4_DAT7_PAA7, SDMMC4, UP, NORMAL, INPUT),
181   -
182   - /* BLINK pinmux */
183   - DEFAULT_PINMUX(CLK_32K_OUT_PA0, BLINK, NORMAL, NORMAL, OUTPUT),
184   -
185   - /* KBC pinmux */
186   - DEFAULT_PINMUX(KB_COL0_PQ0, KBC, UP, NORMAL, INPUT),
187   - DEFAULT_PINMUX(KB_COL1_PQ1, KBC, UP, NORMAL, INPUT),
188   - DEFAULT_PINMUX(KB_COL2_PQ2, KBC, UP, NORMAL, INPUT),
189   - DEFAULT_PINMUX(KB_ROW0_PR0, KBC, UP, NORMAL, INPUT),
190   - DEFAULT_PINMUX(KB_ROW1_PR1, KBC, UP, NORMAL, INPUT),
191   -
192   - /* Misc */
193   - DEFAULT_PINMUX(PV0, RSVD1, NORMAL, TRISTATE, OUTPUT),
194   - DEFAULT_PINMUX(KB_ROW7_PR7, RSVD1, UP, NORMAL, INPUT),
195   -
196   - /* UARTA pinmux (BR_UART_TXD/RXD on Servo board) */
197   - DEFAULT_PINMUX(KB_ROW9_PS1, UARTA, UP, NORMAL, OUTPUT),
198   - DEFAULT_PINMUX(KB_ROW10_PS2, UARTA, UP, TRISTATE, INPUT),
199   -
200   - /* I2CPWR pinmux (I2C5) */
201   - I2C_PINMUX(PWR_I2C_SCL_PZ6, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
202   - I2C_PINMUX(PWR_I2C_SDA_PZ7, I2CPWR, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
203   -
204   - /* RTCK pinmux */
205   - DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, INPUT),
206   -
207   - /* CLK pinmux */
208   - DEFAULT_PINMUX(CLK_32K_IN, CLK, NORMAL, TRISTATE, INPUT),
209   -
210   - /* PWRON pinmux */
211   - DEFAULT_PINMUX(CORE_PWR_REQ, PWRON, NORMAL, NORMAL, OUTPUT),
212   -
213   - /* CPU pinmux */
214   - DEFAULT_PINMUX(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT),
215   -
216   - /* PMI pinmux */
217   - DEFAULT_PINMUX(PWR_INT_N, PMI, NORMAL, TRISTATE, INPUT),
218   -
219   - /* RESET_OUT_N pinmux */
220   - DEFAULT_PINMUX(RESET_OUT_N, RESET_OUT_N, NORMAL, NORMAL, OUTPUT),
221   -
222   - /* EXTPERIPH3 pinmux */
223   - DEFAULT_PINMUX(CLK3_OUT_PEE0, EXTPERIPH3, NORMAL, NORMAL, OUTPUT),
224   -
225   - /* I2C1 pinmux */
226   - I2C_PINMUX(GEN1_I2C_SCL_PC4, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
227   - I2C_PINMUX(GEN1_I2C_SDA_PC5, I2C1, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
228   -
229   - /* UARTB, GPS */
230   - DEFAULT_PINMUX(UART2_CTS_N_PJ5, UARTB, NORMAL, TRISTATE, INPUT),
231   - DEFAULT_PINMUX(UART2_RTS_N_PJ6, UARTB, NORMAL, NORMAL, OUTPUT),
232   - DEFAULT_PINMUX(UART2_RXD_PC3, IRDA, NORMAL, TRISTATE, INPUT),
233   - DEFAULT_PINMUX(UART2_TXD_PC2, IRDA, NORMAL, NORMAL, OUTPUT),
234   -
235   - /* UARTC (WIFI/BT) */
236   - DEFAULT_PINMUX(UART3_CTS_N_PA1, UARTC, NORMAL, TRISTATE, INPUT),
237   - DEFAULT_PINMUX(UART3_RTS_N_PC0, UARTC, NORMAL, NORMAL, OUTPUT),
238   - DEFAULT_PINMUX(UART3_RXD_PW7, UARTC, NORMAL, TRISTATE, INPUT),
239   - DEFAULT_PINMUX(UART3_TXD_PW6, UARTC, NORMAL, NORMAL, OUTPUT),
240   -
241   - /* CEC pinmux */
242   - CEC_PINMUX(HDMI_CEC_PEE3, CEC, NORMAL, NORMAL, INPUT, DEFAULT, DISABLE),
243   -
244   - /* I2C4 (HDMI_DDC) pinmux */
245   - DDC_PINMUX(DDC_SCL_PV4, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
246   - DDC_PINMUX(DDC_SDA_PV5, I2C4, NORMAL, NORMAL, INPUT, DEFAULT, HIGH),
247   -
248   - /* USB pinmux */
249   - USB_PINMUX(USB_VBUS_EN0_PN4, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
250   - USB_PINMUX(USB_VBUS_EN1_PN5, USB, NORMAL, NORMAL, INPUT, DEFAULT, ENABLE),
251   -
252   - /* Unused, marked SNN_ on schematic, TRISTATE 'em */
253   - DEFAULT_PINMUX(PBB0, RSVD3, NORMAL, TRISTATE, INPUT),
254   - DEFAULT_PINMUX(PBB3, RSVD3, NORMAL, TRISTATE, INPUT),
255   - DEFAULT_PINMUX(PBB4, RSVD3, NORMAL, TRISTATE, INPUT),
256   - DEFAULT_PINMUX(PBB5, RSVD2, NORMAL, TRISTATE, INPUT),
257   - DEFAULT_PINMUX(PBB6, RSVD1, NORMAL, TRISTATE, INPUT),
258   - DEFAULT_PINMUX(PBB7, RSVD1, NORMAL, TRISTATE, INPUT),
259   - DEFAULT_PINMUX(PCC1, RSVD1, NORMAL, TRISTATE, INPUT),
260   - DEFAULT_PINMUX(PCC2, RSVD1, NORMAL, TRISTATE, INPUT),
261   - DEFAULT_PINMUX(PH3, GMI, NORMAL, TRISTATE, INPUT),
262   - DEFAULT_PINMUX(PI7, GMI, NORMAL, TRISTATE, INPUT),
263   - DEFAULT_PINMUX(PJ2, RSVD1, NORMAL, TRISTATE, INPUT),
264   - DEFAULT_PINMUX(GPIO_X5_AUD_PX5, RSVD3, NORMAL, TRISTATE, INPUT),
265   - DEFAULT_PINMUX(GPIO_X6_AUD_PX6, GMI, NORMAL, TRISTATE, INPUT),
266   - DEFAULT_PINMUX(GPIO_W2_AUD_PW2, RSVD1, NORMAL, TRISTATE, INPUT),
267   - DEFAULT_PINMUX(PFF2, RSVD1, NORMAL, TRISTATE, INPUT),
268   - DEFAULT_PINMUX(USB_VBUS_EN2_PFF1, RSVD1, NORMAL, TRISTATE, INPUT),
269   - DEFAULT_PINMUX(KB_COL5_PQ5, RSVD1, NORMAL, TRISTATE, INPUT),
270   - DEFAULT_PINMUX(KB_ROW2_PR2, RSVD1, NORMAL, TRISTATE, INPUT),
271   - DEFAULT_PINMUX(KB_ROW3_PR3, KBC, NORMAL, TRISTATE, INPUT),
272   - DEFAULT_PINMUX(KB_ROW5_PR5, RSVD2, NORMAL, TRISTATE, INPUT),
273   - DEFAULT_PINMUX(KB_ROW6_PR6, KBC, NORMAL, TRISTATE, INPUT),
274   - DEFAULT_PINMUX(KB_ROW13_PS5, RSVD1, NORMAL, TRISTATE, INPUT),
275   - DEFAULT_PINMUX(KB_ROW14_PS6, RSVD1, NORMAL, TRISTATE, INPUT),
276   - DEFAULT_PINMUX(KB_ROW16_PT0, RSVD1, NORMAL, TRISTATE, INPUT),
277   - DEFAULT_PINMUX(OWR, RSVD1, NORMAL, TRISTATE, INPUT),
278   - DEFAULT_PINMUX(ULPI_DATA7_PO0, ULPI, NORMAL, TRISTATE, INPUT),
279   - DEFAULT_PINMUX(DAP3_DIN_PP1, RSVD1, NORMAL, TRISTATE, INPUT),
280   - DEFAULT_PINMUX(DAP3_FS_PP0, RSVD1, NORMAL, TRISTATE, INPUT),
281   - DEFAULT_PINMUX(DAP3_SCLK_PP3, RSVD2, NORMAL, TRISTATE, INPUT),
282   - DEFAULT_PINMUX(CLK2_OUT_PW5, RSVD1, NORMAL, TRISTATE, INPUT),
283   - DEFAULT_PINMUX(SDMMC1_WP_N_PV3, RSVD1, NORMAL, TRISTATE, INPUT),
284   - DEFAULT_PINMUX(CAM_MCLK_PCC0, RSVD1, NORMAL, TRISTATE, INPUT),
285   - DEFAULT_PINMUX(CLK3_REQ_PEE1, RSVD1, NORMAL, TRISTATE, INPUT),
286   - DEFAULT_PINMUX(SPDIF_OUT_PK5, RSVD1, NORMAL, TRISTATE, INPUT),
  295 +static const struct pmux_drvgrp_config venice2_drvgrps[] = {
287 296 };
288 297  
289   -static struct pmux_pingrp_config unused_pins_lowpower[] = {
290   - DEFAULT_PINMUX(DAP_MCLK1_REQ_PEE2, RSVD3, DOWN, TRISTATE, OUTPUT),
291   -};
292   -
293   -/* Initially setting all used GPIO's to non-TRISTATE */
294   -static struct pmux_pingrp_config tegra124_pinmux_set_nontristate[] = {
295   - DEFAULT_PINMUX(GPIO_X4_AUD_PX4, RSVD1, DOWN, NORMAL, OUTPUT),
296   - DEFAULT_PINMUX(GPIO_X7_AUD_PX7, RSVD1, DOWN, NORMAL, OUTPUT),
297   - DEFAULT_PINMUX(GPIO_W2_AUD_PW2, RSVD1, UP, NORMAL, INPUT),
298   - DEFAULT_PINMUX(GPIO_X3_AUD_PX3, RSVD3, UP, NORMAL, INPUT),
299   -
300   - /* EN_VDD_BL */
301   - DEFAULT_PINMUX(DAP3_DOUT_PP2, I2S2, DOWN, NORMAL, OUTPUT),
302   -
303   - /* MODEM */
304   - DEFAULT_PINMUX(PV0, RSVD3, NORMAL, NORMAL, INPUT),
305   - DEFAULT_PINMUX(PV1, RSVD1, NORMAL, NORMAL, INPUT),
306   -
307   - /* BOOT_SEL0-3 */
308   - DEFAULT_PINMUX(PG0, GMI, NORMAL, NORMAL, INPUT),
309   - DEFAULT_PINMUX(PG1, GMI, NORMAL, NORMAL, INPUT),
310   - DEFAULT_PINMUX(PG2, GMI, NORMAL, NORMAL, INPUT),
311   - DEFAULT_PINMUX(PG3, GMI, NORMAL, NORMAL, INPUT),
312   -
313   - DEFAULT_PINMUX(CLK2_REQ_PCC5, RSVD3, NORMAL, NORMAL, OUTPUT),
314   -
315   - DEFAULT_PINMUX(KB_COL3_PQ3, KBC, UP, NORMAL, OUTPUT),
316   - DEFAULT_PINMUX(KB_COL4_PQ4, SDMMC3, UP, NORMAL, INPUT),
317   - DEFAULT_PINMUX(KB_COL6_PQ6, KBC, UP, NORMAL, OUTPUT),
318   - DEFAULT_PINMUX(KB_COL7_PQ7, KBC, UP, NORMAL, OUTPUT),
319   - DEFAULT_PINMUX(KB_ROW4_PR4, KBC, DOWN, NORMAL, INPUT),
320   - DEFAULT_PINMUX(KB_ROW8_PS0, KBC, UP, NORMAL, INPUT),
321   -
322   - DEFAULT_PINMUX(PU4, RSVD3, NORMAL, NORMAL, INPUT),
323   - DEFAULT_PINMUX(PU5, RSVD3, NORMAL, NORMAL, OUTPUT),
324   - DEFAULT_PINMUX(PU6, RSVD3, NORMAL, NORMAL, INPUT),
325   -
326   - DEFAULT_PINMUX(HDMI_INT_PN7, RSVD1, DOWN, NORMAL, INPUT),
327   - DEFAULT_PINMUX(SPDIF_IN_PK6, RSVD2, NORMAL, NORMAL, INPUT),
328   - DEFAULT_PINMUX(SDMMC3_CD_N_PV2, SDMMC3, UP, NORMAL, INPUT),
329   -
330   - /* TS_SHDN_L */
331   - DEFAULT_PINMUX(PK1, GMI, NORMAL, NORMAL, OUTPUT),
332   -};
333   -
334   -static struct pmux_drvgrp_config venice2_padctrl[] = {
335   - /* (_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
336   - DEFAULT_PADCFG(SDIO3, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR,
337   - SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, NONE, NONE),
338   -};
339 298 #endif /* PINMUX_CONFIG_VENICE2_H */
board/nvidia/venice2/venice2.c
Diff comments   View file @ 44cfc3a
... ... @@ -6,12 +6,9 @@
6 6 */
7 7  
8 8 #include <common.h>
9   -#include <asm-generic/gpio.h>
10 9 #include <asm/arch/gpio.h>
11   -#include <asm/arch/gp_padctrl.h>
12 10 #include <asm/arch/pinmux.h>
13 11 #include "pinmux-config-venice2.h"
14   -#include <i2c.h>
15 12  
16 13 /*
17 14 * Routine: pinmux_init
18 15  
19 16  
20 17  
... ... @@ -19,17 +16,15 @@
19 16 */
20 17 void pinmux_init(void)
21 18 {
22   - pinmux_config_pingrp_table(tegra124_pinmux_set_nontristate,
23   - ARRAY_SIZE(tegra124_pinmux_set_nontristate));
  19 + pinmux_set_tristate_input_clamping();
24 20  
25   - pinmux_config_pingrp_table(tegra124_pinmux_common,
26   - ARRAY_SIZE(tegra124_pinmux_common));
  21 + gpio_config_table(venice2_gpio_inits,
  22 + ARRAY_SIZE(venice2_gpio_inits));
27 23  
28   - pinmux_config_pingrp_table(unused_pins_lowpower,
29   - ARRAY_SIZE(unused_pins_lowpower));
  24 + pinmux_config_pingrp_table(venice2_pingrps,
  25 + ARRAY_SIZE(venice2_pingrps));
30 26  
31   - /* Initialize any non-default pad configs (APB_MISC_GP regs) */
32   - pinmux_config_drvgrp_table(venice2_padctrl,
33   - ARRAY_SIZE(venice2_padctrl));
  27 + pinmux_config_drvgrp_table(venice2_drvgrps,
  28 + ARRAY_SIZE(venice2_drvgrps));
34 29 }
drivers/gpio/tegra_gpio.c
Diff comments   View file @ 44cfc3a
... ... @@ -221,6 +221,26 @@
221 221 return 0;
222 222 }
223 223  
  224 +void gpio_config_table(const struct tegra_gpio_config *config, int len)
  225 +{
  226 + int i;
  227 +
  228 + for (i = 0; i < len; i++) {
  229 + switch (config[i].init) {
  230 + case TEGRA_GPIO_INIT_IN:
  231 + gpio_direction_input(config[i].gpio);
  232 + break;
  233 + case TEGRA_GPIO_INIT_OUT0:
  234 + gpio_direction_output(config[i].gpio, 0);
  235 + break;
  236 + case TEGRA_GPIO_INIT_OUT1:
  237 + gpio_direction_output(config[i].gpio, 1);
  238 + break;
  239 + }
  240 + set_config(config[i].gpio, 1);
  241 + }
  242 +}
  243 +
224 244 /*
225 245 * Display Tegra GPIO information
226 246 */
drivers/mmc/tegra_mmc.c
Diff comments   View file @ 44cfc3a
... ... @@ -18,7 +18,7 @@
18 18  
19 19 DECLARE_GLOBAL_DATA_PTR;
20 20  
21   -struct mmc_host mmc_host[MAX_HOSTS];
  21 +struct mmc_host mmc_host[CONFIG_SYS_MMC_MAX_DEVICE];
22 22  
23 23 #ifndef CONFIG_OF_CONTROL
24 24 #error "Please enable device tree support to use this driver"
25 25  
... ... @@ -669,13 +669,14 @@
669 669  
670 670 void tegra_mmc_init(void)
671 671 {
672   - int node_list[MAX_HOSTS], count;
  672 + int node_list[CONFIG_SYS_MMC_MAX_DEVICE], count;
673 673 const void *blob = gd->fdt_blob;
674 674 debug("%s entry\n", __func__);
675 675  
676 676 /* See if any Tegra124 MMC controllers are present */
677 677 count = fdtdec_find_aliases_for_id(blob, "sdhci",
678   - COMPAT_NVIDIA_TEGRA124_SDMMC, node_list, MAX_HOSTS);
  678 + COMPAT_NVIDIA_TEGRA124_SDMMC, node_list,
  679 + CONFIG_SYS_MMC_MAX_DEVICE);
679 680 debug("%s: count of Tegra124 sdhci nodes is %d\n", __func__, count);
680 681 if (process_nodes(blob, node_list, count)) {
681 682 printf("%s: Error processing T30 mmc node(s)!\n", __func__);
... ... @@ -684,7 +685,8 @@
684 685  
685 686 /* See if any Tegra30 MMC controllers are present */
686 687 count = fdtdec_find_aliases_for_id(blob, "sdhci",
687   - COMPAT_NVIDIA_TEGRA30_SDMMC, node_list, MAX_HOSTS);
  688 + COMPAT_NVIDIA_TEGRA30_SDMMC, node_list,
  689 + CONFIG_SYS_MMC_MAX_DEVICE);
688 690 debug("%s: count of T30 sdhci nodes is %d\n", __func__, count);
689 691 if (process_nodes(blob, node_list, count)) {
690 692 printf("%s: Error processing T30 mmc node(s)!\n", __func__);
... ... @@ -693,7 +695,8 @@
693 695  
694 696 /* Now look for any Tegra20 MMC controllers */
695 697 count = fdtdec_find_aliases_for_id(blob, "sdhci",
696   - COMPAT_NVIDIA_TEGRA20_SDMMC, node_list, MAX_HOSTS);
  698 + COMPAT_NVIDIA_TEGRA20_SDMMC, node_list,
  699 + CONFIG_SYS_MMC_MAX_DEVICE);
697 700 debug("%s: count of T20 sdhci nodes is %d\n", __func__, count);
698 701 if (process_nodes(blob, node_list, count)) {
699 702 printf("%s: Error processing T20 mmc node(s)!\n", __func__);
include/configs/beaver.h
Diff comments   View file @ 44cfc3a
... ... @@ -21,6 +21,9 @@
21 21  
22 22 #include "tegra30-common.h"
23 23  
  24 +/* VDD core PMIC */
  25 +#define CONFIG_TEGRA_VDD_CORE_TPS62366A_SET1
  26 +
24 27 /* Enable fdt support for Beaver. Flash the image in u-boot-dtb.bin */
25 28 #define CONFIG_DEFAULT_DEVICE_TREE tegra30-beaver
26 29 #define CONFIG_OF_CONTROL
include/configs/cardhu.h
Diff comments   View file @ 44cfc3a
... ... @@ -21,6 +21,9 @@
21 21  
22 22 #include "tegra30-common.h"
23 23  
  24 +/* VDD core PMIC */
  25 +#define CONFIG_TEGRA_VDD_CORE_TPS62361B_SET3
  26 +
24 27 /* Enable fdt support for Cardhu. Flash the image in u-boot-dtb.bin */
25 28 #define CONFIG_DEFAULT_DEVICE_TREE tegra30-cardhu
26 29 #define CONFIG_OF_CONTROL
include/configs/tegra-common.h
Diff comments   View file @ 44cfc3a
... ... @@ -48,6 +48,13 @@
48 48 #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
49 49  
50 50 /*
  51 + * Common HW configuration.
  52 + * If this varies between SoCs later, move to tegraNN-common.h
  53 + * Note: This is number of devices, not max device ID.
  54 + */
  55 +#define CONFIG_SYS_MMC_MAX_DEVICE 4
  56 +
  57 +/*
51 58 * select serial console configuration
52 59 */
53 60 #define CONFIG_CONS_INDEX 1