at91: Add esd gmbh OTC570 board support

This patch adds support for esd gmbh OTC570 board. The OTC570 is based on an Atmel AT91SAM9263 SoC. Signed-off-by: Daniel Gorsulowski <Daniel.Gorsulowski@esd.eu>

at91: Add esd gmbh OTC570 board support
This patch adds support for esd gmbh OTC570 board. The OTC570 is based on an Atmel AT91SAM9263 SoC. Signed-off-by: Daniel Gorsulowski <Daniel.Gorsulowski@esd.eu>
Daniel Gorsulowski · Tom Rix
1 parent 0b692dcb19
Showing 10 changed files with 712 additions and 0 deletions Side-by-side Diff
MAINTAINERS
MAKEALL
Makefile
board/esd/otc570/Makefile
board/esd/otc570/config.mk
board/esd/otc570/otc570.c
board/esd/otc570/partition.c
include/configs/otc570.h
tools/Makefile
tools/logos/esd.bmp
@@ -572,6 +572,7 @@
 Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
  
 	meesc		ARM926EJS (AT91SAM9263 SoC)
+	otc570		ARM926EJS (AT91SAM9263 SoC)
  
 Sedji Gaouaou<sedji.gaouaou@atmel.com>
 	at91sam9g10ek		ARM926EJS (AT91SAM9G10 SoC)
@@ -659,6 +659,7 @@
 	meesc			\
 	mp2usb			\
 	m501sk			\
+	otc570			\
 	pm9261			\
 	pm9263			\
 	SBC35_A9G20		\
@@ -2870,6 +2870,9 @@
 	fi;
 	@$(MKCONFIG) -a at91sam9m10g45ek arm arm926ejs at91sam9m10g45ek atmel at91
  
+otc570_config	:	unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm926ejs otc570 esd at91
+
 pm9263_config	:	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm926ejs pm9263 ronetix at91
  
+#
+# (C) Copyright 2003-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Stelian Pop <stelian.pop@leadtechdesign.com>
+# Lead Tech Design <www.leadtechdesign.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS-y				+= $(BOARD).o
+COBJS-$(CONFIG_HAS_DATAFLASH)	+= partition.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
+TEXT_BASE = 0x23f00000
+/*
+ * (C) Copyright 2010
+ * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
+ * esd electronic system design gmbh <www.esd.eu>
+ *
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/at91sam9263.h>
+#include <asm/arch/at91sam9_matrix.h>
+#include <asm/arch/at91sam9_smc.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/at91_pmc.h>
+#include <asm/arch/at91_rstc.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/io.h>
+#include <atmel_lcdc.h>
+#include <lcd.h>
+#include <netdev.h>
+#ifdef CONFIG_LCD_INFO
+#include <nand.h>
+#include <version.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscelaneous platform dependent initialisations
+ */
+
+static int hw_rev = -1;	/* hardware revision */
+
+int get_hw_rev(void)
+{
+	if (hw_rev >= 0)
+		return hw_rev;
+
+	hw_rev = at91_get_gpio_value(AT91_PIN_PB19);
+	hw_rev |= at91_get_gpio_value(AT91_PIN_PB20) << 1;
+	hw_rev |= at91_get_gpio_value(AT91_PIN_PB21) << 2;
+	hw_rev |= at91_get_gpio_value(AT91_PIN_PB22) << 3;
+
+	if (hw_rev == 15)
+		hw_rev = 0;
+
+	return hw_rev;
+}
+
+#ifdef CONFIG_CMD_NAND
+static void otc570_nand_hw_init(void)
+{
+	unsigned long csa;
+
+	/* Enable CS3 */
+	csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
+	at91_sys_write(AT91_MATRIX_EBI0CSA,
+		csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
+
+	/* Configure SMC CS3 for NAND/SmartMedia */
+	at91_sys_write(AT91_SMC_SETUP(3),
+		AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
+		AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
+	at91_sys_write(AT91_SMC_PULSE(3),
+		AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
+		AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
+	at91_sys_write(AT91_SMC_CYCLE(3),
+		AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
+	at91_sys_write(AT91_SMC_MODE(3),
+		AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
+		AT91_SMC_EXNWMODE_DISABLE |
+		AT91_SMC_DBW_8 |
+		AT91_SMC_TDF_(2));
+
+	/* Configure RDY/BSY */
+	at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+
+	/* Enable NandFlash */
+	at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+}
+#endif /* CONFIG_CMD_NAND */
+
+#ifdef CONFIG_MACB
+static void otc570_macb_hw_init(void)
+{
+	/* Enable clock */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
+	at91_macb_hw_init();
+}
+#endif
+
+/*
+ * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT
+ * controller debugging
+ * The ET1100 is located at physical address 0x70000000
+ * Its process memory is located at physical address 0x70001000
+ */
+static void otc570_ethercat_hw_init(void)
+{
+	/* Configure SMC EBI1_CS0 for EtherCAT */
+	at91_sys_write(AT91_SMC1_SETUP(0),
+		AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
+		AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
+	at91_sys_write(AT91_SMC1_PULSE(0),
+		AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(9) |
+		AT91_SMC_NRDPULSE_(5) | AT91_SMC_NCS_RDPULSE_(9));
+	at91_sys_write(AT91_SMC1_CYCLE(0),
+		AT91_SMC_NWECYCLE_(10) | AT91_SMC_NRDCYCLE_(6));
+	/*
+	 * Configure behavior at external wait signal, byte-select mode, 16 bit
+	 * data bus width, none data float wait states and TDF optimization
+	 */
+	at91_sys_write(AT91_SMC1_MODE(0),
+		AT91_SMC_READMODE | AT91_SMC_EXNWMODE_READY |
+		AT91_SMC_BAT_SELECT | AT91_SMC_DBW_16 | AT91_SMC_TDF_(0) |
+		AT91_SMC_TDFMODE);
+
+	/* Configure RDY/BSY */
+	at91_set_B_periph(AT91_PIN_PE20, 0);	/* EBI1_NWAIT */
+}
+
+#ifdef CONFIG_LCD
+/* Number of columns and rows, pixel clock in Hz and hsync/vsync polarity */
+vidinfo_t panel_info = {
+	.vl_col =		640,
+	.vl_row =		480,
+	.vl_clk =		25175000,
+	.vl_sync =		ATMEL_LCDC_INVLINE_INVERTED |
+				ATMEL_LCDC_INVFRAME_INVERTED,
+
+	.vl_bpix =		3,	/* Bits per pixel, 0 = 1bit, 3 = 8bit */
+	.vl_tft =		1,	/* 0 = passive, 1 = TFT */
+	.vl_vsync_len =		1,	/* Length of vertical sync in NOL */
+	.vl_upper_margin =	35,	/* Idle lines at the frame start */
+	.vl_lower_margin =	5,	/* Idle lines at the end of the frame */
+	.vl_hsync_len =		5,	/* Width of the LCDHSYNC pulse */
+	.vl_left_margin =	112,	/* Idle cycles at the line beginning */
+	.vl_right_margin =	1,	/* Idle cycles at the end of the line */
+
+	.mmio =			AT91SAM9263_LCDC_BASE,
+};
+
+void lcd_enable(void)
+{
+	at91_set_gpio_value(AT91_PIN_PA30, 0);	/* power up */
+}
+
+void lcd_disable(void)
+{
+	at91_set_gpio_value(AT91_PIN_PA30, 1);	/* power down */
+}
+
+static void otc570_lcd_hw_init(void)
+{
+	at91_set_A_periph(AT91_PIN_PC0, 0);	/* LCDVSYNC */
+	at91_set_A_periph(AT91_PIN_PC1, 0);	/* LCDHSYNC */
+	at91_set_A_periph(AT91_PIN_PC2, 0);	/* LCDDOTCK */
+	at91_set_A_periph(AT91_PIN_PC3, 0);	/* LCDDEN */
+	at91_set_B_periph(AT91_PIN_PB9, 0);	/* LCDCC */
+	at91_set_A_periph(AT91_PIN_PC6, 0);	/* LCDD2 */
+	at91_set_A_periph(AT91_PIN_PC7, 0);	/* LCDD3 */
+	at91_set_A_periph(AT91_PIN_PC8, 0);	/* LCDD4 */
+	at91_set_A_periph(AT91_PIN_PC9, 0);	/* LCDD5 */
+	at91_set_A_periph(AT91_PIN_PC10, 0);	/* LCDD6 */
+	at91_set_A_periph(AT91_PIN_PC11, 0);	/* LCDD7 */
+	at91_set_A_periph(AT91_PIN_PC14, 0);	/* LCDD10 */
+	at91_set_A_periph(AT91_PIN_PC15, 0);	/* LCDD11 */
+	at91_set_A_periph(AT91_PIN_PC16, 0);	/* LCDD12 */
+	at91_set_B_periph(AT91_PIN_PC12, 0);	/* LCDD13 */
+	at91_set_A_periph(AT91_PIN_PC18, 0);	/* LCDD14 */
+	at91_set_A_periph(AT91_PIN_PC19, 0);	/* LCDD15 */
+	at91_set_A_periph(AT91_PIN_PC22, 0);	/* LCDD18 */
+	at91_set_A_periph(AT91_PIN_PC23, 0);	/* LCDD19 */
+	at91_set_A_periph(AT91_PIN_PC24, 0);	/* LCDD20 */
+	at91_set_B_periph(AT91_PIN_PC17, 0);	/* LCDD21 */
+	at91_set_A_periph(AT91_PIN_PC26, 0);	/* LCDD22 */
+	at91_set_A_periph(AT91_PIN_PC27, 0);	/* LCDD23 */
+	at91_set_gpio_output(AT91_PIN_PA30, 1);	/* PCI */
+
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_LCDC);
+
+	gd->fb_base = CONFIG_OTC570_LCD_BASE;
+}
+
+#ifdef CONFIG_LCD_INFO
+void lcd_show_board_info(void)
+{
+	ulong dram_size, nand_size;
+	int i;
+	char temp[32];
+
+	dram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		dram_size += gd->bd->bi_dram[i].size;
+	nand_size = 0;
+	for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
+		nand_size += nand_info[i].size;
+
+	lcd_printf("\n%s\n", U_BOOT_VERSION);
+	lcd_printf("%s CPU at %s MHz\n", AT91_CPU_NAME,
+					strmhz(temp, get_cpu_clk_rate()));
+	lcd_printf("  %ld MB SDRAM, %ld MB NAND\n",
+		dram_size >> 20,
+		nand_size >> 20 );
+	lcd_printf("  Board            : esd ARM9 HMI Panel - OTC570\n");
+	lcd_printf("  Hardware-revision: 1.%d\n", get_hw_rev());
+	lcd_printf("  Mach-type        : %lu\n", gd->bd->bi_arch_number);
+}
+#endif /* CONFIG_LCD_INFO */
+#endif /* CONFIG_LCD */
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM;
+	gd->bd->bi_dram[0].size = get_ram_size((long *) PHYS_SDRAM, (1 << 27));
+	return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+	int rc = 0;
+#ifdef CONFIG_MACB
+	rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x00);
+#endif
+	return rc;
+}
+
+int checkboard(void)
+{
+	char str[32];
+
+	puts("Board: esd ARM9 HMI Panel - OTC570");
+	if (getenv_r("serial#", str, sizeof(str)) > 0) {
+		puts(", serial# ");
+		puts(str);
+	}
+	printf("\nHardware-revision: 1.%d\n", get_hw_rev());
+	printf("Mach-type: %lu\n", gd->bd->bi_arch_number);
+	return 0;
+}
+
+#ifdef CONFIG_SERIAL_TAG
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+	char *str;
+
+	char *serial = getenv("serial#");
+	if (serial) {
+		str = strchr(serial, '_');
+		if (str && (strlen(str) >= 4)) {
+			serialnr->high = (*(str + 1) << 8) | *(str + 2);
+			serialnr->low = simple_strtoul(str + 3, NULL, 16);
+		}
+	} else {
+		serialnr->high = 0;
+		serialnr->low = 0;
+	}
+}
+#endif
+
+#ifdef CONFIG_REVISION_TAG
+u32 get_board_rev(void)
+{
+	return hw_rev | 0x100;
+}
+#endif
+
+#ifdef CONFIG_MISC_INIT_R
+int misc_init_r(void)
+{
+	char str[64];
+
+	at91_set_gpio_output(AT91_PIN_PA29, 1);
+	at91_set_A_periph(AT91_PIN_PA26, 1);			/* TXD0 */
+	at91_set_A_periph(AT91_PIN_PA27, 0);			/* RXD0 */
+	at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US0);
+	/* Set USART_MODE = 1 (RS485) */
+	at91_sys_write((0xFFF8C004 - AT91_BASE_SYS), 1);
+
+	printf("USART0: ");
+
+	if (getenv_r("usart0", str, sizeof(str)) == -1) {
+		printf("No entry - assuming 1-wire\n");
+		/* CTS pin, works as mode select pin (0 = 1-wire; 1 = RS485) */
+		at91_set_gpio_output(AT91_PIN_PA29, 0);
+	} else {
+		if (strcmp(str, "1-wire") == 0) {
+			printf("%s\n", str);
+			at91_set_gpio_output(AT91_PIN_PA29, 0);
+		} else if (strcmp(str, "rs485") == 0) {
+			printf("%s\n", str);
+			at91_set_gpio_output(AT91_PIN_PA29, 1);
+		} else {
+			printf("Wrong entry - assuming 1-wire ");
+			printf("(valid values are '1-wire' or 'rs485')\n");
+			at91_set_gpio_output(AT91_PIN_PA29, 0);
+		}
+	}
+	printf("Display memory address: 0x%08lX\n", gd->fb_base);
+
+	return 0;
+}
+#endif /* CONFIG_MISC_INIT_R */
+
+int board_init(void)
+{
+	/* Peripheral Clock Enable Register */
+	at91_sys_write(AT91_PMC_PCER,	1 << AT91SAM9263_ID_PIOA |
+					1 << AT91SAM9263_ID_PIOB |
+					1 << AT91SAM9263_ID_PIOCDE |
+					1 << AT91SAM9263_ID_TWI |
+					1 << AT91SAM9263_ID_SPI0 |
+					1 << AT91SAM9263_ID_LCDC |
+					1 << AT91SAM9263_ID_UHP);
+
+	/* arch number of OTC570-Board */
+	gd->bd->bi_arch_number = MACH_TYPE_OTC570;
+
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+	at91_serial_hw_init();
+#ifdef CONFIG_CMD_NAND
+	otc570_nand_hw_init();
+#endif
+	otc570_ethercat_hw_init();
+#ifdef CONFIG_HAS_DATAFLASH
+	at91_spi0_hw_init(1 << 0);
+#endif
+#ifdef CONFIG_MACB
+	otc570_macb_hw_init();
+#endif
+#ifdef CONFIG_AT91_CAN
+	at91_can_hw_init();
+#endif
+#ifdef CONFIG_USB_OHCI_NEW
+	at91_uhp_hw_init();
+#endif
+#ifdef CONFIG_LCD
+	otc570_lcd_hw_init();
+#endif
+	return 0;
+}
+/*
+ * (C) Copyright 2008
+ * Ulf Samuelsson <ulf@atmel.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+#include <config.h>
+#include <asm/hardware.h>
+#include <dataflash.h>
+
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
+
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
+};
+
+/* define the area offsets */
+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
+	{0x00000000, 0x000041FF, FLAG_PROTECT_SET,   0, "Bootstrap"},
+	{0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
+	{0x00008400, 0x00041FFF, FLAG_PROTECT_SET,   0, "U-Boot"},
+};
+/*
+ * (C) Copyright 2010
+ * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
+ * esd electronic system design gmbh <www.esd.eu>
+ *
+ * (C) Copyright 2007-2008
+ * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Lead Tech Design <www.leadtechdesign.com>
+ *
+ * Configuation settings for the esd OTC570 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/* Common stuff */
+#define CONFIG_OTC570			1	/* Board is esd OTC570 */
+#define CONFIG_ARM926EJS		1	/* This is an ARM926EJS Core */
+#define CONFIG_AT91SAM9263		1	/* It's an AT91SAM9263 SoC */
+#define CONFIG_SYS_HZ			1000	/* decrementer freq */
+#define CONFIG_DISPLAY_BOARDINFO	1
+#define CONFIG_DISPLAY_CPUINFO		1	/* display cpu info and speed */
+#define CONFIG_PREBOOT				/* enable preboot variable */
+#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS	1
+#define CONFIG_INITRD_TAG		1
+#define CONFIG_SERIAL_TAG		1
+#define CONFIG_REVISION_TAG		1
+#undef CONFIG_USE_IRQ				/* don't need IRQ/FIQ stuff */
+
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SKIP_RELOCATE_UBOOT
+#define CONFIG_MISC_INIT_R		1	/* Call misc_init_r */
+
+#define CONFIG_ARCH_CPU_INIT
+
+/*
+ * Hardware drivers
+ */
+
+/* Console output */
+#define CONFIG_ATMEL_USART		1
+#undef CONFIG_USART0
+#undef CONFIG_USART1
+#undef CONFIG_USART2
+#define CONFIG_USART3			1	/* USART 3 is DBGU */
+
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_ZERO_BOOTDELAY_CHECK	1
+
+/* LCD */
+#define CONFIG_LCD			1
+#define LCD_BPP				LCD_COLOR8
+
+#undef CONFIG_SPLASH_SCREEN
+
+#ifndef CONFIG_SPLASH_SCREEN
+#define CONFIG_LCD_LOGO			1
+#define CONFIG_LCD_INFO			1
+#undef CONFIG_LCD_INFO_BELOW_LOGO
+#endif /* CONFIG_SPLASH_SCREEN */
+
+#undef LCD_TEST_PATTERN
+#define CONFIG_SYS_WHITE_ON_BLACK	1
+#define CONFIG_ATMEL_LCD		1
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	1
+#define CONFIG_OTC570_LCD_BASE		0x23E00000	/* LCD is in SDRAM */
+#define CONFIG_CMD_BMP			1
+
+/* RTC and I2C stuff */
+#define CONFIG_RTC_DS1338		1
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68
+#undef CONFIG_HARD_I2C
+#define CONFIG_SOFT_I2C			1
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+
+#ifdef CONFIG_SOFT_I2C
+#define CONFIG_I2C_CMD_TREE		1
+#define CONFIG_I2C_MULTI_BUS		1
+/* Enable peripheral clock and configure data and clock pins for pio */
+#define I2C_INIT { \
+	at91_sys_write(AT91_PMC_PCER,	1 << AT91SAM9263_ID_PIOB |	\
+					1 << AT91SAM9263_ID_PIOCDE);	\
+	at91_set_gpio_output(AT91_PIN_PB4, 0);				\
+	at91_set_gpio_output(AT91_PIN_PB5, 0);				\
+}
+/* Configure data pin as output */
+#define I2C_ACTIVE			at91_set_gpio_output(AT91_PIN_PB4, 0)
+/* Configure data pin as input */
+#define I2C_TRISTATE			at91_set_gpio_input(AT91_PIN_PB4, 0)
+/* Read data pin */
+#define I2C_READ			at91_get_gpio_value(AT91_PIN_PB4)
+/* Set data pin */
+#define I2C_SDA(bit)			at91_set_gpio_value(AT91_PIN_PB4, bit)
+/* Set clock pin */
+#define I2C_SCL(bit)			at91_set_gpio_value(AT91_PIN_PB5, bit)
+#define I2C_DELAY			udelay(2) /* 1/4 I2C clock duration */
+#endif /* CONFIG_SOFT_I2C */
+
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_ZERO_BOOTDELAY_CHECK	1
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE	1
+#define CONFIG_BOOTP_BOOTPATH		1
+#define CONFIG_BOOTP_GATEWAY		1
+#define CONFIG_BOOTP_HOSTNAME		1
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+#undef CONFIG_CMD_AUTOSCRIPT
+#undef CONFIG_CMD_FPGA
+#undef CONFIG_CMD_LOADS
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_CMD_PING			1
+#define CONFIG_CMD_DHCP			1
+#define CONFIG_CMD_NAND			1
+#define CONFIG_CMD_USB			1
+#define CONFIG_CMD_I2C			1
+#define CONFIG_CMD_DATE			1
+
+/* LED */
+#define CONFIG_AT91_LED			1
+
+/* SDRAM */
+#define CONFIG_NR_DRAM_BANKS			1
+#define PHYS_SDRAM				0x20000000
+
+/* DataFlash */
+#define CONFIG_ATMEL_DATAFLASH_SPI
+#define CONFIG_HAS_DATAFLASH			1
+#define CONFIG_SYS_SPI_WRITE_TOUT		(5 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_MAX_DATAFLASH_BANKS		1
+#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
+#define AT91_SPI_CLK				15000000
+#define DATAFLASH_TCSS				(0x1a << 16)
+#define DATAFLASH_TCHS				(0x1 << 24)
+
+/* NOR flash is not populated, disable it */
+#define CONFIG_SYS_NO_FLASH			1
+
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE		1
+#define CONFIG_SYS_NAND_BASE			0x40000000
+#define CONFIG_SYS_NAND_DBW_8			1
+/* our ALE is AD21 */
+#define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
+/* our CLE is AD22 */
+#define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
+#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PD15
+#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PA22
+#define CONFIG_SYS_64BIT_VSPRINTF		/* needed for nand_util.c */
+#endif
+
+/* Ethernet */
+#define CONFIG_MACB				1
+#define CONFIG_RMII				1
+#define CONFIG_NET_MULTI			1
+#define CONFIG_NET_RETRY_COUNT			20
+#undef CONFIG_RESET_PHY_R
+
+/* USB */
+#define CONFIG_USB_ATMEL
+#define CONFIG_USB_OHCI_NEW			1
+#define CONFIG_DOS_PARTITION			1
+#define CONFIG_SYS_USB_OHCI_CPU_INIT		1
+#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00a00000
+#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9263"
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
+#define CONFIG_USB_STORAGE			1
+#define CONFIG_CMD_FAT				1
+
+#define CONFIG_SYS_LOAD_ADDR			0x22000000 /* load address */
+
+#define CONFIG_SYS_MEMTEST_START		PHYS_SDRAM
+#define CONFIG_SYS_MEMTEST_END			0x23e00000
+
+#define CONFIG_SYS_USE_DATAFLASH		1
+#undef CONFIG_SYS_USE_NANDFLASH
+
+/* CAN */
+#define CONFIG_AT91_CAN				1
+
+/* hw-controller addresses */
+#define CONFIG_ET1100_BASE			0x70000000
+
+/* bootstrap + u-boot + env in dataflash on CS0 */
+#define CONFIG_ENV_IS_IN_DATAFLASH	1
+#define CONFIG_SYS_MONITOR_BASE		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \
+					0x8400)
+#define CONFIG_ENV_OFFSET		0x4200
+#define CONFIG_ENV_ADDR			(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + \
+					CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_SIZE			0x4200
+
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
+
+#define CONFIG_SYS_PROMPT		"=> "
+#define CONFIG_SYS_CBSIZE		256
+#define CONFIG_SYS_MAXARGS		16
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_LONGHELP		1
+#define CONFIG_CMDLINE_EDITING		1
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + \
+					128*1024, 0x1000)
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* 128 bytes for initial data */
+
+#define CONFIG_STACKSIZE		(32 * 1024)	/* regular stack */
+
+#ifdef CONFIG_USE_IRQ
+#error CONFIG_USE_IRQ not supported
+#endif
+
+#endif
@@ -112,6 +112,9 @@
 ifeq ($(VENDOR),atmel)
 LOGO_BMP= logos/atmel.bmp
 endif
+ifeq ($(VENDOR),esd)
+LOGO_BMP= logos/esd.bmp
+endif
 ifeq ($(VENDOR),ronetix)
 LOGO_BMP= logos/ronetix.bmp
 endif
...	...	@@ -572,6 +572,7 @@
572	572	Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
573	573
574	574	meesc ARM926EJS (AT91SAM9263 SoC)
	575	+ otc570 ARM926EJS (AT91SAM9263 SoC)
575	576
576	577	Sedji Gaouaou<sedji.gaouaou@atmel.com>
577	578	at91sam9g10ek ARM926EJS (AT91SAM9G10 SoC)
...	...	@@ -659,6 +659,7 @@
659	659	meesc \
660	660	mp2usb \
661	661	m501sk \
	662	+ otc570 \
662	663	pm9261 \
663	664	pm9263 \
664	665	SBC35_A9G20 \
...	...	@@ -2870,6 +2870,9 @@
2870	2870	fi;
2871	2871	@$(MKCONFIG) -a at91sam9m10g45ek arm arm926ejs at91sam9m10g45ek atmel at91
2872	2872
	2873	+otc570_config : unconfig
	2874	+ @$(MKCONFIG) $(@:_config=) arm arm926ejs otc570 esd at91
	2875	+
2873	2876	pm9263_config : unconfig
2874	2877	@$(MKCONFIG) $(@:_config=) arm arm926ejs pm9263 ronetix at91
2875	2878
	1	+#
	2	+# (C) Copyright 2003-2008
	3	+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	+#
	5	+# (C) Copyright 2008
	6	+# Stelian Pop <stelian.pop@leadtechdesign.com>
	7	+# Lead Tech Design <www.leadtechdesign.com>
	8	+#
	9	+# See file CREDITS for list of people who contributed to this
	10	+# project.
	11	+#
	12	+# This program is free software; you can redistribute it and/or
	13	+# modify it under the terms of the GNU General Public License as
	14	+# published by the Free Software Foundation; either version 2 of
	15	+# the License, or (at your option) any later version.
	16	+#
	17	+# This program is distributed in the hope that it will be useful,
	18	+# but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	+# GNU General Public License for more details.
	21	+#
	22	+# You should have received a copy of the GNU General Public License
	23	+# along with this program; if not, write to the Free Software
	24	+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	+# MA 02111-1307 USA
	26	+#
	27	+
	28	+include $(TOPDIR)/config.mk
	29	+
	30	+LIB = $(obj)lib$(BOARD).a
	31	+
	32	+COBJS-y += $(BOARD).o
	33	+COBJS-$(CONFIG_HAS_DATAFLASH) += partition.o
	34	+
	35	+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
	36	+OBJS := $(addprefix $(obj),$(COBJS-y))
	37	+SOBJS := $(addprefix $(obj),$(SOBJS))
	38	+
	39	+$(LIB): $(obj).depend $(OBJS) $(SOBJS)
	40	+ $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
	41	+
	42	+clean:
	43	+ rm -f $(SOBJS) $(OBJS)
	44	+
	45	+distclean: clean
	46	+ rm -f $(LIB) core *.bak $(obj).depend
	47	+
	48	+#########################################################################
	49	+
	50	+# defines $(obj).depend target
	51	+include $(SRCTREE)/rules.mk
	52	+
	53	+sinclude $(obj).depend
	54	+
	55	+#########################################################################
	1	+/*
	2	+ * (C) Copyright 2010
	3	+ * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
	4	+ * esd electronic system design gmbh <www.esd.eu>
	5	+ *
	6	+ * (C) Copyright 2007-2008
	7	+ * Stelian Pop <stelian.pop@leadtechdesign.com>
	8	+ * Lead Tech Design <www.leadtechdesign.com>
	9	+ *
	10	+ * See file CREDITS for list of people who contributed to this
	11	+ * project.
	12	+ *
	13	+ * This program is free software; you can redistribute it and/or
	14	+ * modify it under the terms of the GNU General Public License as
	15	+ * published by the Free Software Foundation; either version 2 of
	16	+ * the License, or (at your option) any later version.
	17	+ *
	18	+ * This program is distributed in the hope that it will be useful,
	19	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	20	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	21	+ * GNU General Public License for more details.
	22	+ *
	23	+ * You should have received a copy of the GNU General Public License
	24	+ * along with this program; if not, write to the Free Software
	25	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	26	+ * MA 02111-1307 USA
	27	+ */
	28	+
	29	+#include <common.h>
	30	+#include <asm/arch/at91sam9263.h>
	31	+#include <asm/arch/at91sam9_matrix.h>
	32	+#include <asm/arch/at91sam9_smc.h>
	33	+#include <asm/arch/at91_common.h>
	34	+#include <asm/arch/at91_pmc.h>
	35	+#include <asm/arch/at91_rstc.h>
	36	+#include <asm/arch/clk.h>
	37	+#include <asm/arch/gpio.h>
	38	+#include <asm/arch/hardware.h>
	39	+#include <asm/arch/io.h>
	40	+#include <atmel_lcdc.h>
	41	+#include <lcd.h>
	42	+#include <netdev.h>
	43	+#ifdef CONFIG_LCD_INFO
	44	+#include <nand.h>
	45	+#include <version.h>
	46	+#endif
	47	+
	48	+DECLARE_GLOBAL_DATA_PTR;
	49	+
	50	+/*
	51	+ * Miscelaneous platform dependent initialisations
	52	+ */
	53	+
	54	+static int hw_rev = -1; /* hardware revision */
	55	+
	56	+int get_hw_rev(void)
	57	+{
	58	+ if (hw_rev >= 0)
	59	+ return hw_rev;
	60	+
	61	+ hw_rev = at91_get_gpio_value(AT91_PIN_PB19);
	62	+ hw_rev \|= at91_get_gpio_value(AT91_PIN_PB20) << 1;
	63	+ hw_rev \|= at91_get_gpio_value(AT91_PIN_PB21) << 2;
	64	+ hw_rev \|= at91_get_gpio_value(AT91_PIN_PB22) << 3;
	65	+
	66	+ if (hw_rev == 15)
	67	+ hw_rev = 0;
	68	+
	69	+ return hw_rev;
	70	+}
	71	+
	72	+#ifdef CONFIG_CMD_NAND
	73	+static void otc570_nand_hw_init(void)
	74	+{
	75	+ unsigned long csa;
	76	+
	77	+ /* Enable CS3 */
	78	+ csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
	79	+ at91_sys_write(AT91_MATRIX_EBI0CSA,
	80	+ csa \| AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
	81	+
	82	+ /* Configure SMC CS3 for NAND/SmartMedia */
	83	+ at91_sys_write(AT91_SMC_SETUP(3),
	84	+ AT91_SMC_NWESETUP_(1) \| AT91_SMC_NCS_WRSETUP_(0) \|
	85	+ AT91_SMC_NRDSETUP_(1) \| AT91_SMC_NCS_RDSETUP_(0));
	86	+ at91_sys_write(AT91_SMC_PULSE(3),
	87	+ AT91_SMC_NWEPULSE_(3) \| AT91_SMC_NCS_WRPULSE_(3) \|
	88	+ AT91_SMC_NRDPULSE_(3) \| AT91_SMC_NCS_RDPULSE_(3));
	89	+ at91_sys_write(AT91_SMC_CYCLE(3),
	90	+ AT91_SMC_NWECYCLE_(5) \| AT91_SMC_NRDCYCLE_(5));
	91	+ at91_sys_write(AT91_SMC_MODE(3),
	92	+ AT91_SMC_READMODE \| AT91_SMC_WRITEMODE \|
	93	+ AT91_SMC_EXNWMODE_DISABLE \|
	94	+ AT91_SMC_DBW_8 \|
	95	+ AT91_SMC_TDF_(2));
	96	+
	97	+ /* Configure RDY/BSY */
	98	+ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
	99	+
	100	+ /* Enable NandFlash */
	101	+ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
	102	+}
	103	+#endif /* CONFIG_CMD_NAND */
	104	+
	105	+#ifdef CONFIG_MACB
	106	+static void otc570_macb_hw_init(void)
	107	+{
	108	+ /* Enable clock */
	109	+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
	110	+ at91_macb_hw_init();
	111	+}
	112	+#endif
	113	+
	114	+/*
	115	+ * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT
	116	+ * controller debugging
	117	+ * The ET1100 is located at physical address 0x70000000
	118	+ * Its process memory is located at physical address 0x70001000
	119	+ */
	120	+static void otc570_ethercat_hw_init(void)
	121	+{
	122	+ /* Configure SMC EBI1_CS0 for EtherCAT */
	123	+ at91_sys_write(AT91_SMC1_SETUP(0),
	124	+ AT91_SMC_NWESETUP_(0) \| AT91_SMC_NCS_WRSETUP_(0) \|
	125	+ AT91_SMC_NRDSETUP_(0) \| AT91_SMC_NCS_RDSETUP_(0));
	126	+ at91_sys_write(AT91_SMC1_PULSE(0),
	127	+ AT91_SMC_NWEPULSE_(4) \| AT91_SMC_NCS_WRPULSE_(9) \|
	128	+ AT91_SMC_NRDPULSE_(5) \| AT91_SMC_NCS_RDPULSE_(9));
	129	+ at91_sys_write(AT91_SMC1_CYCLE(0),
	130	+ AT91_SMC_NWECYCLE_(10) \| AT91_SMC_NRDCYCLE_(6));
	131	+ /*
	132	+ * Configure behavior at external wait signal, byte-select mode, 16 bit
	133	+ * data bus width, none data float wait states and TDF optimization
	134	+ */
	135	+ at91_sys_write(AT91_SMC1_MODE(0),
	136	+ AT91_SMC_READMODE \| AT91_SMC_EXNWMODE_READY \|
	137	+ AT91_SMC_BAT_SELECT \| AT91_SMC_DBW_16 \| AT91_SMC_TDF_(0) \|
	138	+ AT91_SMC_TDFMODE);
	139	+
	140	+ /* Configure RDY/BSY */
	141	+ at91_set_B_periph(AT91_PIN_PE20, 0); /* EBI1_NWAIT */
	142	+}
	143	+
	144	+#ifdef CONFIG_LCD
	145	+/* Number of columns and rows, pixel clock in Hz and hsync/vsync polarity */
	146	+vidinfo_t panel_info = {
	147	+ .vl_col = 640,
	148	+ .vl_row = 480,
	149	+ .vl_clk = 25175000,
	150	+ .vl_sync = ATMEL_LCDC_INVLINE_INVERTED \|
	151	+ ATMEL_LCDC_INVFRAME_INVERTED,
	152	+
	153	+ .vl_bpix = 3, /* Bits per pixel, 0 = 1bit, 3 = 8bit */
	154	+ .vl_tft = 1, /* 0 = passive, 1 = TFT */
	155	+ .vl_vsync_len = 1, /* Length of vertical sync in NOL */
	156	+ .vl_upper_margin = 35, /* Idle lines at the frame start */
	157	+ .vl_lower_margin = 5, /* Idle lines at the end of the frame */
	158	+ .vl_hsync_len = 5, /* Width of the LCDHSYNC pulse */
	159	+ .vl_left_margin = 112, /* Idle cycles at the line beginning */
	160	+ .vl_right_margin = 1, /* Idle cycles at the end of the line */
	161	+
	162	+ .mmio = AT91SAM9263_LCDC_BASE,
	163	+};
	164	+
	165	+void lcd_enable(void)
	166	+{
	167	+ at91_set_gpio_value(AT91_PIN_PA30, 0); /* power up */
	168	+}
	169	+
	170	+void lcd_disable(void)
	171	+{
	172	+ at91_set_gpio_value(AT91_PIN_PA30, 1); /* power down */
	173	+}
	174	+
	175	+static void otc570_lcd_hw_init(void)
	176	+{
	177	+ at91_set_A_periph(AT91_PIN_PC0, 0); /* LCDVSYNC */
	178	+ at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
	179	+ at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
	180	+ at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDDEN */
	181	+ at91_set_B_periph(AT91_PIN_PB9, 0); /* LCDCC */
	182	+ at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDD2 */
	183	+ at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDD3 */
	184	+ at91_set_A_periph(AT91_PIN_PC8, 0); /* LCDD4 */
	185	+ at91_set_A_periph(AT91_PIN_PC9, 0); /* LCDD5 */
	186	+ at91_set_A_periph(AT91_PIN_PC10, 0); /* LCDD6 */
	187	+ at91_set_A_periph(AT91_PIN_PC11, 0); /* LCDD7 */
	188	+ at91_set_A_periph(AT91_PIN_PC14, 0); /* LCDD10 */
	189	+ at91_set_A_periph(AT91_PIN_PC15, 0); /* LCDD11 */
	190	+ at91_set_A_periph(AT91_PIN_PC16, 0); /* LCDD12 */
	191	+ at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD13 */
	192	+ at91_set_A_periph(AT91_PIN_PC18, 0); /* LCDD14 */
	193	+ at91_set_A_periph(AT91_PIN_PC19, 0); /* LCDD15 */
	194	+ at91_set_A_periph(AT91_PIN_PC22, 0); /* LCDD18 */
	195	+ at91_set_A_periph(AT91_PIN_PC23, 0); /* LCDD19 */
	196	+ at91_set_A_periph(AT91_PIN_PC24, 0); /* LCDD20 */
	197	+ at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD21 */
	198	+ at91_set_A_periph(AT91_PIN_PC26, 0); /* LCDD22 */
	199	+ at91_set_A_periph(AT91_PIN_PC27, 0); /* LCDD23 */
	200	+ at91_set_gpio_output(AT91_PIN_PA30, 1); /* PCI */
	201	+
	202	+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_LCDC);
	203	+
	204	+ gd->fb_base = CONFIG_OTC570_LCD_BASE;
	205	+}
	206	+
	207	+#ifdef CONFIG_LCD_INFO
	208	+void lcd_show_board_info(void)
	209	+{
	210	+ ulong dram_size, nand_size;
	211	+ int i;
	212	+ char temp[32];
	213	+
	214	+ dram_size = 0;
	215	+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
	216	+ dram_size += gd->bd->bi_dram[i].size;
	217	+ nand_size = 0;
	218	+ for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
	219	+ nand_size += nand_info[i].size;
	220	+
	221	+ lcd_printf("\n%s\n", U_BOOT_VERSION);
	222	+ lcd_printf("%s CPU at %s MHz\n", AT91_CPU_NAME,
	223	+ strmhz(temp, get_cpu_clk_rate()));
	224	+ lcd_printf(" %ld MB SDRAM, %ld MB NAND\n",
	225	+ dram_size >> 20,
	226	+ nand_size >> 20 );
	227	+ lcd_printf(" Board : esd ARM9 HMI Panel - OTC570\n");
	228	+ lcd_printf(" Hardware-revision: 1.%d\n", get_hw_rev());
	229	+ lcd_printf(" Mach-type : %lu\n", gd->bd->bi_arch_number);
	230	+}
	231	+#endif /* CONFIG_LCD_INFO */
	232	+#endif /* CONFIG_LCD */
	233	+
	234	+int dram_init(void)
	235	+{
	236	+ gd->bd->bi_dram[0].start = PHYS_SDRAM;
	237	+ gd->bd->bi_dram[0].size = get_ram_size((long *) PHYS_SDRAM, (1 << 27));
	238	+ return 0;
	239	+}
	240	+
	241	+int board_eth_init(bd_t *bis)
	242	+{
	243	+ int rc = 0;
	244	+#ifdef CONFIG_MACB
	245	+ rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x00);
	246	+#endif
	247	+ return rc;
	248	+}
	249	+
	250	+int checkboard(void)
	251	+{
	252	+ char str[32];
	253	+
	254	+ puts("Board: esd ARM9 HMI Panel - OTC570");
	255	+ if (getenv_r("serial#", str, sizeof(str)) > 0) {
	256	+ puts(", serial# ");
	257	+ puts(str);
	258	+ }
	259	+ printf("\nHardware-revision: 1.%d\n", get_hw_rev());
	260	+ printf("Mach-type: %lu\n", gd->bd->bi_arch_number);
	261	+ return 0;
	262	+}
	263	+
	264	+#ifdef CONFIG_SERIAL_TAG
	265	+void get_board_serial(struct tag_serialnr *serialnr)
	266	+{
	267	+ char *str;
	268	+
	269	+ char *serial = getenv("serial#");
	270	+ if (serial) {
	271	+ str = strchr(serial, '_');
	272	+ if (str && (strlen(str) >= 4)) {
	273	+ serialnr->high = ((str + 1) << 8) \| (str + 2);
	274	+ serialnr->low = simple_strtoul(str + 3, NULL, 16);
	275	+ }
	276	+ } else {
	277	+ serialnr->high = 0;
	278	+ serialnr->low = 0;
	279	+ }
	280	+}
	281	+#endif
	282	+
	283	+#ifdef CONFIG_REVISION_TAG
	284	+u32 get_board_rev(void)
	285	+{
	286	+ return hw_rev \| 0x100;
	287	+}
	288	+#endif
	289	+
	290	+#ifdef CONFIG_MISC_INIT_R
	291	+int misc_init_r(void)
	292	+{
	293	+ char str[64];
	294	+
	295	+ at91_set_gpio_output(AT91_PIN_PA29, 1);
	296	+ at91_set_A_periph(AT91_PIN_PA26, 1); /* TXD0 */
	297	+ at91_set_A_periph(AT91_PIN_PA27, 0); /* RXD0 */
	298	+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US0);
	299	+ /* Set USART_MODE = 1 (RS485) */
	300	+ at91_sys_write((0xFFF8C004 - AT91_BASE_SYS), 1);
	301	+
	302	+ printf("USART0: ");
	303	+
	304	+ if (getenv_r("usart0", str, sizeof(str)) == -1) {
	305	+ printf("No entry - assuming 1-wire\n");
	306	+ /* CTS pin, works as mode select pin (0 = 1-wire; 1 = RS485) */
	307	+ at91_set_gpio_output(AT91_PIN_PA29, 0);
	308	+ } else {
	309	+ if (strcmp(str, "1-wire") == 0) {
	310	+ printf("%s\n", str);
	311	+ at91_set_gpio_output(AT91_PIN_PA29, 0);
	312	+ } else if (strcmp(str, "rs485") == 0) {
	313	+ printf("%s\n", str);
	314	+ at91_set_gpio_output(AT91_PIN_PA29, 1);
	315	+ } else {
	316	+ printf("Wrong entry - assuming 1-wire ");
	317	+ printf("(valid values are '1-wire' or 'rs485')\n");
	318	+ at91_set_gpio_output(AT91_PIN_PA29, 0);
	319	+ }
	320	+ }
	321	+ printf("Display memory address: 0x%08lX\n", gd->fb_base);
	322	+
	323	+ return 0;
	324	+}
	325	+#endif /* CONFIG_MISC_INIT_R */
	326	+
	327	+int board_init(void)
	328	+{
	329	+ /* Peripheral Clock Enable Register */
	330	+ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_PIOA \|
	331	+ 1 << AT91SAM9263_ID_PIOB \|
	332	+ 1 << AT91SAM9263_ID_PIOCDE \|
	333	+ 1 << AT91SAM9263_ID_TWI \|
	334	+ 1 << AT91SAM9263_ID_SPI0 \|
	335	+ 1 << AT91SAM9263_ID_LCDC \|
	336	+ 1 << AT91SAM9263_ID_UHP);
	337	+
	338	+ /* arch number of OTC570-Board */
	339	+ gd->bd->bi_arch_number = MACH_TYPE_OTC570;
	340	+
	341	+ /* adress of boot parameters */
	342	+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
	343	+
	344	+ at91_serial_hw_init();
	345	+#ifdef CONFIG_CMD_NAND
	346	+ otc570_nand_hw_init();
	347	+#endif
	348	+ otc570_ethercat_hw_init();
	349	+#ifdef CONFIG_HAS_DATAFLASH
	350	+ at91_spi0_hw_init(1 << 0);
	351	+#endif
	352	+#ifdef CONFIG_MACB
	353	+ otc570_macb_hw_init();
	354	+#endif
	355	+#ifdef CONFIG_AT91_CAN
	356	+ at91_can_hw_init();
	357	+#endif
	358	+#ifdef CONFIG_USB_OHCI_NEW
	359	+ at91_uhp_hw_init();
	360	+#endif
	361	+#ifdef CONFIG_LCD
	362	+ otc570_lcd_hw_init();
	363	+#endif
	364	+ return 0;
	365	+}
	1	+/*
	2	+ * (C) Copyright 2008
	3	+ * Ulf Samuelsson <ulf@atmel.com>
	4	+ *
	5	+ * This program is free software; you can redistribute it and/or
	6	+ * modify it under the terms of the GNU General Public License as
	7	+ * published by the Free Software Foundation; either version 2 of
	8	+ * the License, or (at your option) any later version.
	9	+ *
	10	+ * This program is distributed in the hope that it will be useful,
	11	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	+ * GNU General Public License for more details.
	14	+ *
	15	+ * You should have received a copy of the GNU General Public License
	16	+ * along with this program; if not, write to the Free Software
	17	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	18	+ * MA 02111-1307 USA
	19	+ *
	20	+ */
	21	+#include <common.h>
	22	+#include <config.h>
	23	+#include <asm/hardware.h>
	24	+#include <dataflash.h>
	25	+
	26	+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
	27	+
	28	+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
	29	+ {CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0}, /* Logical adress, CS */
	30	+};
	31	+
	32	+/* define the area offsets */
	33	+dataflash_protect_t area_list[NB_DATAFLASH_AREA] = {
	34	+ {0x00000000, 0x000041FF, FLAG_PROTECT_SET, 0, "Bootstrap"},
	35	+ {0x00004200, 0x000083FF, FLAG_PROTECT_CLEAR, 0, "Environment"},
	36	+ {0x00008400, 0x00041FFF, FLAG_PROTECT_SET, 0, "U-Boot"},
	37	+};
...	...	@@ -112,6 +112,9 @@
112	112	ifeq ($(VENDOR),atmel)
113	113	LOGO_BMP= logos/atmel.bmp
114	114	endif
	115	+ifeq ($(VENDOR),esd)
	116	+LOGO_BMP= logos/esd.bmp
	117	+endif
115	118	ifeq ($(VENDOR),ronetix)
116	119	LOGO_BMP= logos/ronetix.bmp
117	120	endif