Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit 45123804200a268c3bfc879b49bd30aef565b79b

Authored by Sjoerd Simons
Committed by Tom Rini
1 parent f2fae512f2
Exists in smarc_8mq_lf_v2020.04 and in 9 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

am335x, guardian: Add support for the bosch guardian board 

Add support for the Bosch Guardian board.

CPU  : AM335X-GP rev 2.1
Model: Bosch AM335x Guardian
I2C:   ready
DRAM:  256 MiB
NAND:  512 MiB
MMC:   OMAP SD/MMC: 0

Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Felix Brack <fb@ltec.ch>

Showing 13 changed files with 1121 additions and 1 deletions Side-by-side Diff

... ... @@ -1563,6 +1563,7 @@
1563 1563 source "arch/arm/mach-imx/Kconfig"
1564 1564  
1565 1565 source "board/bosch/shc/Kconfig"
  1566 +source "board/bosch/guardian/Kconfig"
1566 1567 source "board/CarMediaLab/flea3/Kconfig"
1567 1568 source "board/Marvell/aspenite/Kconfig"
1568 1569 source "board/Marvell/gplugd/Kconfig"
arch/arm/dts/Makefile
Diff comments   View file @ 4512380
... ... @@ -251,7 +251,8 @@
251 251 am335x-pdu001.dtb \
252 252 am335x-chiliboard.dtb \
253 253 am335x-sl50.dtb \
254   - am335x-base0033.dtb
  254 + am335x-base0033.dtb \
  255 + am335x-guardian.dtb
255 256 dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \
256 257 am43x-epos-evm.dtb \
257 258 am437x-idk-evm.dtb \
arch/arm/dts/am335x-guardian-u-boot.dtsi
Diff comments   View file @ 4512380
  1 +// SPDX-License-Identifier: GPL-2.0+
  2 +/*
  3 + * Copyright (C) 2018 EETS GmbH - https://www.eets.ch/
  4 + * Copyright (C) 2018 Robert Bosch Power Tools GmbH
  5 + */
  6 +
  7 +/ {
  8 + ocp {
  9 + u-boot,dm-pre-reloc;
  10 + };
  11 +};
  12 +
  13 +&l4_wkup {
  14 + u-boot,dm-pre-reloc;
  15 +};
  16 +
  17 +&mmc1 {
  18 + u-boot,dm-pre-reloc;
  19 +};
  20 +
  21 +&mmc1_pins {
  22 + u-boot,dm-pre-reloc;
  23 +};
  24 +
  25 +&rtc {
  26 + clocks = <&l4_per_clkctrl AM3_CLKDIV32K_CLKCTRL 0>;
  27 + clock-names = "int-clk";
  28 +};
  29 +
  30 +&scm {
  31 + u-boot,dm-pre-reloc;
  32 +};
  33 +
  34 +&uart0 {
  35 + u-boot,dm-pre-reloc;
  36 +};
  37 +
  38 +&uart0_pins {
  39 + u-boot,dm-pre-reloc;
  40 +};
  41 +
  42 +&usb {
  43 + u-boot,dm-pre-reloc;
  44 +};
  45 +
  46 +&usb_ctrl_mod {
  47 + u-boot,dm-pre-reloc;
  48 +};
  49 +
  50 +&usb0 {
  51 + u-boot,dm-pre-reloc;
  52 +};
  53 +
  54 +&usb0_phy {
  55 + u-boot,dm-pre-reloc;
  56 +};
  57 +
  58 +&am33xx_pinmux {
  59 + u-boot,dm-pre-reloc;
  60 +
  61 + lcd0_pins: pinmux_lcd0_pins {
  62 + pinctrl-single,pins = <
  63 + AM33XX_IOPAD(0x908, PIN_OUTPUT_PULLUP | MUX_MODE7)
  64 + >;
  65 + };
  66 +};
arch/arm/dts/am335x-guardian.dts
Diff comments   View file @ 4512380
  1 +// SPDX-License-Identifier: GPL-2.0
  2 +/*
  3 + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
  4 + * Copyright (C) 2018 Robert Bosch Power Tools GmbH
  5 + */
  6 +/dts-v1/;
  7 +
  8 +#include "am33xx.dtsi"
  9 +#include <dt-bindings/input/input.h>
  10 +#include <dt-bindings/interrupt-controller/irq.h>
  11 +
  12 +/ {
  13 + model = "Bosch AM335x Guardian";
  14 + compatible = "bosch,am335x-guardian", "ti,am33xx";
  15 +
  16 + chosen {
  17 + stdout-path = &uart0;
  18 + tick-timer = &timer2;
  19 + };
  20 +
  21 + cpus {
  22 + cpu@0 {
  23 + cpu0-supply = <&dcdc2_reg>;
  24 + };
  25 + };
  26 +
  27 + memory@80000000 {
  28 + device_type = "memory";
  29 + reg = <0x80000000 0x10000000>; /* 256 MB */
  30 + };
  31 +
  32 + gpio_keys {
  33 + compatible = "gpio-keys";
  34 + pinctrl-names = "default";
  35 + pinctrl-0 = <&gpio_keys_pins>;
  36 +
  37 + button21 {
  38 + label = "guardian-power-button";
  39 + linux,code = <KEY_POWER>;
  40 + gpios = <&gpio2 21 0>;
  41 + wakeup-source;
  42 + };
  43 + };
  44 +
  45 + leds {
  46 + compatible = "gpio-leds";
  47 + pinctrl-names = "default";
  48 + pinctrl-0 = <&leds_pins>;
  49 +
  50 + led1 {
  51 + label = "green:heartbeat";
  52 + gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>;
  53 + linux,default-trigger = "heartbeat";
  54 + default-state = "off";
  55 + };
  56 +
  57 + led2 {
  58 + label = "green:mmc0";
  59 + gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
  60 + linux,default-trigger = "mmc0";
  61 + default-state = "off";
  62 + };
  63 + };
  64 +
  65 + panel {
  66 + compatible = "ti,tilcdc,panel";
  67 + pinctrl-names = "default", "sleep";
  68 + pinctrl-0 = <&lcd_pins_default &lcd_disen_pins>;
  69 + pinctrl-1 = <&lcd_pins_sleep>;
  70 +
  71 + display-timings {
  72 + 320x240 {
  73 + hactive = <320>;
  74 + vactive = <240>;
  75 + hback-porch = <68>;
  76 + hfront-porch = <20>;
  77 + hsync-len = <1>;
  78 + vback-porch = <18>;
  79 + vfront-porch = <4>;
  80 + vsync-len = <1>;
  81 + clock-frequency = <9000000>;
  82 + hsync-active = <0>;
  83 + vsync-active = <0>;
  84 + };
  85 + };
  86 + panel-info {
  87 + ac-bias = <255>;
  88 + ac-bias-intrpt = <0>;
  89 + dma-burst-sz = <16>;
  90 + bpp = <24>;
  91 + bus-width = <16>;
  92 + fdd = <0x80>;
  93 + sync-edge = <0>;
  94 + sync-ctrl = <1>;
  95 + raster-order = <0>;
  96 + fifo-th = <0>;
  97 + };
  98 +
  99 + };
  100 +
  101 + pwm7: dmtimer-pwm {
  102 + compatible = "ti,omap-dmtimer-pwm";
  103 + ti,timers = <&timer7>;
  104 + pinctrl-names = "default";
  105 + pinctrl-0 = <&dmtimer7_pins>;
  106 + };
  107 +
  108 + vmmcsd_fixed: regulator-3v3 {
  109 + compatible = "regulator-fixed";
  110 + regulator-name = "vmmcsd_fixed";
  111 + regulator-min-microvolt = <3300000>;
  112 + regulator-max-microvolt = <3300000>;
  113 + };
  114 +};
  115 +
  116 +&cppi41dma {
  117 + status = "okay";
  118 +};
  119 +
  120 +&elm {
  121 + status = "okay";
  122 +};
  123 +
  124 +&gpmc {
  125 + pinctrl-names = "default";
  126 + pinctrl-0 = <&nandflash_pins>;
  127 + ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
  128 + status = "okay";
  129 +
  130 + nand@0,0 {
  131 + compatible = "ti,omap2-nand";
  132 + reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
  133 + interrupt-parent = <&gpmc>;
  134 + interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
  135 + <1 IRQ_TYPE_NONE>; /* termcount */
  136 + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
  137 + ti,nand-ecc-opt = "bch16";
  138 + ti,elm-id = <&elm>;
  139 + nand-bus-width = <8>;
  140 + gpmc,device-width = <1>;
  141 + gpmc,sync-clk-ps = <0>;
  142 + gpmc,cs-on-ns = <0>;
  143 + gpmc,cs-rd-off-ns = <44>;
  144 + gpmc,cs-wr-off-ns = <44>;
  145 + gpmc,adv-on-ns = <6>;
  146 + gpmc,adv-rd-off-ns = <34>;
  147 + gpmc,adv-wr-off-ns = <44>;
  148 + gpmc,we-on-ns = <0>;
  149 + gpmc,we-off-ns = <40>;
  150 + gpmc,oe-on-ns = <0>;
  151 + gpmc,oe-off-ns = <54>;
  152 + gpmc,access-ns = <64>;
  153 + gpmc,rd-cycle-ns = <82>;
  154 + gpmc,wr-cycle-ns = <82>;
  155 + gpmc,bus-turnaround-ns = <0>;
  156 + gpmc,cycle2cycle-delay-ns = <0>;
  157 + gpmc,clk-activation-ns = <0>;
  158 + gpmc,wr-access-ns = <40>;
  159 + gpmc,wr-data-mux-bus-ns = <0>;
  160 +
  161 + /*
  162 + * MTD partition table
  163 + *
  164 + * All SPL-* partitions are sized to minimal length which can
  165 + * be independently programmable. For NAND flash this is equal
  166 + * to size of erase-block.
  167 + */
  168 + #address-cells = <1>;
  169 + #size-cells = <1>;
  170 +
  171 + partition@0 {
  172 + label = "SPL";
  173 + reg = <0x0 0x40000>;
  174 + };
  175 +
  176 + partition@1 {
  177 + label = "SPL.backup1";
  178 + reg = <0x40000 0x40000>;
  179 + };
  180 +
  181 + partition@2 {
  182 + label = "SPL.backup2";
  183 + reg = <0x80000 0x40000>;
  184 + };
  185 +
  186 + partition@3 {
  187 + label = "SPL.backup3";
  188 + reg = <0xc0000 0x40000>;
  189 + };
  190 +
  191 + partition@4 {
  192 + label = "u-boot";
  193 + reg = <0x100000 0x100000>;
  194 + };
  195 +
  196 + partition@5 {
  197 + label = "u-boot.backup1";
  198 + reg = <0x200000 0x100000>;
  199 + };
  200 +
  201 + partition@6 {
  202 + label = "u-boot-env";
  203 + reg = <0x300000 0x40000>;
  204 + };
  205 +
  206 + partition@7 {
  207 + label = "u-boot-env.backup1";
  208 + reg = <0x340000 0x40000>;
  209 + };
  210 +
  211 + partition@8 {
  212 + label = "UBI";
  213 + reg = <0x380000 0x1fc80000>;
  214 + };
  215 + };
  216 +};
  217 +
  218 +&i2c0 {
  219 + pinctrl-names = "default";
  220 + pinctrl-0 = <&i2c0_pins>;
  221 + clock-frequency = <400000>;
  222 + status = "okay";
  223 +
  224 + tps: tps@24 {
  225 + reg = <0x24>;
  226 + };
  227 +};
  228 +
  229 +&lcdc {
  230 + blue-and-red-wiring = "crossed";
  231 + status = "okay";
  232 +};
  233 +
  234 +&mmc1 {
  235 + bus-width = <0x4>;
  236 + pinctrl-names = "default";
  237 + pinctrl-0 = <&mmc1_pins>;
  238 + cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
  239 + vmmc-supply = <&vmmcsd_fixed>;
  240 + status = "okay";
  241 +};
  242 +
  243 +&rtc {
  244 + clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
  245 + clock-names = "ext-clk", "int-clk";
  246 + system-power-controller;
  247 +};
  248 +
  249 +&spi0 {
  250 + ti,pindir-d0-out-d1-in;
  251 + pinctrl-names = "default";
  252 + pinctrl-0 = <&spi0_pins>;
  253 + status = "okay";
  254 +};
  255 +
  256 +/include/ "tps65217.dtsi"
  257 +
  258 +&tps {
  259 + ti,pmic-shutdown-controller;
  260 + interrupt-parent = <&intc>;
  261 + interrupts = <7>; /* NMI */
  262 +
  263 + backlight {
  264 + isel = <1>; /* 1 - ISET1, 2 ISET2 */
  265 + fdim = <100>; /* TPS65217_BL_FDIM_100HZ */
  266 + default-brightness = <100>;
  267 + };
  268 +
  269 + regulators {
  270 + dcdc1_reg: regulator@0 {
  271 + regulator-name = "vdds_dpr";
  272 + regulator-always-on;
  273 + };
  274 +
  275 + dcdc2_reg: regulator@1 {
  276 + regulator-name = "vdd_mpu";
  277 + regulator-min-microvolt = <925000>;
  278 + regulator-max-microvolt = <1351500>;
  279 + regulator-boot-on;
  280 + regulator-always-on;
  281 + };
  282 +
  283 + dcdc3_reg: regulator@2 {
  284 + regulator-name = "vdd_core";
  285 + regulator-min-microvolt = <925000>;
  286 + regulator-max-microvolt = <1150000>;
  287 + regulator-boot-on;
  288 + regulator-always-on;
  289 + };
  290 +
  291 + ldo1_reg: regulator@3 {
  292 + regulator-name = "vio,vrtc,vdds";
  293 + regulator-always-on;
  294 + };
  295 +
  296 + ldo2_reg: regulator@4 {
  297 + regulator-name = "vdd_3v3aux";
  298 + regulator-always-on;
  299 + };
  300 +
  301 + ldo3_reg: regulator@5 {
  302 + regulator-name = "vdd_1v8";
  303 + regulator-min-microvolt = <1800000>;
  304 + regulator-max-microvolt = <1800000>;
  305 + regulator-always-on;
  306 + };
  307 +
  308 + ldo4_reg: regulator@6 {
  309 + regulator-name = "vdd_3v3a";
  310 + regulator-always-on;
  311 + };
  312 + };
  313 +};
  314 +
  315 +&tscadc {
  316 + status = "okay";
  317 +
  318 + adc {
  319 + ti,adc-channels = <0 1 2 3 4 5 6>;
  320 + };
  321 +};
  322 +
  323 +&uart0 {
  324 + pinctrl-names = "default";
  325 + pinctrl-0 = <&uart0_pins>;
  326 + status = "okay";
  327 +};
  328 +
  329 +&usb {
  330 + status = "okay";
  331 +};
  332 +
  333 +&usb_ctrl_mod {
  334 + status = "okay";
  335 +};
  336 +
  337 +&usb0 {
  338 + dr_mode = "peripheral";
  339 + status = "okay";
  340 +};
  341 +
  342 +&usb0_phy {
  343 + status = "okay";
  344 +};
  345 +
  346 +&usb1 {
  347 + dr_mode = "host";
  348 + status = "okay";
  349 +};
  350 +
  351 +&usb1_phy {
  352 + status = "okay";
  353 +};
  354 +
  355 +&am33xx_pinmux {
  356 + pinctrl-names = "default";
  357 + pinctrl-0 = <&clkout2_pin &gpio_pins>;
  358 +
  359 + clkout2_pin: pinmux_clkout2_pin {
  360 + pinctrl-single,pins = <
  361 + AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3)
  362 + >;
  363 + };
  364 +
  365 + dmtimer7_pins: pinmux_dmtimer7_pins {
  366 + pinctrl-single,pins = <
  367 + AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE5)
  368 + >;
  369 + };
  370 +
  371 + gpio_keys_pins: pinmux_gpio_keys_pins {
  372 + pinctrl-single,pins = <
  373 + AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE7)
  374 + >;
  375 + };
  376 +
  377 + gpio_pins: pinmux_gpio_pins {
  378 + pinctrl-single,pins = <
  379 + AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE7)
  380 + AM33XX_IOPAD(0x990, PIN_OUTPUT | MUX_MODE7)
  381 + >;
  382 + };
  383 +
  384 + i2c0_pins: pinmux_i2c0_pins {
  385 + pinctrl-single,pins = <
  386 + AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)
  387 + AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)
  388 + >;
  389 + };
  390 +
  391 + lcd_disen_pins: pinmux_lcd_disen_pins {
  392 + pinctrl-single,pins = <
  393 + AM33XX_IOPAD(0x9a4, PIN_OUTPUT_PULLUP | SLEWCTRL_SLOW | MUX_MODE7)
  394 + >;
  395 + };
  396 +
  397 + lcd_pins_default: pinmux_lcd_pins_default {
  398 + pinctrl-single,pins = <
  399 + AM33XX_IOPAD(0x820, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
  400 + AM33XX_IOPAD(0x824, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
  401 + AM33XX_IOPAD(0x828, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
  402 + AM33XX_IOPAD(0x82c, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
  403 + AM33XX_IOPAD(0x830, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
  404 + AM33XX_IOPAD(0x834, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
  405 + AM33XX_IOPAD(0x838, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
  406 + AM33XX_IOPAD(0x83c, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE1)
  407 + AM33XX_IOPAD(0x8a0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
  408 + AM33XX_IOPAD(0x8a4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
  409 + AM33XX_IOPAD(0x8a8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
  410 + AM33XX_IOPAD(0x8ac, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
  411 + AM33XX_IOPAD(0x8b0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
  412 + AM33XX_IOPAD(0x8b4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
  413 + AM33XX_IOPAD(0x8b8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
  414 + AM33XX_IOPAD(0x8bc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
  415 + AM33XX_IOPAD(0x8c0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
  416 + AM33XX_IOPAD(0x8c4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
  417 + AM33XX_IOPAD(0x8c8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
  418 + AM33XX_IOPAD(0x8cc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
  419 + AM33XX_IOPAD(0x8d0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
  420 + AM33XX_IOPAD(0x8d4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
  421 + AM33XX_IOPAD(0x8d8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
  422 + AM33XX_IOPAD(0x8dc, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
  423 + AM33XX_IOPAD(0x8e0, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
  424 + AM33XX_IOPAD(0x8e4, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
  425 + AM33XX_IOPAD(0x8e8, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
  426 + AM33XX_IOPAD(0x8ec, PIN_OUTPUT | SLEWCTRL_SLOW | MUX_MODE0)
  427 + >;
  428 + };
  429 +
  430 + lcd_pins_sleep: pinmux_lcd_pins_sleep {
  431 + pinctrl-single,pins = <
  432 + AM33XX_IOPAD(0x8a0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
  433 + AM33XX_IOPAD(0x8a4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
  434 + AM33XX_IOPAD(0x8a8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
  435 + AM33XX_IOPAD(0x8ac, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
  436 + AM33XX_IOPAD(0x8b0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
  437 + AM33XX_IOPAD(0x8b4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
  438 + AM33XX_IOPAD(0x8b8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
  439 + AM33XX_IOPAD(0x8bc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
  440 + AM33XX_IOPAD(0x8c0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
  441 + AM33XX_IOPAD(0x8c4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
  442 + AM33XX_IOPAD(0x8c8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
  443 + AM33XX_IOPAD(0x8cc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
  444 + AM33XX_IOPAD(0x8d0, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
  445 + AM33XX_IOPAD(0x8d4, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
  446 + AM33XX_IOPAD(0x8d8, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
  447 + AM33XX_IOPAD(0x8dc, PULL_DISABLE | SLEWCTRL_SLOW | MUX_MODE7)
  448 + AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7)
  449 + AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7)
  450 + AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7)
  451 + AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | SLEWCTRL_SLOW | MUX_MODE7)
  452 + >;
  453 + };
  454 +
  455 + leds_pins: pinmux_leds_pins {
  456 + pinctrl-single,pins = <
  457 + AM33XX_IOPAD(0x868, PIN_OUTPUT | MUX_MODE7)
  458 + AM33XX_IOPAD(0x86c, PIN_OUTPUT | MUX_MODE7)
  459 + >;
  460 + };
  461 +
  462 + mmc1_pins: pinmux_mmc1_pins {
  463 + pinctrl-single,pins = <
  464 + AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0)
  465 + AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0)
  466 + AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0)
  467 + AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0)
  468 + AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0)
  469 + AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0)
  470 + AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7)
  471 + >;
  472 + };
  473 +
  474 + spi0_pins: pinmux_spi0_pins {
  475 + pinctrl-single,pins = <
  476 + AM33XX_IOPAD(0x950, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
  477 + AM33XX_IOPAD(0x954, PIN_OUTPUT_PULLUP | MUX_MODE0)
  478 + AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0)
  479 + AM33XX_IOPAD(0x95c, PIN_OUTPUT_PULLUP | MUX_MODE0)
  480 + >;
  481 + };
  482 +
  483 + uart0_pins: pinmux_uart0_pins {
  484 + pinctrl-single,pins = <
  485 + AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)
  486 + AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
  487 + >;
  488 + };
  489 +
  490 + nandflash_pins: pinmux_nandflash_pins {
  491 + pinctrl-single,pins = <
  492 + AM33XX_IOPAD(0x800, PIN_INPUT | MUX_MODE0)
  493 + AM33XX_IOPAD(0x804, PIN_INPUT | MUX_MODE0)
  494 + AM33XX_IOPAD(0x808, PIN_INPUT | MUX_MODE0)
  495 + AM33XX_IOPAD(0x80c, PIN_INPUT | MUX_MODE0)
  496 + AM33XX_IOPAD(0x810, PIN_INPUT | MUX_MODE0)
  497 + AM33XX_IOPAD(0x814, PIN_INPUT | MUX_MODE0)
  498 + AM33XX_IOPAD(0x818, PIN_INPUT | MUX_MODE0)
  499 + AM33XX_IOPAD(0x81c, PIN_INPUT | MUX_MODE0)
  500 + AM33XX_IOPAD(0x870, PIN_INPUT | MUX_MODE0)
  501 + AM33XX_IOPAD(0x874, PIN_OUTPUT | MUX_MODE0)
  502 + AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0)
  503 + AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0)
  504 + AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0)
  505 + AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0)
  506 + AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0)
  507 + >;
  508 + };
  509 +};
arch/arm/mach-omap2/am33xx/Kconfig
Diff comments   View file @ 4512380
... ... @@ -87,6 +87,13 @@
87 87 imply CMD_DM
88 88 imply CMD_SPL
89 89  
  90 +config TARGET_AM335X_GUARDIAN
  91 + bool "Support am335x based guardian board from bosch"
  92 + select DM
  93 + select DM_SERIAL
  94 + select DM_GPIO
  95 + select DM_USB
  96 +
90 97 config TARGET_AM335X_SL50
91 98 bool "Support am335x_sl50"
92 99 select BOARD_LATE_INIT
board/bosch/guardian/Kconfig
Diff comments   View file @ 4512380
  1 +if TARGET_AM335X_GUARDIAN
  2 +
  3 +config SYS_BOARD
  4 + default "guardian"
  5 +
  6 +config SYS_VENDOR
  7 + default "bosch"
  8 +
  9 +config SYS_SOC
  10 + default "am33xx"
  11 +
  12 +config SYS_CONFIG_NAME
  13 + default "am335x_guardian"
  14 +
  15 +endif
board/bosch/guardian/MAINTAINERS
Diff comments   View file @ 4512380
  1 +Guardian BOARD
  2 +M: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
  3 +S: Maintained
  4 +F: board/bosch/guardian/
  5 +F: include/configs/am335x_guardian.h
  6 +F: configs/am335x_guardian_defconfig
board/bosch/guardian/Makefile
Diff comments   View file @ 4512380
  1 +# SPDX-License-Identifier: GPL-2.0+
  2 +#
  3 +# Makefile
  4 +#
  5 +# Copyright (C) 2018 Robert Bosch Power Tools GmbH
  6 +#
  7 +
  8 +ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
  9 +obj-y := mux.o
  10 +endif
  11 +
  12 +obj-y += board.o
board/bosch/guardian/board.c
Diff comments   View file @ 4512380
  1 +// SPDX-License-Identifier: GPL-2.0+
  2 +/*
  3 + * board.c
  4 + *
  5 + * Board functions for Bosch Guardian
  6 + *
  7 + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  8 + * Copyright (C) 2018 Robert Bosch Power Tools GmbH
  9 + */
  10 +
  11 +#include <common.h>
  12 +#include <cpsw.h>
  13 +#include <dm.h>
  14 +#include <environment.h>
  15 +#include <environment.h>
  16 +#include <errno.h>
  17 +#include <i2c.h>
  18 +#include <miiphy.h>
  19 +#include <panel.h>
  20 +#include <power/tps65217.h>
  21 +#include <power/tps65910.h>
  22 +#include <spl.h>
  23 +#include <watchdog.h>
  24 +#include <asm/arch/clock.h>
  25 +#include <asm/arch/cpu.h>
  26 +#include <asm/arch/ddr_defs.h>
  27 +#include <asm/arch/gpio.h>
  28 +#include <asm/arch/hardware.h>
  29 +#include <asm/arch/mem.h>
  30 +#include <asm/arch/mmc_host_def.h>
  31 +#include <asm/arch/omap.h>
  32 +#include <asm/arch/sys_proto.h>
  33 +#include <asm/emif.h>
  34 +#include <asm/gpio.h>
  35 +#include <asm/io.h>
  36 +#include "board.h"
  37 +
  38 +DECLARE_GLOBAL_DATA_PTR;
  39 +
  40 +#ifndef CONFIG_SKIP_LOWLEVEL_INIT
  41 +static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  42 +
  43 +static const struct ddr_data ddr3_data = {
  44 + .datardsratio0 = MT41K128M16JT125K_RD_DQS,
  45 + .datawdsratio0 = MT41K128M16JT125K_WR_DQS,
  46 + .datafwsratio0 = MT41K128M16JT125K_PHY_FIFO_WE,
  47 + .datawrsratio0 = MT41K128M16JT125K_PHY_WR_DATA,
  48 +};
  49 +
  50 +static const struct cmd_control ddr3_cmd_ctrl_data = {
  51 + .cmd0csratio = MT41K128M16JT125K_RATIO,
  52 + .cmd0iclkout = MT41K128M16JT125K_INVERT_CLKOUT,
  53 +
  54 + .cmd1csratio = MT41K128M16JT125K_RATIO,
  55 + .cmd1iclkout = MT41K128M16JT125K_INVERT_CLKOUT,
  56 +
  57 + .cmd2csratio = MT41K128M16JT125K_RATIO,
  58 + .cmd2iclkout = MT41K128M16JT125K_INVERT_CLKOUT,
  59 +};
  60 +
  61 +static struct emif_regs ddr3_emif_reg_data = {
  62 + .sdram_config = MT41K128M16JT125K_EMIF_SDCFG,
  63 + .ref_ctrl = MT41K128M16JT125K_EMIF_SDREF,
  64 + .sdram_tim1 = MT41K128M16JT125K_EMIF_TIM1,
  65 + .sdram_tim2 = MT41K128M16JT125K_EMIF_TIM2,
  66 + .sdram_tim3 = MT41K128M16JT125K_EMIF_TIM3,
  67 + .zq_config = MT41K128M16JT125K_ZQ_CFG,
  68 + .emif_ddr_phy_ctlr_1 = MT41K128M16JT125K_EMIF_READ_LATENCY,
  69 +};
  70 +
  71 +#define OSC (V_OSCK / 1000000)
  72 +const struct dpll_params dpll_ddr = {
  73 + 400, OSC - 1, 1, -1, -1, -1, -1};
  74 +
  75 +void am33xx_spl_board_init(void)
  76 +{
  77 + int mpu_vdd;
  78 + int usb_cur_lim;
  79 +
  80 + /* Get the frequency */
  81 + dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
  82 +
  83 + if (i2c_probe(TPS65217_CHIP_PM))
  84 + return;
  85 +
  86 + /*
  87 + * Increase USB current limit to 1300mA or 1800mA and set
  88 + * the MPU voltage controller as needed.
  89 + */
  90 + if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
  91 + usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
  92 + mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
  93 + } else {
  94 + usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
  95 + mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
  96 + }
  97 +
  98 + if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
  99 + TPS65217_POWER_PATH,
  100 + usb_cur_lim,
  101 + TPS65217_USB_INPUT_CUR_LIMIT_MASK))
  102 + puts("tps65217_reg_write failure\n");
  103 +
  104 + /* Set DCDC3 (CORE) voltage to 1.125V */
  105 + if (tps65217_voltage_update(TPS65217_DEFDCDC3,
  106 + TPS65217_DCDC_VOLT_SEL_1125MV)) {
  107 + puts("tps65217_voltage_update failure\n");
  108 + return;
  109 + }
  110 +
  111 + /* Set CORE Frequencies to OPP100 */
  112 + do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
  113 +
  114 + /* Set DCDC2 (MPU) voltage */
  115 + if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
  116 + puts("tps65217_voltage_update failure\n");
  117 + return;
  118 + }
  119 +
  120 + /*
  121 + * Set LDO3 to 1.8V and LDO4 to 3.3V
  122 + */
  123 + if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
  124 + TPS65217_DEFLS1,
  125 + TPS65217_LDO_VOLTAGE_OUT_1_8,
  126 + TPS65217_LDO_MASK))
  127 + puts("tps65217_reg_write failure\n");
  128 +
  129 + if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
  130 + TPS65217_DEFLS2,
  131 + TPS65217_LDO_VOLTAGE_OUT_3_3,
  132 + TPS65217_LDO_MASK))
  133 + puts("tps65217_reg_write failure\n");
  134 +
  135 + /* Set MPU Frequency to what we detected now that voltages are set */
  136 + do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
  137 +}
  138 +
  139 +const struct dpll_params *get_dpll_ddr_params(void)
  140 +{
  141 + enable_i2c0_pin_mux();
  142 + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
  143 +
  144 + return &dpll_ddr;
  145 +}
  146 +
  147 +void set_uart_mux_conf(void)
  148 +{
  149 + enable_uart0_pin_mux();
  150 +}
  151 +
  152 +void set_mux_conf_regs(void)
  153 +{
  154 + enable_board_pin_mux();
  155 +}
  156 +
  157 +const struct ctrl_ioregs ioregs = {
  158 + .cm0ioctl = MT41K128M16JT125K_IOCTRL_VALUE,
  159 + .cm1ioctl = MT41K128M16JT125K_IOCTRL_VALUE,
  160 + .cm2ioctl = MT41K128M16JT125K_IOCTRL_VALUE,
  161 + .dt0ioctl = MT41K128M16JT125K_IOCTRL_VALUE,
  162 + .dt1ioctl = MT41K128M16JT125K_IOCTRL_VALUE,
  163 +};
  164 +
  165 +void sdram_init(void)
  166 +{
  167 + config_ddr(400, &ioregs,
  168 + &ddr3_data,
  169 + &ddr3_cmd_ctrl_data,
  170 + &ddr3_emif_reg_data, 0);
  171 +}
  172 +#endif
  173 +
  174 +int board_init(void)
  175 +{
  176 +#if defined(CONFIG_HW_WATCHDOG)
  177 + hw_watchdog_init();
  178 +#endif
  179 +
  180 + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  181 +
  182 +#ifdef CONFIG_NAND
  183 + gpmc_init();
  184 +#endif
  185 + return 0;
  186 +}
board/bosch/guardian/board.h
Diff comments   View file @ 4512380
  1 +/* SPDX-License-Identifier: GPL-2.0+ */
  2 +/*
  3 + * board.h
  4 + *
  5 + * Board header for Bosch Guardian
  6 + *
  7 + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  8 + * Copyright (C) 2018 Robert Bosch Power Tools GmbH
  9 + */
  10 +
  11 +#ifndef _BOARD_H_
  12 +#define _BOARD_H_
  13 +
  14 +void enable_uart0_pin_mux(void);
  15 +void enable_i2c0_pin_mux(void);
  16 +void enable_board_pin_mux(void);
  17 +#endif
board/bosch/guardian/mux.c
Diff comments   View file @ 4512380
  1 +// SPDX-License-Identifier: GPL-2.0+
  2 +/*
  3 + * mux.c
  4 + *
  5 + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  6 + * Copyright (C) 2018 Robert Bosch Power Tools GmbH
  7 + */
  8 +
  9 +#include <common.h>
  10 +#include <i2c.h>
  11 +#include <asm/arch/hardware.h>
  12 +#include <asm/arch/mux.h>
  13 +#include <asm/arch/sys_proto.h>
  14 +#include <asm/io.h>
  15 +#include "board.h"
  16 +
  17 +static struct module_pin_mux uart0_pin_mux[] = {
  18 + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)},
  19 + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
  20 + {-1},
  21 +};
  22 +
  23 +static struct module_pin_mux i2c0_pin_mux[] = {
  24 + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
  25 + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
  26 + {-1},
  27 +};
  28 +
  29 +static struct module_pin_mux adc_voltages_en[] = {
  30 + {OFFSET(mcasp0_ahclkx), (MODE(7) | PULLUP_EN)},
  31 + {-1},
  32 +};
  33 +
  34 +static struct module_pin_mux asp_power_en[] = {
  35 + {OFFSET(mcasp0_aclkx), (MODE(7) | PULLUP_EN)},
  36 + {-1},
  37 +};
  38 +
  39 +static struct module_pin_mux switch_off_3v6_pin_mux[] = {
  40 + {OFFSET(mii1_txd0), (MODE(7) | PULLUP_EN)},
  41 + /*
  42 + * The uart1 lines are made floating inputs, based on the Guardian
  43 + * A2 Sample Power Supply Schematics
  44 + */
  45 + {OFFSET(uart1_rxd), (MODE(7) | PULLUDDIS)},
  46 + {OFFSET(uart1_txd), (MODE(7) | PULLUDDIS)},
  47 + {-1},
  48 +};
  49 +
  50 +#ifdef CONFIG_NAND
  51 +static struct module_pin_mux nand_pin_mux[] = {
  52 + {OFFSET(gpmc_ad0), (MODE(0) | PULLUDDIS | RXACTIVE)},
  53 + {OFFSET(gpmc_ad1), (MODE(0) | PULLUDDIS | RXACTIVE)},
  54 + {OFFSET(gpmc_ad2), (MODE(0) | PULLUDDIS | RXACTIVE)},
  55 + {OFFSET(gpmc_ad3), (MODE(0) | PULLUDDIS | RXACTIVE)},
  56 + {OFFSET(gpmc_ad4), (MODE(0) | PULLUDDIS | RXACTIVE)},
  57 + {OFFSET(gpmc_ad5), (MODE(0) | PULLUDDIS | RXACTIVE)},
  58 + {OFFSET(gpmc_ad6), (MODE(0) | PULLUDDIS | RXACTIVE)},
  59 + {OFFSET(gpmc_ad7), (MODE(0) | PULLUDDIS | RXACTIVE)},
  60 +#ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
  61 + {OFFSET(gpmc_ad8), (MODE(0) | PULLUDDIS | RXACTIVE)},
  62 + {OFFSET(gpmc_ad9), (MODE(0) | PULLUDDIS | RXACTIVE)},
  63 + {OFFSET(gpmc_ad10), (MODE(0) | PULLUDDIS | RXACTIVE)},
  64 + {OFFSET(gpmc_ad11), (MODE(0) | PULLUDDIS | RXACTIVE)},
  65 + {OFFSET(gpmc_ad12), (MODE(0) | PULLUDDIS | RXACTIVE)},
  66 + {OFFSET(gpmc_ad13), (MODE(0) | PULLUDDIS | RXACTIVE)},
  67 + {OFFSET(gpmc_ad14), (MODE(0) | PULLUDDIS | RXACTIVE)},
  68 + {OFFSET(gpmc_ad15), (MODE(0) | PULLUDDIS | RXACTIVE)},
  69 +#endif
  70 + {OFFSET(gpmc_wait0), (MODE(0) | PULLUP_EN | RXACTIVE)},
  71 + {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN)},
  72 + {OFFSET(gpmc_csn0), (MODE(0) | PULLUP_EN)},
  73 + {OFFSET(gpmc_wen), (MODE(0) | PULLDOWN_EN)},
  74 + {OFFSET(gpmc_oen_ren), (MODE(0) | PULLDOWN_EN)},
  75 + {OFFSET(gpmc_advn_ale), (MODE(0) | PULLDOWN_EN)},
  76 + {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLDOWN_EN)},
  77 + {-1},
  78 +};
  79 +#endif
  80 +
  81 +void enable_uart0_pin_mux(void)
  82 +{
  83 + configure_module_pin_mux(uart0_pin_mux);
  84 +}
  85 +
  86 +void enable_i2c0_pin_mux(void)
  87 +{
  88 + configure_module_pin_mux(i2c0_pin_mux);
  89 +}
  90 +
  91 +void enable_board_pin_mux(void)
  92 +{
  93 +#ifdef CONFIG_NAND
  94 + configure_module_pin_mux(nand_pin_mux);
  95 +#endif
  96 + configure_module_pin_mux(adc_voltages_en);
  97 + configure_module_pin_mux(asp_power_en);
  98 + configure_module_pin_mux(switch_off_3v6_pin_mux);
  99 +}
configs/am335x_guardian_defconfig
Diff comments   View file @ 4512380
  1 +CONFIG_ARM=y
  2 +CONFIG_ARCH_OMAP2PLUS=y
  3 +CONFIG_SPL_GPIO_SUPPORT=y
  4 +CONFIG_SPL_LIBCOMMON_SUPPORT=y
  5 +CONFIG_SPL_LIBGENERIC_SUPPORT=y
  6 +CONFIG_AM33XX=y
  7 +CONFIG_TARGET_AM335X_GUARDIAN=y
  8 +CONFIG_SPL_MMC_SUPPORT=y
  9 +CONFIG_SPL_SERIAL_SUPPORT=y
  10 +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
  11 +CONFIG_SPL=y
  12 +CONFIG_SPL_LIBDISK_SUPPORT=y
  13 +CONFIG_DISTRO_DEFAULTS=y
  14 +CONFIG_BOOTSTAGE_STASH_ADDR=0x0
  15 +CONFIG_CONSOLE_MUX=y
  16 +CONFIG_SYS_CONSOLE_INFO_QUIET=y
  17 +CONFIG_VERSION_VARIABLE=y
  18 +CONFIG_ARCH_MISC_INIT=y
  19 +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
  20 +CONFIG_SPL_SEPARATE_BSS=y
  21 +CONFIG_SPL_ENV_SUPPORT=y
  22 +CONFIG_SPL_ETH_SUPPORT=y
  23 +CONFIG_SPL_I2C_SUPPORT=y
  24 +CONFIG_SPL_MUSB_NEW_SUPPORT=y
  25 +CONFIG_SPL_NET_SUPPORT=y
  26 +CONFIG_SPL_NET_VCI_STRING="Guardian U-Boot SPL"
  27 +CONFIG_SPL_POWER_SUPPORT=y
  28 +CONFIG_SPL_USB_GADGET=y
  29 +CONFIG_SPL_USB_ETHER=y
  30 +CONFIG_SPL_WATCHDOG_SUPPORT=y
  31 +CONFIG_SPL_YMODEM_SUPPORT=y
  32 +CONFIG_AUTOBOOT_KEYED=y
  33 +CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
  34 +CONFIG_AUTOBOOT_DELAY_STR="d"
  35 +CONFIG_AUTOBOOT_STOP_STR=" "
  36 +CONFIG_CMD_SPL=y
  37 +CONFIG_CMD_SPL_NAND_OFS=0x0
  38 +CONFIG_CMD_ASKENV=y
  39 +# CONFIG_CMD_FLASH is not set
  40 +CONFIG_CMD_GPIO=y
  41 +CONFIG_CMD_GPT=y
  42 +CONFIG_CMD_I2C=y
  43 +CONFIG_CMD_MMC=y
  44 +CONFIG_CMD_MTD=y
  45 +CONFIG_CMD_NAND=y
  46 +CONFIG_CMD_USB=y
  47 +# CONFIG_CMD_SETEXPR is not set
  48 +CONFIG_CMD_EXT4_WRITE=y
  49 +CONFIG_CMD_MTDPARTS=y
  50 +CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:256k(SPL),256k(SPL.backup1),256k(SPL.backup2),256k(SPL.backup3),1m(u-boot),1m(u-boot.backup1),256k(u-boot-env),256k(u-boot-env.backup1),-(UBI)"
  51 +CONFIG_CMD_UBI=y
  52 +# CONFIG_SPL_DOS_PARTITION is not set
  53 +# CONFIG_ISO_PARTITION is not set
  54 +# CONFIG_SPL_EFI_PARTITION is not set
  55 +CONFIG_OF_CONTROL=y
  56 +CONFIG_SPL_OF_CONTROL=y
  57 +CONFIG_DEFAULT_DEVICE_TREE="am335x-guardian"
  58 +CONFIG_ENV_IS_IN_NAND=y
  59 +CONFIG_SPL_ENV_IS_NOWHERE=y
  60 +CONFIG_SPL_DM=y
  61 +CONFIG_BOOTCOUNT_LIMIT=y
  62 +CONFIG_BOOTCOUNT_ENV=y
  63 +CONFIG_MISC=y
  64 +CONFIG_DM_MMC=y
  65 +CONFIG_MMC_OMAP_HS=y
  66 +CONFIG_MTD=y
  67 +CONFIG_NAND=y
  68 +CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
  69 +CONFIG_SYS_NAND_U_BOOT_OFFS=0x100000
  70 +CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND=0x200000
  71 +CONFIG_MTD_UBI_FASTMAP=y
  72 +CONFIG_PHYLIB=y
  73 +CONFIG_DM_ETH=y
  74 +CONFIG_PHY=y
  75 +CONFIG_NOP_PHY=y
  76 +CONFIG_PINCTRL=y
  77 +CONFIG_PINCTRL_SINGLE=y
  78 +CONFIG_USB=y
  79 +CONFIG_DM_USB_GADGET=y
  80 +CONFIG_SPL_DM_USB_GADGET=y
  81 +CONFIG_USB_MUSB_HOST=y
  82 +CONFIG_USB_MUSB_GADGET=y
  83 +CONFIG_USB_MUSB_TI=y
  84 +CONFIG_USB_MUSB_DSPS=y
  85 +CONFIG_USB_GADGET=y
  86 +CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
  87 +CONFIG_USB_GADGET_VENDOR_NUM=0x0451
  88 +CONFIG_USB_GADGET_PRODUCT_NUM=0xd022
  89 +CONFIG_USB_ETHER=y
  90 +CONFIG_FAT_WRITE=y
include/configs/am335x_guardian.h
Diff comments   View file @ 4512380
  1 +/* SPDX-License-Identifier: GPL-2.0+ */
  2 +/*
  3 + * am335x_guardian_.h
  4 + *
  5 + * Copyright (C) 2018 Robert Bosch Power Tools GmbH
  6 + * Copyright (C) 2018 sjoerd Simons <sjoerd.simons@collabora.co.uk>
  7 + *
  8 + */
  9 +
  10 +#ifndef __CONFIG_AM335X_GUARDIAN_H
  11 +#define __CONFIG_AM335X_GUARDIAN_H
  12 +
  13 +#include <configs/ti_am335x_common.h>
  14 +
  15 +#ifndef CONFIG_SPL_BUILD
  16 +#define CONFIG_TIMESTAMP
  17 +#endif
  18 +
  19 +/* Clock Defines */
  20 +#define V_OSCK 24000000 /* Clock output from T2 */
  21 +#define V_SCLK (V_OSCK)
  22 +
  23 +#ifndef CONFIG_SPL_BUILD
  24 +
  25 +#define MEM_LAYOUT_ENV_SETTINGS \
  26 + "scriptaddr=0x80000000\0" \
  27 + "pxefile_addr_r=0x80100000\0" \
  28 + "kernel_addr_r=0x82000000\0" \
  29 + "fdt_addr_r=0x88000000\0" \
  30 + "ramdisk_addr_r=0x88080000\0" \
  31 +
  32 +#define BOOT_TARGET_DEVICES(func) \
  33 + func(MMC, mmc, 0) \
  34 + func(UBIFS, ubifs, 0) \
  35 + func(PXE, pxe, na) \
  36 + func(DHCP, dhcp, na)
  37 +
  38 +#define AM335XX_BOARD_FDTFILE "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0"
  39 +
  40 +#include <config_distro_bootcmd.h>
  41 +
  42 +#define CONFIG_EXTRA_ENV_SETTINGS \
  43 + AM335XX_BOARD_FDTFILE \
  44 + MEM_LAYOUT_ENV_SETTINGS \
  45 + BOOTENV \
  46 + "bootlimit=3\0" \
  47 + "altbootcmd=" \
  48 + "setenv boot_config \"extlinux-rollback.conf\"; " \
  49 + "run distro_bootcmd\0"
  50 +
  51 +#endif /* CONFIG_SPL_BUILD */
  52 +
  53 +/* NS16550 Configuration */
  54 +#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
  55 +#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
  56 +#define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */
  57 +#define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
  58 +#define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
  59 +#define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
  60 +
  61 +/* PMIC support */
  62 +#define CONFIG_POWER_TPS65217
  63 +
  64 +/* Bootcount using the RTC block */
  65 +#define CONFIG_SYS_BOOTCOUNT_LE
  66 +
  67 +#ifdef CONFIG_NAND
  68 +#define CONFIG_ENV_OFFSET 0x300000
  69 +#define CONFIG_ENV_OFFSET_REDUND 0x340000
  70 +#define CONFIG_ENV_SIZE 0x040000
  71 +
  72 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE
  73 +#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
  74 + CONFIG_SYS_NAND_PAGE_SIZE)
  75 +#define CONFIG_SYS_NAND_PAGE_SIZE 4096
  76 +#define CONFIG_SYS_NAND_OOBSIZE 256
  77 +#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
  78 +
  79 +#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
  80 + 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \
  81 + 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \
  82 + 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \
  83 + 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, \
  84 + 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, \
  85 + 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, \
  86 + 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
  87 + 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, \
  88 + 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, \
  89 + 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, \
  90 + 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, \
  91 + 120, 121, 122, 123, 124, 125, 126, 127, 128, 129, \
  92 + 130, 131, 132, 133, 134, 135, 136, 137, 138, 139, \
  93 + 140, 141, 142, 143, 144, 145, 146, 147, 148, 149, \
  94 + 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, \
  95 + 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, \
  96 + 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, \
  97 + 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, \
  98 + 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, \
  99 + 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, \
  100 + }
  101 +#define CONFIG_SYS_NAND_ECCSIZE 512
  102 +#define CONFIG_SYS_NAND_ECCBYTES 26
  103 +#define CONFIG_SYS_NAND_ONFI_DETECTION
  104 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH16_CODE_HW
  105 +#define MTDIDS_DEFAULT "nand0=nand.0"
  106 +
  107 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
  108 +
  109 +#endif /* CONFIG_NAND */
  110 +
  111 +#endif /* ! __CONFIG_AM335X_GUARDIAN_H */