Commit 452f67407b20ab6a37c037d0975ea717d2f254e9
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3e0bc4473a
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Adjust configuration of XENIAX board
(chip select and GPIO required for USB operation)
Showing 2 changed files with 6 additions and 3 deletions Side-by-side Diff
CHANGELOG
| ... | ... | @@ -2,6 +2,9 @@ |
| 2 | 2 | Changes for U-Boot 1.1.3: |
| 3 | 3 | ====================================================================== |
| 4 | 4 | |
| 5 | +* Adjust configuration of XENIAX board | |
| 6 | + (chip select and GPIO required for USB operation) | |
| 7 | + | |
| 5 | 8 | * Fix typos in cpu/85xx/start.S which caused DataTLB exception to be |
| 6 | 9 | routed to the Watchdog handler |
| 7 | 10 | Patch by Eugene Surovegin, 18 Jun 2005 |
include/configs/xaeniax.h
| ... | ... | @@ -236,7 +236,7 @@ |
| 236 | 236 | * GP30 == SDATA_OUT is 0 |
| 237 | 237 | * GP81 == NSSPCLK is 0 |
| 238 | 238 | */ |
| 239 | -#define CFG_GPCR0_VAL 0x40C31868 | |
| 239 | +#define CFG_GPCR0_VAL 0x40C31848 | |
| 240 | 240 | #define CFG_GPCR1_VAL 0x00000000 |
| 241 | 241 | #define CFG_GPCR2_VAL 0x00020000 |
| 242 | 242 | |
| 243 | 243 | |
| ... | ... | @@ -455,10 +455,10 @@ |
| 455 | 455 | * [14:12] 010 - RRR2: CS deselect to CS time: 2*(2*MemClk) = 40 ns |
| 456 | 456 | * [11:08] 0010 - RDN2: Address to data valid in bursts: (2+1)*MemClk = 30 ns |
| 457 | 457 | * [07:04] 0110 - RDF2: Address for first access: (6+1)*MemClk = 70 ns |
| 458 | - * [03] 0 - 32 Bit bus width | |
| 458 | + * [03] 1 - 16 Bit bus width | |
| 459 | 459 | * [02:00] 100 - variable latency I/O |
| 460 | 460 | */ |
| 461 | -#define CFG_MSC1_VAL 0x1224A264 | |
| 461 | +#define CFG_MSC1_VAL 0x1224A26C | |
| 462 | 462 | |
| 463 | 463 | /* This is the configuration for nCS4/5 -> LAN |
| 464 | 464 | * configuration for nCS5: |