Eric Lee / smarc-uboot

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Commit 45db5424e40c4f64e36ffa679cd03cc4c8f220ac

Authored by Peng Fan
Committed by guoyin.chen
1 parent d5f1110c68
Exists in smarc-m6.0.1_2.1.0-ga

MLK-12030: imx: mx7d: fix the temperature checking for TO1.1 

We can rely on finish bit for temperature reading for TO1.1.
Also introduce CHIP_REV_xx macros for 7D.

Signed-off-by: Peng Fan <Peng.Fan@freescale.com>

Showing 2 changed files with 26 additions and 9 deletions Side-by-side Diff

arch/arm/include/asm/arch-mx7/imx-regs.h
Diff comments   View file @ 45db542
... ... @@ -216,6 +216,8 @@
216 216 #define FEC_QUIRK_ENET_MAC
217 217 #define SNVS_LPGPR 0x68
218 218  
  219 +#define CHIP_REV_1_0 0x10
  220 +#define CHIP_REV_1_1 0x11
219 221 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
220 222 #include <asm/types.h>
221 223  
drivers/thermal/imx_thermal.c
Diff comments   View file @ 45db542
... ... @@ -12,6 +12,8 @@
12 12 #include <fuse.h>
13 13 #include <asm/io.h>
14 14 #include <asm/arch/clock.h>
  15 +#include <asm/arch/imx-regs.h>
  16 +#include <asm/arch/sys_proto.h>
15 17 #include <dm.h>
16 18 #include <errno.h>
17 19 #include <malloc.h>
... ... @@ -126,6 +128,7 @@
126 128 #define TEMPERATURE_HOT 85
127 129 #define TEMPERATURE_MAX 125
128 130 #define MEASURE_FREQ 327
  131 +#define TEMPSENSE1_FINISHED (1 << 11)
129 132  
130 133 static int read_cpu_temperature(struct udevice *dev)
131 134 {
132 135  
... ... @@ -168,18 +171,30 @@
168 171 writel(TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK, &ccm_anatop->tempsense1_clr);
169 172 writel(TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_MASK, &ccm_anatop->tempsense1_set);
170 173  
171   - start = get_timer(0);
172   - /* Wait max 100ms */
173   - do {
174   - /*
175   - * Since we can not rely on finish bit, use 1ms delay to get
176   - * temperature. From RM, 17us is enough to get data, but
177   - * to gurantee to get the data, delay 100ms here.
178   - */
  174 + if (is_soc_rev(CHIP_REV_1_1) >= 0) {
  175 + /* make sure that the latest temp is valid */
  176 + while ((readl(&ccm_anatop->tempsense1) &
  177 + TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK) == 0)
  178 + udelay(10000);
179 179 reg = readl(&ccm_anatop->tempsense1);
180 180 tmp = (reg & TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK)
181 181 >> TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT;
182   - } while (get_timer(0) < (start + 100));
  182 + } else {
  183 + start = get_timer(0);
  184 + /* Wait max 100ms */
  185 + do {
  186 + /*
  187 + * Since we can not rely on finish bit, use 100ms
  188 + * delay to get temperature. From RM, 17us is
  189 + * enough to get data, but to gurantee to get
  190 + * the data, delay 100ms here.
  191 + */
  192 + reg = readl(&ccm_anatop->tempsense1);
  193 + tmp = (reg &
  194 + TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK)
  195 + >> TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT;
  196 + } while (get_timer(0) < (start + 100));
  197 + }
183 198  
184 199 writel(TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK, &ccm_anatop->tempsense1_clr);
185 200