Commit 45f89f340b4d8aa099fd022260dcb13cf3321b61
Committed by
Wolfgang Denk
Wolfgang Denk
1 parent
aa0c7a86cd
Exists in
master
and in
54 other branches
ep8248: add support for device tree and secondary Ethernet interface.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@noser.com>
Showing 2 changed files with 29 additions and 32 deletions Side-by-side Diff
board/ep8248/ep8248.c
| ... | ... | @@ -35,8 +35,8 @@ |
| 35 | 35 | * according to the five values podr/pdir/ppar/psor/pdat for that entry |
| 36 | 36 | */ |
| 37 | 37 | |
| 38 | -#define CONFIG_SYS_FCC1 (CONFIG_ETHER_INDEX == 1) | |
| 39 | -#define CONFIG_SYS_FCC2 (CONFIG_ETHER_INDEX == 2) | |
| 38 | +#define CONFIG_SYS_FCC1 (CONFIG_ETHER_ON_FCC1 == 1) | |
| 39 | +#define CONFIG_SYS_FCC2 (CONFIG_ETHER_ON_FCC2 == 1) | |
| 40 | 40 | |
| 41 | 41 | const iop_conf_t iop_conf_tab[4][32] = { |
| 42 | 42 | |
| ... | ... | @@ -261,4 +261,11 @@ |
| 261 | 261 | |
| 262 | 262 | return 0; |
| 263 | 263 | } |
| 264 | + | |
| 265 | +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) | |
| 266 | +void ft_board_setup(void *blob, bd_t *bd) | |
| 267 | +{ | |
| 268 | + ft_cpu_setup( blob, bd); | |
| 269 | +} | |
| 270 | +#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ |
include/configs/ep8248.h
| ... | ... | @@ -50,51 +50,42 @@ |
| 50 | 50 | |
| 51 | 51 | #define CONFIG_SYS_BCSR 0xFA000000 |
| 52 | 52 | |
| 53 | -/* | |
| 54 | - * Select ethernet configuration | |
| 55 | - * | |
| 56 | - * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, | |
| 57 | - * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for | |
| 58 | - * SCC, 1-3 for FCC) | |
| 59 | - * | |
| 60 | - * If CONFIG_ETHER_NONE is defined, then either the ethernet routines | |
| 61 | - * must be defined elsewhere (as for the console), or CONFIG_CMD_NET | |
| 62 | - * must be unset. | |
| 63 | - */ | |
| 53 | +/* Pass open firmware flat device tree */ | |
| 54 | +#define CONFIG_OF_LIBFDT 1 | |
| 55 | +#define CONFIG_OF_BOARD_SETUP 1 | |
| 56 | + | |
| 57 | +#define OF_TBCLK (bd->bi_busfreq / 4) | |
| 58 | +#define OF_STDOUT_PATH "/soc/cpm/serial <at> 11a80" | |
| 59 | + | |
| 60 | +/* Select ethernet configuration */ | |
| 64 | 61 | #undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */ |
| 65 | 62 | #define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */ |
| 66 | 63 | #undef CONFIG_ETHER_NONE /* No external Ethernet */ |
| 67 | 64 | |
| 68 | -#ifdef CONFIG_ETHER_ON_FCC | |
| 65 | +#define CONFIG_NET_MULTI | |
| 66 | +#define CONFIG_SYS_CPMFCR_RAMTYPE 0 | |
| 67 | +#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) | |
| 69 | 68 | |
| 70 | -#define CONFIG_ETHER_INDEX 1 /* FCC1 is used for Ethernet */ | |
| 71 | - | |
| 72 | -#if (CONFIG_ETHER_INDEX == 1) | |
| 73 | - | |
| 69 | +#define CONFIG_HAS_ETH0 | |
| 70 | +#define CONFIG_ETHER_ON_FCC1 1 | |
| 74 | 71 | /* - Rx clock is CLK10 |
| 75 | 72 | * - Tx clock is CLK11 |
| 76 | 73 | * - BDs/buffers on 60x bus |
| 77 | 74 | * - Full duplex |
| 78 | 75 | */ |
| 79 | -#define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK) | |
| 80 | -#define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF1CS_CLK10 | CMXFCR_TF1CS_CLK11) | |
| 81 | -#define CONFIG_SYS_CPMFCR_RAMTYPE 0 | |
| 82 | -#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) | |
| 76 | +#define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK) | |
| 77 | +#define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK10 | CMXFCR_TF1CS_CLK11) | |
| 83 | 78 | |
| 84 | -#elif (CONFIG_ETHER_INDEX == 2) | |
| 85 | - | |
| 79 | +#define CONFIG_HAS_ETH1 | |
| 80 | +#define CONFIG_ETHER_ON_FCC2 1 | |
| 86 | 81 | /* - Rx clock is CLK13 |
| 87 | 82 | * - Tx clock is CLK14 |
| 88 | 83 | * - BDs/buffers on 60x bus |
| 89 | 84 | * - Full duplex |
| 90 | 85 | */ |
| 91 | -#define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) | |
| 92 | -#define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) | |
| 93 | -#define CONFIG_SYS_CPMFCR_RAMTYPE 0 | |
| 94 | -#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) | |
| 86 | +#define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) | |
| 87 | +#define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) | |
| 95 | 88 | |
| 96 | -#endif /* CONFIG_ETHER_INDEX */ | |
| 97 | - | |
| 98 | 89 | #define CONFIG_MII /* MII PHY management */ |
| 99 | 90 | #define CONFIG_BITBANGMII /* Bit-banged MDIO interface */ |
| 100 | 91 | /* |
| ... | ... | @@ -112,8 +103,6 @@ |
| 112 | 103 | else *(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFD |
| 113 | 104 | |
| 114 | 105 | #define MIIDELAY udelay(1) |
| 115 | - | |
| 116 | -#endif /* CONFIG_ETHER_ON_FCC */ | |
| 117 | 106 | |
| 118 | 107 | #ifndef CONFIG_8260_CLKIN |
| 119 | 108 | #define CONFIG_8260_CLKIN 66000000 /* in Hz */ |