Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit 468548cdb8de7048c95831435fd7b9f55465d4f2

Authored by Lokesh Vutla
1 parent 5d9e43c1c1
Exists in v2017.01-smarct4x and in 2 other branches v2017.01-smarct3x, v2017.01-smarct3x-emmc

spl: Add support for enabling dcache 

Add support for enabling d-cache in SPL. The sequence in SPL tries to
replicate the sequence done in U-Boot except that MMU entries were added
for SRAM.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>

Showing 4 changed files with 92 additions and 10 deletions Side-by-side Diff

arch/arm/include/asm/cache.h
Diff comments   View file @ 468548c
... ... @@ -39,6 +39,7 @@
39 39 void arm_init_domains(void);
40 40 void cpu_cache_initialization(void);
41 41 void dram_bank_mmu_setup(int bank);
  42 +void sram_bank_mmu_setup(phys_addr_t start, phys_addr_t size);
42 43  
43 44 #endif
44 45  
arch/arm/lib/cache-cp15.c
Diff comments   View file @ 468548c
... ... @@ -94,16 +94,8 @@
94 94 mmu_page_table_flush(startpt, stoppt);
95 95 }
96 96  
97   -__weak void dram_bank_mmu_setup(int bank)
  97 +static void set_section_caches(int i)
98 98 {
99   - bd_t *bd = gd->bd;
100   - int i;
101   -
102   - debug("%s: bank: %d\n", __func__, bank);
103   - for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
104   - i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) +
105   - (bd->bi_dram[bank].size >> MMU_SECTION_SHIFT);
106   - i++) {
107 99 #if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
108 100 set_section_dcache(i, DCACHE_WRITETHROUGH);
109 101 #elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC)
110 102  
... ... @@ -111,9 +103,33 @@
111 103 #else
112 104 set_section_dcache(i, DCACHE_WRITEBACK);
113 105 #endif
114   - }
115 106 }
116 107  
  108 +__weak void dram_bank_mmu_setup(int bank)
  109 +{
  110 + bd_t *bd = gd->bd;
  111 + int i;
  112 +
  113 + debug("%s: bank: %d\n", __func__, bank);
  114 + for (i = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
  115 + i < (bd->bi_dram[bank].start >> MMU_SECTION_SHIFT) +
  116 + (bd->bi_dram[bank].size >> MMU_SECTION_SHIFT); i++)
  117 + set_section_caches(i);
  118 +}
  119 +
  120 +#if defined(CONFIG_SPL_BUILD) && (defined(CONFIG_SPL_MAX_SIZE) || \
  121 + defined(CONFIG_SPL_MAX_FOOTPRINT))
  122 +__weak void sram_bank_mmu_setup(phys_addr_t start, phys_addr_t size)
  123 +{
  124 + int i;
  125 +
  126 + for (i = start >> MMU_SECTION_SHIFT;
  127 + i < (start >> MMU_SECTION_SHIFT) + (size >> MMU_SECTION_SHIFT);
  128 + i++)
  129 + set_section_caches(i);
  130 +}
  131 +#endif
  132 +
117 133 /* to activate the MMU we need to set up virtual memory: use 1M areas */
118 134 static inline void mmu_setup(void)
119 135 {
... ... @@ -128,6 +144,16 @@
128 144 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
129 145 dram_bank_mmu_setup(i);
130 146 }
  147 +
  148 +#if defined(CONFIG_SPL_BUILD)
  149 +#if defined(CONFIG_SPL_MAX_SIZE)
  150 + sram_bank_mmu_setup(CONFIG_SPL_TEXT_BASE,
  151 + ALIGN(CONFIG_SPL_MAX_SIZE, MMU_SECTION_SIZE));
  152 +#elif defined(CONFIG_SPL_MAX_FOOTPRINT)
  153 + sram_bank_mmu_setup(CONFIG_SPL_TEXT_BASE,
  154 + ALIGN(CONFIG_SPL_MAX_FOOTPRINT, MMU_SECTION_SIZE));
  155 +#endif
  156 +#endif
131 157  
132 158 #ifdef CONFIG_ARMV7_LPAE
133 159 /* Set up 4 PTE entries pointing to our 4 1GB page tables */
arch/arm/mach-omap2/omap-cache.c
Diff comments   View file @ 468548c
... ... @@ -62,6 +62,21 @@
62 62 set_section_dcache(i, ARMV7_DCACHE_POLICY);
63 63 }
64 64  
  65 +#ifdef CONFIG_SPL_BUILD
  66 +void sram_bank_mmu_setup(phys_addr_t start, phys_addr_t size)
  67 +{
  68 + int i;
  69 + phys_addr_t end;
  70 +
  71 + start = start >> MMU_SECTION_SHIFT;
  72 + size = size >> MMU_SECTION_SHIFT;
  73 + end = start + size;
  74 +
  75 + for (i = start; i <= end; i++)
  76 + set_section_dcache(i, ARMV7_DCACHE_POLICY);
  77 +}
  78 +#endif
  79 +
65 80 void arm_init_domains(void)
66 81 {
67 82 u32 reg;
... ... @@ -327,6 +327,34 @@
327 327 return -ENODEV;
328 328 }
329 329  
  330 +#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \
  331 + defined(CONFIG_ARM)
  332 +static int reserve_mmu(void)
  333 +{
  334 + phys_addr_t ram_top = 0;
  335 + /* reserve TLB table */
  336 + gd->arch.tlb_size = PGTABLE_SIZE;
  337 +
  338 +#ifdef CONFIG_SYS_SDRAM_BASE
  339 + ram_top = CONFIG_SYS_SDRAM_BASE;
  340 +#endif
  341 + ram_top += get_effective_memsize();
  342 + gd->arch.tlb_addr = ram_top - gd->arch.tlb_size;
  343 + debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
  344 + gd->arch.tlb_addr + gd->arch.tlb_size);
  345 + return 0;
  346 +}
  347 +
  348 +__weak void dram_init_banksize(void)
  349 +{
  350 +#if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE)
  351 + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  352 + gd->bd->bi_dram[0].size = get_effective_memsize();
  353 +#endif
  354 +}
  355 +
  356 +#endif
  357 +
330 358 void board_init_r(gd_t *dummy1, ulong dummy2)
331 359 {
332 360 u32 spl_boot_list[] = {
... ... @@ -341,6 +369,13 @@
341 369 debug(">>spl:board_init_r()\n");
342 370 gd->bd = &bdata;
343 371  
  372 +#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \
  373 + defined(CONFIG_ARM)
  374 + dram_init_banksize();
  375 + reserve_mmu();
  376 + enable_caches();
  377 +#endif
  378 +
344 379 #if defined(CONFIG_SYS_SPL_MALLOC_START)
345 380 mem_malloc_init(CONFIG_SYS_SPL_MALLOC_START,
346 381 CONFIG_SYS_SPL_MALLOC_SIZE);
... ... @@ -370,6 +405,11 @@
370 405 puts("SPL: failed to boot from all boot devices\n");
371 406 hang();
372 407 }
  408 +
  409 +#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \
  410 + defined(CONFIG_ARM)
  411 + cleanup_before_linux();
  412 +#endif
373 413  
374 414 switch (spl_image.os) {
375 415 case IH_OS_U_BOOT: