driver: timer: Add the Atmel PIT timer driver

Add the new Atmel PIT timer driver, which supports the driver model and device tree. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>

driver: timer: Add the Atmel PIT timer driver
Add the new Atmel PIT timer driver, which supports the driver model and device tree. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
Wenyou.Yang@microchip.com · Tom Rini
1 parent deff9b1d2a
Showing 5 changed files with 103 additions and 0 deletions Side-by-side Diff
arch/arm/mach-at91/arm926ejs/Makefile
arch/arm/mach-at91/armv7/Makefile
drivers/timer/Kconfig
drivers/timer/Makefile
drivers/timer/atmel_pit_timer.c
@@ -22,7 +22,9 @@
 obj-y += clock.o
 obj-y += cpu.o
 obj-y	+= reset.o
+ifeq ($(CONFIG_ATMEL_PIT_TIMER),)
 obj-y	+= timer.o
+endif
  
 ifndef CONFIG_SKIP_LOWLEVEL_INIT
 obj-y	+= lowlevel_init.o
@@ -14,5 +14,7 @@
 obj-y += clock.o
 obj-y += cpu.o
 obj-y += reset.o
+ifeq ($(CONFIG_ATMEL_PIT_TIMER),)
 obj-y += timer.o
+endif
@@ -44,6 +44,14 @@
 	  Select this to enable a timer for Altera devices. Please find
 	  details on the "Embedded Peripherals IP User Guide" of Altera.
  
+config ATMEL_PIT_TIMER
+	bool "Atmel periodic interval timer support"
+	depends on TIMER
+	help
+	  Select this to enable a periodic interval timer for Atmel devices,
+	  it is designed to offer maximum accuracy and efficient management,
+	  even for systems with long response time.
+
 config SANDBOX_TIMER
 	bool "Sandbox timer support"
 	depends on SANDBOX && TIMER
@@ -15,4 +15,5 @@
 obj-$(CONFIG_AG101P_TIMER) += ag101p_timer.o
 obj-$(CONFIG_AE3XX_TIMER) += ae3xx_timer.o
 obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o
+obj-$(CONFIG_ATMEL_PIT_TIMER) += atmel_pit_timer.o
+/*
+ * Copyright (C) 2017 Microchip Corporation
+ * 		      Wenyou.Yang <wenyou.yang@microchip.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <timer.h>
+#include <asm/io.h>
+
+#define AT91_PIT_VALUE		0xfffff
+#define AT91_PIT_PITEN		BIT(24)		/* Timer Enabled */
+
+struct atmel_pit_regs {
+	u32	mode;
+	u32	status;
+	u32	value;
+	u32	value_image;
+};
+
+struct atmel_pit_platdata {
+	struct atmel_pit_regs *regs;
+};
+
+static int atmel_pit_get_count(struct udevice *dev, u64 *count)
+{
+	struct atmel_pit_platdata *plat = dev_get_platdata(dev);
+	struct atmel_pit_regs *const regs = plat->regs;
+	u32 val = readl(&regs->value_image);
+
+	*count = timer_conv_64(val);
+
+	return 0;
+}
+
+static int atmel_pit_probe(struct udevice *dev)
+{
+	struct atmel_pit_platdata *plat = dev_get_platdata(dev);
+	struct atmel_pit_regs *const regs = plat->regs;
+	struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+	struct clk clk;
+	ulong clk_rate;
+	int ret;
+
+	ret = clk_get_by_index(dev, 0, &clk);
+	if (ret)
+		return -EINVAL;
+
+	clk_rate = clk_get_rate(&clk);
+	if (!clk_rate)
+		return -EINVAL;
+
+	uc_priv->clock_rate = clk_rate / 16;
+
+	writel(AT91_PIT_VALUE | AT91_PIT_PITEN, &regs->mode);
+
+	return 0;
+}
+
+static int atmel_pit_ofdata_to_platdata(struct udevice *dev)
+{
+	struct atmel_pit_platdata *plat = dev_get_platdata(dev);
+
+	plat->regs = (struct atmel_pit_regs *)devfdt_get_addr_ptr(dev);
+
+	return 0;
+}
+
+static const struct timer_ops atmel_pit_ops = {
+	.get_count = atmel_pit_get_count,
+};
+
+static const struct udevice_id atmel_pit_ids[] = {
+	{ .compatible = "atmel,at91sam9260-pit" },
+	{ }
+};
+
+U_BOOT_DRIVER(atmel_pit) = {
+	.name	= "atmel_pit",
+	.id	= UCLASS_TIMER,
+	.of_match = atmel_pit_ids,
+	.ofdata_to_platdata = atmel_pit_ofdata_to_platdata,
+	.platdata_auto_alloc_size = sizeof(struct atmel_pit_platdata),
+	.probe	= atmel_pit_probe,
+	.ops	= &atmel_pit_ops,
+	.flags	= DM_FLAG_PRE_RELOC,
+};
...	...	@@ -22,7 +22,9 @@
22	22	obj-y += clock.o
23	23	obj-y += cpu.o
24	24	obj-y += reset.o
	25	+ifeq ($(CONFIG_ATMEL_PIT_TIMER),)
25	26	obj-y += timer.o
	27	+endif
26	28
27	29	ifndef CONFIG_SKIP_LOWLEVEL_INIT
28	30	obj-y += lowlevel_init.o
...	...	@@ -14,5 +14,7 @@
14	14	obj-y += clock.o
15	15	obj-y += cpu.o
16	16	obj-y += reset.o
	17	+ifeq ($(CONFIG_ATMEL_PIT_TIMER),)
17	18	obj-y += timer.o
	19	+endif
...	...	@@ -44,6 +44,14 @@
44	44	Select this to enable a timer for Altera devices. Please find
45	45	details on the "Embedded Peripherals IP User Guide" of Altera.
46	46
	47	+config ATMEL_PIT_TIMER
	48	+ bool "Atmel periodic interval timer support"
	49	+ depends on TIMER
	50	+ help
	51	+ Select this to enable a periodic interval timer for Atmel devices,
	52	+ it is designed to offer maximum accuracy and efficient management,
	53	+ even for systems with long response time.
	54	+
47	55	config SANDBOX_TIMER
48	56	bool "Sandbox timer support"
49	57	depends on SANDBOX && TIMER
...	...	@@ -15,4 +15,5 @@
15	15	obj-$(CONFIG_AG101P_TIMER) += ag101p_timer.o
16	16	obj-$(CONFIG_AE3XX_TIMER) += ae3xx_timer.o
17	17	obj-$(CONFIG_ROCKCHIP_TIMER) += rockchip_timer.o
	18	+obj-$(CONFIG_ATMEL_PIT_TIMER) += atmel_pit_timer.o
	1	+/*
	2	+ * Copyright (C) 2017 Microchip Corporation
	3	+ * Wenyou.Yang <wenyou.yang@microchip.com>
	4	+ *
	5	+ * SPDX-License-Identifier: GPL-2.0+
	6	+ */
	7	+
	8	+#include <common.h>
	9	+#include <clk.h>
	10	+#include <dm.h>
	11	+#include <timer.h>
	12	+#include <asm/io.h>
	13	+
	14	+#define AT91_PIT_VALUE 0xfffff
	15	+#define AT91_PIT_PITEN BIT(24) /* Timer Enabled */
	16	+
	17	+struct atmel_pit_regs {
	18	+ u32 mode;
	19	+ u32 status;
	20	+ u32 value;
	21	+ u32 value_image;
	22	+};
	23	+
	24	+struct atmel_pit_platdata {
	25	+ struct atmel_pit_regs *regs;
	26	+};
	27	+
	28	+static int atmel_pit_get_count(struct udevice dev, u64 count)
	29	+{
	30	+ struct atmel_pit_platdata *plat = dev_get_platdata(dev);
	31	+ struct atmel_pit_regs *const regs = plat->regs;
	32	+ u32 val = readl(&regs->value_image);
	33	+
	34	+ *count = timer_conv_64(val);
	35	+
	36	+ return 0;
	37	+}
	38	+
	39	+static int atmel_pit_probe(struct udevice *dev)
	40	+{
	41	+ struct atmel_pit_platdata *plat = dev_get_platdata(dev);
	42	+ struct atmel_pit_regs *const regs = plat->regs;
	43	+ struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
	44	+ struct clk clk;
	45	+ ulong clk_rate;
	46	+ int ret;
	47	+
	48	+ ret = clk_get_by_index(dev, 0, &clk);
	49	+ if (ret)
	50	+ return -EINVAL;
	51	+
	52	+ clk_rate = clk_get_rate(&clk);
	53	+ if (!clk_rate)
	54	+ return -EINVAL;
	55	+
	56	+ uc_priv->clock_rate = clk_rate / 16;
	57	+
	58	+ writel(AT91_PIT_VALUE \| AT91_PIT_PITEN, &regs->mode);
	59	+
	60	+ return 0;
	61	+}
	62	+
	63	+static int atmel_pit_ofdata_to_platdata(struct udevice *dev)
	64	+{
	65	+ struct atmel_pit_platdata *plat = dev_get_platdata(dev);
	66	+
	67	+ plat->regs = (struct atmel_pit_regs *)devfdt_get_addr_ptr(dev);
	68	+
	69	+ return 0;
	70	+}
	71	+
	72	+static const struct timer_ops atmel_pit_ops = {
	73	+ .get_count = atmel_pit_get_count,
	74	+};
	75	+
	76	+static const struct udevice_id atmel_pit_ids[] = {
	77	+ { .compatible = "atmel,at91sam9260-pit" },
	78	+ { }
	79	+};
	80	+
	81	+U_BOOT_DRIVER(atmel_pit) = {
	82	+ .name = "atmel_pit",
	83	+ .id = UCLASS_TIMER,
	84	+ .of_match = atmel_pit_ids,
	85	+ .ofdata_to_platdata = atmel_pit_ofdata_to_platdata,
	86	+ .platdata_auto_alloc_size = sizeof(struct atmel_pit_platdata),
	87	+ .probe = atmel_pit_probe,
	88	+ .ops = &atmel_pit_ops,
	89	+ .flags = DM_FLAG_PRE_RELOC,
	90	+};