Eric Lee / smarc-uboot

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Commit 489929be0221bb7d4c46bb5bc6083650b78f73e0

Authored by Peng Fan
1 parent ceb324a291
Exists in smarc-rel_imx_4.1.15_2.0.0_ga

MLK-12693-2 nand: mxs: correct bitflip for erased NAND page 

This patch is a porting of
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/?h=imx_4.1.15_1.0.0_ga&id=e4dacc44d22e9474ec456cb330df525cd805ea38
"
i.MX6QP and i.MX7D BCH module integrated a new feature to detect the
bitflip number for erased NAND page. So for these two platform, set the
erase threshold to gf/2 and if bitflip detected, GPMI driver will
correct the data to all 0xFF.

Also updated the imx6qp dts file to ditinguish the GPMI module for i.MX6Q
with the one for i.MX6QP.
"

In this patch, i.MX6UL is added and threshold changed to use ecc_strength.

Signed-off-by: Peng Fan <peng.fan@nxp.com>

Showing 2 changed files with 22 additions and 2 deletions Side-by-side Diff

arch/arm/include/asm/imx-common/regs-bch.h
Diff comments   View file @ 489929b
... ... @@ -5,7 +5,7 @@
5 5 * on behalf of DENX Software Engineering GmbH
6 6 *
7 7 * Based on code from LTIB:
8   - * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  8 + * Copyright 2008-2010, 2016 Freescale Semiconductor, Inc. All Rights Reserved.
9 9 *
10 10 * SPDX-License-Identifier: GPL-2.0+
11 11 */
... ... @@ -41,6 +41,7 @@
41 41 mxs_reg_32(hw_bch_dbgahbmread)
42 42 mxs_reg_32(hw_bch_blockname)
43 43 mxs_reg_32(hw_bch_version)
  44 + mxs_reg_32(hw_bch_debug1)
44 45 };
45 46 #endif
46 47  
... ... @@ -76,6 +77,9 @@
76 77  
77 78 #define BCH_MODE_ERASE_THRESHOLD_MASK 0xff
78 79 #define BCH_MODE_ERASE_THRESHOLD_OFFSET 0
  80 +#define BCH_MODE_ERASE_THRESHOLD(v) \
  81 + (((v) << BCH_MODE_ERASE_THRESHOLD_OFFSET) & \
  82 + BCH_MODE_ERASE_THRESHOLD_MASK)
79 83  
80 84 #define BCH_ENCODEPTR_ADDR_MASK 0xffffffff
81 85 #define BCH_ENCODEPTR_ADDR_OFFSET 0
drivers/mtd/nand/mxs_nand.c
Diff comments   View file @ 489929b
... ... @@ -688,10 +688,12 @@
688 688 {
689 689 struct mxs_nand_info *nand_info = nand->priv;
690 690 struct mxs_dma_desc *d;
  691 + struct mxs_bch_regs *bch_regs = (struct mxs_bch_regs *)MXS_BCH_BASE;
691 692 uint32_t channel = MXS_DMA_CHANNEL_AHB_APBH_GPMI0 + nand_info->cur_chip;
692 693 uint32_t corrected = 0, failed = 0;
693 694 uint8_t *status;
694 695 int i, ret;
  696 + int flag = 0;
695 697  
696 698 /* Compile the DMA descriptor - wait for ready. */
697 699 d = mxs_nand_get_dma_desc(nand_info);
698 700  
... ... @@ -795,8 +797,13 @@
795 797 if (status[i] == 0x00)
796 798 continue;
797 799  
798   - if (status[i] == 0xff)
  800 + if (status[i] == 0xff) {
  801 + if (is_mx6dqp() || is_soc_type(MXC_SOC_MX7) ||
  802 + is_cpu_type(MXC_CPU_MX6UL))
  803 + if (readl(bch_regs->hw_bch_debug1))
  804 + flag = 1;
799 805 continue;
  806 + }
800 807  
801 808 if (status[i] == 0xfe) {
802 809 if (mxs_nand_erased_page(mtd, nand,
... ... @@ -828,6 +835,9 @@
828 835  
829 836 memcpy(buf, nand_info->data_buf, mtd->writesize);
830 837  
  838 + if (flag)
  839 + memset(buf, 0xff, mtd->writesize);
  840 +
831 841 rtn:
832 842 mxs_nand_return_dma_descs(nand_info);
833 843  
... ... @@ -1149,6 +1159,12 @@
1149 1159 tmp |= (14 == galois_field ? 1 : 0) <<
1150 1160 BCH_FLASHLAYOUT1_GF13_0_GF14_1_OFFSET;
1151 1161 writel(tmp, &bch_regs->hw_bch_flash0layout1);
  1162 +
  1163 + /* Set erase threshold to ecc strength for mx6ul, mx6qp and mx7 */
  1164 + if (is_mx6dqp() || is_soc_type(MXC_SOC_MX7) ||
  1165 + is_cpu_type(MXC_CPU_MX6UL))
  1166 + writel(BCH_MODE_ERASE_THRESHOLD(ecc_strength),
  1167 + &bch_regs->hw_bch_mode);
1152 1168  
1153 1169 /* Set *all* chip selects to use layout 0 */
1154 1170 writel(0, &bch_regs->hw_bch_layoutselect);