Commit 4914a68de79bc5879f4ee7f0abc5d796f88167f1
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a55957b9ad
Exists in
smarc_8mq_lf_v2020.04
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ARM: uniphier: add PLL settings for PXs3
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Showing 1 changed file with 55 additions and 0 deletions Side-by-side Diff
arch/arm/mach-uniphier/clk/pll-pxs3.c
| 1 | 1 | /* |
| 2 | + * Copyright (C) 2017 Socionext Inc. | |
| 3 | + * | |
| 2 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
| 3 | 5 | */ |
| 4 | 6 | |
| 7 | +#include <linux/delay.h> | |
| 8 | + | |
| 5 | 9 | #include "../init.h" |
| 10 | +#include "../sc64-regs.h" | |
| 11 | +#include "pll.h" | |
| 6 | 12 | |
| 13 | +/* PLL type: SSC */ | |
| 14 | +#define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* CPU/ARM */ | |
| 15 | +#define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* misc */ | |
| 16 | +#define SC_SPLL2CTRL (SC_BASE_ADDR | 0x1420) /* DSP */ | |
| 17 | +#define SC_VPPLLCTRL (SC_BASE_ADDR | 0x1430) /* VPE */ | |
| 18 | +#define SC_VGPLLCTRL (SC_BASE_ADDR | 0x1440) | |
| 19 | +#define SC_DECPLLCTRL (SC_BASE_ADDR | 0x1450) | |
| 20 | +#define SC_ENCPLLCTRL (SC_BASE_ADDR | 0x1460) | |
| 21 | +#define SC_PXFPLLCTRL (SC_BASE_ADDR | 0x1470) | |
| 22 | +#define SC_DPLL0CTRL (SC_BASE_ADDR | 0x1480) /* DDR memory 0 */ | |
| 23 | +#define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1490) /* DDR memory 1 */ | |
| 24 | +#define SC_DPLL2CTRL (SC_BASE_ADDR | 0x14a0) /* DDR memory 2 */ | |
| 25 | +#define SC_VSPLLCTRL (SC_BASE_ADDR | 0x14c0) | |
| 26 | + | |
| 27 | +/* PLL type: VPLL27 */ | |
| 28 | +#define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500) | |
| 29 | +#define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520) | |
| 30 | + | |
| 31 | +/* PLL type: DSPLL */ | |
| 32 | +#define SC_VPLL8KCTRL (SC_BASE_ADDR | 0x1540) | |
| 33 | + | |
| 7 | 34 | void uniphier_pxs3_pll_init(void) |
| 8 | 35 | { |
| 36 | + uniphier_ld20_sscpll_init(SC_CPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4); | |
| 37 | + /* do nothing for SPLL */ | |
| 38 | + uniphier_ld20_sscpll_init(SC_SPLL2CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4); | |
| 39 | + uniphier_ld20_sscpll_init(SC_VPPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); | |
| 40 | + uniphier_ld20_sscpll_init(SC_VGPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); | |
| 41 | + uniphier_ld20_sscpll_init(SC_DECPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); | |
| 42 | + uniphier_ld20_sscpll_init(SC_ENCPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4); | |
| 43 | + uniphier_ld20_sscpll_init(SC_PXFPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); | |
| 44 | + uniphier_ld20_sscpll_init(SC_VSPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); | |
| 45 | + | |
| 46 | + mdelay(1); | |
| 47 | + | |
| 48 | + uniphier_ld20_sscpll_ssc_en(SC_CPLLCTRL); | |
| 49 | + uniphier_ld20_sscpll_ssc_en(SC_SPLL2CTRL); | |
| 50 | + uniphier_ld20_sscpll_ssc_en(SC_VPPLLCTRL); | |
| 51 | + uniphier_ld20_sscpll_ssc_en(SC_VGPLLCTRL); | |
| 52 | + uniphier_ld20_sscpll_ssc_en(SC_DECPLLCTRL); | |
| 53 | + uniphier_ld20_sscpll_ssc_en(SC_ENCPLLCTRL); | |
| 54 | + uniphier_ld20_sscpll_ssc_en(SC_PXFPLLCTRL); | |
| 55 | + uniphier_ld20_sscpll_ssc_en(SC_DPLL0CTRL); | |
| 56 | + uniphier_ld20_sscpll_ssc_en(SC_DPLL1CTRL); | |
| 57 | + uniphier_ld20_sscpll_ssc_en(SC_DPLL2CTRL); | |
| 58 | + uniphier_ld20_sscpll_ssc_en(SC_VSPLLCTRL); | |
| 59 | + | |
| 60 | + uniphier_ld20_vpll27_init(SC_VPLL27FCTRL); | |
| 61 | + uniphier_ld20_vpll27_init(SC_VPLL27ACTRL); | |
| 62 | + | |
| 63 | + uniphier_ld20_dspll_init(SC_VPLL8KCTRL); | |
| 9 | 64 | } |