board: ge: bx50v3: Setup LDB_DI_CLK source

To generate accurate pixel clocks required by the displays we need to set the ldb_di_clk source on bx50v3 to PLL3 and b850v3 to PLL5. Since PLL5 is disabled on reset, we need to enable PLL5. Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com> Cc: Stefano Babic <sbabic@denx.de>

board: ge: bx50v3: Setup LDB_DI_CLK source
To generate accurate pixel clocks required by the displays we need to set the ldb_di_clk source on bx50v3 to PLL3 and b850v3 to PLL5. Since PLL5 is disabled on reset, we need to enable PLL5. Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com> Cc: Stefano Babic <sbabic@denx.de>
Akshay Bhat · Stefano Babic
1 parent de708da0e8
Showing 1 changed file with 43 additions and 0 deletions Side-by-side Diff
board/ge/bx50v3/bx50v3.c
@@ -394,11 +394,46 @@
 } } };
 size_t display_count = ARRAY_SIZE(displays);
  
+static void enable_videopll(void)
+{
+	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	s32 timeout = 100000;
+
+	setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
+
+	/* set video pll to 910MHz (24MHz * (37+11/12))
+	* video pll post div to 910/4 = 227.5MHz
+	*/
+	clrsetbits_le32(&ccm->analog_pll_video,
+			BM_ANADIG_PLL_VIDEO_DIV_SELECT |
+			BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
+			BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
+			BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0));
+
+	writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
+	writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
+
+	clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
+
+	while (timeout--)
+		if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
+			break;
+
+	if (timeout < 0)
+		printf("Warning: video pll lock timeout!\n");
+
+	clrsetbits_le32(&ccm->analog_pll_video,
+			BM_ANADIG_PLL_VIDEO_BYPASS,
+			BM_ANADIG_PLL_VIDEO_ENABLE);
+}
+
 static void setup_display_b850v3(void)
 {
 	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  
+	enable_videopll();
+
 	/* IPU1 D0 clock is 227.5 / 3.5 = 65MHz */
 	clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
  
@@ -508,6 +543,14 @@
  
 	setup_iomux_uart();
  
+#if defined(CONFIG_VIDEO_IPUV3)
+	if (IS_ENABLED(CONFIG_TARGET_GE_B850V3))
+		/* Set LDB clock to Video PLL */
+		select_ldb_di_clock_source(MXC_PLL5_CLK);
+	else
+		/* Set LDB clock to USB PLL */
+		select_ldb_di_clock_source(MXC_PLL3_SW_CLK);
+#endif
 	return 0;
 }
...	...	@@ -394,11 +394,46 @@
394	394	} } };
395	395	size_t display_count = ARRAY_SIZE(displays);
396	396
	397	+static void enable_videopll(void)
	398	+{
	399	+ struct mxc_ccm_reg ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	400	+ s32 timeout = 100000;
	401	+
	402	+ setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
	403	+
	404	+ /* set video pll to 910MHz (24MHz * (37+11/12))
	405	+ * video pll post div to 910/4 = 227.5MHz
	406	+ */
	407	+ clrsetbits_le32(&ccm->analog_pll_video,
	408	+ BM_ANADIG_PLL_VIDEO_DIV_SELECT \|
	409	+ BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
	410	+ BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) \|
	411	+ BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0));
	412	+
	413	+ writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
	414	+ writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
	415	+
	416	+ clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
	417	+
	418	+ while (timeout--)
	419	+ if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
	420	+ break;
	421	+
	422	+ if (timeout < 0)
	423	+ printf("Warning: video pll lock timeout!\n");
	424	+
	425	+ clrsetbits_le32(&ccm->analog_pll_video,
	426	+ BM_ANADIG_PLL_VIDEO_BYPASS,
	427	+ BM_ANADIG_PLL_VIDEO_ENABLE);
	428	+}
	429	+
397	430	static void setup_display_b850v3(void)
398	431	{
399	432	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
400	433	struct iomuxc iomux = (struct iomuxc )IOMUXC_BASE_ADDR;
401	434
	435	+ enable_videopll();
	436	+
402	437	/* IPU1 D0 clock is 227.5 / 3.5 = 65MHz */
403	438	clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
404	439
...	...	@@ -508,6 +543,14 @@
508	543
509	544	setup_iomux_uart();
510	545
	546	+#if defined(CONFIG_VIDEO_IPUV3)
	547	+ if (IS_ENABLED(CONFIG_TARGET_GE_B850V3))
	548	+ /* Set LDB clock to Video PLL */
	549	+ select_ldb_di_clock_source(MXC_PLL5_CLK);
	550	+ else
	551	+ /* Set LDB clock to USB PLL */
	552	+ select_ldb_di_clock_source(MXC_PLL3_SW_CLK);
	553	+#endif
511	554	return 0;
512	555	}
513	556