Eric Lee / smarc-uboot

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Commit 495f3774be68e44a85b7e4b4f7964f8312bd8fc8

Authored by Andy Shevchenko
Committed by Bin Meng
1 parent e71de54a49
Exists in smarc_8mq_lf_v2020.04 and in 17 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

x86: Add Intel Edison board files 

Add Intel Edison board which is using U-Boot.

The patch is based on work done by the following people (in alphabetical
order):
	Aiden Park <aiden.park@intel.com>
	Dukjoon Jeon <dukjoon.jeon@intel.com>
	eric.park <eric.park@intel.com>
	Fabien Chereau <fabien.chereau@intel.com>
	Felipe Balbi <felipe.balbi@linux.intel.com>
	Scott D Phillips <scott.d.phillips@intel.com>
	Sebastien Colleur <sebastienx.colleur@intel.com>
	Steve Sakoman <steve.sakoman@intel.com>
	Vincent Tinelli <vincent.tinelli@intel.com>

In case we're building for Intel Edison, we must have 4096 bytes of
zeroes in the beginning on u-boot.bin. This is done in
board/intel/edison/config.mk.

First run sets hardware_id environment variable which is read from
System Controller Unit (SCU).

Serial number (serial# environment variable) is generated based on eMMC
CID.

MAC address on USB network interface is unique to the board but kept the
same all over the time.

Set mac address from U-Boot using following scheme:
	OUI = 02:00:86
	next 3 bytes of MAC address set from eMMC serial number

This allows to have a unique mac address across reboot and flashing.

Signed-off-by: Vincent Tinelli <vincent.tinelli@intel.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
[bmeng: Add MAINTAINERS file for Intel Edison board]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

Showing 13 changed files with 429 additions and 0 deletions Side-by-side Diff

arch/x86/cpu/tangier/Kconfig
Diff comments   View file @ 495f377
... ... @@ -18,4 +18,8 @@
18 18 help
19 19 Space in bytes in eSRAM used as Cache-As-RAM (CAR).
20 20 Note this size must not exceed eSRAM's total size.
  21 +
  22 +config SYS_USB_OTG_BASE
  23 + hex
  24 + default 0xf9100000
arch/x86/dts/Makefile
Diff comments   View file @ 495f377
... ... @@ -10,6 +10,7 @@
10 10 cougarcanyon2.dtb \
11 11 crownbay.dtb \
12 12 dfi-bt700-q7x-151.dtb \
  13 + edison.dtb \
13 14 efi.dtb \
14 15 galileo.dtb \
15 16 minnowmax.dtb \
arch/x86/dts/edison.dts
Diff comments   View file @ 495f377
  1 +/*
  2 + * Copyright (c) 2017 Intel Corporation
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +/dts-v1/;
  8 +
  9 +#include <dt-bindings/gpio/x86-gpio.h>
  10 +#include <dt-bindings/interrupt-router/intel-irq.h>
  11 +
  12 +/include/ "skeleton.dtsi"
  13 +/include/ "rtc.dtsi"
  14 +/include/ "tsc_timer.dtsi"
  15 +
  16 +/ {
  17 + model = "Intel Edison";
  18 + compatible = "intel,edison";
  19 +
  20 + aliases {
  21 + serial0 = &serial0;
  22 + };
  23 +
  24 + chosen {
  25 + stdout-path = &serial0;
  26 + };
  27 +
  28 + cpus {
  29 + #address-cells = <1>;
  30 + #size-cells = <0>;
  31 +
  32 + cpu@0 {
  33 + device_type = "cpu";
  34 + compatible = "cpu-x86";
  35 + reg = <0>;
  36 + intel,apic-id = <0>;
  37 + };
  38 +
  39 + cpu@1 {
  40 + device_type = "cpu";
  41 + compatible = "cpu-x86";
  42 + reg = <1>;
  43 + intel,apic-id = <2>;
  44 + };
  45 + };
  46 +
  47 + pci {
  48 + compatible = "pci-x86";
  49 + #address-cells = <3>;
  50 + #size-cells = <2>;
  51 + u-boot,dm-pre-reloc;
  52 + ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000
  53 + 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
  54 + 0x01000000 0x0 0x2000 0x2000 0 0xe000>;
  55 + };
  56 +
  57 + serial0: serial@ff010180 {
  58 + compatible = "intel,mid-uart";
  59 + reg = <0xff010180 0x100>;
  60 + reg-shift = <0>;
  61 + clock-frequency = <29491200>;
  62 + current-speed = <115200>;
  63 + };
  64 +
  65 + emmc: mmc@ff3fc000 {
  66 + compatible = "intel,sdhci-tangier";
  67 + reg = <0xff3fc000 0x1000>;
  68 + };
  69 +
  70 +/*
  71 + * FIXME: For now U-Boot DM model doesn't allow to power up this controller.
  72 + * Enabling it will make U-Boot hang.
  73 + *
  74 + sdcard: mmc@ff3fa000 {
  75 + compatible = "intel,sdhci-tangier";
  76 + reg = <0xff3fa000 0x1000>;
  77 + };
  78 + */
  79 +
  80 + pmu: power@ff00b000 {
  81 + compatible = "intel,pmu-mid";
  82 + reg = <0xff00b000 0x1000>;
  83 + };
  84 +
  85 + scu: ipc@ff009000 {
  86 + compatible = "intel,scu-ipc";
  87 + reg = <0xff009000 0x1000>;
  88 + };
  89 +};
... ... @@ -35,6 +35,13 @@
35 35 Intel Platform Controller Hub EG20T, other system components and
36 36 peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS.
37 37  
  38 +config TARGET_EDISON
  39 + bool "Edison"
  40 + help
  41 + This is the Intel Edison Compute Module. It contains a dual core Intel
  42 + Atom Tangier CPU, 1 GB RAM integrated on package. There is also 4 GB
  43 + eMMC flash on board, Wi-Fi, Bluetooth 4 and USB controllers.
  44 +
38 45 config TARGET_GALILEO
39 46 bool "Galileo"
40 47 help
... ... @@ -64,6 +71,7 @@
64 71 source "board/intel/bayleybay/Kconfig"
65 72 source "board/intel/cougarcanyon2/Kconfig"
66 73 source "board/intel/crownbay/Kconfig"
  74 +source "board/intel/edison/Kconfig"
67 75 source "board/intel/galileo/Kconfig"
68 76 source "board/intel/minnowmax/Kconfig"
69 77  
board/intel/edison/Kconfig
Diff comments   View file @ 495f377
  1 +if TARGET_EDISON
  2 +
  3 +config SYS_BOARD
  4 + default "edison"
  5 +
  6 +config SYS_VENDOR
  7 + default "intel"
  8 +
  9 +config SYS_SOC
  10 + default "tangier"
  11 +
  12 +config SYS_CONFIG_NAME
  13 + default "edison"
  14 +
  15 +config SYS_TEXT_BASE
  16 + default 0x01101000
  17 +
  18 +config BOARD_SPECIFIC_OPTIONS # dummy
  19 + def_bool y
  20 + select X86_LOAD_FROM_32_BIT
  21 + select INTEL_MID
  22 + select INTEL_TANGIER
  23 + select BOARD_LATE_INIT
  24 + select MD5
  25 +
  26 +endif
board/intel/edison/MAINTAINERS
Diff comments   View file @ 495f377
  1 +Intel Edison Board
  2 +M: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
  3 +S: Maintained
  4 +F: board/intel/edison
  5 +F: include/configs/edison.h
  6 +F: configs/edison_defconfig
board/intel/edison/Makefile
Diff comments   View file @ 495f377
  1 +#
  2 +# Copyright (c) 2017 Intel Corporation
  3 +#
  4 +# SPDX-License-Identifier: GPL-2.0+
  5 +#
  6 +
  7 +obj-y += start.o edison.o
board/intel/edison/config.mk
Diff comments   View file @ 495f377
  1 +#
  2 +# Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
  3 +# Copyright (c) 2017 Intel Corporation
  4 +#
  5 +# SPDX-License-Identifier: GPL-2.0 BSD-3-Clause
  6 +#
  7 +
  8 +# Add 4096 bytes of zeroes to u-boot.bin
  9 +quiet_cmd_mkalign_eds = EDSALGN $@
  10 +cmd_mkalign_eds = \
  11 + dd if=$^ of=$@ bs=4k seek=1 2>/dev/null && \
  12 + mv $@ $^
  13 +
  14 +ALL-y += u-boot-align.bin
  15 +u-boot-align.bin: u-boot.bin
  16 + $(call if_changed,mkalign_eds)
  17 +
  18 +HOSTCFLAGS_autoconf.mk.dep = -Wno-variadic-macros
board/intel/edison/edison.c
Diff comments   View file @ 495f377
  1 +/*
  2 + * Copyright (c) 2017 Intel Corporation
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +#include <common.h>
  7 +#include <dwc3-uboot.h>
  8 +#include <mmc.h>
  9 +#include <u-boot/md5.h>
  10 +#include <usb.h>
  11 +#include <watchdog.h>
  12 +
  13 +#include <linux/usb/gadget.h>
  14 +
  15 +#include <asm/cache.h>
  16 +#include <asm/scu.h>
  17 +#include <asm/u-boot-x86.h>
  18 +
  19 +DECLARE_GLOBAL_DATA_PTR;
  20 +
  21 +static struct dwc3_device dwc3_device_data = {
  22 + .maximum_speed = USB_SPEED_HIGH,
  23 + .base = CONFIG_SYS_USB_OTG_BASE,
  24 + .dr_mode = USB_DR_MODE_PERIPHERAL,
  25 + .index = 0,
  26 +};
  27 +
  28 +int usb_gadget_handle_interrupts(int controller_index)
  29 +{
  30 + dwc3_uboot_handle_interrupt(controller_index);
  31 + WATCHDOG_RESET();
  32 + return 0;
  33 +}
  34 +
  35 +int board_usb_init(int index, enum usb_init_type init)
  36 +{
  37 + if (index == 0 && init == USB_INIT_DEVICE)
  38 + return dwc3_uboot_init(&dwc3_device_data);
  39 + return -EINVAL;
  40 +}
  41 +
  42 +int board_usb_cleanup(int index, enum usb_init_type init)
  43 +{
  44 + if (index == 0 && init == USB_INIT_DEVICE) {
  45 + dwc3_uboot_exit(index);
  46 + return 0;
  47 + }
  48 + return -EINVAL;
  49 +}
  50 +
  51 +static void assign_serial(void)
  52 +{
  53 + struct mmc *mmc = find_mmc_device(0);
  54 + unsigned char ssn[16];
  55 + char usb0addr[18];
  56 + char serial[33];
  57 + int i;
  58 +
  59 + if (!mmc)
  60 + return;
  61 +
  62 + md5((unsigned char *)mmc->cid, sizeof(mmc->cid), ssn);
  63 +
  64 + snprintf(usb0addr, sizeof(usb0addr), "02:00:86:%02x:%02x:%02x",
  65 + ssn[13], ssn[14], ssn[15]);
  66 + setenv("usb0addr", usb0addr);
  67 +
  68 + for (i = 0; i < 16; i++)
  69 + snprintf(&serial[2 * i], 3, "%02x", ssn[i]);
  70 + setenv("serial#", serial);
  71 +
  72 +#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE)
  73 + saveenv();
  74 +#endif
  75 +}
  76 +
  77 +static void assign_hardware_id(void)
  78 +{
  79 + struct ipc_ifwi_version v;
  80 + char hardware_id[4];
  81 + int ret;
  82 +
  83 + ret = scu_ipc_command(IPCMSG_GET_FW_REVISION, 1, NULL, 0, (u32 *)&v, 4);
  84 + if (ret < 0)
  85 + printf("Can't retrieve hardware revision\n");
  86 +
  87 + snprintf(hardware_id, sizeof(hardware_id), "%02X", v.hardware_id);
  88 + setenv("hardware_id", hardware_id);
  89 +
  90 +#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE)
  91 + saveenv();
  92 +#endif
  93 +}
  94 +
  95 +int board_late_init(void)
  96 +{
  97 + if (!getenv("serial#"))
  98 + assign_serial();
  99 +
  100 + if (!getenv("hardware_id"))
  101 + assign_hardware_id();
  102 +
  103 + return 0;
  104 +}
board/intel/edison/start.S
Diff comments   View file @ 495f377
  1 +/*
  2 + * Copyright (c) 2011 The Chromium OS Authors.
  3 + * (C) Copyright 2008
  4 + * Graeme Russ, graeme.russ@gmail.com.
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +/* board early intialization */
  10 +.globl early_board_init
  11 +early_board_init:
  12 + /* No 32-bit board specific initialisation */
  13 + jmp early_board_init_ret
configs/edison_defconfig
Diff comments   View file @ 495f377
  1 +CONFIG_X86=y
  2 +CONFIG_VENDOR_INTEL=y
  3 +CONFIG_DEFAULT_DEVICE_TREE="edison"
  4 +CONFIG_TARGET_EDISON=y
  5 +CONFIG_SMP=y
  6 +# CONFIG_ARCH_EARLY_INIT_R is not set
  7 +# CONFIG_BOARD_EARLY_INIT_F is not set
  8 +CONFIG_HUSH_PARSER=y
  9 +CONFIG_CMD_CPU=y
  10 +# CONFIG_CMD_IMLS is not set
  11 +CONFIG_CMD_ASKENV=y
  12 +CONFIG_CMD_GREPENV=y
  13 +CONFIG_CMD_ENV_CALLBACK=y
  14 +CONFIG_CMD_ENV_FLAGS=y
  15 +CONFIG_CMD_MEMINFO=y
  16 +# CONFIG_CMD_FLASH is not set
  17 +CONFIG_CMD_GPT=y
  18 +CONFIG_CMD_MMC=y
  19 +CONFIG_CMD_PART=y
  20 +CONFIG_CMD_DFU=y
  21 +# CONFIG_CMD_NFS is not set
  22 +CONFIG_CMD_TIMER=y
  23 +CONFIG_CMD_HASH=y
  24 +CONFIG_CMD_EXT4=y
  25 +CONFIG_CMD_EXT4_WRITE=y
  26 +CONFIG_CMD_FAT=y
  27 +CONFIG_CMD_FS_GENERIC=y
  28 +CONFIG_OF_CONTROL=y
  29 +CONFIG_OF_EMBED=y
  30 +CONFIG_CPU=y
  31 +CONFIG_DFU_MMC=y
  32 +CONFIG_DFU_RAM=y
  33 +CONFIG_MMC=y
  34 +CONFIG_DM_MMC=y
  35 +CONFIG_MMC_SDHCI=y
  36 +CONFIG_MMC_SDHCI_SDMA=y
  37 +CONFIG_MMC_SDHCI_TANGIER=y
  38 +CONFIG_DM_PCI=y
  39 +CONFIG_DM_PCI_COMPAT=y
  40 +CONFIG_DM_RTC=y
  41 +CONFIG_INTEL_MID_SERIAL=y
  42 +CONFIG_TIMER=y
  43 +CONFIG_USB_DWC3=y
  44 +CONFIG_USB_DWC3_GADGET=y
  45 +CONFIG_USB_GADGET=y
  46 +CONFIG_USB_GADGET_DOWNLOAD=y
  47 +CONFIG_G_DNL_MANUFACTURER="Intel"
  48 +CONFIG_G_DNL_VENDOR_NUM=0x8087
  49 +CONFIG_G_DNL_PRODUCT_NUM=0x0a99
  50 +CONFIG_TANGIER_WATCHDOG=y
  51 +CONFIG_FAT_WRITE=y
  52 +CONFIG_USE_PRIVATE_LIBGCC=y
  53 +CONFIG_SHA1=y
... ... @@ -18,6 +18,8 @@
18 18 work with minimal adjustments on other x86 boards since coreboot deals with
19 19 most of the low-level details.
20 20  
  21 +U-Boot is a main bootloader on Intel Edison board.
  22 +
21 23 U-Boot also supports booting directly from x86 reset vector, without coreboot.
22 24 In this case, known as bare mode, from the fact that it runs on the
23 25 'bare metal', U-Boot acts like a BIOS replacement. The following platforms
... ... @@ -61,6 +63,16 @@
61 63 to point to a new board. You can also change the Cache-As-RAM (CAR) related
62 64 settings here if the default values do not fit your new board.
63 65  
  66 +Build Instructions for U-Boot as main bootloader
  67 +------------------------------------------------
  68 +
  69 +Intel Edison instructions:
  70 +
  71 +Simple you can build U-Boot and obtain u-boot.bin
  72 +
  73 +$ make edison_defconfig
  74 +$ make all
  75 +
64 76 Build Instructions for U-Boot as BIOS replacement (bare mode)
65 77 -------------------------------------------------------------
66 78 Building a ROM version of U-Boot (hereafter referred to as u-boot.rom) is a
... ... @@ -454,6 +466,33 @@
454 466 'zboot' can be used to boot the kernel:
455 467  
456 468 => zboot 01000000 - 04000000 1b1ab50
  469 +
  470 +Updating U-Boot on Edison
  471 +-------------------------
  472 +By default Intel Edison boards are shipped with preinstalled heavily
  473 +patched U-Boot v2014.04. Though it supports DFU which we may be able to
  474 +use.
  475 +
  476 +1. Prepare u-boot.bin as described in chapter above. You still need one
  477 +more step (if and only if you have original U-Boot), i.e. run the
  478 +following command:
  479 +
  480 +$ truncate -s %4096 u-boot.bin
  481 +
  482 +2. Run your board and interrupt booting to U-Boot console. In the console
  483 +call:
  484 +
  485 + => run do_force_flash_os
  486 +
  487 +3. Wait for few seconds, it will prepare environment variable and runs
  488 +DFU. Run DFU command from the host system:
  489 +
  490 +$ dfu-util -v -d 8087:0a99 --alt u-boot0 -D u-boot.bin
  491 +
  492 +4. Return to U-Boot console and following hint. i.e. push Ctrl+C, and
  493 +reset the board:
  494 +
  495 + => reset
457 496  
458 497 CPU Microcode
459 498 -------------
include/configs/edison.h
Diff comments   View file @ 495f377
  1 +/*
  2 + * Copyright (c) 2017 Intel Corp.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef __CONFIG_H
  8 +#define __CONFIG_H
  9 +
  10 +#include <asm/ibmpc.h>
  11 +
  12 +/* Boot */
  13 +#define CONFIG_CMD_ZBOOT
  14 +#define CONFIG_BOOTCOMMAND "run bootcmd"
  15 +
  16 +/* DISK Partition support */
  17 +#define CONFIG_RANDOM_UUID
  18 +
  19 +/* Miscellaneous configurable options */
  20 +#define CONFIG_SYS_LONGHELP
  21 +
  22 +#define CONFIG_SYS_CBSIZE 2048
  23 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  24 +#define CONFIG_SYS_MAXARGS 128
  25 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  26 +
  27 +#define CONFIG_AUTO_COMPLETE
  28 +
  29 +/* Memory */
  30 +#define CONFIG_SYS_LOAD_ADDR 0x100000
  31 +#define CONFIG_PHYSMEM
  32 +
  33 +#define CONFIG_NR_DRAM_BANKS 3
  34 +
  35 +#define CONFIG_SYS_STACK_SIZE (32 * 1024)
  36 +
  37 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  38 +#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
  39 +
  40 +#define CONFIG_SYS_MALLOC_LEN (128 * 1024 * 1024)
  41 +
  42 +#define CONFIG_SYS_MEMTEST_START 0x00100000
  43 +#define CONFIG_SYS_MEMTEST_END 0x01000000
  44 +
  45 +/* Environment */
  46 +#define CONFIG_ENV_IS_IN_MMC
  47 +#define CONFIG_SYS_MMC_ENV_DEV 0
  48 +#define CONFIG_SYS_MMC_ENV_PART 0
  49 +#define CONFIG_ENV_SIZE (64 * 1024)
  50 +#define CONFIG_ENV_OFFSET (3 * 1024 * 1024)
  51 +#define CONFIG_ENV_OFFSET_REDUND (6 * 1024 * 1024)
  52 +#define CONFIG_SUPPORT_EMMC_BOOT
  53 +
  54 +/* PCI */
  55 +#define CONFIG_CMD_PCI
  56 +
  57 +/* RTC */
  58 +#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0
  59 +#define CONFIG_RTC_MC146818
  60 +
  61 +#endif