Eric Lee / smarc-uboot

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Commit 49f783650020c62fdba4a78d4d272dca22d33662

Authored by Heiko Schocher
Committed by Tom Rini
1 parent 847e6693cc
Exists in master and in 53 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

arm, am33xx: move rtc32k_enable() to common place 

move rtc32k_enable() to common place so all am33xx boards can use it.

Signed-off-by: Heiko Schocher <hs@denx.de>
Cc: Matt Porter <mporter@ti.com>
Cc: Lars Poeschel <poeschel@lemonage.de>
Cc: Tom Rini <trini@ti.com>
Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com>

Showing 6 changed files with 20 additions and 64 deletions Side-by-side Diff

arch/arm/cpu/armv7/am33xx/board.c
Diff comments   View file @ 49f7836
... ... @@ -149,4 +149,22 @@
149 149 #endif
150 150 return 0;
151 151 }
  152 +
  153 +#ifdef CONFIG_SPL_BUILD
  154 +void rtc32k_enable(void)
  155 +{
  156 + struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
  157 +
  158 + /*
  159 + * Unlock the RTC's registers. For more details please see the
  160 + * RTC_SS section of the TRM. In order to unlock we need to
  161 + * write these specific values (keys) in this order.
  162 + */
  163 + writel(0x83e70b13, &rtc->kick0r);
  164 + writel(0x95a4f1e0, &rtc->kick1r);
  165 +
  166 + /* Enable the RTC 32K OSC by setting bits 3 and 6. */
  167 + writel((1 << 3) | (1 << 6), &rtc->osc);
  168 +}
  169 +#endif
arch/arm/include/asm/arch-am33xx/sys_proto.h
Diff comments   View file @ 49f7836
... ... @@ -41,5 +41,7 @@
41 41 void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
42 42 u32 size);
43 43 void omap_nand_switch_ecc(uint32_t, uint32_t);
  44 +
  45 +void rtc32k_enable(void);
44 46 #endif
board/isee/igep0033/board.c
Diff comments   View file @ 49f7836
... ... @@ -51,22 +51,6 @@
51 51 #define UART_CLK_RUNNING_MASK 0x1
52 52 #define UART_SMART_IDLE_EN (0x1 << 0x3)
53 53  
54   -static void rtc32k_enable(void)
55   -{
56   - struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
57   -
58   - /*
59   - * Unlock the RTC's registers. For more details please see the
60   - * RTC_SS section of the TRM. In order to unlock we need to
61   - * write these specific values (keys) in this order.
62   - */
63   - writel(0x83e70b13, &rtc->kick0r);
64   - writel(0x95a4f1e0, &rtc->kick1r);
65   -
66   - /* Enable the RTC 32K OSC by setting bits 3 and 6. */
67   - writel((1 << 3) | (1 << 6), &rtc->osc);
68   -}
69   -
70 54 static const struct ddr_data ddr3_data = {
71 55 .datardsratio0 = K4B2G1646EBIH9_RD_DQS,
72 56 .datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
board/phytec/pcm051/board.c
Diff comments   View file @ 49f7836
... ... @@ -59,22 +59,6 @@
59 59 /* DDR RAM defines */
60 60 #define DDR_CLK_MHZ 303 /* DDR_DPLL_MULT value */
61 61  
62   -static void rtc32k_enable(void)
63   -{
64   - struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
65   -
66   - /*
67   - * Unlock the RTC's registers. For more details please see the
68   - * RTC_SS section of the TRM. In order to unlock we need to
69   - * write these specific values (keys) in this order.
70   - */
71   - writel(0x83e70b13, &rtc->kick0r);
72   - writel(0x95a4f1e0, &rtc->kick1r);
73   -
74   - /* Enable the RTC 32K OSC by setting bits 3 and 6. */
75   - writel((1 << 3) | (1 << 6), &rtc->osc);
76   -}
77   -
78 62 static const struct ddr_data ddr3_data = {
79 63 .datardsratio0 = MT41J256M8HX15E_RD_DQS,
80 64 .datawdsratio0 = MT41J256M8HX15E_WR_DQS,
board/ti/am335x/board.c
Diff comments   View file @ 49f7836
... ... @@ -132,22 +132,6 @@
132 132 #define UART_CLK_RUNNING_MASK 0x1
133 133 #define UART_SMART_IDLE_EN (0x1 << 0x3)
134 134  
135   -static void rtc32k_enable(void)
136   -{
137   - struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
138   -
139   - /*
140   - * Unlock the RTC's registers. For more details please see the
141   - * RTC_SS section of the TRM. In order to unlock we need to
142   - * write these specific values (keys) in this order.
143   - */
144   - writel(0x83e70b13, &rtc->kick0r);
145   - writel(0x95a4f1e0, &rtc->kick1r);
146   -
147   - /* Enable the RTC 32K OSC by setting bits 3 and 6. */
148   - writel((1 << 3) | (1 << 6), &rtc->osc);
149   -}
150   -
151 135 static const struct ddr_data ddr2_data = {
152 136 .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
153 137 (MT47H128M16RT25E_RD_DQS<<20) |
board/ti/ti814x/evm.c
Diff comments   View file @ 49f7836
... ... @@ -48,22 +48,6 @@
48 48 #define UART_CLK_RUNNING_MASK 0x1
49 49 #define UART_SMART_IDLE_EN (0x1 << 0x3)
50 50  
51   -static void rtc32k_enable(void)
52   -{
53   - struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE;
54   -
55   - /*
56   - * Unlock the RTC's registers. For more details please see the
57   - * RTC_SS section of the TRM. In order to unlock we need to
58   - * write these specific values (keys) in this order.
59   - */
60   - writel(0x83e70b13, &rtc->kick0r);
61   - writel(0x95a4f1e0, &rtc->kick1r);
62   -
63   - /* Enable the RTC 32K OSC by setting bits 3 and 6. */
64   - writel((1 << 3) | (1 << 6), &rtc->osc);
65   -}
66   -
67 51 static void uart_enable(void)
68 52 {
69 53 u32 regVal;