Commit 4a48cfc4e57b4b247d94a614b2fbfcf03aa45ea1

Authored by Stanislav Galabov
Committed by Daniel Schwierzeck
1 parent 78757d52c8

Add support for 64-bit MIPS to examples/standalone

Signed-off-by: Stanislav Galabov <sgalabov@gmail.com>

Showing 1 changed file with 18 additions and 0 deletions Side-by-side Diff

examples/standalone/stubs.c
... ... @@ -65,6 +65,7 @@
65 65 : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "ip");
66 66 #endif
67 67 #elif defined(CONFIG_MIPS)
  68 +#ifdef CONFIG_CPU_MIPS64
68 69 /*
69 70 * k0 ($26) holds the pointer to the global_data; t9 ($25) is a call-
70 71 * clobbered register that is also used to set gp ($26). Note that the
71 72  
... ... @@ -76,10 +77,27 @@
76 77 asm volatile ( \
77 78 " .globl " #x "\n" \
78 79 #x ":\n" \
  80 +" ld $25, %0($26)\n" \
  81 +" ld $25, %1($25)\n" \
  82 +" jr $25\n" \
  83 + : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "t9");
  84 +#else
  85 +/*
  86 + * k0 ($26) holds the pointer to the global_data; t9 ($25) is a call-
  87 + * clobbered register that is also used to set gp ($26). Note that the
  88 + * jr instruction also executes the instruction immediately following
  89 + * it; however, GCC/mips generates an additional `nop' after each asm
  90 + * statement
  91 + */
  92 +#define EXPORT_FUNC(f, a, x, ...) \
  93 + asm volatile ( \
  94 +" .globl " #x "\n" \
  95 +#x ":\n" \
79 96 " lw $25, %0($26)\n" \
80 97 " lw $25, %1($25)\n" \
81 98 " jr $25\n" \
82 99 : : "i"(offsetof(gd_t, jt)), "i"(FO(x)) : "t9");
  100 +#endif
83 101 #elif defined(CONFIG_NIOS2)
84 102 /*
85 103 * gp holds the pointer to the global_data, r8 is call-clobbered