Commit 4a4ef819c20d93699378930592a62a098a42ad82
1 parent
fd90ac4654
Exists in
smarc_8mm-imx_v2019.04_4.19.35_1.1.0
and in
1 other branch
MLK-22179-2 imx8mn_evk: Enable FSPI DQS loopback for high freq
There is an divider on imx8mn will always divide 2 to flexspi root clock. So actual SCLK output to device is 50Mhz on imx8mn not 100Mhz. After changing the root clock setting to configure SCLK to 100Mhz, found the read data is not correct. Must enable the internal DQS pad loopback to fix the problem. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 9ff3ae4f9ebbb81bd42d81729cec4525c6e9b33e)
Showing 3 changed files with 10 additions and 2 deletions Side-by-side Diff
arch/arm/dts/fsl-imx8mn-ddr4-evk.dts
| ... | ... | @@ -73,6 +73,7 @@ |
| 73 | 73 | MX8MN_IOMUXC_NAND_ALE__QSPI_A_SCLK 0x1c4 |
| 74 | 74 | MX8MN_IOMUXC_NAND_CE0_B__QSPI_A_SS0_B 0x84 |
| 75 | 75 | |
| 76 | + MX8MN_IOMUXC_NAND_DQS__QSPI_A_DQS 0x40000084 | |
| 76 | 77 | MX8MN_IOMUXC_NAND_DATA00__QSPI_A_DATA0 0x84 |
| 77 | 78 | MX8MN_IOMUXC_NAND_DATA01__QSPI_A_DATA1 0x84 |
| 78 | 79 | MX8MN_IOMUXC_NAND_DATA02__QSPI_A_DATA2 0x84 |
arch/arm/mach-imx/imx8m/clock_imx8mm.c
| ... | ... | @@ -728,8 +728,14 @@ |
| 728 | 728 | * sys pll1 100M |
| 729 | 729 | */ |
| 730 | 730 | clock_enable(CCGR_QSPI, 0); |
| 731 | - clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON | | |
| 732 | - CLK_ROOT_SOURCE_SEL(7)); | |
| 731 | + | |
| 732 | + if (is_imx8mn()) { | |
| 733 | + clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON | | |
| 734 | + CLK_ROOT_SOURCE_SEL(1) | CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2)); | |
| 735 | + } else { | |
| 736 | + clock_set_target_val(QSPI_CLK_ROOT, CLK_ROOT_ON | | |
| 737 | + CLK_ROOT_SOURCE_SEL(7)); | |
| 738 | + } | |
| 733 | 739 | clock_enable(CCGR_QSPI, 1); |
| 734 | 740 | |
| 735 | 741 | return 0; |
include/configs/imx8mn_evk.h