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Commit 4a68489e12313a7fa8740463dee0eea2985eb563

Authored by Shengzhou Liu
Committed by York Sun
1 parent 074596c0b5
Exists in v2017.01-smarct4x and in 25 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2017.01-smarct3x, v2017.01-smarct3x-emmc

drivers/ddr/fsl: update workaround for erratum A-008511 

Per the latest erratum document, update step 4 and step 8, only
DEBUG_29[21] is changed, all other bits should not be changed.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

Showing 2 changed files with 10 additions and 3 deletions Side-by-side Diff

drivers/ddr/fsl/fsl_ddr_gen4.c
Diff comments   View file @ 4a68489
... ... @@ -240,8 +240,10 @@
240 240 /* Disable DRAM VRef training */
241 241 ddr_out32(&ddr->ddr_cdr2,
242 242 regs->ddr_cdr2 & ~DDR_CDR2_VREF_TRAIN_EN);
243   - /* Disable deskew */
244   - ddr_out32(&ddr->debug[28], 0x400);
  243 + /* disable transmit bit deskew */
  244 + temp32 = ddr_in32(&ddr->debug[28]);
  245 + temp32 |= DDR_TX_BD_DIS;
  246 + ddr_out32(&ddr->debug[28], temp32);
245 247 /* Disable D_INIT */
246 248 ddr_out32(&ddr->sdram_cfg_2,
247 249 regs->ddr_sdram_cfg_2 & ~SDRAM_CFG2_D_INIT);
... ... @@ -358,7 +360,9 @@
358 360 debug("MR6 = 0x%08x\n", temp32);
359 361 }
360 362 ddr_out32(&ddr->sdram_md_cntl, 0);
361   - ddr_out32(&ddr->debug[28], 0); /* Enable deskew */
  363 + temp32 = ddr_in32(&ddr->debug[28]);
  364 + temp32 &= ~DDR_TX_BD_DIS; /* Enable deskew */
  365 + ddr_out32(&ddr->debug[28], temp32);
362 366 ddr_out32(&ddr->debug[1], 0x400); /* restart deskew */
363 367 /* wait for idle */
364 368 timeout = 40;
include/fsl_ddr_sdram.h
Diff comments   View file @ 4a68489
... ... @@ -189,6 +189,9 @@
189 189 #define DDR_MR5_CA_PARITY_LAT_4_CLK 0x1 /* for DDR4-1600/1866/2133 */
190 190 #define DDR_MR5_CA_PARITY_LAT_5_CLK 0x2 /* for DDR4-2400 */
191 191  
  192 +/* DEBUG_29 register */
  193 +#define DDR_TX_BD_DIS (1 << 10) /* Transmit Bit Deskew Disable */
  194 +
192 195  
193 196 #if (defined(CONFIG_SYS_FSL_DDR_VER) && \
194 197 (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7))