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Commit 4ab333b765db5cd00b297b4c0e3cd3af5fe320fc

Authored by Marek Vasut
1 parent 97ce274d97
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

arm: socfpga: Move cache_enable to CPU code 

Move icache_enable() and dcache_enable() function calls from
board code into the CPU code and into the enable_caches()
function. This is how the cache enabling code was designed
to work.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@altera.com>
Cc: Pavel Machek <pavel@denx.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
Cc: Albert Aribaud <albert.u.boot@aribaud.net>
Cc: Wolfgang Denk <wd@denx.de>
Acked-by: Pavel Machek <pavel@denx.de>

Showing 2 changed files with 10 additions and 3 deletions Inline Diff

arch/arm/cpu/armv7/socfpga/misc.c
Diff comments   View file @ 4ab333b
1 /* 1 /*
2 * Copyright (C) 2012 Altera Corporation <www.altera.com> 2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #include <common.h> 7 #include <common.h>
8 #include <asm/io.h> 8 #include <asm/io.h>
9 #include <altera.h> 9 #include <altera.h>
10 #include <miiphy.h> 10 #include <miiphy.h>
11 #include <netdev.h> 11 #include <netdev.h>
12 #include <asm/arch/reset_manager.h> 12 #include <asm/arch/reset_manager.h>
13 #include <asm/arch/system_manager.h> 13 #include <asm/arch/system_manager.h>
14 #include <asm/arch/dwmmc.h> 14 #include <asm/arch/dwmmc.h>
15 #include <asm/arch/nic301.h> 15 #include <asm/arch/nic301.h>
16 #include <asm/arch/scu.h> 16 #include <asm/arch/scu.h>
17 #include <asm/pl310.h> 17 #include <asm/pl310.h>
18 18
19 DECLARE_GLOBAL_DATA_PTR; 19 DECLARE_GLOBAL_DATA_PTR;
20 20
21 static struct pl310_regs *const pl310 = 21 static struct pl310_regs *const pl310 =
22 (struct pl310_regs *)CONFIG_SYS_PL310_BASE; 22 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
23 static struct socfpga_system_manager *sysmgr_regs = 23 static struct socfpga_system_manager *sysmgr_regs =
24 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; 24 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
25 static struct nic301_registers *nic301_regs = 25 static struct nic301_registers *nic301_regs =
26 (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; 26 (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
27 static struct scu_registers *scu_regs = 27 static struct scu_registers *scu_regs =
28 (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; 28 (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
29 29
30 int dram_init(void) 30 int dram_init(void)
31 { 31 {
32 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); 32 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
33 return 0; 33 return 0;
34 } 34 }
35 35
36 void enable_caches(void)
37 {
38 #ifndef CONFIG_SYS_ICACHE_OFF
39 icache_enable();
40 #endif
41 #ifndef CONFIG_SYS_DCACHE_OFF
42 dcache_enable();
43 #endif
44 }
45
36 /* 46 /*
37 * DesignWare Ethernet initialization 47 * DesignWare Ethernet initialization
38 */ 48 */
39 #ifdef CONFIG_DESIGNWARE_ETH 49 #ifdef CONFIG_DESIGNWARE_ETH
40 int cpu_eth_init(bd_t *bis) 50 int cpu_eth_init(bd_t *bis)
41 { 51 {
42 #if CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS 52 #if CONFIG_EMAC_BASE == SOCFPGA_EMAC0_ADDRESS
43 const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB; 53 const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL0_LSB;
44 #elif CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS 54 #elif CONFIG_EMAC_BASE == SOCFPGA_EMAC1_ADDRESS
45 const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB; 55 const int physhift = SYSMGR_EMACGRP_CTRL_PHYSEL1_LSB;
46 #else 56 #else
47 #error "Incorrect CONFIG_EMAC_BASE value!" 57 #error "Incorrect CONFIG_EMAC_BASE value!"
48 #endif 58 #endif
49 59
50 /* Initialize EMAC. This needs to be done at least once per boot. */ 60 /* Initialize EMAC. This needs to be done at least once per boot. */
51 61
52 /* 62 /*
53 * Putting the EMAC controller to reset when configuring the PHY 63 * Putting the EMAC controller to reset when configuring the PHY
54 * interface select at System Manager 64 * interface select at System Manager
55 */ 65 */
56 socfpga_emac_reset(1); 66 socfpga_emac_reset(1);
57 67
58 /* Clearing emac0 PHY interface select to 0 */ 68 /* Clearing emac0 PHY interface select to 0 */
59 clrbits_le32(&sysmgr_regs->emacgrp_ctrl, 69 clrbits_le32(&sysmgr_regs->emacgrp_ctrl,
60 SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift); 70 SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << physhift);
61 71
62 /* configure to PHY interface select choosed */ 72 /* configure to PHY interface select choosed */
63 setbits_le32(&sysmgr_regs->emacgrp_ctrl, 73 setbits_le32(&sysmgr_regs->emacgrp_ctrl,
64 SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift); 74 SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII << physhift);
65 75
66 /* Release the EMAC controller from reset */ 76 /* Release the EMAC controller from reset */
67 socfpga_emac_reset(0); 77 socfpga_emac_reset(0);
68 78
69 /* initialize and register the emac */ 79 /* initialize and register the emac */
70 return designware_initialize(CONFIG_EMAC_BASE, 80 return designware_initialize(CONFIG_EMAC_BASE,
71 CONFIG_PHY_INTERFACE_MODE); 81 CONFIG_PHY_INTERFACE_MODE);
72 } 82 }
73 #endif 83 #endif
74 84
75 #ifdef CONFIG_DWMMC 85 #ifdef CONFIG_DWMMC
76 /* 86 /*
77 * Initializes MMC controllers. 87 * Initializes MMC controllers.
78 * to override, implement board_mmc_init() 88 * to override, implement board_mmc_init()
79 */ 89 */
80 int cpu_mmc_init(bd_t *bis) 90 int cpu_mmc_init(bd_t *bis)
81 { 91 {
82 return socfpga_dwmmc_init(SOCFPGA_SDMMC_ADDRESS, 92 return socfpga_dwmmc_init(SOCFPGA_SDMMC_ADDRESS,
83 CONFIG_HPS_SDMMC_BUSWIDTH, 0); 93 CONFIG_HPS_SDMMC_BUSWIDTH, 0);
84 } 94 }
85 #endif 95 #endif
86 96
87 #if defined(CONFIG_DISPLAY_CPUINFO) 97 #if defined(CONFIG_DISPLAY_CPUINFO)
88 /* 98 /*
89 * Print CPU information 99 * Print CPU information
90 */ 100 */
91 int print_cpuinfo(void) 101 int print_cpuinfo(void)
92 { 102 {
93 puts("CPU: Altera SoCFPGA Platform\n"); 103 puts("CPU: Altera SoCFPGA Platform\n");
94 return 0; 104 return 0;
95 } 105 }
96 #endif 106 #endif
97 107
98 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \ 108 #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
99 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE) 109 defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
100 int overwrite_console(void) 110 int overwrite_console(void)
101 { 111 {
102 return 0; 112 return 0;
103 } 113 }
104 #endif 114 #endif
105 115
106 #ifdef CONFIG_FPGA 116 #ifdef CONFIG_FPGA
107 /* 117 /*
108 * FPGA programming support for SoC FPGA Cyclone V 118 * FPGA programming support for SoC FPGA Cyclone V
109 */ 119 */
110 static Altera_desc altera_fpga[] = { 120 static Altera_desc altera_fpga[] = {
111 { 121 {
112 /* Family */ 122 /* Family */
113 Altera_SoCFPGA, 123 Altera_SoCFPGA,
114 /* Interface type */ 124 /* Interface type */
115 fast_passive_parallel, 125 fast_passive_parallel,
116 /* No limitation as additional data will be ignored */ 126 /* No limitation as additional data will be ignored */
117 -1, 127 -1,
118 /* No device function table */ 128 /* No device function table */
119 NULL, 129 NULL,
120 /* Base interface address specified in driver */ 130 /* Base interface address specified in driver */
121 NULL, 131 NULL,
122 /* No cookie implementation */ 132 /* No cookie implementation */
123 0 133 0
124 }, 134 },
125 }; 135 };
126 136
127 /* add device descriptor to FPGA device table */ 137 /* add device descriptor to FPGA device table */
128 static void socfpga_fpga_add(void) 138 static void socfpga_fpga_add(void)
129 { 139 {
130 int i; 140 int i;
131 fpga_init(); 141 fpga_init();
132 for (i = 0; i < ARRAY_SIZE(altera_fpga); i++) 142 for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
133 fpga_add(fpga_altera, &altera_fpga[i]); 143 fpga_add(fpga_altera, &altera_fpga[i]);
134 } 144 }
135 #else 145 #else
136 static inline void socfpga_fpga_add(void) {} 146 static inline void socfpga_fpga_add(void) {}
137 #endif 147 #endif
138 148
139 int arch_cpu_init(void) 149 int arch_cpu_init(void)
140 { 150 {
141 /* 151 /*
142 * If the HW watchdog is NOT enabled, make sure it is not running, 152 * If the HW watchdog is NOT enabled, make sure it is not running,
143 * for example because it was enabled in the preloader. This might 153 * for example because it was enabled in the preloader. This might
144 * trigger a watchdog-triggered reboot of Linux kernel later. 154 * trigger a watchdog-triggered reboot of Linux kernel later.
145 */ 155 */
146 #ifndef CONFIG_HW_WATCHDOG 156 #ifndef CONFIG_HW_WATCHDOG
147 socfpga_watchdog_reset(); 157 socfpga_watchdog_reset();
148 #endif 158 #endif
149 return 0; 159 return 0;
150 } 160 }
151 161
152 /* 162 /*
153 * Convert all NIC-301 AMBA slaves from secure to non-secure 163 * Convert all NIC-301 AMBA slaves from secure to non-secure
154 */ 164 */
155 static void socfpga_nic301_slave_ns(void) 165 static void socfpga_nic301_slave_ns(void)
156 { 166 {
157 writel(0x1, &nic301_regs->lwhps2fpgaregs); 167 writel(0x1, &nic301_regs->lwhps2fpgaregs);
158 writel(0x1, &nic301_regs->hps2fpgaregs); 168 writel(0x1, &nic301_regs->hps2fpgaregs);
159 writel(0x1, &nic301_regs->acp); 169 writel(0x1, &nic301_regs->acp);
160 writel(0x1, &nic301_regs->rom); 170 writel(0x1, &nic301_regs->rom);
161 writel(0x1, &nic301_regs->ocram); 171 writel(0x1, &nic301_regs->ocram);
162 writel(0x1, &nic301_regs->sdrdata); 172 writel(0x1, &nic301_regs->sdrdata);
163 } 173 }
164 174
165 int misc_init_r(void) 175 int misc_init_r(void)
166 { 176 {
167 socfpga_bridges_reset(1); 177 socfpga_bridges_reset(1);
168 socfpga_nic301_slave_ns(); 178 socfpga_nic301_slave_ns();
169 179
170 /* 180 /*
171 * Private components security: 181 * Private components security:
172 * U-Boot : configure private timer, global timer and cpu component 182 * U-Boot : configure private timer, global timer and cpu component
173 * access as non secure for kernel stage (as required by Linux) 183 * access as non secure for kernel stage (as required by Linux)
174 */ 184 */
175 setbits_le32(&scu_regs->sacr, 0xfff); 185 setbits_le32(&scu_regs->sacr, 0xfff);
176 186
177 /* Configure the L2 controller to make SDRAM start at 0 */ 187 /* Configure the L2 controller to make SDRAM start at 0 */
178 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET 188 #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
179 writel(0x2, &nic301_regs->remap); 189 writel(0x2, &nic301_regs->remap);
180 #else 190 #else
181 writel(0x1, &nic301_regs->remap); /* remap.mpuzero */ 191 writel(0x1, &nic301_regs->remap); /* remap.mpuzero */
182 writel(0x1, &pl310->pl310_addr_filter_start); 192 writel(0x1, &pl310->pl310_addr_filter_start);
183 #endif 193 #endif
184 194
185 /* Add device descriptor to FPGA device table */ 195 /* Add device descriptor to FPGA device table */
186 socfpga_fpga_add(); 196 socfpga_fpga_add();
187 return 0; 197 return 0;
188 } 198 }
189 199
board/altera/socfpga/socfpga_cyclone5.c
Diff comments   View file @ 4ab333b
1 /* 1 /*
2 * Copyright (C) 2012 Altera Corporation <www.altera.com> 2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
3 * 3 *
4 * SPDX-License-Identifier: GPL-2.0+ 4 * SPDX-License-Identifier: GPL-2.0+
5 */ 5 */
6 6
7 #include <common.h> 7 #include <common.h>
8 #include <asm/arch/reset_manager.h> 8 #include <asm/arch/reset_manager.h>
9 #include <asm/io.h> 9 #include <asm/io.h>
10 10
11 #include <netdev.h> 11 #include <netdev.h>
12 12
13 DECLARE_GLOBAL_DATA_PTR; 13 DECLARE_GLOBAL_DATA_PTR;
14 14
15 /* 15 /*
16 * Print Board information 16 * Print Board information
17 */ 17 */
18 int checkboard(void) 18 int checkboard(void)
19 { 19 {
20 puts("BOARD: Altera SoCFPGA Cyclone5 Board\n"); 20 puts("BOARD: Altera SoCFPGA Cyclone5 Board\n");
21 return 0; 21 return 0;
22 } 22 }
23 23
24 /* 24 /*
25 * Initialization function which happen at early stage of c code 25 * Initialization function which happen at early stage of c code
26 */ 26 */
27 int board_early_init_f(void) 27 int board_early_init_f(void)
28 { 28 {
29 return 0; 29 return 0;
30 } 30 }
31 31
32 /* 32 /*
33 * Miscellaneous platform dependent initialisations 33 * Miscellaneous platform dependent initialisations
34 */ 34 */
35 int board_init(void) 35 int board_init(void)
36 { 36 {
37 icache_enable();
38 dcache_enable();
39
40 /* Address of boot parameters for ATAG (if ATAG is used) */ 37 /* Address of boot parameters for ATAG (if ATAG is used) */
41 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 38 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
42 39
43 return 0; 40 return 0;
44 } 41 }
45 42