arm: socfpga: Move cache_enable to CPU code

Move icache_enable() and dcache_enable() function calls from board code into the CPU code and into the enable_caches() function. This is how the cache enabling code was designed to work. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Wolfgang Denk <wd@denx.de> Acked-by: Pavel Machek <pavel@denx.de>

arm: socfpga: Move cache_enable to CPU code
Move icache_enable() and dcache_enable() function calls from board code into the CPU code and into the enable_caches() function. This is how the cache enabling code was designed to work. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Wolfgang Denk <wd@denx.de> Acked-by: Pavel Machek <pavel@denx.de>
Marek Vasut
1 parent 97ce274d97
Showing 2 changed files with 10 additions and 3 deletions Side-by-side Diff
arch/arm/cpu/armv7/socfpga/misc.c
board/altera/socfpga/socfpga_cyclone5.c
@@ -33,6 +33,16 @@
 	return 0;
 }
  
+void enable_caches(void)
+{
+#ifndef CONFIG_SYS_ICACHE_OFF
+	icache_enable();
+#endif
+#ifndef CONFIG_SYS_DCACHE_OFF
+	dcache_enable();
+#endif
+}
+
 /*
  * DesignWare Ethernet initialization
  */
@@ -34,9 +34,6 @@
  */
 int board_init(void)
 {
-	icache_enable();
-	dcache_enable();
-
 	/* Address of boot parameters for ATAG (if ATAG is used) */
 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
...	...	@@ -33,6 +33,16 @@
33	33	return 0;
34	34	}
35	35
	36	+void enable_caches(void)
	37	+{
	38	+#ifndef CONFIG_SYS_ICACHE_OFF
	39	+ icache_enable();
	40	+#endif
	41	+#ifndef CONFIG_SYS_DCACHE_OFF
	42	+ dcache_enable();
	43	+#endif
	44	+}
	45	+
36	46	/*
37	47	* DesignWare Ethernet initialization
38	48	*/
...	...	@@ -34,9 +34,6 @@
34	34	*/
35	35	int board_init(void)
36	36	{
37		- icache_enable();
38		- dcache_enable();
39		-
40	37	/* Address of boot parameters for ATAG (if ATAG is used) */
41	38	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
42	39