mcx: support for HTKW mcx board

This patch adds support for the HTKW mcx AM3517-based board. Serial, Ethernet, NAND, MMC, RTC, EHCI USB host and both NAND and MMC SPLs are supported. Signed-off-by: Ilya Yanok <yanok@emcraft.com> Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Tom Rini <tom.rini@gmail.com> Cc: Detlev Zundel <dzu@denx.de> Acked-by: Igor Grinberg <grinberg@compulab.co.il>

mcx: support for HTKW mcx board
This patch adds support for the HTKW mcx AM3517-based board. Serial, Ethernet, NAND, MMC, RTC, EHCI USB host and both NAND and MMC SPLs are supported. Signed-off-by: Ilya Yanok <yanok@emcraft.com> Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Tom Rini <tom.rini@gmail.com> Cc: Detlev Zundel <dzu@denx.de> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Ilya Yanok · Albert ARIBAUD
1 parent 1fdabedd0c
Showing 6 changed files with 941 additions and 0 deletions Side-by-side Diff
MAINTAINERS
board/htkw/mcx/Makefile
board/htkw/mcx/mcx.c
board/htkw/mcx/mcx.h
boards.cfg
include/configs/mcx.h
@@ -929,6 +929,10 @@
  
 	omap2420h4	ARM1136EJS
  
+Ilya Yanok <yanok@emcraft.com>
+
+	mcx		ARM ARMV7 (AM35x SoC)
+
 Syed Mohammed Khasim <sm.khasim@gmail.com>
 Sughosh Ganu <urwithsughosh@gmail.com>
  
+#
+# Copyright (C) 2011 Ilya Yanok, Emcraft Systems
+#
+# Based on ti/evm/Makefile
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= $(BOARD).o
+
+SRCS	:= $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+/*
+ * Copyright (C) 2011 Ilya Yanok, Emcraft Systems
+ *
+ * Based on ti/evm/evm.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/mux.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-types.h>
+#include <asm/gpio.h>
+#include <asm/omap_gpio.h>
+#include "errno.h"
+#include <i2c.h>
+#ifdef CONFIG_USB_EHCI
+#include <usb.h>
+#include <asm/ehci-omap.h>
+#endif
+#include "mcx.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_USB_EHCI
+static struct omap_usbhs_board_data usbhs_bdata = {
+	.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
+	.port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
+	.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
+};
+
+int ehci_hcd_init(void)
+{
+	return omap_ehci_hcd_init(&usbhs_bdata);
+}
+
+int ehci_hcd_stop(void)
+{
+	return omap_ehci_hcd_stop();
+}
+#endif
+
+/*
+ * Routine: board_init
+ * Description: Early hardware init.
+ */
+int board_init(void)
+{
+	gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+	/* boot param addr */
+	gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+	return 0;
+}
+
+/*
+ * Routine: misc_init_r
+ * Description: late init.
+ */
+int misc_init_r(void)
+{
+	dieid_num_r();
+
+	return 0;
+}
+
+/*
+ * Routine: set_muxconf_regs
+ * Description: Setting up the configuration Mux registers specific to the
+ *		hardware. Many pins need to be moved from protect to primary
+ *		mode.
+ */
+void set_muxconf_regs(void)
+{
+	MUX_MCX();
+}
+
+#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
+int board_mmc_init(bd_t *bis)
+{
+	return omap_mmc_init(0);
+}
+#endif
+
+#ifdef CONFIG_USB_EHCI_OMAP
+#define USB_HOST_PWR_EN		132
+int board_usb_init(void)
+{
+	if (gpio_request(USB_HOST_PWR_EN, "USB_HOST_PWR_EN") < 0) {
+		puts("Failed to get USB_HOST_PWR_EN pin\n");
+		return -ENODEV;
+	}
+	gpio_direction_output(USB_HOST_PWR_EN, 1);
+
+	return 0;
+}
+#endif
+/*
+ * Copyright (C) 2011 Ilya Yanok, Emcraft Systems
+ *
+ * Based on ti/evm/evm.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _AM3517EVM_H_
+#define _AM3517EVM_H_
+
+const omap3_sysinfo sysinfo = {
+	DDR_DISCRETE,
+	"HTKW mcx Board",
+	"NAND",
+};
+
+/*
+ * IEN  - Input Enable
+ * IDIS - Input Disable
+ * PTD  - Pull type Down
+ * PTU  - Pull type Up
+ * DIS  - Pull type selection is inactive
+ * EN   - Pull type selection is active
+ * M0   - Mode 0
+ * The commented string gives the final mux configuration for that pin
+ */
+#define MUX_MCX() \
+	/* SDRC */\
+	MUX_VAL(CP(SDRC_D0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D3),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D4),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D5),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D6),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D7),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D8),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D9),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D10),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D11),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D12),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D13),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D14),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D15),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D16),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D17),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D18),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D19),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D20),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D21),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D22),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D23),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D24),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D25),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D26),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D27),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D28),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D29),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D30),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_D31),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_CLK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS0),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS1),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS2),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS3),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SDRC_DQS0N),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(SDRC_DQS1N),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(SDRC_DQS2N),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(SDRC_DQS3N),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(SDRC_CKE0),		(M0)) \
+	MUX_VAL(CP(SDRC_CKE1),		(M0)) \
+	MUX_VAL(CP(STRBEN_DLY0),	(IEN  | PTD | EN  | M0)) \
+					/*sdrc_strben_dly0*/\
+	MUX_VAL(CP(STRBEN_DLY1),	(IEN  | PTD | EN  | M0)) \
+					/*sdrc_strben_dly1*/\
+	/* GPMC */\
+	MUX_VAL(CP(GPMC_A1),		(IEN | PTU | EN  | M4)) \
+	MUX_VAL(CP(GPMC_A2),		(IEN | PTU | EN  | M4)) \
+	MUX_VAL(CP(GPMC_A3),		(IEN | PTU | EN  | M4)) \
+	MUX_VAL(CP(GPMC_A4),		(IEN | PTU | EN  | M4)) \
+	MUX_VAL(CP(GPMC_A5),		(IEN | PTU | EN  | M4)) \
+	MUX_VAL(CP(GPMC_A6),		(IEN | PTU | EN  | M4)) \
+	MUX_VAL(CP(GPMC_A7),		(IEN | PTU | EN  | M4)) \
+	MUX_VAL(CP(GPMC_A8),		(IEN | PTU | EN  | M4)) \
+	MUX_VAL(CP(GPMC_A9),		(IEN | PTU | EN  | M4)) \
+	MUX_VAL(CP(GPMC_A10),		(IDIS | PTU | DIS | M4)) \
+					/* GPIO_43 LCD buffer enable */ \
+	MUX_VAL(CP(GPMC_D0),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D1),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D2),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D3),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D4),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D5),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D6),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D7),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D8),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D9),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D10),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D11),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D12),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D13),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D14),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_D15),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS0),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NCS1),		(IEN | PTU | EN  | M4)) \
+	MUX_VAL(CP(GPMC_NCS2),		(IEN | PTU | EN  | M4)) \
+	MUX_VAL(CP(GPMC_NCS3),		(IEN | PTU | EN  | M4)) \
+	MUX_VAL(CP(GPMC_NCS4),		(IEN | PTU | EN  | M4))\
+	MUX_VAL(CP(GPMC_NCS5),		(IEN | PTU | EN  | M4)) \
+	MUX_VAL(CP(GPMC_NCS6),		(IEN | PTU | EN  | M4)) \
+					/* GPIO_57 TS_PenIRQn */\
+	MUX_VAL(CP(GPMC_NCS7),		(IEN | PTU | EN  | M4)) \
+					/* GPIO_58 ETHERNET RESET */\
+	MUX_VAL(CP(GPMC_CLK),		(IEN | PTU | EN  | M4)) \
+	MUX_VAL(CP(GPMC_NADV_ALE),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_NOE),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_NWE),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(GPMC_NBE0_CLE),	(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_NBE1),		(IEN  | PTU | DIS  | M4)) \
+					/* GPIO_61 SD-CARD CD */ \
+	MUX_VAL(CP(GPMC_NWP),		(IDIS  | PTU | EN | M4)) \
+			/* GPIO_62 Nand write protect, keep enabled */ \
+	MUX_VAL(CP(GPMC_WAIT0),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(GPMC_WAIT1),		(IEN | PTU | EN  | M4))\
+	MUX_VAL(CP(GPMC_WAIT2),		(IEN  | PTU | EN  | M4))\
+	MUX_VAL(CP(GPMC_WAIT3),		(IEN | PTU | EN  | M4)) \
+					/* GPIO_65 SD-CARD WP */\
+	/* DSS */\
+	MUX_VAL(CP(DSS_PCLK),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_HSYNC),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_VSYNC),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_ACBIAS),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA0),		(IEN | PTU | EN  | M4))\
+	MUX_VAL(CP(DSS_DATA1),		(IEN | PTU | EN  | M4)) \
+	MUX_VAL(CP(DSS_DATA2),		(IEN | PTU | EN  | M4)) \
+	MUX_VAL(CP(DSS_DATA3),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA4),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA5),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA6),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA7),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA8),		(IEN | PTU | EN  | M4)) \
+	MUX_VAL(CP(DSS_DATA9),		(IEN | PTU | EN  | M4)) \
+	MUX_VAL(CP(DSS_DATA10),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA11),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA12),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA13),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA14),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA15),		(IDIS | PTD | DIS | M0))\
+	MUX_VAL(CP(DSS_DATA16),		(IEN | PTU | EN  | M4)) \
+	MUX_VAL(CP(DSS_DATA17),		(IEN | PTU | EN  | M4)) \
+	MUX_VAL(CP(DSS_DATA18),		(IEN | PTU | EN  | M4)) \
+	MUX_VAL(CP(DSS_DATA19),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA20),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA21),		(IDIS | PTD | DIS | M0))  \
+	MUX_VAL(CP(DSS_DATA22),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(DSS_DATA23),		(IDIS | PTD | DIS | M0)) \
+	/* CAMERA */\
+	MUX_VAL(CP(CAM_HS),		(IEN  | PTU | EN  | M4)) \
+	MUX_VAL(CP(CAM_VS),		(IEN  | PTU | EN  | M4)) \
+	MUX_VAL(CP(CAM_XCLKA),		(IEN  | PTD | EN  | M4)) \
+	MUX_VAL(CP(CAM_PCLK),		(IEN  | PTU | EN  | M4)) \
+	MUX_VAL(CP(CAM_FLD),		(IEN  | PTD | EN  | M4)) \
+	MUX_VAL(CP(CAM_D0),		(IEN  | PTD | EN  | M4)) \
+	MUX_VAL(CP(CAM_D1),		(IEN  | PTD | EN  | M4)) \
+	MUX_VAL(CP(CAM_D2),		(IEN  | PTD | EN  | M4)) \
+	MUX_VAL(CP(CAM_D3),		(IEN  | PTD | EN  | M4)) \
+	MUX_VAL(CP(CAM_D4),		(IEN  | PTD | EN  | M4)) \
+	MUX_VAL(CP(CAM_D5),		(IEN  | PTD | EN  | M4)) \
+	MUX_VAL(CP(CAM_D6),		(IEN  | PTD | EN  | M4)) \
+	MUX_VAL(CP(CAM_D7),		(IEN  | PTD | EN  | M4)) \
+	MUX_VAL(CP(CAM_D8),		(IEN  | PTD | EN  | M4)) \
+	MUX_VAL(CP(CAM_D9),		(IEN  | PTD | EN  | M4)) \
+	MUX_VAL(CP(CAM_D10),		(IEN  | PTD | EN  | M4)) \
+	MUX_VAL(CP(CAM_D11),		(IEN  | PTD | EN  | M4)) \
+	MUX_VAL(CP(CAM_XCLKB),		(IEN  | PTD | EN  | M4)) \
+	MUX_VAL(CP(CAM_WEN),		(IEN  | PTD | EN  | M4)) \
+	MUX_VAL(CP(CAM_STROBE),		(IEN  | PTD | EN  | M4)) \
+	MUX_VAL(CP(CSI2_DX0),		(IEN  | PTD | EN  | M4)) \
+	MUX_VAL(CP(CSI2_DY0),		(IEN  | PTD | EN  | M4)) \
+	MUX_VAL(CP(CSI2_DX1),		(IEN  | PTD | EN  | M4)) \
+	MUX_VAL(CP(CSI2_DY1),		(IEN  | PTD | EN  | M4)) \
+	/* MMC */\
+	MUX_VAL(CP(MMC1_CLK),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(MMC1_CMD),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MMC1_DAT0),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MMC1_DAT1),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MMC1_DAT2),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MMC1_DAT3),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MMC1_DAT4),		(IEN  | PTU | EN  | M4)) \
+	MUX_VAL(CP(MMC1_DAT5),		(IEN  | PTU | EN  | M4)) \
+	MUX_VAL(CP(MMC1_DAT6),		(IEN  | PTU | EN  | M4)) \
+	MUX_VAL(CP(MMC1_DAT7),		(IEN  | PTU | EN  | M4)) \
+	\
+	MUX_VAL(CP(MMC2_CLK),		(IEN  | PTD | EN  | M4)) \
+	MUX_VAL(CP(MMC2_CMD),		(IDIS | PTD | DIS | M4)) \
+					/* GPIO_131 LCD Enable */ \
+	MUX_VAL(CP(MMC2_DAT0),		(IDIS | PTD | DIS  | M4)) \
+					/* GPIO_132 USB host Enable */\
+	MUX_VAL(CP(MMC2_DAT1),		(IDIS  | PTD | DIS  | M4)) \
+					/* GPIO_133 HDMI PD */\
+	MUX_VAL(CP(MMC2_DAT2),		(IEN  | PTU | EN  | M4)) \
+	MUX_VAL(CP(MMC2_DAT3),		(IEN  | PTU | EN  | M4))\
+	/* McBSP */\
+	MUX_VAL(CP(MCBSP_CLKS),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(MCBSP1_CLKR),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP1_FSR),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(MCBSP1_DX),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP1_DR),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP1_FSX),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCBSP1_CLKX),	(IEN  | PTD | DIS | M0)) \
+	\
+	MUX_VAL(CP(MCBSP2_FSX),		(IEN  | PTU | EN  | M4))\
+	MUX_VAL(CP(MCBSP2_CLKX),	(IEN  | PTU | EN  | M4)) \
+	MUX_VAL(CP(MCBSP2_DR),		(IEN  | PTU | EN  | M4)) \
+	MUX_VAL(CP(MCBSP2_DX),		(IEN  | PTU | EN  | M4))\
+	\
+	MUX_VAL(CP(MCBSP3_DX),		(IEN  | PTU | EN  | M4)) \
+	MUX_VAL(CP(MCBSP3_DR),		(IEN  | PTU | EN  | M4)) \
+	MUX_VAL(CP(MCBSP3_CLKX),	(IEN  | PTU | EN  | M4)) \
+	MUX_VAL(CP(MCBSP3_FSX),		(IEN  | PTU | EN  | M4))\
+	\
+	MUX_VAL(CP(MCBSP4_CLKX),	(IDIS | PTD | DIS | M4)) \
+					/* GPIO_152 USB phy2 reset */\
+	MUX_VAL(CP(MCBSP4_DR),		(IEN | PTU | EN | M4)) \
+					/* GPIO_153 */\
+	MUX_VAL(CP(MCBSP4_DX),		(IDIS | PTD | DIS | M4)) \
+					/* GPIO_154 USB phy1 reset */\
+	MUX_VAL(CP(MCBSP4_FSX),		(IEN | PTU | EN | M4)) \
+					/* GPIO_155 TS_BUSY */\
+	/* UART */\
+	MUX_VAL(CP(UART1_TX),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART1_RTS),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART1_CTS),		(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(UART1_RX),		(IEN  | PTD | DIS | M0)) \
+	\
+	MUX_VAL(CP(UART2_CTS),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(UART2_RTS),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART2_TX),		(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART2_RX),		(IEN  | PTD | DIS | M0)) \
+	\
+	MUX_VAL(CP(UART3_CTS_RCTX),	(IEN  | PTU | DIS | M0)) \
+	MUX_VAL(CP(UART3_RTS_SD),	(IDIS | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART3_RX_IRRX),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(UART3_TX_IRTX),	(IDIS | PTD | DIS | M0)) \
+	/* I2C */\
+	MUX_VAL(CP(I2C1_SCL),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C1_SDA),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C2_SCL),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C2_SDA),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C3_SCL),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C3_SDA),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C4_SCL),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(I2C4_SDA),		(IEN  | PTU | EN  | M0)) \
+	/* McSPI */\
+	MUX_VAL(CP(MCSPI1_CLK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI1_SIMO),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI1_SOMI),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(MCSPI1_CS0),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(MCSPI1_CS1),		(IEN  | PTU | EN  | M4)) \
+	MUX_VAL(CP(MCSPI1_CS2),		(IEN  | PTU | EN  | M4)) \
+	MUX_VAL(CP(MCSPI1_CS3),		(IEN  | PTU | EN  | M4)) \
+	MUX_VAL(CP(MCSPI2_CLK),		(IEN  | PTD | DIS | M3)) \
+					/* HSUSB2_dat7 */\
+	MUX_VAL(CP(MCSPI2_SIMO),	(IEN  | PTD | DIS | M3)) \
+					/* HSUSB2_dat4 */\
+	MUX_VAL(CP(MCSPI2_SOMI),	(IEN  | PTD | DIS | M3)) \
+					/* HSUSB2_dat5 */\
+	MUX_VAL(CP(MCSPI2_CS0),		(IEN  | PTD | DIS | M3)) \
+					/* HSUSB2_dat6 */\
+	MUX_VAL(CP(MCSPI2_CS1),		(IEN  | PTD | DIS | M3)) \
+					/* HSUSB2_dat3 */\
+	/* CCDC */\
+	MUX_VAL(CP(CCDC_PCLK),		(IEN  | PTD | EN  | M4)) \
+	MUX_VAL(CP(CCDC_FIELD),		(IEN  | PTD | EN  | M4)) \
+	MUX_VAL(CP(CCDC_HD),		(IEN  | PTD | EN  | M4)) \
+	MUX_VAL(CP(CCDC_VD),		(IEN  | PTD | EN  | M4)) \
+	MUX_VAL(CP(CCDC_WEN),		(IEN  | PTD | EN  | M4)) \
+	MUX_VAL(CP(CCDC_DATA0),		(IEN  | PTD | EN  | M4)) \
+	MUX_VAL(CP(CCDC_DATA1),		(IEN  | PTD | EN  | M4)) \
+	MUX_VAL(CP(CCDC_DATA2),		(IEN  | PTD | EN  | M4)) \
+	MUX_VAL(CP(CCDC_DATA3),		(IEN  | PTD | EN  | M4)) \
+	MUX_VAL(CP(CCDC_DATA4),		(IEN  | PTD | EN  | M4)) \
+	MUX_VAL(CP(CCDC_DATA5),		(IEN  | PTD | EN  | M4)) \
+	MUX_VAL(CP(CCDC_DATA6),		(IEN  | PTD | EN  | M4)) \
+	MUX_VAL(CP(CCDC_DATA7),		(IEN  | PTD | EN  | M4)) \
+	/* RMII */\
+	MUX_VAL(CP(RMII_MDIO_DATA),	(IEN  |  M0)) \
+	MUX_VAL(CP(RMII_MDIO_CLK),	(M0)) \
+	MUX_VAL(CP(RMII_RXD0),		(IEN  | PTD | M0)) \
+	MUX_VAL(CP(RMII_RXD1),		(IEN  | PTD | M0)) \
+	MUX_VAL(CP(RMII_CRS_DV),	(IEN  | PTD | M0)) \
+	MUX_VAL(CP(RMII_RXER),		(PTD | M0)) \
+	MUX_VAL(CP(RMII_TXD0),		(PTD | M0)) \
+	MUX_VAL(CP(RMII_TXD1),		(PTD | M0)) \
+	MUX_VAL(CP(RMII_TXEN),		(PTD | M0)) \
+	MUX_VAL(CP(RMII_50MHZ_CLK),	(IEN  | PTD | EN  | M0)) \
+	/* HECC */\
+	MUX_VAL(CP(HECC1_TXD),		(IEN  | PTD | EN  | M4)) \
+	MUX_VAL(CP(HECC1_RXD),		(IEN  | PTD | EN  | M4)) \
+	/* HSUSB */\
+	MUX_VAL(CP(HSUSB0_CLK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_STP),		(IDIS | PTU | EN  | M0)) \
+	MUX_VAL(CP(HSUSB0_DIR),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_NXT),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA0),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA1),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA3),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA4),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA5),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA6),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(HSUSB0_DATA7),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(USB0_DRVBUS),	(IEN  | PTD | EN  | M0)) \
+	/* HDQ */\
+	MUX_VAL(CP(HDQ_SIO),		(IEN  | PTD | EN  | M4)) \
+	/* Control and debug */\
+	MUX_VAL(CP(SYS_32K),		(IEN  | PTD | EN  | M4)) \
+	MUX_VAL(CP(SYS_CLKREQ),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SYS_NIRQ),		(IEN  | PTD | EN  | M4)) \
+	MUX_VAL(CP(SYS_NRESWARM),	(IEN | PTU | DIS | M4)) \
+					/* SYS_nRESWARM */\
+	MUX_VAL(CP(SYS_BOOT0),		(IEN  | PTD | DIS | M4)) \
+	MUX_VAL(CP(SYS_BOOT1),		(IEN  | PTD | DIS | M4)) \
+	MUX_VAL(CP(SYS_BOOT2),		(IEN  | PTD | DIS | M4)) \
+	MUX_VAL(CP(SYS_BOOT3),		(IEN  | PTD | DIS | M4)) \
+	MUX_VAL(CP(SYS_BOOT4),		(IEN  | PTD | DIS | M4)) \
+	MUX_VAL(CP(SYS_BOOT5),		(IEN  | PTD | DIS | M4))\
+	MUX_VAL(CP(SYS_BOOT6),		(IEN  | PTD | DIS | M4))\
+	MUX_VAL(CP(SYS_BOOT7),		(IEN  | PTD | DIS | M4)) \
+	MUX_VAL(CP(SYS_BOOT8),		(IEN  | PTD | DIS | M4)) \
+	\
+	MUX_VAL(CP(SYS_OFF_MODE),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(SYS_CLKOUT1),	(IEN  | PTD | DIS | M4))\
+	MUX_VAL(CP(SYS_CLKOUT2),	(IDIS | PTU | DIS | M4))\
+	/* JTAG */\
+	MUX_VAL(CP(JTAG_nTRST),		(IEN | PTU | EN  | M4)) \
+	MUX_VAL(CP(JTAG_TCK),		(IEN | PTU | EN  | M4)) \
+	MUX_VAL(CP(JTAG_TMS),		(IEN | PTU | EN  | M4)) \
+	MUX_VAL(CP(JTAG_TDI),		(IEN | PTU | EN  | M4)) \
+	MUX_VAL(CP(JTAG_EMU0),		(IEN | PTU | EN  | M4)) \
+	MUX_VAL(CP(JTAG_EMU1),		(IEN | PTU | EN  | M4))\
+	/* ETK (ES2 onwards) */\
+	MUX_VAL(CP(ETK_CLK_ES2),	(IDIS  | PTD | DIS | M3)) \
+					/* hsusb1_stp */ \
+	MUX_VAL(CP(ETK_CTL_ES2),	(IDIS  | PTD | DIS | M3)) \
+					/* hsusb1_clk */\
+	MUX_VAL(CP(ETK_D0_ES2),		(IEN  | PTD | EN | M3)) \
+	MUX_VAL(CP(ETK_D1_ES2),		(IEN  | PTD | EN | M3)) \
+	MUX_VAL(CP(ETK_D2_ES2),		(IEN  | PTD | EN | M3)) \
+	MUX_VAL(CP(ETK_D3_ES2),		(IEN  | PTD | EN | M3)) \
+	MUX_VAL(CP(ETK_D4_ES2),		(IEN  | PTD | EN | M3)) \
+	MUX_VAL(CP(ETK_D5_ES2),		(IEN  | PTD | EN | M3)) \
+	MUX_VAL(CP(ETK_D6_ES2),		(IEN  | PTD | EN | M3)) \
+	MUX_VAL(CP(ETK_D7_ES2),		(IEN  | PTD | EN | M3)) \
+	MUX_VAL(CP(ETK_D8_ES2),		(IEN  | PTD | EN | M3)) \
+	MUX_VAL(CP(ETK_D9_ES2),		(IEN  | PTD | EN | M3)) \
+	MUX_VAL(CP(ETK_D10_ES2),	(IEN  | PTD | DIS | M4)) \
+	MUX_VAL(CP(ETK_D11_ES2),	(IEN  | PTD | DIS | M4)) \
+	MUX_VAL(CP(ETK_D12_ES2),	(IEN  | PTD | DIS | M4)) \
+	MUX_VAL(CP(ETK_D13_ES2),	(IEN  | PTD | DIS | M4)) \
+	MUX_VAL(CP(ETK_D14_ES2),	(IEN  | PTD | DIS | M4)) \
+	MUX_VAL(CP(ETK_D15_ES2),	(IEN  | PTD | DIS | M4)) \
+	/* Die to Die */\
+	MUX_VAL(CP(D2D_MCAD34),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD35),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_MCAD36),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_CLK26MI),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_NRESPWRON),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_NRESWARM),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(D2D_ARM9NIRQ),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_UMA2P6FIQ),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_SPINT),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_FRINT),		(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_DMAREQ0),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_DMAREQ1),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_DMAREQ2),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_DMAREQ3),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTRST),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTDI),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTDO),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTMS),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GTCK),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_N3GRTCK),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_MSTDBY),		(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(D2D_SWAKEUP),	(IEN  | PTD | EN  | M0)) \
+	MUX_VAL(CP(D2D_IDLEREQ),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_IDLEACK),	(IEN  | PTU | EN  | M0)) \
+	MUX_VAL(CP(D2D_MWRITE),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_SWRITE),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_MREAD),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_SREAD),		(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_MBUSFLAG),	(IEN  | PTD | DIS | M0)) \
+	MUX_VAL(CP(D2D_SBUSFLAG),	(IEN  | PTD | DIS | M0)) \
+
+#endif
@@ -219,6 +219,7 @@
 omap3_evm_quick_nand         arm         armv7       evm                 ti             omap3
 omap3_sdp3430                arm         armv7       sdp3430             ti             omap3
 devkit8000                   arm         armv7       devkit8000          timll          omap3
+mcx                          arm         armv7       mcx                 htkw           omap3
 tricorder                    arm         armv7       tricorder           corscience     omap3
 twister                      arm         armv7       twister             technexion     omap3
 omap4_panda                  arm         armv7       panda               ti             omap4
+/*
+ * Copyright (C) 2011 Ilya Yanok, Emcraft Systems
+ *
+ * Based on omap3_evm_config.h
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_OMAP			/* in a TI OMAP core */
+#define CONFIG_OMAP34XX			/* which is a 34XX */
+#define CONFIG_OMAP3_MCX		/* working with mcx */
+
+#define MACH_TYPE_MCX			3656
+#define CONFIG_MACH_TYPE	MACH_TYPE_MCX
+
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
+#define CONFIG_EMIF4	/* The chip has EMIF4 controller */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+#include <asm/arch/omap3.h>
+
+#define CONFIG_OF_LIBFDT
+#define CONFIG_FIT
+
+/*
+ * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
+ * and older u-boot.bin with the new U-Boot SPL.
+ */
+#define CONFIG_SYS_TEXT_BASE		0x80008000
+
+/*
+ * Display CPU and Board information
+ */
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+/* Clock Defines */
+#define V_OSCK			26000000	/* Clock output from T2 */
+#define V_SCLK			(V_OSCK >> 1)
+
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/*
+ * Size of malloc() pool
+ */
+#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB sector */
+#define CONFIG_SYS_MALLOC_LEN		(1024 << 10)
+/*
+ * DDR related
+ */
+#define CONFIG_SYS_CS0_SIZE		(256 * 1024 * 1024)
+
+/*
+ * Hardware drivers
+ */
+
+/*
+ * NS16550 Configuration
+ */
+#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+
+/*
+ * select serial console configuration
+ */
+#define CONFIG_CONS_INDEX		3
+#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
+#define CONFIG_SERIAL3			3	/* UART3 */
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE			115200
+#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
+					115200}
+#define CONFIG_MMC
+#define CONFIG_OMAP_HSMMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DOS_PARTITION
+
+/* EHCI */
+#define CONFIG_USB_STORAGE
+#define CONFIG_OMAP3_GPIO_5
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_OMAP
+#define CONFIG_USB_ULPI
+#define CONFIG_USB_ULPI_VIEWPORT_OMAP
+/*#define CONFIG_EHCI_DCACHE*/ /* leave it disabled for now */
+#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO	154
+#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO	152
+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
+
+/* commands to include */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
+#define CONFIG_CMD_FAT		/* FAT support			*/
+#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
+#define CONFIG_CMD_MMC		/* MMC support			*/
+#define CONFIG_CMD_FAT		/* FAT support			*/
+#define CONFIG_CMD_USB
+#define CONFIG_CMD_NAND		/* NAND support			*/
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_RBTREE
+#define CONFIG_LZO
+#define CONFIG_MTD_PARTITIONS
+#define CONFIG_MTD_DEVICE
+#define CONFIG_CMD_MTDPARTS
+
+#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
+#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
+#undef CONFIG_CMD_IMI		/* iminfo			*/
+#undef CONFIG_CMD_IMLS		/* List all found images	*/
+
+#define CONFIG_SYS_NO_FLASH
+#define CONFIG_HARD_I2C
+#define CONFIG_SYS_I2C_SPEED		100000
+#define CONFIG_SYS_I2C_SLAVE		1
+#define CONFIG_SYS_I2C_BUS		0
+#define CONFIG_DRIVER_OMAP34XX_I2C
+
+/* RTC */
+#define CONFIG_RTC_DS1337
+#define CONFIG_SYS_I2C_RTC_ADDR		0x68
+
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NFS
+/*
+ * Board NAND Info.
+ */
+#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
+							/* to access nand */
+#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
+							/* to access */
+							/* nand at CS0 */
+
+#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
+							/* NAND devices */
+#define CONFIG_SYS_64BIT_VSPRINTF		/* needed for nand_util.c */
+
+#define CONFIG_JFFS2_NAND
+/* nand device jffs2 lives on */
+#define CONFIG_JFFS2_DEV		"nand0"
+/* start of jffs2 partition */
+#define CONFIG_JFFS2_PART_OFFSET	0x680000
+#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* sz of jffs2 part */
+
+/* Environment information */
+#define CONFIG_BOOTDELAY	10
+
+#define CONFIG_BOOTFILE		"uImage"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"loadaddr=0x82000000\0" \
+	"console=ttyO2,115200n8\0" \
+	"mmcargs=setenv bootargs console=${console} " \
+		"root=/dev/mmcblk0p2 rw " \
+		"rootfstype=ext3 rootwait\0" \
+	"nandargs=setenv bootargs console=${console} " \
+		"root=/dev/mtdblock4 rw " \
+		"rootfstype=jffs2\0" \
+	"loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
+	"bootscript=echo Running bootscript from mmc ...; " \
+		"source ${loadaddr}\0" \
+	"loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
+	"mmcboot=echo Booting from mmc ...; " \
+		"run mmcargs; " \
+		"bootm ${loadaddr}\0" \
+	"nandboot=echo Booting from nand ...; " \
+		"run nandargs; " \
+		"nand read ${loadaddr} 280000 400000; " \
+		"bootm ${loadaddr}\0" \
+
+#define CONFIG_BOOTCOMMAND \
+	"if mmc init; then " \
+		"if run loadbootscript; then " \
+			"run bootscript; " \
+		"else " \
+			"if run loaduimage; then " \
+				"run mmcboot; " \
+			"else run nandboot; " \
+			"fi; " \
+		"fi; " \
+	"else run nandboot; fi"
+
+#define CONFIG_AUTO_COMPLETE
+/*
+ * Miscellaneous configurable options
+ */
+#define V_PROMPT			"mcx # "
+
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_PROMPT		V_PROMPT
+#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
+					sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS		16	/* max number of command */
+						/* args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
+#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
+					0x01F00000) /* 31MB */
+
+#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
+								/* address */
+
+/*
+ * AM3517 has 12 GP timers, they can be driven by the system clock
+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
+ * This rate is divided by a local divisor.
+ */
+#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
+#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
+#define CONFIG_SYS_HZ			1000
+
+/*
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(128 << 10)	/* regular stack 128 KiB */
+
+/*
+ * Physical Memory Map
+ */
+#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
+#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
+#define PHYS_SDRAM_1_SIZE	(32 << 20)	/* at least 32 MiB */
+#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1
+
+/*
+ * FLASH and environment organization
+ */
+
+/* **** PISMO SUPPORT *** */
+
+/* Configure the PISMO */
+#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
+
+#define CONFIG_NAND_OMAP_GPMC
+#define GPMC_NAND_ECC_LP_x16_LAYOUT
+#define CONFIG_ENV_IS_IN_NAND
+#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */
+
+#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
+#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
+#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET
+
+/*
+ * CFI FLASH driver setup
+ */
+/* timeout values are in ticks */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
+#define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)
+
+/* Flash banks JFFS2 should use */
+#define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
+					CONFIG_SYS_MAX_NAND_DEVICE)
+#define CONFIG_SYS_JFFS2_MEM_NAND
+/* use flash_info[2] */
+#define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
+#define CONFIG_SYS_JFFS2_NUM_BANKS	1
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
+#define CONFIG_SYS_INIT_RAM_SIZE	0x800
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+
+/* Defines for SPL */
+#define CONFIG_SPL
+#define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SPL_NAND_SOFTECC
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
+
+#define CONFIG_SPL_TEXT_BASE		0x40200000 /*CONFIG_SYS_SRAM_START*/
+#define CONFIG_SPL_MAX_SIZE		(45 << 10)
+#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
+
+/* move malloc and bss high to prevent clashing with the main image */
+#define CONFIG_SYS_SPL_MALLOC_START	0x8f000000
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x80000
+#define CONFIG_SPL_BSS_START_ADDR	0x8f080000 /* end of RAM */
+#define CONFIG_SPL_BSS_MAX_SIZE		0x80000
+
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"
+
+/* NAND boot config */
+#define CONFIG_SYS_NAND_PAGE_COUNT	64
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
+#define CONFIG_SYS_NAND_ECCPOS		{40, 41, 42, 43, 44, 45, 46, 47,\
+					 48, 49, 50, 51, 52, 53, 54, 55,\
+					 56, 57, 58, 59, 60, 61, 62, 63}
+#define CONFIG_SYS_NAND_ECCSIZE		256
+#define CONFIG_SYS_NAND_ECCBYTES	3
+
+#define CONFIG_SYS_NAND_ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / \
+						CONFIG_SYS_NAND_ECCSIZE)
+#define CONFIG_SYS_NAND_ECCTOTAL       (CONFIG_SYS_NAND_ECCBYTES * \
+						CONFIG_SYS_NAND_ECCSTEPS)
+
+#define CONFIG_SYS_NAND_U_BOOT_START   CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000
+
+/*
+ * ethernet support
+ *
+ */
+#if defined(CONFIG_CMD_NET)
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_DRIVER_TI_EMAC_USE_RMII
+#define CONFIG_MII
+#define CONFIG_BOOTP_DEFAULT
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT 10
+#endif
+
+#endif /* __CONFIG_H */
...	...	@@ -929,6 +929,10 @@
929	929
930	930	omap2420h4 ARM1136EJS
931	931
	932	+Ilya Yanok <yanok@emcraft.com>
	933	+
	934	+ mcx ARM ARMV7 (AM35x SoC)
	935	+
932	936	Syed Mohammed Khasim <sm.khasim@gmail.com>
933	937	Sughosh Ganu <urwithsughosh@gmail.com>
934	938
	1	+#
	2	+# Copyright (C) 2011 Ilya Yanok, Emcraft Systems
	3	+#
	4	+# Based on ti/evm/Makefile
	5	+#
	6	+# This program is free software; you can redistribute it and/or modify
	7	+# it under the terms of the GNU General Public License as published by
	8	+# the Free Software Foundation; either version 2 of the License, or
	9	+# (at your option) any later version.
	10	+#
	11	+# This program is distributed in the hope that it will be useful,
	12	+# but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	+# GNU General Public License for more details.
	15	+#
	16	+# You should have received a copy of the GNU General Public License
	17	+# along with this program; if not, write to the Free Software
	18	+# Foundation, Inc.
	19	+#
	20	+
	21	+include $(TOPDIR)/config.mk
	22	+
	23	+LIB = $(obj)lib$(BOARD).o
	24	+
	25	+COBJS := $(BOARD).o
	26	+
	27	+SRCS := $(COBJS:.o=.c)
	28	+OBJS := $(addprefix $(obj),$(COBJS))
	29	+
	30	+$(LIB): $(obj).depend $(OBJS)
	31	+ $(call cmd_link_o_target, $(OBJS))
	32	+
	33	+#########################################################################
	34	+
	35	+# defines $(obj).depend target
	36	+include $(SRCTREE)/rules.mk
	37	+
	38	+sinclude $(obj).depend
	1	+/*
	2	+ * Copyright (C) 2011 Ilya Yanok, Emcraft Systems
	3	+ *
	4	+ * Based on ti/evm/evm.c
	5	+ *
	6	+ * This program is free software; you can redistribute it and/or modify
	7	+ * it under the terms of the GNU General Public License as published by
	8	+ * the Free Software Foundation; either version 2 of the License, or
	9	+ * (at your option) any later version.
	10	+ *
	11	+ * This program is distributed in the hope that it will be useful,
	12	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	+ * GNU General Public License for more details.
	15	+ *
	16	+ * You should have received a copy of the GNU General Public License
	17	+ * along with this program; if not, write to the Free Software
	18	+ * Foundation, Inc.
	19	+ */
	20	+
	21	+#include <common.h>
	22	+#include <asm/io.h>
	23	+#include <asm/arch/mem.h>
	24	+#include <asm/arch/mmc_host_def.h>
	25	+#include <asm/arch/mux.h>
	26	+#include <asm/arch/sys_proto.h>
	27	+#include <asm/mach-types.h>
	28	+#include <asm/gpio.h>
	29	+#include <asm/omap_gpio.h>
	30	+#include "errno.h"
	31	+#include <i2c.h>
	32	+#ifdef CONFIG_USB_EHCI
	33	+#include <usb.h>
	34	+#include <asm/ehci-omap.h>
	35	+#endif
	36	+#include "mcx.h"
	37	+
	38	+DECLARE_GLOBAL_DATA_PTR;
	39	+
	40	+#ifdef CONFIG_USB_EHCI
	41	+static struct omap_usbhs_board_data usbhs_bdata = {
	42	+ .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
	43	+ .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
	44	+ .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
	45	+};
	46	+
	47	+int ehci_hcd_init(void)
	48	+{
	49	+ return omap_ehci_hcd_init(&usbhs_bdata);
	50	+}
	51	+
	52	+int ehci_hcd_stop(void)
	53	+{
	54	+ return omap_ehci_hcd_stop();
	55	+}
	56	+#endif
	57	+
	58	+/*
	59	+ * Routine: board_init
	60	+ * Description: Early hardware init.
	61	+ */
	62	+int board_init(void)
	63	+{
	64	+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
	65	+ /* boot param addr */
	66	+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
	67	+
	68	+ return 0;
	69	+}
	70	+
	71	+/*
	72	+ * Routine: misc_init_r
	73	+ * Description: late init.
	74	+ */
	75	+int misc_init_r(void)
	76	+{
	77	+ dieid_num_r();
	78	+
	79	+ return 0;
	80	+}
	81	+
	82	+/*
	83	+ * Routine: set_muxconf_regs
	84	+ * Description: Setting up the configuration Mux registers specific to the
	85	+ * hardware. Many pins need to be moved from protect to primary
	86	+ * mode.
	87	+ */
	88	+void set_muxconf_regs(void)
	89	+{
	90	+ MUX_MCX();
	91	+}
	92	+
	93	+#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
	94	+int board_mmc_init(bd_t *bis)
	95	+{
	96	+ return omap_mmc_init(0);
	97	+}
	98	+#endif
	99	+
	100	+#ifdef CONFIG_USB_EHCI_OMAP
	101	+#define USB_HOST_PWR_EN 132
	102	+int board_usb_init(void)
	103	+{
	104	+ if (gpio_request(USB_HOST_PWR_EN, "USB_HOST_PWR_EN") < 0) {
	105	+ puts("Failed to get USB_HOST_PWR_EN pin\n");
	106	+ return -ENODEV;
	107	+ }
	108	+ gpio_direction_output(USB_HOST_PWR_EN, 1);
	109	+
	110	+ return 0;
	111	+}
	112	+#endif
	1	+/*
	2	+ * Copyright (C) 2011 Ilya Yanok, Emcraft Systems
	3	+ *
	4	+ * Based on ti/evm/evm.h
	5	+ *
	6	+ * This program is free software; you can redistribute it and/or modify
	7	+ * it under the terms of the GNU General Public License as published by
	8	+ * the Free Software Foundation; either version 2 of the License, or
	9	+ * (at your option) any later version.
	10	+ *
	11	+ * This program is distributed in the hope that it will be useful,
	12	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	+ * GNU General Public License for more details.
	15	+ *
	16	+ * You should have received a copy of the GNU General Public License
	17	+ * along with this program; if not, write to the Free Software
	18	+ * Foundation, Inc.
	19	+ */
	20	+
	21	+#ifndef _AM3517EVM_H_
	22	+#define _AM3517EVM_H_
	23	+
	24	+const omap3_sysinfo sysinfo = {
	25	+ DDR_DISCRETE,
	26	+ "HTKW mcx Board",
	27	+ "NAND",
	28	+};
	29	+
	30	+/*
	31	+ * IEN - Input Enable
	32	+ * IDIS - Input Disable
	33	+ * PTD - Pull type Down
	34	+ * PTU - Pull type Up
	35	+ * DIS - Pull type selection is inactive
	36	+ * EN - Pull type selection is active
	37	+ * M0 - Mode 0
	38	+ * The commented string gives the final mux configuration for that pin
	39	+ */
	40	+#define MUX_MCX() \
	41	+ /* SDRC */\
	42	+ MUX_VAL(CP(SDRC_D0), (IEN \| PTD \| DIS \| M0)) \
	43	+ MUX_VAL(CP(SDRC_D1), (IEN \| PTD \| DIS \| M0)) \
	44	+ MUX_VAL(CP(SDRC_D2), (IEN \| PTD \| DIS \| M0)) \
	45	+ MUX_VAL(CP(SDRC_D3), (IEN \| PTD \| DIS \| M0)) \
	46	+ MUX_VAL(CP(SDRC_D4), (IEN \| PTD \| DIS \| M0)) \
	47	+ MUX_VAL(CP(SDRC_D5), (IEN \| PTD \| DIS \| M0)) \
	48	+ MUX_VAL(CP(SDRC_D6), (IEN \| PTD \| DIS \| M0)) \
	49	+ MUX_VAL(CP(SDRC_D7), (IEN \| PTD \| DIS \| M0)) \
	50	+ MUX_VAL(CP(SDRC_D8), (IEN \| PTD \| DIS \| M0)) \
	51	+ MUX_VAL(CP(SDRC_D9), (IEN \| PTD \| DIS \| M0)) \
	52	+ MUX_VAL(CP(SDRC_D10), (IEN \| PTD \| DIS \| M0)) \
	53	+ MUX_VAL(CP(SDRC_D11), (IEN \| PTD \| DIS \| M0)) \
	54	+ MUX_VAL(CP(SDRC_D12), (IEN \| PTD \| DIS \| M0)) \
	55	+ MUX_VAL(CP(SDRC_D13), (IEN \| PTD \| DIS \| M0)) \
	56	+ MUX_VAL(CP(SDRC_D14), (IEN \| PTD \| DIS \| M0)) \
	57	+ MUX_VAL(CP(SDRC_D15), (IEN \| PTD \| DIS \| M0)) \
	58	+ MUX_VAL(CP(SDRC_D16), (IEN \| PTD \| DIS \| M0)) \
	59	+ MUX_VAL(CP(SDRC_D17), (IEN \| PTD \| DIS \| M0)) \
	60	+ MUX_VAL(CP(SDRC_D18), (IEN \| PTD \| DIS \| M0)) \
	61	+ MUX_VAL(CP(SDRC_D19), (IEN \| PTD \| DIS \| M0)) \
	62	+ MUX_VAL(CP(SDRC_D20), (IEN \| PTD \| DIS \| M0)) \
	63	+ MUX_VAL(CP(SDRC_D21), (IEN \| PTD \| DIS \| M0)) \
	64	+ MUX_VAL(CP(SDRC_D22), (IEN \| PTD \| DIS \| M0)) \
	65	+ MUX_VAL(CP(SDRC_D23), (IEN \| PTD \| DIS \| M0)) \
	66	+ MUX_VAL(CP(SDRC_D24), (IEN \| PTD \| DIS \| M0)) \
	67	+ MUX_VAL(CP(SDRC_D25), (IEN \| PTD \| DIS \| M0)) \
	68	+ MUX_VAL(CP(SDRC_D26), (IEN \| PTD \| DIS \| M0)) \
	69	+ MUX_VAL(CP(SDRC_D27), (IEN \| PTD \| DIS \| M0)) \
	70	+ MUX_VAL(CP(SDRC_D28), (IEN \| PTD \| DIS \| M0)) \
	71	+ MUX_VAL(CP(SDRC_D29), (IEN \| PTD \| DIS \| M0)) \
	72	+ MUX_VAL(CP(SDRC_D30), (IEN \| PTD \| DIS \| M0)) \
	73	+ MUX_VAL(CP(SDRC_D31), (IEN \| PTD \| DIS \| M0)) \
	74	+ MUX_VAL(CP(SDRC_CLK), (IEN \| PTD \| DIS \| M0)) \
	75	+ MUX_VAL(CP(SDRC_DQS0), (IEN \| PTD \| DIS \| M0)) \
	76	+ MUX_VAL(CP(SDRC_DQS1), (IEN \| PTD \| DIS \| M0)) \
	77	+ MUX_VAL(CP(SDRC_DQS2), (IEN \| PTD \| DIS \| M0)) \
	78	+ MUX_VAL(CP(SDRC_DQS3), (IEN \| PTD \| DIS \| M0)) \
	79	+ MUX_VAL(CP(SDRC_DQS0N), (IEN \| PTD \| EN \| M0)) \
	80	+ MUX_VAL(CP(SDRC_DQS1N), (IEN \| PTD \| EN \| M0)) \
	81	+ MUX_VAL(CP(SDRC_DQS2N), (IEN \| PTD \| EN \| M0)) \
	82	+ MUX_VAL(CP(SDRC_DQS3N), (IEN \| PTD \| EN \| M0)) \
	83	+ MUX_VAL(CP(SDRC_CKE0), (M0)) \
	84	+ MUX_VAL(CP(SDRC_CKE1), (M0)) \
	85	+ MUX_VAL(CP(STRBEN_DLY0), (IEN \| PTD \| EN \| M0)) \
	86	+ /sdrc_strben_dly0/\
	87	+ MUX_VAL(CP(STRBEN_DLY1), (IEN \| PTD \| EN \| M0)) \
	88	+ /sdrc_strben_dly1/\
	89	+ /* GPMC */\
	90	+ MUX_VAL(CP(GPMC_A1), (IEN \| PTU \| EN \| M4)) \
	91	+ MUX_VAL(CP(GPMC_A2), (IEN \| PTU \| EN \| M4)) \
	92	+ MUX_VAL(CP(GPMC_A3), (IEN \| PTU \| EN \| M4)) \
	93	+ MUX_VAL(CP(GPMC_A4), (IEN \| PTU \| EN \| M4)) \
	94	+ MUX_VAL(CP(GPMC_A5), (IEN \| PTU \| EN \| M4)) \
	95	+ MUX_VAL(CP(GPMC_A6), (IEN \| PTU \| EN \| M4)) \
	96	+ MUX_VAL(CP(GPMC_A7), (IEN \| PTU \| EN \| M4)) \
	97	+ MUX_VAL(CP(GPMC_A8), (IEN \| PTU \| EN \| M4)) \
	98	+ MUX_VAL(CP(GPMC_A9), (IEN \| PTU \| EN \| M4)) \
	99	+ MUX_VAL(CP(GPMC_A10), (IDIS \| PTU \| DIS \| M4)) \
	100	+ /* GPIO_43 LCD buffer enable */ \
	101	+ MUX_VAL(CP(GPMC_D0), (IEN \| PTU \| EN \| M0)) \
	102	+ MUX_VAL(CP(GPMC_D1), (IEN \| PTU \| EN \| M0)) \
	103	+ MUX_VAL(CP(GPMC_D2), (IEN \| PTU \| EN \| M0)) \
	104	+ MUX_VAL(CP(GPMC_D3), (IEN \| PTU \| EN \| M0)) \
	105	+ MUX_VAL(CP(GPMC_D4), (IEN \| PTU \| EN \| M0)) \
	106	+ MUX_VAL(CP(GPMC_D5), (IEN \| PTU \| EN \| M0)) \
	107	+ MUX_VAL(CP(GPMC_D6), (IEN \| PTU \| EN \| M0)) \
	108	+ MUX_VAL(CP(GPMC_D7), (IEN \| PTU \| EN \| M0)) \
	109	+ MUX_VAL(CP(GPMC_D8), (IEN \| PTU \| EN \| M0)) \
	110	+ MUX_VAL(CP(GPMC_D9), (IEN \| PTU \| EN \| M0)) \
	111	+ MUX_VAL(CP(GPMC_D10), (IEN \| PTU \| EN \| M0)) \
	112	+ MUX_VAL(CP(GPMC_D11), (IEN \| PTU \| EN \| M0)) \
	113	+ MUX_VAL(CP(GPMC_D12), (IEN \| PTU \| EN \| M0)) \
	114	+ MUX_VAL(CP(GPMC_D13), (IEN \| PTU \| EN \| M0)) \
	115	+ MUX_VAL(CP(GPMC_D14), (IEN \| PTU \| EN \| M0)) \
	116	+ MUX_VAL(CP(GPMC_D15), (IEN \| PTU \| EN \| M0)) \
	117	+ MUX_VAL(CP(GPMC_NCS0), (IDIS \| PTU \| EN \| M0)) \
	118	+ MUX_VAL(CP(GPMC_NCS1), (IEN \| PTU \| EN \| M4)) \
	119	+ MUX_VAL(CP(GPMC_NCS2), (IEN \| PTU \| EN \| M4)) \
	120	+ MUX_VAL(CP(GPMC_NCS3), (IEN \| PTU \| EN \| M4)) \
	121	+ MUX_VAL(CP(GPMC_NCS4), (IEN \| PTU \| EN \| M4))\
	122	+ MUX_VAL(CP(GPMC_NCS5), (IEN \| PTU \| EN \| M4)) \
	123	+ MUX_VAL(CP(GPMC_NCS6), (IEN \| PTU \| EN \| M4)) \
	124	+ /* GPIO_57 TS_PenIRQn */\
	125	+ MUX_VAL(CP(GPMC_NCS7), (IEN \| PTU \| EN \| M4)) \
	126	+ /* GPIO_58 ETHERNET RESET */\
	127	+ MUX_VAL(CP(GPMC_CLK), (IEN \| PTU \| EN \| M4)) \
	128	+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS \| PTD \| DIS \| M0)) \
	129	+ MUX_VAL(CP(GPMC_NOE), (IDIS \| PTD \| DIS \| M0)) \
	130	+ MUX_VAL(CP(GPMC_NWE), (IDIS \| PTD \| DIS \| M0)) \
	131	+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS \| PTU \| EN \| M0)) \
	132	+ MUX_VAL(CP(GPMC_NBE1), (IEN \| PTU \| DIS \| M4)) \
	133	+ /* GPIO_61 SD-CARD CD */ \
	134	+ MUX_VAL(CP(GPMC_NWP), (IDIS \| PTU \| EN \| M4)) \
	135	+ /* GPIO_62 Nand write protect, keep enabled */ \
	136	+ MUX_VAL(CP(GPMC_WAIT0), (IEN \| PTU \| EN \| M0)) \
	137	+ MUX_VAL(CP(GPMC_WAIT1), (IEN \| PTU \| EN \| M4))\
	138	+ MUX_VAL(CP(GPMC_WAIT2), (IEN \| PTU \| EN \| M4))\
	139	+ MUX_VAL(CP(GPMC_WAIT3), (IEN \| PTU \| EN \| M4)) \
	140	+ /* GPIO_65 SD-CARD WP */\
	141	+ /* DSS */\
	142	+ MUX_VAL(CP(DSS_PCLK), (IDIS \| PTD \| DIS \| M0)) \
	143	+ MUX_VAL(CP(DSS_HSYNC), (IDIS \| PTD \| DIS \| M0)) \
	144	+ MUX_VAL(CP(DSS_VSYNC), (IDIS \| PTD \| DIS \| M0)) \
	145	+ MUX_VAL(CP(DSS_ACBIAS), (IDIS \| PTD \| DIS \| M0)) \
	146	+ MUX_VAL(CP(DSS_DATA0), (IEN \| PTU \| EN \| M4))\
	147	+ MUX_VAL(CP(DSS_DATA1), (IEN \| PTU \| EN \| M4)) \
	148	+ MUX_VAL(CP(DSS_DATA2), (IEN \| PTU \| EN \| M4)) \
	149	+ MUX_VAL(CP(DSS_DATA3), (IDIS \| PTD \| DIS \| M0)) \
	150	+ MUX_VAL(CP(DSS_DATA4), (IDIS \| PTD \| DIS \| M0)) \
	151	+ MUX_VAL(CP(DSS_DATA5), (IDIS \| PTD \| DIS \| M0)) \
	152	+ MUX_VAL(CP(DSS_DATA6), (IDIS \| PTD \| DIS \| M0)) \
	153	+ MUX_VAL(CP(DSS_DATA7), (IDIS \| PTD \| DIS \| M0)) \
	154	+ MUX_VAL(CP(DSS_DATA8), (IEN \| PTU \| EN \| M4)) \
	155	+ MUX_VAL(CP(DSS_DATA9), (IEN \| PTU \| EN \| M4)) \
	156	+ MUX_VAL(CP(DSS_DATA10), (IDIS \| PTD \| DIS \| M0)) \
	157	+ MUX_VAL(CP(DSS_DATA11), (IDIS \| PTD \| DIS \| M0)) \
	158	+ MUX_VAL(CP(DSS_DATA12), (IDIS \| PTD \| DIS \| M0)) \
	159	+ MUX_VAL(CP(DSS_DATA13), (IDIS \| PTD \| DIS \| M0)) \
	160	+ MUX_VAL(CP(DSS_DATA14), (IDIS \| PTD \| DIS \| M0)) \
	161	+ MUX_VAL(CP(DSS_DATA15), (IDIS \| PTD \| DIS \| M0))\
	162	+ MUX_VAL(CP(DSS_DATA16), (IEN \| PTU \| EN \| M4)) \
	163	+ MUX_VAL(CP(DSS_DATA17), (IEN \| PTU \| EN \| M4)) \
	164	+ MUX_VAL(CP(DSS_DATA18), (IEN \| PTU \| EN \| M4)) \
	165	+ MUX_VAL(CP(DSS_DATA19), (IDIS \| PTD \| DIS \| M0)) \
	166	+ MUX_VAL(CP(DSS_DATA20), (IDIS \| PTD \| DIS \| M0)) \
	167	+ MUX_VAL(CP(DSS_DATA21), (IDIS \| PTD \| DIS \| M0)) \
	168	+ MUX_VAL(CP(DSS_DATA22), (IDIS \| PTD \| DIS \| M0)) \
	169	+ MUX_VAL(CP(DSS_DATA23), (IDIS \| PTD \| DIS \| M0)) \
	170	+ /* CAMERA */\
	171	+ MUX_VAL(CP(CAM_HS), (IEN \| PTU \| EN \| M4)) \
	172	+ MUX_VAL(CP(CAM_VS), (IEN \| PTU \| EN \| M4)) \
	173	+ MUX_VAL(CP(CAM_XCLKA), (IEN \| PTD \| EN \| M4)) \
	174	+ MUX_VAL(CP(CAM_PCLK), (IEN \| PTU \| EN \| M4)) \
	175	+ MUX_VAL(CP(CAM_FLD), (IEN \| PTD \| EN \| M4)) \
	176	+ MUX_VAL(CP(CAM_D0), (IEN \| PTD \| EN \| M4)) \
	177	+ MUX_VAL(CP(CAM_D1), (IEN \| PTD \| EN \| M4)) \
	178	+ MUX_VAL(CP(CAM_D2), (IEN \| PTD \| EN \| M4)) \
	179	+ MUX_VAL(CP(CAM_D3), (IEN \| PTD \| EN \| M4)) \
	180	+ MUX_VAL(CP(CAM_D4), (IEN \| PTD \| EN \| M4)) \
	181	+ MUX_VAL(CP(CAM_D5), (IEN \| PTD \| EN \| M4)) \
	182	+ MUX_VAL(CP(CAM_D6), (IEN \| PTD \| EN \| M4)) \
	183	+ MUX_VAL(CP(CAM_D7), (IEN \| PTD \| EN \| M4)) \
	184	+ MUX_VAL(CP(CAM_D8), (IEN \| PTD \| EN \| M4)) \
	185	+ MUX_VAL(CP(CAM_D9), (IEN \| PTD \| EN \| M4)) \
	186	+ MUX_VAL(CP(CAM_D10), (IEN \| PTD \| EN \| M4)) \
	187	+ MUX_VAL(CP(CAM_D11), (IEN \| PTD \| EN \| M4)) \
	188	+ MUX_VAL(CP(CAM_XCLKB), (IEN \| PTD \| EN \| M4)) \
	189	+ MUX_VAL(CP(CAM_WEN), (IEN \| PTD \| EN \| M4)) \
	190	+ MUX_VAL(CP(CAM_STROBE), (IEN \| PTD \| EN \| M4)) \
	191	+ MUX_VAL(CP(CSI2_DX0), (IEN \| PTD \| EN \| M4)) \
	192	+ MUX_VAL(CP(CSI2_DY0), (IEN \| PTD \| EN \| M4)) \
	193	+ MUX_VAL(CP(CSI2_DX1), (IEN \| PTD \| EN \| M4)) \
	194	+ MUX_VAL(CP(CSI2_DY1), (IEN \| PTD \| EN \| M4)) \
	195	+ /* MMC */\
	196	+ MUX_VAL(CP(MMC1_CLK), (IEN \| PTU \| EN \| M0)) \
	197	+ MUX_VAL(CP(MMC1_CMD), (IEN \| PTU \| DIS \| M0)) \
	198	+ MUX_VAL(CP(MMC1_DAT0), (IEN \| PTU \| DIS \| M0)) \
	199	+ MUX_VAL(CP(MMC1_DAT1), (IEN \| PTU \| DIS \| M0)) \
	200	+ MUX_VAL(CP(MMC1_DAT2), (IEN \| PTU \| DIS \| M0)) \
	201	+ MUX_VAL(CP(MMC1_DAT3), (IEN \| PTU \| DIS \| M0)) \
	202	+ MUX_VAL(CP(MMC1_DAT4), (IEN \| PTU \| EN \| M4)) \
	203	+ MUX_VAL(CP(MMC1_DAT5), (IEN \| PTU \| EN \| M4)) \
	204	+ MUX_VAL(CP(MMC1_DAT6), (IEN \| PTU \| EN \| M4)) \
	205	+ MUX_VAL(CP(MMC1_DAT7), (IEN \| PTU \| EN \| M4)) \
	206	+ \
	207	+ MUX_VAL(CP(MMC2_CLK), (IEN \| PTD \| EN \| M4)) \
	208	+ MUX_VAL(CP(MMC2_CMD), (IDIS \| PTD \| DIS \| M4)) \
	209	+ /* GPIO_131 LCD Enable */ \
	210	+ MUX_VAL(CP(MMC2_DAT0), (IDIS \| PTD \| DIS \| M4)) \
	211	+ /* GPIO_132 USB host Enable */\
	212	+ MUX_VAL(CP(MMC2_DAT1), (IDIS \| PTD \| DIS \| M4)) \
	213	+ /* GPIO_133 HDMI PD */\
	214	+ MUX_VAL(CP(MMC2_DAT2), (IEN \| PTU \| EN \| M4)) \
	215	+ MUX_VAL(CP(MMC2_DAT3), (IEN \| PTU \| EN \| M4))\
	216	+ /* McBSP */\
	217	+ MUX_VAL(CP(MCBSP_CLKS), (IEN \| PTU \| DIS \| M0)) \
	218	+ MUX_VAL(CP(MCBSP1_CLKR), (IEN \| PTD \| DIS \| M0)) \
	219	+ MUX_VAL(CP(MCBSP1_FSR), (IDIS \| PTU \| EN \| M0)) \
	220	+ MUX_VAL(CP(MCBSP1_DX), (IDIS \| PTD \| DIS \| M0)) \
	221	+ MUX_VAL(CP(MCBSP1_DR), (IEN \| PTD \| DIS \| M0)) \
	222	+ MUX_VAL(CP(MCBSP1_FSX), (IEN \| PTD \| DIS \| M0)) \
	223	+ MUX_VAL(CP(MCBSP1_CLKX), (IEN \| PTD \| DIS \| M0)) \
	224	+ \
	225	+ MUX_VAL(CP(MCBSP2_FSX), (IEN \| PTU \| EN \| M4))\
	226	+ MUX_VAL(CP(MCBSP2_CLKX), (IEN \| PTU \| EN \| M4)) \
	227	+ MUX_VAL(CP(MCBSP2_DR), (IEN \| PTU \| EN \| M4)) \
	228	+ MUX_VAL(CP(MCBSP2_DX), (IEN \| PTU \| EN \| M4))\
	229	+ \
	230	+ MUX_VAL(CP(MCBSP3_DX), (IEN \| PTU \| EN \| M4)) \
	231	+ MUX_VAL(CP(MCBSP3_DR), (IEN \| PTU \| EN \| M4)) \
	232	+ MUX_VAL(CP(MCBSP3_CLKX), (IEN \| PTU \| EN \| M4)) \
	233	+ MUX_VAL(CP(MCBSP3_FSX), (IEN \| PTU \| EN \| M4))\
	234	+ \
	235	+ MUX_VAL(CP(MCBSP4_CLKX), (IDIS \| PTD \| DIS \| M4)) \
	236	+ /* GPIO_152 USB phy2 reset */\
	237	+ MUX_VAL(CP(MCBSP4_DR), (IEN \| PTU \| EN \| M4)) \
	238	+ /* GPIO_153 */\
	239	+ MUX_VAL(CP(MCBSP4_DX), (IDIS \| PTD \| DIS \| M4)) \
	240	+ /* GPIO_154 USB phy1 reset */\
	241	+ MUX_VAL(CP(MCBSP4_FSX), (IEN \| PTU \| EN \| M4)) \
	242	+ /* GPIO_155 TS_BUSY */\
	243	+ /* UART */\
	244	+ MUX_VAL(CP(UART1_TX), (IDIS \| PTD \| DIS \| M0)) \
	245	+ MUX_VAL(CP(UART1_RTS), (IDIS \| PTD \| DIS \| M0)) \
	246	+ MUX_VAL(CP(UART1_CTS), (IEN \| PTU \| DIS \| M0)) \
	247	+ MUX_VAL(CP(UART1_RX), (IEN \| PTD \| DIS \| M0)) \
	248	+ \
	249	+ MUX_VAL(CP(UART2_CTS), (IEN \| PTU \| EN \| M0)) \
	250	+ MUX_VAL(CP(UART2_RTS), (IDIS \| PTD \| DIS \| M0)) \
	251	+ MUX_VAL(CP(UART2_TX), (IDIS \| PTD \| DIS \| M0)) \
	252	+ MUX_VAL(CP(UART2_RX), (IEN \| PTD \| DIS \| M0)) \
	253	+ \
	254	+ MUX_VAL(CP(UART3_CTS_RCTX), (IEN \| PTU \| DIS \| M0)) \
	255	+ MUX_VAL(CP(UART3_RTS_SD), (IDIS \| PTD \| DIS \| M0)) \
	256	+ MUX_VAL(CP(UART3_RX_IRRX), (IEN \| PTD \| DIS \| M0)) \
	257	+ MUX_VAL(CP(UART3_TX_IRTX), (IDIS \| PTD \| DIS \| M0)) \
	258	+ /* I2C */\
	259	+ MUX_VAL(CP(I2C1_SCL), (IEN \| PTU \| EN \| M0)) \
	260	+ MUX_VAL(CP(I2C1_SDA), (IEN \| PTU \| EN \| M0)) \
	261	+ MUX_VAL(CP(I2C2_SCL), (IEN \| PTU \| EN \| M0)) \
	262	+ MUX_VAL(CP(I2C2_SDA), (IEN \| PTU \| EN \| M0)) \
	263	+ MUX_VAL(CP(I2C3_SCL), (IEN \| PTU \| EN \| M0)) \
	264	+ MUX_VAL(CP(I2C3_SDA), (IEN \| PTU \| EN \| M0)) \
	265	+ MUX_VAL(CP(I2C4_SCL), (IEN \| PTU \| EN \| M0)) \
	266	+ MUX_VAL(CP(I2C4_SDA), (IEN \| PTU \| EN \| M0)) \
	267	+ /* McSPI */\
	268	+ MUX_VAL(CP(MCSPI1_CLK), (IEN \| PTD \| DIS \| M0)) \
	269	+ MUX_VAL(CP(MCSPI1_SIMO), (IEN \| PTD \| DIS \| M0)) \
	270	+ MUX_VAL(CP(MCSPI1_SOMI), (IEN \| PTD \| DIS \| M0)) \
	271	+ MUX_VAL(CP(MCSPI1_CS0), (IEN \| PTD \| EN \| M0)) \
	272	+ MUX_VAL(CP(MCSPI1_CS1), (IEN \| PTU \| EN \| M4)) \
	273	+ MUX_VAL(CP(MCSPI1_CS2), (IEN \| PTU \| EN \| M4)) \
	274	+ MUX_VAL(CP(MCSPI1_CS3), (IEN \| PTU \| EN \| M4)) \
	275	+ MUX_VAL(CP(MCSPI2_CLK), (IEN \| PTD \| DIS \| M3)) \
	276	+ /* HSUSB2_dat7 */\
	277	+ MUX_VAL(CP(MCSPI2_SIMO), (IEN \| PTD \| DIS \| M3)) \
	278	+ /* HSUSB2_dat4 */\
	279	+ MUX_VAL(CP(MCSPI2_SOMI), (IEN \| PTD \| DIS \| M3)) \
	280	+ /* HSUSB2_dat5 */\
	281	+ MUX_VAL(CP(MCSPI2_CS0), (IEN \| PTD \| DIS \| M3)) \
	282	+ /* HSUSB2_dat6 */\
	283	+ MUX_VAL(CP(MCSPI2_CS1), (IEN \| PTD \| DIS \| M3)) \
	284	+ /* HSUSB2_dat3 */\
	285	+ /* CCDC */\
	286	+ MUX_VAL(CP(CCDC_PCLK), (IEN \| PTD \| EN \| M4)) \
	287	+ MUX_VAL(CP(CCDC_FIELD), (IEN \| PTD \| EN \| M4)) \
	288	+ MUX_VAL(CP(CCDC_HD), (IEN \| PTD \| EN \| M4)) \
	289	+ MUX_VAL(CP(CCDC_VD), (IEN \| PTD \| EN \| M4)) \
	290	+ MUX_VAL(CP(CCDC_WEN), (IEN \| PTD \| EN \| M4)) \
	291	+ MUX_VAL(CP(CCDC_DATA0), (IEN \| PTD \| EN \| M4)) \
	292	+ MUX_VAL(CP(CCDC_DATA1), (IEN \| PTD \| EN \| M4)) \
	293	+ MUX_VAL(CP(CCDC_DATA2), (IEN \| PTD \| EN \| M4)) \
	294	+ MUX_VAL(CP(CCDC_DATA3), (IEN \| PTD \| EN \| M4)) \
	295	+ MUX_VAL(CP(CCDC_DATA4), (IEN \| PTD \| EN \| M4)) \
	296	+ MUX_VAL(CP(CCDC_DATA5), (IEN \| PTD \| EN \| M4)) \
	297	+ MUX_VAL(CP(CCDC_DATA6), (IEN \| PTD \| EN \| M4)) \
	298	+ MUX_VAL(CP(CCDC_DATA7), (IEN \| PTD \| EN \| M4)) \
	299	+ /* RMII */\
	300	+ MUX_VAL(CP(RMII_MDIO_DATA), (IEN \| M0)) \
	301	+ MUX_VAL(CP(RMII_MDIO_CLK), (M0)) \
	302	+ MUX_VAL(CP(RMII_RXD0), (IEN \| PTD \| M0)) \
	303	+ MUX_VAL(CP(RMII_RXD1), (IEN \| PTD \| M0)) \
	304	+ MUX_VAL(CP(RMII_CRS_DV), (IEN \| PTD \| M0)) \
	305	+ MUX_VAL(CP(RMII_RXER), (PTD \| M0)) \
	306	+ MUX_VAL(CP(RMII_TXD0), (PTD \| M0)) \
	307	+ MUX_VAL(CP(RMII_TXD1), (PTD \| M0)) \
	308	+ MUX_VAL(CP(RMII_TXEN), (PTD \| M0)) \
	309	+ MUX_VAL(CP(RMII_50MHZ_CLK), (IEN \| PTD \| EN \| M0)) \
	310	+ /* HECC */\
	311	+ MUX_VAL(CP(HECC1_TXD), (IEN \| PTD \| EN \| M4)) \
	312	+ MUX_VAL(CP(HECC1_RXD), (IEN \| PTD \| EN \| M4)) \
	313	+ /* HSUSB */\
	314	+ MUX_VAL(CP(HSUSB0_CLK), (IEN \| PTD \| DIS \| M0)) \
	315	+ MUX_VAL(CP(HSUSB0_STP), (IDIS \| PTU \| EN \| M0)) \
	316	+ MUX_VAL(CP(HSUSB0_DIR), (IEN \| PTD \| DIS \| M0)) \
	317	+ MUX_VAL(CP(HSUSB0_NXT), (IEN \| PTD \| DIS \| M0)) \
	318	+ MUX_VAL(CP(HSUSB0_DATA0), (IEN \| PTD \| DIS \| M0)) \
	319	+ MUX_VAL(CP(HSUSB0_DATA1), (IEN \| PTD \| DIS \| M0)) \
	320	+ MUX_VAL(CP(HSUSB0_DATA2), (IEN \| PTD \| DIS \| M0)) \
	321	+ MUX_VAL(CP(HSUSB0_DATA3), (IEN \| PTD \| DIS \| M0)) \
	322	+ MUX_VAL(CP(HSUSB0_DATA4), (IEN \| PTD \| DIS \| M0)) \
	323	+ MUX_VAL(CP(HSUSB0_DATA5), (IEN \| PTD \| DIS \| M0)) \
	324	+ MUX_VAL(CP(HSUSB0_DATA6), (IEN \| PTD \| DIS \| M0)) \
	325	+ MUX_VAL(CP(HSUSB0_DATA7), (IEN \| PTD \| DIS \| M0)) \
	326	+ MUX_VAL(CP(USB0_DRVBUS), (IEN \| PTD \| EN \| M0)) \
	327	+ /* HDQ */\
	328	+ MUX_VAL(CP(HDQ_SIO), (IEN \| PTD \| EN \| M4)) \
	329	+ /* Control and debug */\
	330	+ MUX_VAL(CP(SYS_32K), (IEN \| PTD \| EN \| M4)) \
	331	+ MUX_VAL(CP(SYS_CLKREQ), (IEN \| PTD \| DIS \| M0)) \
	332	+ MUX_VAL(CP(SYS_NIRQ), (IEN \| PTD \| EN \| M4)) \
	333	+ MUX_VAL(CP(SYS_NRESWARM), (IEN \| PTU \| DIS \| M4)) \
	334	+ /* SYS_nRESWARM */\
	335	+ MUX_VAL(CP(SYS_BOOT0), (IEN \| PTD \| DIS \| M4)) \
	336	+ MUX_VAL(CP(SYS_BOOT1), (IEN \| PTD \| DIS \| M4)) \
	337	+ MUX_VAL(CP(SYS_BOOT2), (IEN \| PTD \| DIS \| M4)) \
	338	+ MUX_VAL(CP(SYS_BOOT3), (IEN \| PTD \| DIS \| M4)) \
	339	+ MUX_VAL(CP(SYS_BOOT4), (IEN \| PTD \| DIS \| M4)) \
	340	+ MUX_VAL(CP(SYS_BOOT5), (IEN \| PTD \| DIS \| M4))\
	341	+ MUX_VAL(CP(SYS_BOOT6), (IEN \| PTD \| DIS \| M4))\
	342	+ MUX_VAL(CP(SYS_BOOT7), (IEN \| PTD \| DIS \| M4)) \
	343	+ MUX_VAL(CP(SYS_BOOT8), (IEN \| PTD \| DIS \| M4)) \
	344	+ \
	345	+ MUX_VAL(CP(SYS_OFF_MODE), (IEN \| PTD \| DIS \| M0)) \
	346	+ MUX_VAL(CP(SYS_CLKOUT1), (IEN \| PTD \| DIS \| M4))\
	347	+ MUX_VAL(CP(SYS_CLKOUT2), (IDIS \| PTU \| DIS \| M4))\
	348	+ /* JTAG */\
	349	+ MUX_VAL(CP(JTAG_nTRST), (IEN \| PTU \| EN \| M4)) \
	350	+ MUX_VAL(CP(JTAG_TCK), (IEN \| PTU \| EN \| M4)) \
	351	+ MUX_VAL(CP(JTAG_TMS), (IEN \| PTU \| EN \| M4)) \
	352	+ MUX_VAL(CP(JTAG_TDI), (IEN \| PTU \| EN \| M4)) \
	353	+ MUX_VAL(CP(JTAG_EMU0), (IEN \| PTU \| EN \| M4)) \
	354	+ MUX_VAL(CP(JTAG_EMU1), (IEN \| PTU \| EN \| M4))\
	355	+ /* ETK (ES2 onwards) */\
	356	+ MUX_VAL(CP(ETK_CLK_ES2), (IDIS \| PTD \| DIS \| M3)) \
	357	+ /* hsusb1_stp */ \
	358	+ MUX_VAL(CP(ETK_CTL_ES2), (IDIS \| PTD \| DIS \| M3)) \
	359	+ /* hsusb1_clk */\
	360	+ MUX_VAL(CP(ETK_D0_ES2), (IEN \| PTD \| EN \| M3)) \
	361	+ MUX_VAL(CP(ETK_D1_ES2), (IEN \| PTD \| EN \| M3)) \
	362	+ MUX_VAL(CP(ETK_D2_ES2), (IEN \| PTD \| EN \| M3)) \
	363	+ MUX_VAL(CP(ETK_D3_ES2), (IEN \| PTD \| EN \| M3)) \
	364	+ MUX_VAL(CP(ETK_D4_ES2), (IEN \| PTD \| EN \| M3)) \
	365	+ MUX_VAL(CP(ETK_D5_ES2), (IEN \| PTD \| EN \| M3)) \
	366	+ MUX_VAL(CP(ETK_D6_ES2), (IEN \| PTD \| EN \| M3)) \
	367	+ MUX_VAL(CP(ETK_D7_ES2), (IEN \| PTD \| EN \| M3)) \
	368	+ MUX_VAL(CP(ETK_D8_ES2), (IEN \| PTD \| EN \| M3)) \
	369	+ MUX_VAL(CP(ETK_D9_ES2), (IEN \| PTD \| EN \| M3)) \
	370	+ MUX_VAL(CP(ETK_D10_ES2), (IEN \| PTD \| DIS \| M4)) \
	371	+ MUX_VAL(CP(ETK_D11_ES2), (IEN \| PTD \| DIS \| M4)) \
	372	+ MUX_VAL(CP(ETK_D12_ES2), (IEN \| PTD \| DIS \| M4)) \
	373	+ MUX_VAL(CP(ETK_D13_ES2), (IEN \| PTD \| DIS \| M4)) \
	374	+ MUX_VAL(CP(ETK_D14_ES2), (IEN \| PTD \| DIS \| M4)) \
	375	+ MUX_VAL(CP(ETK_D15_ES2), (IEN \| PTD \| DIS \| M4)) \
	376	+ /* Die to Die */\
	377	+ MUX_VAL(CP(D2D_MCAD34), (IEN \| PTD \| EN \| M0)) \
	378	+ MUX_VAL(CP(D2D_MCAD35), (IEN \| PTD \| EN \| M0)) \
	379	+ MUX_VAL(CP(D2D_MCAD36), (IEN \| PTD \| EN \| M0)) \
	380	+ MUX_VAL(CP(D2D_CLK26MI), (IEN \| PTD \| DIS \| M0)) \
	381	+ MUX_VAL(CP(D2D_NRESPWRON), (IEN \| PTD \| EN \| M0)) \
	382	+ MUX_VAL(CP(D2D_NRESWARM), (IEN \| PTU \| EN \| M0)) \
	383	+ MUX_VAL(CP(D2D_ARM9NIRQ), (IEN \| PTD \| DIS \| M0)) \
	384	+ MUX_VAL(CP(D2D_UMA2P6FIQ), (IEN \| PTD \| DIS \| M0)) \
	385	+ MUX_VAL(CP(D2D_SPINT), (IEN \| PTD \| EN \| M0)) \
	386	+ MUX_VAL(CP(D2D_FRINT), (IEN \| PTD \| EN \| M0)) \
	387	+ MUX_VAL(CP(D2D_DMAREQ0), (IEN \| PTD \| DIS \| M0)) \
	388	+ MUX_VAL(CP(D2D_DMAREQ1), (IEN \| PTD \| DIS \| M0)) \
	389	+ MUX_VAL(CP(D2D_DMAREQ2), (IEN \| PTD \| DIS \| M0)) \
	390	+ MUX_VAL(CP(D2D_DMAREQ3), (IEN \| PTD \| DIS \| M0)) \
	391	+ MUX_VAL(CP(D2D_N3GTRST), (IEN \| PTD \| DIS \| M0)) \
	392	+ MUX_VAL(CP(D2D_N3GTDI), (IEN \| PTD \| DIS \| M0)) \
	393	+ MUX_VAL(CP(D2D_N3GTDO), (IEN \| PTD \| DIS \| M0)) \
	394	+ MUX_VAL(CP(D2D_N3GTMS), (IEN \| PTD \| DIS \| M0)) \
	395	+ MUX_VAL(CP(D2D_N3GTCK), (IEN \| PTD \| DIS \| M0)) \
	396	+ MUX_VAL(CP(D2D_N3GRTCK), (IEN \| PTD \| DIS \| M0)) \
	397	+ MUX_VAL(CP(D2D_MSTDBY), (IEN \| PTU \| EN \| M0)) \
	398	+ MUX_VAL(CP(D2D_SWAKEUP), (IEN \| PTD \| EN \| M0)) \
	399	+ MUX_VAL(CP(D2D_IDLEREQ), (IEN \| PTD \| DIS \| M0)) \
	400	+ MUX_VAL(CP(D2D_IDLEACK), (IEN \| PTU \| EN \| M0)) \
	401	+ MUX_VAL(CP(D2D_MWRITE), (IEN \| PTD \| DIS \| M0)) \
	402	+ MUX_VAL(CP(D2D_SWRITE), (IEN \| PTD \| DIS \| M0)) \
	403	+ MUX_VAL(CP(D2D_MREAD), (IEN \| PTD \| DIS \| M0)) \
	404	+ MUX_VAL(CP(D2D_SREAD), (IEN \| PTD \| DIS \| M0)) \
	405	+ MUX_VAL(CP(D2D_MBUSFLAG), (IEN \| PTD \| DIS \| M0)) \
	406	+ MUX_VAL(CP(D2D_SBUSFLAG), (IEN \| PTD \| DIS \| M0)) \
	407	+
	408	+#endif
...	...	@@ -219,6 +219,7 @@
219	219	omap3_evm_quick_nand arm armv7 evm ti omap3
220	220	omap3_sdp3430 arm armv7 sdp3430 ti omap3
221	221	devkit8000 arm armv7 devkit8000 timll omap3
	222	+mcx arm armv7 mcx htkw omap3
222	223	tricorder arm armv7 tricorder corscience omap3
223	224	twister arm armv7 twister technexion omap3
224	225	omap4_panda arm armv7 panda ti omap4
	1	+/*
	2	+ * Copyright (C) 2011 Ilya Yanok, Emcraft Systems
	3	+ *
	4	+ * Based on omap3_evm_config.h
	5	+ *
	6	+ * This program is free software; you can redistribute it and/or modify
	7	+ * it under the terms of the GNU General Public License as published by
	8	+ * the Free Software Foundation; either version 2 of the License, or
	9	+ * (at your option) any later version.
	10	+ *
	11	+ * This program is distributed in the hope that it will be useful,
	12	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	+ * GNU General Public License for more details.
	15	+ *
	16	+ * You should have received a copy of the GNU General Public License
	17	+ * along with this program; if not, write to the Free Software
	18	+ * Foundation, Inc.
	19	+ */
	20	+
	21	+#ifndef __CONFIG_H
	22	+#define __CONFIG_H
	23	+
	24	+/*
	25	+ * High Level Configuration Options
	26	+ */
	27	+#define CONFIG_OMAP /* in a TI OMAP core */
	28	+#define CONFIG_OMAP34XX /* which is a 34XX */
	29	+#define CONFIG_OMAP3_MCX /* working with mcx */
	30	+
	31	+#define MACH_TYPE_MCX 3656
	32	+#define CONFIG_MACH_TYPE MACH_TYPE_MCX
	33	+
	34	+#define CONFIG_SYS_CACHELINE_SIZE 64
	35	+
	36	+#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
	37	+
	38	+#include <asm/arch/cpu.h> /* get chip and board defs */
	39	+#include <asm/arch/omap3.h>
	40	+
	41	+#define CONFIG_OF_LIBFDT
	42	+#define CONFIG_FIT
	43	+
	44	+/*
	45	+ * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader
	46	+ * and older u-boot.bin with the new U-Boot SPL.
	47	+ */
	48	+#define CONFIG_SYS_TEXT_BASE 0x80008000
	49	+
	50	+/*
	51	+ * Display CPU and Board information
	52	+ */
	53	+#define CONFIG_DISPLAY_CPUINFO
	54	+#define CONFIG_DISPLAY_BOARDINFO
	55	+
	56	+/* Clock Defines */
	57	+#define V_OSCK 26000000 /* Clock output from T2 */
	58	+#define V_SCLK (V_OSCK >> 1)
	59	+
	60	+#define CONFIG_MISC_INIT_R
	61	+
	62	+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	63	+#define CONFIG_SETUP_MEMORY_TAGS
	64	+#define CONFIG_INITRD_TAG
	65	+#define CONFIG_REVISION_TAG
	66	+
	67	+/*
	68	+ * Size of malloc() pool
	69	+ */
	70	+#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
	71	+#define CONFIG_SYS_MALLOC_LEN (1024 << 10)
	72	+/*
	73	+ * DDR related
	74	+ */
	75	+#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
	76	+
	77	+/*
	78	+ * Hardware drivers
	79	+ */
	80	+
	81	+/*
	82	+ * NS16550 Configuration
	83	+ */
	84	+#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
	85	+
	86	+#define CONFIG_SYS_NS16550
	87	+#define CONFIG_SYS_NS16550_SERIAL
	88	+#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	89	+#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
	90	+
	91	+/*
	92	+ * select serial console configuration
	93	+ */
	94	+#define CONFIG_CONS_INDEX 3
	95	+#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
	96	+#define CONFIG_SERIAL3 3 /* UART3 */
	97	+
	98	+/* allow to overwrite serial and ethaddr */
	99	+#define CONFIG_ENV_OVERWRITE
	100	+#define CONFIG_BAUDRATE 115200
	101	+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
	102	+ 115200}
	103	+#define CONFIG_MMC
	104	+#define CONFIG_OMAP_HSMMC
	105	+#define CONFIG_GENERIC_MMC
	106	+#define CONFIG_DOS_PARTITION
	107	+
	108	+/* EHCI */
	109	+#define CONFIG_USB_STORAGE
	110	+#define CONFIG_OMAP3_GPIO_5
	111	+#define CONFIG_USB_EHCI
	112	+#define CONFIG_USB_EHCI_OMAP
	113	+#define CONFIG_USB_ULPI
	114	+#define CONFIG_USB_ULPI_VIEWPORT_OMAP
	115	+/#define CONFIG_EHCI_DCACHE/ /* leave it disabled for now */
	116	+#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 154
	117	+#define CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 152
	118	+#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
	119	+
	120	+/* commands to include */
	121	+#include <config_cmd_default.h>
	122	+
	123	+#define CONFIG_CMD_EXT2 /* EXT2 Support */
	124	+#define CONFIG_CMD_FAT /* FAT support */
	125	+#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
	126	+
	127	+#define CONFIG_CMD_DATE
	128	+#define CONFIG_CMD_I2C /* I2C serial bus support */
	129	+#define CONFIG_CMD_MMC /* MMC support */
	130	+#define CONFIG_CMD_FAT /* FAT support */
	131	+#define CONFIG_CMD_USB
	132	+#define CONFIG_CMD_NAND /* NAND support */
	133	+#define CONFIG_CMD_DHCP
	134	+#define CONFIG_CMD_PING
	135	+#define CONFIG_CMD_CACHE
	136	+#define CONFIG_CMD_UBI
	137	+#define CONFIG_CMD_UBIFS
	138	+#define CONFIG_RBTREE
	139	+#define CONFIG_LZO
	140	+#define CONFIG_MTD_PARTITIONS
	141	+#define CONFIG_MTD_DEVICE
	142	+#define CONFIG_CMD_MTDPARTS
	143	+
	144	+#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
	145	+#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
	146	+#undef CONFIG_CMD_IMI /* iminfo */
	147	+#undef CONFIG_CMD_IMLS /* List all found images */
	148	+
	149	+#define CONFIG_SYS_NO_FLASH
	150	+#define CONFIG_HARD_I2C
	151	+#define CONFIG_SYS_I2C_SPEED 100000
	152	+#define CONFIG_SYS_I2C_SLAVE 1
	153	+#define CONFIG_SYS_I2C_BUS 0
	154	+#define CONFIG_DRIVER_OMAP34XX_I2C
	155	+
	156	+/* RTC */
	157	+#define CONFIG_RTC_DS1337
	158	+#define CONFIG_SYS_I2C_RTC_ADDR 0x68
	159	+
	160	+#define CONFIG_CMD_NET
	161	+#define CONFIG_CMD_MII
	162	+#define CONFIG_CMD_NFS
	163	+/*
	164	+ * Board NAND Info.
	165	+ */
	166	+#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
	167	+ /* to access nand */
	168	+#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
	169	+ /* to access */
	170	+ /* nand at CS0 */
	171	+
	172	+#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
	173	+ /* NAND devices */
	174	+#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
	175	+
	176	+#define CONFIG_JFFS2_NAND
	177	+/* nand device jffs2 lives on */
	178	+#define CONFIG_JFFS2_DEV "nand0"
	179	+/* start of jffs2 partition */
	180	+#define CONFIG_JFFS2_PART_OFFSET 0x680000
	181	+#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
	182	+
	183	+/* Environment information */
	184	+#define CONFIG_BOOTDELAY 10
	185	+
	186	+#define CONFIG_BOOTFILE "uImage"
	187	+
	188	+#define CONFIG_EXTRA_ENV_SETTINGS \
	189	+ "loadaddr=0x82000000\0" \
	190	+ "console=ttyO2,115200n8\0" \
	191	+ "mmcargs=setenv bootargs console=${console} " \
	192	+ "root=/dev/mmcblk0p2 rw " \
	193	+ "rootfstype=ext3 rootwait\0" \
	194	+ "nandargs=setenv bootargs console=${console} " \
	195	+ "root=/dev/mtdblock4 rw " \
	196	+ "rootfstype=jffs2\0" \
	197	+ "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
	198	+ "bootscript=echo Running bootscript from mmc ...; " \
	199	+ "source ${loadaddr}\0" \
	200	+ "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
	201	+ "mmcboot=echo Booting from mmc ...; " \
	202	+ "run mmcargs; " \
	203	+ "bootm ${loadaddr}\0" \
	204	+ "nandboot=echo Booting from nand ...; " \
	205	+ "run nandargs; " \
	206	+ "nand read ${loadaddr} 280000 400000; " \
	207	+ "bootm ${loadaddr}\0" \
	208	+
	209	+#define CONFIG_BOOTCOMMAND \
	210	+ "if mmc init; then " \
	211	+ "if run loadbootscript; then " \
	212	+ "run bootscript; " \
	213	+ "else " \
	214	+ "if run loaduimage; then " \
	215	+ "run mmcboot; " \
	216	+ "else run nandboot; " \
	217	+ "fi; " \
	218	+ "fi; " \
	219	+ "else run nandboot; fi"
	220	+
	221	+#define CONFIG_AUTO_COMPLETE
	222	+/*
	223	+ * Miscellaneous configurable options
	224	+ */
	225	+#define V_PROMPT "mcx # "
	226	+
	227	+#define CONFIG_SYS_LONGHELP /* undef to save memory */
	228	+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
	229	+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
	230	+#define CONFIG_SYS_PROMPT V_PROMPT
	231	+#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
	232	+/* Print Buffer Size */
	233	+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	234	+ sizeof(CONFIG_SYS_PROMPT) + 16)
	235	+#define CONFIG_SYS_MAXARGS 16 /* max number of command */
	236	+ /* args */
	237	+/* Boot Argument Buffer Size */
	238	+#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	239	+/* memtest works on */
	240	+#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
	241	+#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
	242	+ 0x01F00000) /* 31MB */
	243	+
	244	+#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
	245	+ /* address */
	246	+
	247	+/*
	248	+ * AM3517 has 12 GP timers, they can be driven by the system clock
	249	+ * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
	250	+ * This rate is divided by a local divisor.
	251	+ */
	252	+#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
	253	+#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
	254	+#define CONFIG_SYS_HZ 1000
	255	+
	256	+/*
	257	+ * Stack sizes
	258	+ *
	259	+ * The stack sizes are set up in start.S using the settings below
	260	+ */
	261	+#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
	262	+
	263	+/*
	264	+ * Physical Memory Map
	265	+ */
	266	+#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
	267	+#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
	268	+#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
	269	+#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
	270	+
	271	+/*
	272	+ * FLASH and environment organization
	273	+ */
	274	+
	275	+/* ** PISMO SUPPORT * */
	276	+
	277	+/* Configure the PISMO */
	278	+#define PISMO1_NAND_SIZE GPMC_SIZE_128M
	279	+
	280	+#define CONFIG_NAND_OMAP_GPMC
	281	+#define GPMC_NAND_ECC_LP_x16_LAYOUT
	282	+#define CONFIG_ENV_IS_IN_NAND
	283	+#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
	284	+
	285	+#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
	286	+#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
	287	+#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
	288	+
	289	+/*
	290	+ * CFI FLASH driver setup
	291	+ */
	292	+/* timeout values are in ticks */
	293	+#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
	294	+#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
	295	+
	296	+/* Flash banks JFFS2 should use */
	297	+#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
	298	+ CONFIG_SYS_MAX_NAND_DEVICE)
	299	+#define CONFIG_SYS_JFFS2_MEM_NAND
	300	+/* use flash_info[2] */
	301	+#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
	302	+#define CONFIG_SYS_JFFS2_NUM_BANKS 1
	303	+
	304	+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	305	+#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
	306	+#define CONFIG_SYS_INIT_RAM_SIZE 0x800
	307	+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	308	+ CONFIG_SYS_INIT_RAM_SIZE - \
	309	+ GENERATED_GBL_DATA_SIZE)
	310	+
	311	+/* Defines for SPL */
	312	+#define CONFIG_SPL
	313	+#define CONFIG_SPL_NAND_SIMPLE
	314	+#define CONFIG_SPL_NAND_SOFTECC
	315	+
	316	+#define CONFIG_SPL_LIBCOMMON_SUPPORT
	317	+#define CONFIG_SPL_LIBDISK_SUPPORT
	318	+#define CONFIG_SPL_I2C_SUPPORT
	319	+#define CONFIG_SPL_MMC_SUPPORT
	320	+#define CONFIG_SPL_FAT_SUPPORT
	321	+#define CONFIG_SPL_LIBGENERIC_SUPPORT
	322	+#define CONFIG_SPL_SERIAL_SUPPORT
	323	+#define CONFIG_SPL_POWER_SUPPORT
	324	+#define CONFIG_SPL_NAND_SUPPORT
	325	+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
	326	+
	327	+#define CONFIG_SPL_TEXT_BASE 0x40200000 /CONFIG_SYS_SRAM_START/
	328	+#define CONFIG_SPL_MAX_SIZE (45 << 10)
	329	+#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
	330	+
	331	+/* move malloc and bss high to prevent clashing with the main image */
	332	+#define CONFIG_SYS_SPL_MALLOC_START 0x8f000000
	333	+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
	334	+#define CONFIG_SPL_BSS_START_ADDR 0x8f080000 /* end of RAM */
	335	+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
	336	+
	337	+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
	338	+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
	339	+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
	340	+
	341	+/* NAND boot config */
	342	+#define CONFIG_SYS_NAND_PAGE_COUNT 64
	343	+#define CONFIG_SYS_NAND_PAGE_SIZE 2048
	344	+#define CONFIG_SYS_NAND_OOBSIZE 64
	345	+#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
	346	+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	347	+#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
	348	+#define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47,\
	349	+ 48, 49, 50, 51, 52, 53, 54, 55,\
	350	+ 56, 57, 58, 59, 60, 61, 62, 63}
	351	+#define CONFIG_SYS_NAND_ECCSIZE 256
	352	+#define CONFIG_SYS_NAND_ECCBYTES 3
	353	+
	354	+#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
	355	+ CONFIG_SYS_NAND_ECCSIZE)
	356	+#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \
	357	+ CONFIG_SYS_NAND_ECCSTEPS)
	358	+
	359	+#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
	360	+
	361	+#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
	362	+
	363	+/*
	364	+ * ethernet support
	365	+ *
	366	+ */
	367	+#if defined(CONFIG_CMD_NET)
	368	+#define CONFIG_DRIVER_TI_EMAC
	369	+#define CONFIG_DRIVER_TI_EMAC_USE_RMII
	370	+#define CONFIG_MII
	371	+#define CONFIG_BOOTP_DEFAULT
	372	+#define CONFIG_BOOTP_DNS
	373	+#define CONFIG_BOOTP_DNS2
	374	+#define CONFIG_BOOTP_SEND_HOSTNAME
	375	+#define CONFIG_NET_RETRY_COUNT 10
	376	+#endif
	377	+
	378	+#endif /* __CONFIG_H */