Eric Lee / smarc-uboot | Embedian Git Server

Commit 4adb46a3144248b2d8b8a68684bee648815c4ada

Authored by Stefan Roese 2015-03-11 19:05:04 +0800

Committed by Luka Perkov 2015-04-11 17:49:00 +0800

Exists in v2017.01-smarct4x and in 37 other branches

arm: armada-xp: Fix SPL for AXP by using save_boot_params_ret

Patch e11c6c27 (arm: Allow lr to be saved by board code) introduced
a different method to return from save_boot_params(). The SPL support
for AXP has been pulled and changing to this new method is now
required for SPL to work correctly.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Luka Perkov <luka.perkov@sartura.hr>

Showing 1 changed file with 1 additions and 1 deletions Inline Diff

arch/arm/cpu/armv7/armada-xp/lowlevel_spl.S

arch/arm/cpu/armv7/armada-xp/lowlevel_spl.S

Diff comments View file @ 4adb46a

1	/*	1	/*
2	* SPDX-License-Identifier: GPL-2.0+	2	* SPDX-License-Identifier: GPL-2.0+
3	*/	3	*/
4		4
5	#include <config.h>	5	#include <config.h>
6	#include <linux/linkage.h>	6	#include <linux/linkage.h>
7		7
8	ENTRY(save_boot_params)	8	ENTRY(save_boot_params)
9	bx lr	9	b save_boot_params_ret
10	ENDPROC(save_boot_params)	10	ENDPROC(save_boot_params)
11		11
12	/*	12	/*
13	* cache_inv - invalidate Cache line	13	* cache_inv - invalidate Cache line
14	* r0 - dest	14	* r0 - dest
15	*/	15	*/
16	.global cache_inv	16	.global cache_inv
17	.type cache_inv, %function	17	.type cache_inv, %function
18	cache_inv:	18	cache_inv:
19		19
20	stmfd sp!, {r1-r12}	20	stmfd sp!, {r1-r12}
21		21
22	mcr p15, 0, r0, c7, c6, 1	22	mcr p15, 0, r0, c7, c6, 1
23		23
24	ldmfd sp!, {r1-r12}	24	ldmfd sp!, {r1-r12}
25	bx lr	25	bx lr
26		26
27		27
28	/*	28	/*
29	* flush_l1_v6 - l1 cache clean invalidate	29	* flush_l1_v6 - l1 cache clean invalidate
30	* r0 - dest	30	* r0 - dest
31	*/	31	*/
32	.global flush_l1_v6	32	.global flush_l1_v6
33	.type flush_l1_v6, %function	33	.type flush_l1_v6, %function
34	flush_l1_v6:	34	flush_l1_v6:
35		35
36	stmfd sp!, {r1-r12}	36	stmfd sp!, {r1-r12}
37		37
38	mcr p15, 0, r0, c7, c10, 5 /* @ data memory barrier */	38	mcr p15, 0, r0, c7, c10, 5 /* @ data memory barrier */
39	mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */	39	mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */
40	mcr p15, 0, r0, c7, c10, 4 /* @ data sync barrier */	40	mcr p15, 0, r0, c7, c10, 4 /* @ data sync barrier */
41		41
42	ldmfd sp!, {r1-r12}	42	ldmfd sp!, {r1-r12}
43	bx lr	43	bx lr
44		44
45		45
46	/*	46	/*
47	* flush_l1_v7 - l1 cache clean invalidate	47	* flush_l1_v7 - l1 cache clean invalidate
48	* r0 - dest	48	* r0 - dest
49	*/	49	*/
50	.global flush_l1_v7	50	.global flush_l1_v7
51	.type flush_l1_v7, %function	51	.type flush_l1_v7, %function
52	flush_l1_v7:	52	flush_l1_v7:
53		53
54	stmfd sp!, {r1-r12}	54	stmfd sp!, {r1-r12}
55		55
56	dmb /* @data memory barrier */	56	dmb /* @data memory barrier */
57	mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */	57	mcr p15, 0, r0, c7, c14, 1 /* @ clean & invalidate D line */
58	dsb /* @data sync barrier */	58	dsb /* @data sync barrier */
59		59
60	ldmfd sp!, {r1-r12}	60	ldmfd sp!, {r1-r12}
61	bx lr	61	bx lr
62		62