Merge git://git.denx.de/u-boot-arc

Tom Rini
2 parents a7b00a7bf6 a811492e4f
Showing 6 changed files Side-by-side Diff
arch/arc/cpu/u-boot.lds
arch/arc/lib/Makefile
board/synopsys/axs101/axs101.c
board/synopsys/axs101/axs10x.h
board/synopsys/axs101/nand.c
include/configs/axs101.h
@@ -13,6 +13,7 @@
 	.text :	{
 		*(.__text_start)
 		*(.__image_copy_start)
+		arch/arc/lib/start.o (.text*)
 		*(.text*)
 	}
  
@@ -4,6 +4,8 @@
 # SPDX-License-Identifier:	GPL-2.0+
 #
  
+extra-y	= start.o
+head-y := start.o
 obj-y += cache.o
 obj-y += cpu.o
 obj-y += interrupts.o
@@ -18,7 +20,6 @@
 obj-y += memset.o
 obj-y += reset.o
 obj-y += timer.o
-obj-y += start.o
 obj-y += ints_low.o
 obj-y += init_helpers.o
  
@@ -9,6 +9,7 @@
 #include <malloc.h>
 #include <netdev.h>
 #include <phy.h>
+#include "axs10x.h"
  
 DECLARE_GLOBAL_DATA_PTR;
  
@@ -39,6 +40,19 @@
 	if (designware_initialize(ARC_DWGMAC_BASE,
 				  PHY_INTERFACE_MODE_RGMII) >= 0)
 		return 1;
+
+	return 0;
+}
+
+
+#define AXS_MB_CREG	0xE0011000
+
+int board_early_init_f(void)
+{
+	if (readl((void __iomem *)AXS_MB_CREG + 0x234) & (1 << 28))
+		gd->board_type = AXS_MB_V3;
+	else
+		gd->board_type = AXS_MB_V2;
  
 	return 0;
 }
+/*
+ * Copyright (C) 2015 Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _BOARD_SYNOPSYS_AXS10X_H
+#define _BOARD_SYNOPSYS_AXS10X_H
+
+enum {
+	AXS_MB_V2,
+	AXS_MB_V3
+};
+
+#endif /* _BOARD_SYNOPSYS_AXS10X_H */
@@ -9,7 +9,10 @@
 #include <malloc.h>
 #include <nand.h>
 #include <asm/io.h>
+#include "axs10x.h"
  
+DECLARE_GLOBAL_DATA_PTR;
+
 #define BUS_WIDTH	8		/* AXI data bus width in bytes	*/
  
 /* DMA buffer descriptor bits & masks */
@@ -231,6 +234,10 @@
 	nand->read_word = axs101_nand_read_word;
 	nand->write_buf = axs101_nand_write_buf;
 	nand->read_buf = axs101_nand_read_buf;
+
+	/* MBv3 has NAND IC with 16-bit data bus */
+	if (gd->board_type == AXS_MB_V3)
+		nand->options |= NAND_BUSWIDTH_16;
  
 	return 0;
 }
@@ -34,6 +34,12 @@
 #define CONFIG_SYS_LOAD_ADDR		0x82000000
  
 /*
+ * This board might be of different versions so handle it
+ */
+#define CONFIG_BOARD_TYPES
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/*
  * NAND Flash configuration
  */
 #define CONFIG_SYS_NO_FLASH
...	...	@@ -13,6 +13,7 @@
13	13	.text : {
14	14	*(.__text_start)
15	15	*(.__image_copy_start)
	16	+ arch/arc/lib/start.o (.text*)
16	17	(.text)
17	18	}
18	19
...	...	@@ -4,6 +4,8 @@
4	4	# SPDX-License-Identifier: GPL-2.0+
5	5	#
6	6
	7	+extra-y = start.o
	8	+head-y := start.o
7	9	obj-y += cache.o
8	10	obj-y += cpu.o
9	11	obj-y += interrupts.o
...	...	@@ -18,7 +20,6 @@
18	20	obj-y += memset.o
19	21	obj-y += reset.o
20	22	obj-y += timer.o
21		-obj-y += start.o
22	23	obj-y += ints_low.o
23	24	obj-y += init_helpers.o
24	25
...	...	@@ -9,6 +9,7 @@
9	9	#include <malloc.h>
10	10	#include <netdev.h>
11	11	#include <phy.h>
	12	+#include "axs10x.h"
12	13
13	14	DECLARE_GLOBAL_DATA_PTR;
14	15
...	...	@@ -39,6 +40,19 @@
39	40	if (designware_initialize(ARC_DWGMAC_BASE,
40	41	PHY_INTERFACE_MODE_RGMII) >= 0)
41	42	return 1;
	43	+
	44	+ return 0;
	45	+}
	46	+
	47	+
	48	+#define AXS_MB_CREG 0xE0011000
	49	+
	50	+int board_early_init_f(void)
	51	+{
	52	+ if (readl((void __iomem *)AXS_MB_CREG + 0x234) & (1 << 28))
	53	+ gd->board_type = AXS_MB_V3;
	54	+ else
	55	+ gd->board_type = AXS_MB_V2;
42	56
43	57	return 0;
44	58	}
	1	+/*
	2	+ * Copyright (C) 2015 Synopsys, Inc. All rights reserved.
	3	+ *
	4	+ * SPDX-License-Identifier: GPL-2.0+
	5	+ */
	6	+
	7	+#ifndef _BOARD_SYNOPSYS_AXS10X_H
	8	+#define _BOARD_SYNOPSYS_AXS10X_H
	9	+
	10	+enum {
	11	+ AXS_MB_V2,
	12	+ AXS_MB_V3
	13	+};
	14	+
	15	+#endif /* _BOARD_SYNOPSYS_AXS10X_H */
...	...	@@ -9,7 +9,10 @@
9	9	#include <malloc.h>
10	10	#include <nand.h>
11	11	#include <asm/io.h>
	12	+#include "axs10x.h"
12	13
	14	+DECLARE_GLOBAL_DATA_PTR;
	15	+
13	16	#define BUS_WIDTH 8 /* AXI data bus width in bytes */
14	17
15	18	/* DMA buffer descriptor bits & masks */
...	...	@@ -231,6 +234,10 @@
231	234	nand->read_word = axs101_nand_read_word;
232	235	nand->write_buf = axs101_nand_write_buf;
233	236	nand->read_buf = axs101_nand_read_buf;
	237	+
	238	+ /* MBv3 has NAND IC with 16-bit data bus */
	239	+ if (gd->board_type == AXS_MB_V3)
	240	+ nand->options \|= NAND_BUSWIDTH_16;
234	241
235	242	return 0;
236	243	}
...	...	@@ -34,6 +34,12 @@
34	34	#define CONFIG_SYS_LOAD_ADDR 0x82000000
35	35
36	36	/*
	37	+ * This board might be of different versions so handle it
	38	+ */
	39	+#define CONFIG_BOARD_TYPES
	40	+#define CONFIG_BOARD_EARLY_INIT_F
	41	+
	42	+/*
37	43	* NAND Flash configuration
38	44	*/
39	45	#define CONFIG_SYS_NO_FLASH