Eric Lee / smarc-uboot | Embedian Git Server

Commit 4b2850ccfd8b387590c9fb4abfffdd0ac5cc8e58

Authored by Ye Li 2018-12-27 13:45:54 +0800

Exists in smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga and in 4 other branches

MLK-20664-1 imx8qxp: spl: Enable SPL container support for NAND

Add the NAND support to SPL container parser and enable it for imx8qxp arm2
nand reworked board.
The SPL NAND will read from nandfit mtdpart (128MB offset) to parsing the entire
boot image and get the 3rd container from it. This requires burning tool (uuu)
to program the entire boot image into nandfit.

Signed-off-by: Ye Li <ye.li@nxp.com>

Showing 4 changed files with 53 additions and 12 deletions Inline Diff

arch/arm/include/asm/arch-imx8/image.h
arch/arm/mach-imx/imx8/parser.c
common/spl/spl_nand.c
include/configs/imx8qxp_arm2.h

arch/arm/include/asm/arch-imx8/image.h

Diff comments View file @ 4b2850c

1	/* SPDX-License-Identifier: GPL-2.0+ */	1	/* SPDX-License-Identifier: GPL-2.0+ */
2	/*	2	/*
3	* Copyright 2018 NXP	3	* Copyright 2018 NXP
4	*/	4	*/
5		5
6	#define IV_MAX_LEN 32	6	#define IV_MAX_LEN 32
7	#define HASH_MAX_LEN 64	7	#define HASH_MAX_LEN 64
8		8
9	#define CONTAINER_HDR_ALIGNMENT 0x400	9	#define CONTAINER_HDR_ALIGNMENT 0x400
10	#define CONTAINER_HDR_EMMC_OFFSET 0	10	#define CONTAINER_HDR_EMMC_OFFSET 0
11	#define CONTAINER_HDR_MMCSD_OFFSET SZ_32K	11	#define CONTAINER_HDR_MMCSD_OFFSET SZ_32K
12	#define CONTAINER_HDR_QSPI_OFFSET SZ_4K	12	#define CONTAINER_HDR_QSPI_OFFSET SZ_4K
13	#define CONTAINER_HDR_NAND_OFFSET SZ_64M	13	#define CONTAINER_HDR_NAND_OFFSET SZ_128M
14		14
15	struct container_hdr{	15	struct container_hdr{
16	uint8_t version;	16	uint8_t version;
17	uint8_t length_lsb;	17	uint8_t length_lsb;
18	uint8_t length_msb;	18	uint8_t length_msb;
19	uint8_t tag;	19	uint8_t tag;
20	uint32_t flags;	20	uint32_t flags;
21	uint16_t sw_version;	21	uint16_t sw_version;
22	uint8_t fuse_version;	22	uint8_t fuse_version;
23	uint8_t num_images;	23	uint8_t num_images;
24	uint16_t sig_blk_offset;	24	uint16_t sig_blk_offset;
25	uint16_t reserved;	25	uint16_t reserved;
26	}__attribute__((packed));	26	}__attribute__((packed));
27		27
28	struct boot_img_t{	28	struct boot_img_t{
29	uint32_t offset;	29	uint32_t offset;
30	uint32_t size;	30	uint32_t size;
31	uint64_t dst;	31	uint64_t dst;
32	uint64_t entry;	32	uint64_t entry;
33	uint32_t hab_flags;	33	uint32_t hab_flags;
34	uint32_t meta;	34	uint32_t meta;
35	uint8_t hash[HASH_MAX_LEN];	35	uint8_t hash[HASH_MAX_LEN];
36	uint8_t iv[IV_MAX_LEN];	36	uint8_t iv[IV_MAX_LEN];
37	}__attribute__((packed));	37	}__attribute__((packed));
38		38
39	struct signature_block_hdr{	39	struct signature_block_hdr{
40	uint8_t version;	40	uint8_t version;
41	uint8_t length_lsb;	41	uint8_t length_lsb;
42	uint8_t length_msb;	42	uint8_t length_msb;
43	uint8_t tag;	43	uint8_t tag;
44	uint16_t srk_table_offset;	44	uint16_t srk_table_offset;
45	uint16_t cert_offset;	45	uint16_t cert_offset;
46	uint16_t blob_offset;	46	uint16_t blob_offset;
47	uint16_t signature_offset;	47	uint16_t signature_offset;
48	uint32_t reserved;	48	uint32_t reserved;
49	}__attribute__((packed));	49	}__attribute__((packed));
50		50

arch/arm/mach-imx/imx8/parser.c

Diff comments View file @ 4b2850c

 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2018 NXP
  */
 #include <common.h>
 #include <spl.h>
 #include <errno.h>
 #include <asm/io.h>
 #include <dm.h>
 #include <mmc.h>
 #include <spi_flash.h>
+#include <nand.h>
 #include <asm/arch/image.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/mach-imx/sci/sci.h>
 #include <asm/mach-imx/boot_mode.h>
 #define MMC_DEV		0
 #define QSPI_DEV	1
-#define RAM_DEV	3
+#define NAND_DEV	2
+#define RAM_DEV		3
 #define SEC_SECURE_RAM_BASE			(0x31800000UL)
 #define SEC_SECURE_RAM_END_BASE			(SEC_SECURE_RAM_BASE + 0xFFFFUL)
 #define SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE	(0x60000000UL)
 #define SECO_PT         2U
 DECLARE_GLOBAL_DATA_PTR;
 #if defined(CONFIG_IMX_TRUSTY_OS)
 /* Pre-declaration of check_rpmb_blob. */
 int check_rpmb_blob(struct mmc *mmc);
 #endif
 static int current_dev_type = MMC_DEV;
 static int start_offset;
 static void *device;
 static int read(u32 start, u32 len, void *load_addr)
 {
 	int ret = -ENODEV;
-	if (!device && current_dev_type != RAM_DEV) {
+	if (current_dev_type != NAND_DEV && current_dev_type != RAM_DEV
+		&& !device) {
 		debug("No device selected\n");
 		return ret;
 	}
 #ifdef CONFIG_SPL_MMC_SUPPORT
 	if (current_dev_type == MMC_DEV) {
 		struct mmc *mmc = (struct mmc *)device;
 		unsigned long count;
 		ret = 0;
 		count = blk_dread(mmc_get_blk_desc(mmc),
 				  start / mmc->read_bl_len,
 				  len / mmc->read_bl_len,
 				  load_addr);
 		if (count == 0) {
 			debug("Read container image failed\n");
 			return -EIO;
 		}
 	}
 #endif
 #ifdef CONFIG_SPL_SPI_LOAD
 	if (current_dev_type == QSPI_DEV) {
 		struct spi_flash *flash = (struct spi_flash *)device;
 		ret = spi_flash_read(flash, start,
 				     len, load_addr);
 		if (ret != 0) {
 			debug("Read container image from QSPI failed\n");
 			return -EIO;
 		}
 	}
 #endif
+#ifdef CONFIG_SPL_NAND_SUPPORT
+	if (current_dev_type == NAND_DEV) {
+		ret = nand_spl_load_image(start, len, load_addr);
+		if (ret != 0) {
+			debug("Read container image from NAND failed\n");
+			return -EIO;
+		}
+	}
+#endif
 	if (current_dev_type == RAM_DEV) {
 		memcpy(load_addr, (const void *)(ulong)start, len);
 		ret = 0;
 	}
 	return ret;
 }
 static int authenticate_image(struct boot_img_t *img, int image_index)
 {
 	sc_ipc_t ipcHndl = gd->arch.ipc_channel_handle;
 	sc_faddr_t start, end;
 	sc_rm_mr_t mr;
 	sc_err_t err;
 	int ret = 0;
 	debug("img %d, dst 0x%llx, src 0x%x, size 0x%x\n",
 	      image_index, img->dst, img->offset, img->size);
 	/* Find the memreg and set permission for seco pt */
 	err = sc_rm_find_memreg(ipcHndl, &mr,
 				img->dst & ~(CONFIG_SYS_CACHELINE_SIZE - 1),
 				ALIGN(img->dst + img->size, CONFIG_SYS_CACHELINE_SIZE));
 	if (err) {
 		printf("can't find memreg for image load address %d, error %d\n",
 		       image_index, err);
 		return -ENOMEM;
 	}
 	err = sc_rm_get_memreg_info(ipcHndl, mr, &start, &end);
 	if (!err)
 		debug("memreg %u 0x%llx -- 0x%llx\n", mr, start, end);
 	err = sc_rm_set_memreg_permissions(ipcHndl, mr,
 					   SECO_PT, SC_RM_PERM_FULL);
 	if (err) {
 		printf("set permission failed for img %d, error %d\n",
 		       image_index, err);
 		return -EPERM;
 	}
 	err = sc_misc_seco_authenticate(ipcHndl, SC_MISC_VERIFY_IMAGE,
 					1 << image_index);
 	if (err) {
 		printf("authenticate img %d failed, return %d\n",
 		       image_index, err);
 		ret = -EIO;
 	}
 	err = sc_rm_set_memreg_permissions(ipcHndl, mr,
 					   SECO_PT, SC_RM_PERM_NONE);
 	if (err) {
 		printf("remove permission failed for img %d, error %d\n",
 		       image_index, err);
 		ret = -EPERM;
 	}
 	return ret;
 }
 static struct boot_img_t *read_auth_image(struct container_hdr *container,
 					  int image_index)
 {
 	struct boot_img_t *images;
 	if (image_index > container->num_images) {
 		debug("Invalid image number\n");
 		return NULL;
 	}
 	images = (struct boot_img_t *)
 			((uint8_t *)container + sizeof(struct container_hdr));
 	if (read(images[image_index].offset + start_offset,
 			images[image_index].size,
 			(void *)images[image_index].entry) < 0) {
 		return NULL;
 	}
 	if (authenticate_image(&images[image_index], image_index)) {
 		printf("Failed to authenticate image %d\n", image_index);
 		return NULL;
 	}
 	return &images[image_index];
 }
 static int read_auth_container(struct spl_image_info *spl_image)
 {
 	sc_ipc_t ipcHndl = gd->arch.ipc_channel_handle;
 	struct container_hdr *container = NULL;
 	uint16_t length;
 	int ret;
 	int i;
 	container = malloc(CONTAINER_HDR_ALIGNMENT);
 	if (!container)
 		return -ENOMEM;
 	ret = read(start_offset, CONTAINER_HDR_ALIGNMENT, (void *)container);
 	if (ret)
 		return ret;
 	if (container->tag != 0x87 && container->version != 0x0) {
 		printf("Wrong container header\n");
 		ret = -EFAULT;
 		goto out;
 	}
 	if (!container->num_images) {
 		printf("Wrong container, no image found\n");
 		ret = -EFAULT;
 		goto out;
 	}
 	length = container->length_lsb + (container->length_msb << 8);
 	debug("container length %u\n", length);
 	memcpy((void *)SEC_SECURE_RAM_BASE, (const void *)container,
 	       ALIGN(length, CONFIG_SYS_CACHELINE_SIZE));
 	ret = sc_misc_seco_authenticate(ipcHndl, SC_MISC_AUTH_CONTAINER,
 					SECO_LOCAL_SEC_SEC_SECURE_RAM_BASE);
 	if (ret) {
 		printf("authenticate container hdr failed, return %d\n", ret);
 		ret = -EFAULT;
 		goto out;
 	}
 	for (i = 0; i < container->num_images; i++) {
 		struct boot_img_t *image = read_auth_image(container, i);
 		if (!image) {
 			ret = -EINVAL;
 			sc_misc_seco_authenticate(ipcHndl, SC_MISC_REL_CONTAINER, 0);
 			goto out;
 		}
 		if (i == 0) {
 			spl_image->load_addr = image->dst;
 			spl_image->entry_point = image->entry;
 		}
 	}
 	sc_misc_seco_authenticate(ipcHndl, SC_MISC_REL_CONTAINER, 0);
 out:
 	free(container);
 	return ret;
 }
 int mmc_load_image_parse_container(struct spl_image_info *spl_image,
 				     struct mmc *mmc, unsigned long sector)
 {
 	int ret = 0;
 	current_dev_type = MMC_DEV;
 	device = mmc;
 	start_offset = sector * mmc->read_bl_len;
 	ret = read_auth_container(spl_image);
 	if (!ret)
 	{
 		/* Images loaded, now check the rpmb keyblob for Trusty OS. */
 #if defined(CONFIG_IMX_TRUSTY_OS)
 		ret = check_rpmb_blob(mmc);
 #endif
 	}
 	return ret;
 }
 int spi_load_image_parse_container(struct spl_image_info *spl_image,
 				   struct spi_flash *flash,
 				   unsigned long offset)
 {
 	int ret = 0;
 	current_dev_type = QSPI_DEV;
 	device = flash;
+	start_offset = offset;
+	ret = read_auth_container(spl_image);
+	return ret;
+}
+int nand_load_image_parse_container(struct spl_image_info *spl_image,
+				   unsigned long offset)
+{
+	int ret = 0;
+	current_dev_type = NAND_DEV;
+	device = NULL;
 	start_offset = offset;
 	ret = read_auth_container(spl_image);
 	return ret;
 }
 int sdp_load_image_parse_container(struct spl_image_info *spl_image,
 				   unsigned long offset)
 {
 	int ret = 0;
 	current_dev_type = RAM_DEV;
 	device = NULL;
 	start_offset = offset;
 	ret = read_auth_container(spl_image);
 	return ret;
 }

common/spl/spl_nand.c

Diff comments View file @ 4b2850c

 /*
  * Copyright (C) 2011
  * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
 #include <config.h>
 #include <spl.h>
 #include <asm/io.h>
 #include <nand.h>
 #include <linux/libfdt_env.h>
 #include <fdt.h>
-#if defined(CONFIG_SPL_NAND_RAW_ONLY)
+#ifdef CONFIG_PARSE_CONTAINER
+int __weak nand_load_image_parse_container(struct spl_image_info *spl_image,
+				   unsigned long offset)
+{
+	return -EINVAL;
+}
+#endif
 uint32_t __weak spl_nand_get_uboot_raw_page(void)
 {
        return CONFIG_SYS_NAND_U_BOOT_OFFS;
 }
+#if defined(CONFIG_SPL_NAND_RAW_ONLY)
 int spl_nand_load_image(struct spl_image_info *spl_image,
 			struct spl_boot_device *bootdev)
 {
 	nand_init();
 	nand_spl_load_image(spl_nand_get_uboot_raw_page(),
 						CONFIG_SYS_NAND_U_BOOT_SIZE,
 						(void *)CONFIG_SYS_NAND_U_BOOT_DST);
 #if defined(CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE)
 	spl_set_header_raw_atf(spl_image);
 #else
 	spl_set_header_raw_uboot(spl_image);
 #endif
 	nand_deselect();
 	return 0;
 }
 #else
 static ulong spl_nand_fit_read(struct spl_load_info *load, ulong offs,
 			       ulong size, void *dst)
 {
 	int ret;
 	ret = nand_spl_load_image(offs, size, dst);
 	if (!ret)
 		return size;
 	else
 		return 0;
 }
 static int spl_nand_load_element(struct spl_image_info *spl_image,
 				 int offset, struct image_header *header)
 {
 	int err;
 	err = nand_spl_load_image(offset, sizeof(*header), (void *)header);
 	if (err)
 		return err;
 	if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
 	    image_get_magic(header) == FDT_MAGIC) {
 		struct spl_load_info load;
 		debug("Found FIT\n");
 		load.dev = NULL;
 		load.priv = NULL;
 		load.filename = NULL;
 		load.bl_len = 1;
 		load.read = spl_nand_fit_read;
 		return spl_load_simple_fit(spl_image, &load, offset, header);
 	} else {
+#ifdef CONFIG_PARSE_CONTAINER
+		return nand_load_image_parse_container(spl_image, offset);
+#else
 		err = spl_parse_image_header(spl_image, header);
 		if (err)
 			return err;
 		return nand_spl_load_image(offset, spl_image->size,
 					   (void *)(ulong)spl_image->load_addr);
+#endif
 	}
 }
 static int spl_nand_load_image(struct spl_image_info *spl_image,
 			       struct spl_boot_device *bootdev)
 {
 	int err;
 	struct image_header *header;
 	int *src __attribute__((unused));
 	int *dst __attribute__((unused));
 #ifdef CONFIG_SPL_NAND_SOFTECC
 	debug("spl: nand - using sw ecc\n");
 #else
 	debug("spl: nand - using hw ecc\n");
 #endif
 	nand_init();
 	/*use CONFIG_SYS_TEXT_BASE as temporary storage area */
 	header = (struct image_header *)(CONFIG_SYS_TEXT_BASE);
 #ifdef CONFIG_SPL_OS_BOOT
 	if (!spl_start_uboot()) {
 		/*
 		 * load parameter image
 		 * load to temp position since nand_spl_load_image reads
 		 * a whole block which is typically larger than
 		 * CONFIG_CMD_SPL_WRITE_SIZE therefore may overwrite
 		 * following sections like BSS
 		 */
 		nand_spl_load_image(CONFIG_CMD_SPL_NAND_OFS,
 			CONFIG_CMD_SPL_WRITE_SIZE,
 			(void *)CONFIG_SYS_TEXT_BASE);
 		/* copy to destintion */
 		for (dst = (int *)CONFIG_SYS_SPL_ARGS_ADDR,
 				src = (int *)CONFIG_SYS_TEXT_BASE;
 				src < (int *)(CONFIG_SYS_TEXT_BASE +
 				CONFIG_CMD_SPL_WRITE_SIZE);
 				src++, dst++) {
 			writel(readl(src), dst);
 		}
 		/* load linux */
 		nand_spl_load_image(CONFIG_SYS_NAND_SPL_KERNEL_OFFS,
 			sizeof(*header), (void *)header);
 		err = spl_parse_image_header(spl_image, header);
 		if (err)
 			return err;
 		if (header->ih_os == IH_OS_LINUX) {
 			/* happy - was a linux */
 			err = nand_spl_load_image(
 				CONFIG_SYS_NAND_SPL_KERNEL_OFFS,
 				spl_image->size,
 				(void *)spl_image->load_addr);
 			nand_deselect();
 			return err;
 		} else {
 			puts("The Expected Linux image was not "
 				"found. Please check your NAND "
 				"configuration.\n");
 			puts("Trying to start u-boot now...\n");
 		}
 	}
 #endif
 #ifdef CONFIG_NAND_ENV_DST
 	spl_nand_load_element(spl_image, CONFIG_ENV_OFFSET, header);
 #ifdef CONFIG_ENV_OFFSET_REDUND
 	spl_nand_load_element(spl_image, CONFIG_ENV_OFFSET_REDUND, header);
 #endif
 #endif
 	/* Load u-boot */
-	err = spl_nand_load_element(spl_image, CONFIG_SYS_NAND_U_BOOT_OFFS,
+	err = spl_nand_load_element(spl_image, spl_nand_get_uboot_raw_page(),
 				    header);
 #ifdef CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND
 #if CONFIG_SYS_NAND_U_BOOT_OFFS != CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND
 	if (err)
 		err = spl_nand_load_element(spl_image,
 					    CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND,
 					    header);
 #endif
 #endif
 	nand_deselect();
 	return err;
 }
 #endif
 /* Use priorty 1 so that Ubi can override this */
 SPL_LOAD_IMAGE_METHOD("NAND", 1, BOOT_DEVICE_NAND, spl_nand_load_image);

include/configs/imx8qxp_arm2.h

Diff comments View file @ 4b2850c

 /*
  * Copyright 2017-2018 NXP
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef __IMX8QXP_ARM2_H
 #define __IMX8QXP_ARM2_H
 #include <linux/sizes.h>
 #include <asm/arch/imx-regs.h>
 #include "imx_env.h"
 #ifdef CONFIG_SPL_BUILD
+#define CONFIG_PARSE_CONTAINER
 #ifdef CONFIG_QSPI_BOOT
 #define CONFIG_SPL_SPI_LOAD
 #endif
 #define CONFIG_SPL_TEXT_BASE            0x0
 #define CONFIG_SPL_MAX_SIZE             (124 * 1024)
 #define CONFIG_SYS_MONITOR_LEN          (1024 * 1024)
 #ifdef CONFIG_NAND_BOOT
+#ifndef CONFIG_PARSE_CONTAINER
 #define CONFIG_SPL_NAND_RAW_ONLY
+#endif
 #define CONFIG_SPL_NAND_SUPPORT
 #define CONFIG_SPL_DMA_SUPPORT
 #define CONFIG_SPL_NAND_MXS
-#define CONFIG_SYS_NAND_U_BOOT_OFFS     (0x4000000)  /*Put the FIT out of first 64MB boot area */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS     (0x8000000)  /*Put the FIT out of first 128MB boot area */
 #define CONFIG_SPL_NAND_BOOT
 #define CONFIG_SYS_NAND_U_BOOT_DST		0x80000000
 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (1024 * 1024 )
 #define CONFIG_SYS_NAND_U_BOOT_START    0x80000000
 #endif
 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR         0x1040 /* (32K + 2Mb)/sector_size */
 #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION              0
 #define CONFIG_SPL_WATCHDOG_SUPPORT
 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
 #define CONFIG_SPL_LDSCRIPT             "arch/arm/cpu/armv8/u-boot-spl.lds"
 #define CONFIG_SPL_STACK                0x013E000
 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 #define CONFIG_SPL_SERIAL_SUPPORT
 #define CONFIG_SPL_BSS_START_ADDR      0x00138000
 #define CONFIG_SPL_BSS_MAX_SIZE        0x8000	/* 20 KB */
 #define CONFIG_SYS_SPL_MALLOC_START    0x00120000
 #define CONFIG_SYS_SPL_MALLOC_SIZE     0x18000   /* 60 KB */
 #define CONFIG_SERIAL_LPUART_BASE      0x5a060000
 #define CONFIG_SYS_ICACHE_OFF
 #define CONFIG_SYS_DCACHE_OFF
 #define CONFIG_MALLOC_F_ADDR            0x00120000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
 #define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
 #define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */
 #define CONFIG_OF_EMBED
 #define CONFIG_ATF_TEXT_BASE 0x80000000
 #define CONFIG_SYS_ATF_START 0x80000000
 /* #define CONFIG_FIT */
 /* Since the SPL runs before ATF, MU1 will not be started yet, so use MU0 */
 #define SC_IPC_CH                       SC_IPC_AP_CH0
 #endif
 #define CONFIG_REMAKE_ELF
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_ARCH_MISC_INIT
 /* Flat Device Tree Definitions */
 #define CONFIG_OF_BOARD_SETUP
 #undef CONFIG_CMD_EXPORTENV
 #undef CONFIG_CMD_IMPORTENV
 #undef CONFIG_CMD_IMLS
 #undef CONFIG_CMD_CRC32
 #undef CONFIG_BOOTM_NETBSD
 #define CONFIG_FSL_ESDHC
 #define CONFIG_FSL_USDHC
 #define CONFIG_SYS_FSL_ESDHC_ADDR       0
 #define USDHC1_BASE_ADDR                0x5B010000
 #define USDHC2_BASE_ADDR                0x5B020000
 #define CONFIG_SUPPORT_EMMC_BOOT	/* eMMC specific */
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_FSL_HSIO
 #ifdef CONFIG_FSL_HSIO
 #define CONFIG_PCIE_IMX8X
 #define CONFIG_CMD_PCI
 #define CONFIG_PCI
 #define CONFIG_PCI_PNP
 #define CONFIG_PCI_SCAN_SHOW
 #endif
 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 /* FUSE command */
 #define CONFIG_CMD_FUSE
 /* GPIO configs */
 #define CONFIG_MXC_GPIO
 /* ENET Config */
 #define CONFIG_MII
 #define CONFIG_FEC_MXC
 #define CONFIG_FEC_XCV_TYPE             RGMII
 #define FEC_QUIRK_ENET_MAC
 #define CONFIG_PHY_GIGE /* Support for 1000BASE-X */
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_ATHEROS
 /* ENET0 connects AR8031 on CPU board, ENET1 connects to base board and MUX with ESAI, default is ESAI */
 #define CONFIG_FEC_ENET_DEV 0
 #if (CONFIG_FEC_ENET_DEV == 0)
 #define IMX_FEC_BASE			0x5B040000
 #define CONFIG_FEC_MXC_PHYADDR          0x0
 #define CONFIG_ETHPRIME                 "eth0"
 #elif (CONFIG_FEC_ENET_DEV == 1)
 #define IMX_FEC_BASE			0x5B050000
 #define CONFIG_FEC_MXC_PHYADDR          0x1
 #define CONFIG_FEC_ENABLE_MAX7322
 #define CONFIG_ETHPRIME                 "eth1"
 #endif
 /* ENET0 MDIO are shared */
 #define CONFIG_FEC_MXC_MDIO_BASE	0x5B040000
 #define CONFIG_LIB_RAND
 #define CONFIG_NET_RANDOM_ETHADDR
 /* MAX7322 */
 #ifdef CONFIG_FEC_ENABLE_MAX7322
 #define CONFIG_MAX7322_I2C_ADDR		0x68
 #define CONFIG_MAX7322_I2C_BUS		0 /* I2C1 */
 #endif
 #ifdef CONFIG_AHAB_BOOT
 #define AHAB_ENV "sec_boot=yes\0"
 #else
 #define AHAB_ENV "sec_boot=no\0"
 #endif
 /* Boot M4 */
 #define M4_BOOT_ENV \
 	"m4_0_image=m4_0.bin\0" \
 	"loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \
 	"m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
 #ifdef CONFIG_NAND_BOOT
-#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(nandboot),32m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs) "
+#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(nandboot),16m(nandfit),32m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs) "
-#else
-#define MFG_NAND_PARTITION ""
 #endif
 #define CONFIG_MFG_ENV_SETTINGS \
 	CONFIG_MFG_ENV_SETTINGS_DEFAULT \
 	"clk_ignore_unused "\
 	"\0" \
 	"initrd_addr=0x83100000\0" \
 	"initrd_high=0xffffffffffffffff\0" \
 	"emmc_dev=0\0" \
 	"sd_dev=1\0" \
-	"mtdparts=mtdparts=gpmi-nand:128m(nandboot),32m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs)\0"
 /* Initial environment variables */
 #ifdef CONFIG_NAND_BOOT
 #define CONFIG_EXTRA_ENV_SETTINGS		\
 	CONFIG_MFG_ENV_SETTINGS \
 	"bootargs=console=ttyLP0,115200 ubi.mtd=5 "  \
 		"root=ubi0:nandrootfs rootfstype=ubifs "		     \
 		MFG_NAND_PARTITION \
 		"\0"\
 	"console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200\0" \
+	"mtdparts=" MFG_NAND_PARTITION "\0" \
 	"fdt_addr=0x83000000\0"
 #else
 #define CONFIG_EXTRA_ENV_SETTINGS		\
 	CONFIG_MFG_ENV_SETTINGS \
 	M4_BOOT_ENV \
 	AHAB_ENV \
 	"script=boot.scr\0" \
 	"image=Image\0" \
 	"panel=NULL\0" \
 	"console=ttyLP0\0" \
 	"earlycon=lpuart32,0x5a060000\0" \
 	"fdt_addr=0x83000000\0"			\
 	"fdt_high=0xffffffffffffffff\0"		\
 	"cntr_addr=0x88000000\0"			\
 	"cntr_file=os_cntr_signed.bin\0" \
 	"boot_fdt=try\0" \
 	"fdt_file=fsl-imx8qxp-lpddr4-arm2.dtb\0" \
 	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
 	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
 	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
 	"mmcautodetect=yes\0" \
 	"mmcargs=setenv bootargs console=${console},${baudrate} earlycon=${earlycon},${baudrate} root=${mmcroot}\0 " \
 	"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
 	"bootscript=echo Running bootscript from mmc ...; " \
 		"source\0" \
 	"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
 	"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
 	"loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}\0" \
 	"auth_os=auth_cntr ${cntr_addr}\0" \
 	"mmcboot=echo Booting from mmc ...; " \
 		"run mmcargs; " \
 		"if test ${sec_boot} = yes; then " \
 			"if run auth_os; then " \
 				"booti ${loadaddr} - ${fdt_addr}; " \
 			"else " \
 				"echo ERR: failed to authenticate; " \
 			"fi; " \
 		"else " \
 			"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
 				"if run loadfdt; then " \
 					"booti ${loadaddr} - ${fdt_addr}; " \
 				"else " \
 					"echo WARN: Cannot load the DT; " \
 				"fi; " \
 			"else " \
 				"echo wait for boot; " \
 			"fi;" \
 		"fi;\0" \
 	"netargs=setenv bootargs console=${console},${baudrate} earlycon=${earlycon},${baudrate} " \
 		"root=/dev/nfs " \
 		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
 	"netboot=echo Booting from net ...; " \
 		"run netargs;  " \
 		"if test ${ip_dyn} = yes; then " \
 			"setenv get_cmd dhcp; " \
 		"else " \
 			"setenv get_cmd tftp; " \
 		"fi; " \
 		"if test ${sec_boot} = yes; then " \
 			"${get_cmd} ${cntr_addr} ${cntr_file}; " \
 			"if run auth_os; then " \
 				"booti ${loadaddr} - ${fdt_addr}; " \
 			"else " \
 				"echo ERR: failed to authenticate; " \
 			"fi; " \
 		"else " \
 			"${get_cmd} ${loadaddr} ${image}; " \
 			"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
 				"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
 					"booti ${loadaddr} - ${fdt_addr}; " \
 				"else " \
 					"echo WARN: Cannot load the DT; " \
 				"fi; " \
 			"else " \
 				"booti; " \
 			"fi;" \
 		"fi;\0"
 #endif
 #ifdef CONFIG_NAND_BOOT
 #define CONFIG_BOOTCOMMAND \
-	"nand read ${loadaddr} 0x8000000 0x2000000;"\
+	"nand read ${loadaddr} 0x9000000 0x2000000;"\
-	"nand read ${fdt_addr} 0xA000000 0x100000;"\
+	"nand read ${fdt_addr} 0xB000000 0x100000;"\
 	"booti ${loadaddr} - ${fdt_addr}"
 #else
 #define CONFIG_BOOTCOMMAND \
 	   "mmc dev ${mmcdev}; if mmc rescan; then " \
 		   "if run loadbootscript; then " \
 			   "run bootscript; " \
 		   "else " \
 			   "if test ${sec_boot} = yes; then " \
 				   "if run loadcntr; then " \
 					   "run mmcboot; " \
 				   "else run netboot; " \
 				   "fi; " \
 			    "else " \
 				   "if run loadimage; then " \
 					   "run mmcboot; " \
 				   "else run netboot; " \
 				   "fi; " \
 			 "fi; " \
 		   "fi; " \
 	   "else booti ${loadaddr} - ${fdt_addr}; fi"
 #endif
 /* Link Definitions */
 #define CONFIG_LOADADDR			0x80280000
 #define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
 #define CONFIG_SYS_INIT_SP_ADDR         0x80200000
 /* Default environment is in SD */
 #define CONFIG_ENV_SIZE			0x2000
 #ifdef CONFIG_NAND_BOOT
 #define CONFIG_ENV_OFFSET       (120 << 20)
 #elif defined(CONFIG_QSPI_BOOT)
 #define CONFIG_ENV_OFFSET       (4 * 1024 * 1024)
 #define CONFIG_ENV_SECT_SIZE	(128 * 1024)
 #define CONFIG_ENV_SPI_BUS	CONFIG_SF_DEFAULT_BUS
 #define CONFIG_ENV_SPI_CS	CONFIG_SF_DEFAULT_CS
 #define CONFIG_ENV_SPI_MODE	CONFIG_SF_DEFAULT_MODE
 #define CONFIG_ENV_SPI_MAX_HZ	CONFIG_SF_DEFAULT_SPEED
 #else
 #define CONFIG_ENV_OFFSET       (64 * SZ_64K)
 #define CONFIG_SYS_MMC_ENV_PART		0	/* user area */
 #endif
 #define CONFIG_SYS_MMC_IMG_LOAD_PART	1
 /* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board
   */
 #ifdef CONFIG_TARGET_IMX8DX_DDR3_ARM2
 #define CONFIG_SYS_MMC_ENV_DEV		0   /* USDHC1 */
 #define CONFIG_MMCROOT			"/dev/mmcblk0p2"  /* USDHC1 */
 #define CONFIG_SYS_FSL_USDHC_NUM	1
 #else
 #define CONFIG_SYS_MMC_ENV_DEV		1   /* USDHC2 */
 #define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2 */
 #define CONFIG_SYS_FSL_USDHC_NUM	2
 #endif
 /* Size of malloc() pool */
 #define CONFIG_SYS_MALLOC_LEN		((CONFIG_ENV_SIZE + (32*1024)) * 1024)
 #define CONFIG_SYS_SDRAM_BASE		0x80000000
 #define CONFIG_NR_DRAM_BANKS		4
 #define PHYS_SDRAM_1			0x80000000
 #define PHYS_SDRAM_2			0x880000000
 #if defined(CONFIG_TARGET_IMX8QXP_DDR3_ARM2) || defined(CONFIG_TARGET_IMX8DX_DDR3_ARM2)
 #define PHYS_SDRAM_1_SIZE		0x40000000	/* 1 GB */
 /* LPDDR4 board total DDR is 3GB */
 #define PHYS_SDRAM_2_SIZE		0x00000000
 #else
 #define PHYS_SDRAM_1_SIZE		0x80000000	/* 2 GB */
 /* LPDDR4 board total DDR is 3GB */
 #define PHYS_SDRAM_2_SIZE		0x40000000	/* 1 GB */
 #endif
 #define CONFIG_SYS_MEMTEST_START    0xA0000000
 #define CONFIG_SYS_MEMTEST_END      (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_1_SIZE >> 2))
 /* Serial */
 #define CONFIG_BAUDRATE			115200
 /* Monitor Command Prompt */
 #define CONFIG_HUSH_PARSER
 #define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
 #define CONFIG_SYS_CBSIZE              1024
 #define CONFIG_SYS_MAXARGS             64
 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
 #define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
 					sizeof(CONFIG_SYS_PROMPT) + 16)
 /* Generic Timer Definitions */
 #define COUNTER_FREQUENCY		8000000	/* 8MHz */
 #ifndef CONFIG_DM_PCA953X
 #define CONFIG_PCA953X
 #define CONFIG_CMD_PCA953X
 #define CONFIG_CMD_PCA953X_INFO
 #endif
 #define CONFIG_IMX_SMMU
 /* MT35XU512ABA1G12 has only one Die, so QSPI0 B won't work */
 #ifdef CONFIG_FSL_FSPI
 #define CONFIG_SF_DEFAULT_BUS		0
 #define CONFIG_SF_DEFAULT_CS		0
 #define CONFIG_SF_DEFAULT_SPEED	40000000
 #define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
 #define FSL_FSPI_FLASH_SIZE		SZ_64M
 #define FSL_FSPI_FLASH_NUM		1
 #define FSPI0_BASE_ADDR			0x5d120000
 #define FSPI0_AMBA_BASE			0
 #define CONFIG_SYS_FSL_FSPI_AHB
 #endif
 #ifdef CONFIG_CMD_NAND
 #define CONFIG_NAND_MXS
 #define CONFIG_CMD_NAND_TRIMFFS
 /* NAND stuff */
 #define CONFIG_SYS_MAX_NAND_DEVICE     1
 #define CONFIG_SYS_NAND_BASE           0x40000000
 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
 #define CONFIG_SYS_NAND_ONFI_DETECTION
 /* DMA stuff, needed for GPMI/MXS NAND support */
 #define CONFIG_APBH_DMA
 #define CONFIG_APBH_DMA_BURST
 #define CONFIG_APBH_DMA_BURST8
 #endif
 /* USB Config */
 #ifdef CONFIG_CMD_USB
 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
 /* USB OTG controller configs */
 #ifdef CONFIG_USB_EHCI_HCD
 #define CONFIG_USB_HOST_ETHER
 #define CONFIG_USB_ETHER_ASIX
 #define CONFIG_MXC_USB_PORTSC		(PORT_PTS_UTMI | PORT_PTS_PTW)
 #endif
 #endif /* CONFIG_CMD_USB */
 #ifdef CONFIG_USB_GADGET
 #define CONFIG_USBD_HS
 #endif
 #if defined(CONFIG_ANDROID_SUPPORT)
 #include "imx8qxp_arm2_android.h"
 #endif
 /* Framebuffer */
 #ifdef CONFIG_VIDEO
 #define CONFIG_VIDEO_IMXDPUV1
 #define CONFIG_VIDEO_BMP_RLE8
 #define CONFIG_SPLASH_SCREEN
 #define CONFIG_SPLASH_SCREEN_ALIGN
 #define CONFIG_BMP_16BPP
 #define CONFIG_VIDEO_LOGO
 #define CONFIG_VIDEO_BMP_LOGO
 #define CONFIG_IMX_VIDEO_SKIP
 #endif
 #define CONFIG_OF_SYSTEM_SETUP
 #define BOOTAUX_RESERVED_MEM_BASE 0x88000000
 #define BOOTAUX_RESERVED_MEM_SIZE 0x08000000 /* Reserve from second 128MB */
 #define CONFIG_CMD_READ
 #define CONFIG_SERIAL_TAG

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Eric Lee 2020-04-16 06:19:45 UTC

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Eric Lee 2020-07-07 11:00:49 UTC

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