Eric Lee / smarc-uboot

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Commit 4bac48b2c7178eb56ea2e53d7a57086802a1560b

Authored by Eric Lee
1 parent ba71de91c1
Exists in v2014.04-smarct33-emmc

Add SMARCT80 Board support

Showing 5 changed files with 127 additions and 26 deletions Inline Diff

arch/arm/include/asm/arch-am33xx/ddr_defs.h
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1 /* 1 /*
2 * ddr_defs.h 2 * ddr_defs.h
3 * 3 *
4 * ddr specific header 4 * ddr specific header
5 * 5 *
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
7 * 7 *
8 * SPDX-License-Identifier: GPL-2.0+ 8 * SPDX-License-Identifier: GPL-2.0+
9 */ 9 */
10 10
11 #ifndef _DDR_DEFS_H 11 #ifndef _DDR_DEFS_H
12 #define _DDR_DEFS_H 12 #define _DDR_DEFS_H
13 13
14 #include <asm/arch/hardware.h> 14 #include <asm/arch/hardware.h>
15 #include <asm/emif.h> 15 #include <asm/emif.h>
16 16
17 /* AM335X EMIF Register values */ 17 /* AM335X EMIF Register values */
18 #define VTP_CTRL_READY (0x1 << 5) 18 #define VTP_CTRL_READY (0x1 << 5)
19 #define VTP_CTRL_ENABLE (0x1 << 6) 19 #define VTP_CTRL_ENABLE (0x1 << 6)
20 #define VTP_CTRL_START_EN (0x1) 20 #define VTP_CTRL_START_EN (0x1)
21 #ifdef CONFIG_AM43XX 21 #ifdef CONFIG_AM43XX
22 #define DDR_CKE_CTRL_NORMAL 0x3 22 #define DDR_CKE_CTRL_NORMAL 0x3
23 #else 23 #else
24 #define DDR_CKE_CTRL_NORMAL 0x1 24 #define DDR_CKE_CTRL_NORMAL 0x1
25 #endif 25 #endif
26 #define PHY_EN_DYN_PWRDN (0x1 << 20) 26 #define PHY_EN_DYN_PWRDN (0x1 << 20)
27 27
28 /* Micron MT47H128M16RT-25E */ 28 /* Micron MT47H128M16RT-25E */
29 #define MT47H128M16RT25E_EMIF_READ_LATENCY 0x100005 29 #define MT47H128M16RT25E_EMIF_READ_LATENCY 0x100005
30 #define MT47H128M16RT25E_EMIF_TIM1 0x0666B3C9 30 #define MT47H128M16RT25E_EMIF_TIM1 0x0666B3C9
31 #define MT47H128M16RT25E_EMIF_TIM2 0x243631CA 31 #define MT47H128M16RT25E_EMIF_TIM2 0x243631CA
32 #define MT47H128M16RT25E_EMIF_TIM3 0x0000033F 32 #define MT47H128M16RT25E_EMIF_TIM3 0x0000033F
33 #define MT47H128M16RT25E_EMIF_SDCFG 0x41805332 33 #define MT47H128M16RT25E_EMIF_SDCFG 0x41805332
34 #define MT47H128M16RT25E_EMIF_SDREF 0x0000081a 34 #define MT47H128M16RT25E_EMIF_SDREF 0x0000081a
35 #define MT47H128M16RT25E_RATIO 0x80 35 #define MT47H128M16RT25E_RATIO 0x80
36 #define MT47H128M16RT25E_INVERT_CLKOUT 0x00 36 #define MT47H128M16RT25E_INVERT_CLKOUT 0x00
37 #define MT47H128M16RT25E_RD_DQS 0x12 37 #define MT47H128M16RT25E_RD_DQS 0x12
38 #define MT47H128M16RT25E_WR_DQS 0x00 38 #define MT47H128M16RT25E_WR_DQS 0x00
39 #define MT47H128M16RT25E_PHY_WRLVL 0x00 39 #define MT47H128M16RT25E_PHY_WRLVL 0x00
40 #define MT47H128M16RT25E_PHY_GATELVL 0x00 40 #define MT47H128M16RT25E_PHY_GATELVL 0x00
41 #define MT47H128M16RT25E_PHY_WR_DATA 0x40 41 #define MT47H128M16RT25E_PHY_WR_DATA 0x40
42 #define MT47H128M16RT25E_PHY_FIFO_WE 0x80 42 #define MT47H128M16RT25E_PHY_FIFO_WE 0x80
43 #define MT47H128M16RT25E_IOCTRL_VALUE 0x18B 43 #define MT47H128M16RT25E_IOCTRL_VALUE 0x18B
44 44
45 /* Micron MT41J128M16JT-125 */ 45 /* Micron MT41J128M16JT-125 */
46 #define MT41J128MJT125_EMIF_READ_LATENCY 0x100006 46 #define MT41J128MJT125_EMIF_READ_LATENCY 0x100006
47 #define MT41J128MJT125_EMIF_TIM1 0x0888A39B 47 #define MT41J128MJT125_EMIF_TIM1 0x0888A39B
48 #define MT41J128MJT125_EMIF_TIM2 0x26337FDA 48 #define MT41J128MJT125_EMIF_TIM2 0x26337FDA
49 #define MT41J128MJT125_EMIF_TIM3 0x501F830F 49 #define MT41J128MJT125_EMIF_TIM3 0x501F830F
50 #define MT41J128MJT125_EMIF_SDCFG 0x61C04AB2 50 #define MT41J128MJT125_EMIF_SDCFG 0x61C04AB2
51 #define MT41J128MJT125_EMIF_SDREF 0x0000093B 51 #define MT41J128MJT125_EMIF_SDREF 0x0000093B
52 #define MT41J128MJT125_ZQ_CFG 0x50074BE4 52 #define MT41J128MJT125_ZQ_CFG 0x50074BE4
53 #define MT41J128MJT125_RATIO 0x40 53 #define MT41J128MJT125_RATIO 0x40
54 #define MT41J128MJT125_INVERT_CLKOUT 0x1 54 #define MT41J128MJT125_INVERT_CLKOUT 0x1
55 #define MT41J128MJT125_RD_DQS 0x3B 55 #define MT41J128MJT125_RD_DQS 0x3B
56 #define MT41J128MJT125_WR_DQS 0x85 56 #define MT41J128MJT125_WR_DQS 0x85
57 #define MT41J128MJT125_PHY_WR_DATA 0xC1 57 #define MT41J128MJT125_PHY_WR_DATA 0xC1
58 #define MT41J128MJT125_PHY_FIFO_WE 0x100 58 #define MT41J128MJT125_PHY_FIFO_WE 0x100
59 #define MT41J128MJT125_IOCTRL_VALUE 0x18B 59 #define MT41J128MJT125_IOCTRL_VALUE 0x18B
60 60
61 /* Micron MT41K128M16JT-187E */ 61 /* Micron MT41K128M16JT-187E */
62 #define MT41K128MJT187E_EMIF_READ_LATENCY 0x06 62 #define MT41K128MJT187E_EMIF_READ_LATENCY 0x06
63 #define MT41K128MJT187E_EMIF_TIM1 0x0888B3DB 63 #define MT41K128MJT187E_EMIF_TIM1 0x0888B3DB
64 #define MT41K128MJT187E_EMIF_TIM2 0x36337FDA 64 #define MT41K128MJT187E_EMIF_TIM2 0x36337FDA
65 #define MT41K128MJT187E_EMIF_TIM3 0x501F830F 65 #define MT41K128MJT187E_EMIF_TIM3 0x501F830F
66 #define MT41K128MJT187E_EMIF_SDCFG 0x61C04AB2 66 #define MT41K128MJT187E_EMIF_SDCFG 0x61C04AB2
67 #define MT41K128MJT187E_EMIF_SDREF 0x0000093B 67 #define MT41K128MJT187E_EMIF_SDREF 0x0000093B
68 #define MT41K128MJT187E_ZQ_CFG 0x50074BE4 68 #define MT41K128MJT187E_ZQ_CFG 0x50074BE4
69 #define MT41K128MJT187E_RATIO 0x40 69 #define MT41K128MJT187E_RATIO 0x40
70 #define MT41K128MJT187E_INVERT_CLKOUT 0x1 70 #define MT41K128MJT187E_INVERT_CLKOUT 0x1
71 #define MT41K128MJT187E_RD_DQS 0x3B 71 #define MT41K128MJT187E_RD_DQS 0x3B
72 #define MT41K128MJT187E_WR_DQS 0x85 72 #define MT41K128MJT187E_WR_DQS 0x85
73 #define MT41K128MJT187E_PHY_WR_DATA 0xC1 73 #define MT41K128MJT187E_PHY_WR_DATA 0xC1
74 #define MT41K128MJT187E_PHY_FIFO_WE 0x100 74 #define MT41K128MJT187E_PHY_FIFO_WE 0x100
75 #define MT41K128MJT187E_IOCTRL_VALUE 0x18B 75 #define MT41K128MJT187E_IOCTRL_VALUE 0x18B
76 76
77 /* Micron MT41J64M16JT-125 */ 77 /* Micron MT41J64M16JT-125 */
78 #define MT41J64MJT125_EMIF_SDCFG 0x61C04A32 78 #define MT41J64MJT125_EMIF_SDCFG 0x61C04A32
79 79
80 /* Micron MT41J256M16JT-125 */ 80 /* Micron MT41J256M16JT-125 */
81 #define MT41J256MJT125_EMIF_SDCFG 0x61C04B32 81 #define MT41J256MJT125_EMIF_SDCFG 0x61C04B32
82 82
83 /* Micron MT41J256M8HX-15E */ 83 /* Micron MT41J256M8HX-15E */
84 #define MT41J256M8HX15E_EMIF_READ_LATENCY 0x100006 84 #define MT41J256M8HX15E_EMIF_READ_LATENCY 0x100006
85 #define MT41J256M8HX15E_EMIF_TIM1 0x0888A39B 85 #define MT41J256M8HX15E_EMIF_TIM1 0x0888A39B
86 #define MT41J256M8HX15E_EMIF_TIM2 0x26337FDA 86 #define MT41J256M8HX15E_EMIF_TIM2 0x26337FDA
87 #define MT41J256M8HX15E_EMIF_TIM3 0x501F830F 87 #define MT41J256M8HX15E_EMIF_TIM3 0x501F830F
88 #define MT41J256M8HX15E_EMIF_SDCFG 0x61C04B32 88 #define MT41J256M8HX15E_EMIF_SDCFG 0x61C04B32
89 #define MT41J256M8HX15E_EMIF_SDREF 0x0000093B 89 #define MT41J256M8HX15E_EMIF_SDREF 0x0000093B
90 #define MT41J256M8HX15E_ZQ_CFG 0x50074BE4 90 #define MT41J256M8HX15E_ZQ_CFG 0x50074BE4
91 #define MT41J256M8HX15E_RATIO 0x40 91 #define MT41J256M8HX15E_RATIO 0x40
92 #define MT41J256M8HX15E_INVERT_CLKOUT 0x1 92 #define MT41J256M8HX15E_INVERT_CLKOUT 0x1
93 #define MT41J256M8HX15E_RD_DQS 0x3B 93 #define MT41J256M8HX15E_RD_DQS 0x3B
94 #define MT41J256M8HX15E_WR_DQS 0x85 94 #define MT41J256M8HX15E_WR_DQS 0x85
95 #define MT41J256M8HX15E_PHY_WR_DATA 0xC1 95 #define MT41J256M8HX15E_PHY_WR_DATA 0xC1
96 #define MT41J256M8HX15E_PHY_FIFO_WE 0x100 96 #define MT41J256M8HX15E_PHY_FIFO_WE 0x100
97 #define MT41J256M8HX15E_IOCTRL_VALUE 0x18B 97 #define MT41J256M8HX15E_IOCTRL_VALUE 0x18B
98 98
99 /* Micron MT41K256M16HA-125E */ 99 /* Micron MT41K256M16HA-125E */
100 #define MT41K256M16HA125E_EMIF_READ_LATENCY 0x100007 100 #define MT41K256M16HA125E_EMIF_READ_LATENCY 0x100007
101 #define MT41K256M16HA125E_EMIF_TIM1 0x0AAAD4DB 101 #define MT41K256M16HA125E_EMIF_TIM1 0x0AAAD4DB
102 #define MT41K256M16HA125E_EMIF_TIM2 0x266B7FDA 102 #define MT41K256M16HA125E_EMIF_TIM2 0x266B7FDA
103 #define MT41K256M16HA125E_EMIF_TIM3 0x501F867F 103 #define MT41K256M16HA125E_EMIF_TIM3 0x501F867F
104 #define MT41K256M16HA125E_EMIF_SDCFG 0x61C05332 104 #define MT41K256M16HA125E_EMIF_SDCFG 0x61C05332
105 #define MT41K256M16HA125E_EMIF_SDREF 0xC30 105 #define MT41K256M16HA125E_EMIF_SDREF 0xC30
106 #define MT41K256M16HA125E_ZQ_CFG 0x50074BE4 106 #define MT41K256M16HA125E_ZQ_CFG 0x50074BE4
107 #define MT41K256M16HA125E_RATIO 0x80 107 #define MT41K256M16HA125E_RATIO 0x80
108 #define MT41K256M16HA125E_INVERT_CLKOUT 0x0 108 #define MT41K256M16HA125E_INVERT_CLKOUT 0x0
109 #define MT41K256M16HA125E_RD_DQS 0x38 109 #define MT41K256M16HA125E_RD_DQS 0x38
110 #define MT41K256M16HA125E_WR_DQS 0x44 110 #define MT41K256M16HA125E_WR_DQS 0x44
111 #define MT41K256M16HA125E_PHY_WR_DATA 0x7D 111 #define MT41K256M16HA125E_PHY_WR_DATA 0x7D
112 #define MT41K256M16HA125E_PHY_FIFO_WE 0x94 112 #define MT41K256M16HA125E_PHY_FIFO_WE 0x94
113 #define MT41K256M16HA125E_IOCTRL_VALUE 0x18B 113 #define MT41K256M16HA125E_IOCTRL_VALUE 0x18B
114 114
115 /* Samsung K4B4G1646E-BYK0 */
116 #define K4B4G1646EBYK0_EMIF_READ_LATENCY 0x100007
117 #define K4B4G1646EBYK0_EMIF_TIM1 0x0AAAE51B
118 #define K4B4G1646EBYK0_EMIF_TIM2 0x267B7FDA
119 #define K4B4G1646EBYK0_EMIF_TIM3 0x501F877F
120 #define K4B4G1646EBYK0_EMIF_SDCFG 0x61C05332
121 #define K4B4G1646EBYK0_EMIF_SDREF 0xC30
122 #define K4B4G1646EBYK0_ZQ_CFG 0x50074BE4
123 #define K4B4G1646EBYK0_RATIO 0x80
124 #define K4B4G1646EBYK0_INVERT_CLKOUT 0x0
125 #define K4B4G1646EBYK0_RD_DQS 0x3B
126 #define K4B4G1646EBYK0_WR_DQS 0x4A
127 #define K4B4G1646EBYK0_PHY_WR_DATA 0x83
128 #define K4B4G1646EBYK0_PHY_FIFO_WE 0xA4
129 #define K4B4G1646EBYK0_IOCTRL_VALUE 0x18B
130
131 /* Micron MT41K256M16HA-125ITE */
132 #define MT41K256M16HA125ITE_EMIF_READ_LATENCY 0x100007
133 #define MT41K256M16HA125ITE_EMIF_TIM1 0x0AAAE51B
134 #define MT41K256M16HA125ITE_EMIF_TIM2 0x267B7FDA
135 #define MT41K256M16HA125ITE_EMIF_TIM3 0x501F877F
136 #define MT41K256M16HA125ITE_EMIF_SDCFG 0x61C05332
137 #define MT41K256M16HA125ITE_EMIF_SDREF 0xC30
138 #define MT41K256M16HA125ITE_ZQ_CFG 0x50074BE4
139 #define MT41K256M16HA125ITE_RATIO 0x80
140 #define MT41K256M16HA125ITE_INVERT_CLKOUT 0x0
141 #define MT41K256M16HA125ITE_RD_DQS 0x3D
142 #define MT41K256M16HA125ITE_WR_DQS 0x4B
143 #define MT41K256M16HA125ITE_PHY_WR_DATA 0x7F
144 #define MT41K256M16HA125ITE_PHY_FIFO_WE 0x9D
145 #define MT41K256M16HA125ITE_IOCTRL_VALUE 0x18B
146
115 /* Micron MT41J512M8RH-125 on EVM v1.5 */ 147 /* Micron MT41J512M8RH-125 on EVM v1.5 */
116 #define MT41J512M8RH125_EMIF_READ_LATENCY 0x100006 148 #define MT41J512M8RH125_EMIF_READ_LATENCY 0x100006
117 #define MT41J512M8RH125_EMIF_TIM1 0x0888A39B 149 #define MT41J512M8RH125_EMIF_TIM1 0x0888A39B
118 #define MT41J512M8RH125_EMIF_TIM2 0x26517FDA 150 #define MT41J512M8RH125_EMIF_TIM2 0x26517FDA
119 #define MT41J512M8RH125_EMIF_TIM3 0x501F84EF 151 #define MT41J512M8RH125_EMIF_TIM3 0x501F84EF
120 #define MT41J512M8RH125_EMIF_SDCFG 0x61C04BB2 152 #define MT41J512M8RH125_EMIF_SDCFG 0x61C04BB2
121 #define MT41J512M8RH125_EMIF_SDREF 0x0000093B 153 #define MT41J512M8RH125_EMIF_SDREF 0x0000093B
122 #define MT41J512M8RH125_ZQ_CFG 0x50074BE4 154 #define MT41J512M8RH125_ZQ_CFG 0x50074BE4
123 #define MT41J512M8RH125_RATIO 0x80 155 #define MT41J512M8RH125_RATIO 0x80
124 #define MT41J512M8RH125_INVERT_CLKOUT 0x0 156 #define MT41J512M8RH125_INVERT_CLKOUT 0x0
125 #define MT41J512M8RH125_RD_DQS 0x3B 157 #define MT41J512M8RH125_RD_DQS 0x3B
126 #define MT41J512M8RH125_WR_DQS 0x3C 158 #define MT41J512M8RH125_WR_DQS 0x3C
127 #define MT41J512M8RH125_PHY_FIFO_WE 0xA5 159 #define MT41J512M8RH125_PHY_FIFO_WE 0xA5
128 #define MT41J512M8RH125_PHY_WR_DATA 0x74 160 #define MT41J512M8RH125_PHY_WR_DATA 0x74
129 #define MT41J512M8RH125_IOCTRL_VALUE 0x18B 161 #define MT41J512M8RH125_IOCTRL_VALUE 0x18B
130 162
131 /* Samsung K4B2G1646E-BIH9 */ 163 /* Samsung K4B2G1646E-BIH9 */
132 #define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x100007 164 #define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x100007
133 #define K4B2G1646EBIH9_EMIF_TIM1 0x0AAAE51B 165 #define K4B2G1646EBIH9_EMIF_TIM1 0x0AAAE51B
134 #define K4B2G1646EBIH9_EMIF_TIM2 0x2A1D7FDA 166 #define K4B2G1646EBIH9_EMIF_TIM2 0x2A1D7FDA
135 #define K4B2G1646EBIH9_EMIF_TIM3 0x501F83FF 167 #define K4B2G1646EBIH9_EMIF_TIM3 0x501F83FF
136 #define K4B2G1646EBIH9_EMIF_SDCFG 0x61C052B2 168 #define K4B2G1646EBIH9_EMIF_SDCFG 0x61C052B2
137 #define K4B2G1646EBIH9_EMIF_SDREF 0x00000C30 169 #define K4B2G1646EBIH9_EMIF_SDREF 0x00000C30
138 #define K4B2G1646EBIH9_ZQ_CFG 0x50074BE4 170 #define K4B2G1646EBIH9_ZQ_CFG 0x50074BE4
139 #define K4B2G1646EBIH9_RATIO 0x80 171 #define K4B2G1646EBIH9_RATIO 0x80
140 #define K4B2G1646EBIH9_INVERT_CLKOUT 0x0 172 #define K4B2G1646EBIH9_INVERT_CLKOUT 0x0
141 #define K4B2G1646EBIH9_RD_DQS 0x35 173 #define K4B2G1646EBIH9_RD_DQS 0x35
142 #define K4B2G1646EBIH9_WR_DQS 0x3A 174 #define K4B2G1646EBIH9_WR_DQS 0x3A
143 #define K4B2G1646EBIH9_PHY_FIFO_WE 0x97 175 #define K4B2G1646EBIH9_PHY_FIFO_WE 0x97
144 #define K4B2G1646EBIH9_PHY_WR_DATA 0x76 176 #define K4B2G1646EBIH9_PHY_WR_DATA 0x76
145 #define K4B2G1646EBIH9_IOCTRL_VALUE 0x18B 177 #define K4B2G1646EBIH9_IOCTRL_VALUE 0x18B
146 178
147 #define LPDDR2_ADDRCTRL_IOCTRL_VALUE 0x294 179 #define LPDDR2_ADDRCTRL_IOCTRL_VALUE 0x294
148 #define LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000 180 #define LPDDR2_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000
149 #define LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000 181 #define LPDDR2_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000
150 #define LPDDR2_DATA0_IOCTRL_VALUE 0x20000294 182 #define LPDDR2_DATA0_IOCTRL_VALUE 0x20000294
151 #define LPDDR2_DATA1_IOCTRL_VALUE 0x20000294 183 #define LPDDR2_DATA1_IOCTRL_VALUE 0x20000294
152 #define LPDDR2_DATA2_IOCTRL_VALUE 0x20000294 184 #define LPDDR2_DATA2_IOCTRL_VALUE 0x20000294
153 #define LPDDR2_DATA3_IOCTRL_VALUE 0x20000294 185 #define LPDDR2_DATA3_IOCTRL_VALUE 0x20000294
154 186
155 #define DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000 187 #define DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000
156 #define DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000 188 #define DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000
157 #define DDR3_ADDRCTRL_IOCTRL_VALUE 0x84 189 #define DDR3_ADDRCTRL_IOCTRL_VALUE 0x84
158 #define DDR3_DATA0_IOCTRL_VALUE 0x84 190 #define DDR3_DATA0_IOCTRL_VALUE 0x84
159 #define DDR3_DATA1_IOCTRL_VALUE 0x84 191 #define DDR3_DATA1_IOCTRL_VALUE 0x84
160 #define DDR3_DATA2_IOCTRL_VALUE 0x84 192 #define DDR3_DATA2_IOCTRL_VALUE 0x84
161 #define DDR3_DATA3_IOCTRL_VALUE 0x84 193 #define DDR3_DATA3_IOCTRL_VALUE 0x84
162 194
163 /** 195 /**
164 * Configure DMM 196 * Configure DMM
165 */ 197 */
166 void config_dmm(const struct dmm_lisa_map_regs *regs); 198 void config_dmm(const struct dmm_lisa_map_regs *regs);
167 199
168 /** 200 /**
169 * Configure SDRAM 201 * Configure SDRAM
170 */ 202 */
171 void config_sdram(const struct emif_regs *regs, int nr); 203 void config_sdram(const struct emif_regs *regs, int nr);
172 void config_sdram_emif4d5(const struct emif_regs *regs, int nr); 204 void config_sdram_emif4d5(const struct emif_regs *regs, int nr);
173 205
174 /** 206 /**
175 * Set SDRAM timings 207 * Set SDRAM timings
176 */ 208 */
177 void set_sdram_timings(const struct emif_regs *regs, int nr); 209 void set_sdram_timings(const struct emif_regs *regs, int nr);
178 210
179 /** 211 /**
180 * Configure DDR PHY 212 * Configure DDR PHY
181 */ 213 */
182 void config_ddr_phy(const struct emif_regs *regs, int nr); 214 void config_ddr_phy(const struct emif_regs *regs, int nr);
183 215
184 struct ddr_cmd_regs { 216 struct ddr_cmd_regs {
185 unsigned int resv0[7]; 217 unsigned int resv0[7];
186 unsigned int cm0csratio; /* offset 0x01C */ 218 unsigned int cm0csratio; /* offset 0x01C */
187 unsigned int resv1[3]; 219 unsigned int resv1[3];
188 unsigned int cm0iclkout; /* offset 0x02C */ 220 unsigned int cm0iclkout; /* offset 0x02C */
189 unsigned int resv2[8]; 221 unsigned int resv2[8];
190 unsigned int cm1csratio; /* offset 0x050 */ 222 unsigned int cm1csratio; /* offset 0x050 */
191 unsigned int resv3[3]; 223 unsigned int resv3[3];
192 unsigned int cm1iclkout; /* offset 0x060 */ 224 unsigned int cm1iclkout; /* offset 0x060 */
193 unsigned int resv4[8]; 225 unsigned int resv4[8];
194 unsigned int cm2csratio; /* offset 0x084 */ 226 unsigned int cm2csratio; /* offset 0x084 */
195 unsigned int resv5[3]; 227 unsigned int resv5[3];
196 unsigned int cm2iclkout; /* offset 0x094 */ 228 unsigned int cm2iclkout; /* offset 0x094 */
197 unsigned int resv6[3]; 229 unsigned int resv6[3];
198 }; 230 };
199 231
200 struct ddr_data_regs { 232 struct ddr_data_regs {
201 unsigned int dt0rdsratio0; /* offset 0x0C8 */ 233 unsigned int dt0rdsratio0; /* offset 0x0C8 */
202 unsigned int resv1[4]; 234 unsigned int resv1[4];
203 unsigned int dt0wdsratio0; /* offset 0x0DC */ 235 unsigned int dt0wdsratio0; /* offset 0x0DC */
204 unsigned int resv2[4]; 236 unsigned int resv2[4];
205 unsigned int dt0wiratio0; /* offset 0x0F0 */ 237 unsigned int dt0wiratio0; /* offset 0x0F0 */
206 unsigned int resv3; 238 unsigned int resv3;
207 unsigned int dt0wimode0; /* offset 0x0F8 */ 239 unsigned int dt0wimode0; /* offset 0x0F8 */
208 unsigned int dt0giratio0; /* offset 0x0FC */ 240 unsigned int dt0giratio0; /* offset 0x0FC */
209 unsigned int resv4; 241 unsigned int resv4;
210 unsigned int dt0gimode0; /* offset 0x104 */ 242 unsigned int dt0gimode0; /* offset 0x104 */
211 unsigned int dt0fwsratio0; /* offset 0x108 */ 243 unsigned int dt0fwsratio0; /* offset 0x108 */
212 unsigned int resv5[4]; 244 unsigned int resv5[4];
213 unsigned int dt0dqoffset; /* offset 0x11C */ 245 unsigned int dt0dqoffset; /* offset 0x11C */
214 unsigned int dt0wrsratio0; /* offset 0x120 */ 246 unsigned int dt0wrsratio0; /* offset 0x120 */
215 unsigned int resv6[4]; 247 unsigned int resv6[4];
216 unsigned int dt0rdelays0; /* offset 0x134 */ 248 unsigned int dt0rdelays0; /* offset 0x134 */
217 unsigned int dt0dldiff0; /* offset 0x138 */ 249 unsigned int dt0dldiff0; /* offset 0x138 */
218 unsigned int resv7[12]; 250 unsigned int resv7[12];
219 }; 251 };
220 252
221 /** 253 /**
222 * This structure represents the DDR registers on AM33XX devices. 254 * This structure represents the DDR registers on AM33XX devices.
223 * We make use of DDR_PHY_BASE_ADDR2 to address the DATA1 registers that 255 * We make use of DDR_PHY_BASE_ADDR2 to address the DATA1 registers that
224 * correspond to DATA1 registers defined here. 256 * correspond to DATA1 registers defined here.
225 */ 257 */
226 struct ddr_regs { 258 struct ddr_regs {
227 unsigned int resv0[3]; 259 unsigned int resv0[3];
228 unsigned int cm0config; /* offset 0x00C */ 260 unsigned int cm0config; /* offset 0x00C */
229 unsigned int cm0configclk; /* offset 0x010 */ 261 unsigned int cm0configclk; /* offset 0x010 */
230 unsigned int resv1[2]; 262 unsigned int resv1[2];
231 unsigned int cm0csratio; /* offset 0x01C */ 263 unsigned int cm0csratio; /* offset 0x01C */
232 unsigned int resv2[3]; 264 unsigned int resv2[3];
233 unsigned int cm0iclkout; /* offset 0x02C */ 265 unsigned int cm0iclkout; /* offset 0x02C */
234 unsigned int resv3[4]; 266 unsigned int resv3[4];
235 unsigned int cm1config; /* offset 0x040 */ 267 unsigned int cm1config; /* offset 0x040 */
236 unsigned int cm1configclk; /* offset 0x044 */ 268 unsigned int cm1configclk; /* offset 0x044 */
237 unsigned int resv4[2]; 269 unsigned int resv4[2];
238 unsigned int cm1csratio; /* offset 0x050 */ 270 unsigned int cm1csratio; /* offset 0x050 */
239 unsigned int resv5[3]; 271 unsigned int resv5[3];
240 unsigned int cm1iclkout; /* offset 0x060 */ 272 unsigned int cm1iclkout; /* offset 0x060 */
241 unsigned int resv6[4]; 273 unsigned int resv6[4];
242 unsigned int cm2config; /* offset 0x074 */ 274 unsigned int cm2config; /* offset 0x074 */
243 unsigned int cm2configclk; /* offset 0x078 */ 275 unsigned int cm2configclk; /* offset 0x078 */
244 unsigned int resv7[2]; 276 unsigned int resv7[2];
245 unsigned int cm2csratio; /* offset 0x084 */ 277 unsigned int cm2csratio; /* offset 0x084 */
246 unsigned int resv8[3]; 278 unsigned int resv8[3];
247 unsigned int cm2iclkout; /* offset 0x094 */ 279 unsigned int cm2iclkout; /* offset 0x094 */
248 unsigned int resv9[12]; 280 unsigned int resv9[12];
249 unsigned int dt0rdsratio0; /* offset 0x0C8 */ 281 unsigned int dt0rdsratio0; /* offset 0x0C8 */
250 unsigned int resv10[4]; 282 unsigned int resv10[4];
251 unsigned int dt0wdsratio0; /* offset 0x0DC */ 283 unsigned int dt0wdsratio0; /* offset 0x0DC */
252 unsigned int resv11[4]; 284 unsigned int resv11[4];
253 unsigned int dt0wiratio0; /* offset 0x0F0 */ 285 unsigned int dt0wiratio0; /* offset 0x0F0 */
254 unsigned int resv12; 286 unsigned int resv12;
255 unsigned int dt0wimode0; /* offset 0x0F8 */ 287 unsigned int dt0wimode0; /* offset 0x0F8 */
256 unsigned int dt0giratio0; /* offset 0x0FC */ 288 unsigned int dt0giratio0; /* offset 0x0FC */
257 unsigned int resv13; 289 unsigned int resv13;
258 unsigned int dt0gimode0; /* offset 0x104 */ 290 unsigned int dt0gimode0; /* offset 0x104 */
259 unsigned int dt0fwsratio0; /* offset 0x108 */ 291 unsigned int dt0fwsratio0; /* offset 0x108 */
260 unsigned int resv14[4]; 292 unsigned int resv14[4];
261 unsigned int dt0dqoffset; /* offset 0x11C */ 293 unsigned int dt0dqoffset; /* offset 0x11C */
262 unsigned int dt0wrsratio0; /* offset 0x120 */ 294 unsigned int dt0wrsratio0; /* offset 0x120 */
263 unsigned int resv15[4]; 295 unsigned int resv15[4];
264 unsigned int dt0rdelays0; /* offset 0x134 */ 296 unsigned int dt0rdelays0; /* offset 0x134 */
265 unsigned int dt0dldiff0; /* offset 0x138 */ 297 unsigned int dt0dldiff0; /* offset 0x138 */
266 }; 298 };
267 299
268 /** 300 /**
269 * Encapsulates DDR CMD control registers. 301 * Encapsulates DDR CMD control registers.
270 */ 302 */
271 struct cmd_control { 303 struct cmd_control {
272 unsigned long cmd0csratio; 304 unsigned long cmd0csratio;
273 unsigned long cmd0csforce; 305 unsigned long cmd0csforce;
274 unsigned long cmd0csdelay; 306 unsigned long cmd0csdelay;
275 unsigned long cmd0iclkout; 307 unsigned long cmd0iclkout;
276 unsigned long cmd1csratio; 308 unsigned long cmd1csratio;
277 unsigned long cmd1csforce; 309 unsigned long cmd1csforce;
278 unsigned long cmd1csdelay; 310 unsigned long cmd1csdelay;
279 unsigned long cmd1iclkout; 311 unsigned long cmd1iclkout;
280 unsigned long cmd2csratio; 312 unsigned long cmd2csratio;
281 unsigned long cmd2csforce; 313 unsigned long cmd2csforce;
282 unsigned long cmd2csdelay; 314 unsigned long cmd2csdelay;
283 unsigned long cmd2iclkout; 315 unsigned long cmd2iclkout;
284 }; 316 };
285 317
286 /** 318 /**
287 * Encapsulates DDR DATA registers. 319 * Encapsulates DDR DATA registers.
288 */ 320 */
289 struct ddr_data { 321 struct ddr_data {
290 unsigned long datardsratio0; 322 unsigned long datardsratio0;
291 unsigned long datawdsratio0; 323 unsigned long datawdsratio0;
292 unsigned long datawiratio0; 324 unsigned long datawiratio0;
293 unsigned long datagiratio0; 325 unsigned long datagiratio0;
294 unsigned long datafwsratio0; 326 unsigned long datafwsratio0;
295 unsigned long datawrsratio0; 327 unsigned long datawrsratio0;
296 }; 328 };
297 329
298 /** 330 /**
299 * Configure DDR CMD control registers 331 * Configure DDR CMD control registers
300 */ 332 */
301 void config_cmd_ctrl(const struct cmd_control *cmd, int nr); 333 void config_cmd_ctrl(const struct cmd_control *cmd, int nr);
302 334
303 /** 335 /**
304 * Configure DDR DATA registers 336 * Configure DDR DATA registers
305 */ 337 */
306 void config_ddr_data(const struct ddr_data *data, int nr); 338 void config_ddr_data(const struct ddr_data *data, int nr);
307 339
308 /** 340 /**
309 * This structure represents the DDR io control on AM33XX devices. 341 * This structure represents the DDR io control on AM33XX devices.
310 */ 342 */
311 struct ddr_cmdtctrl { 343 struct ddr_cmdtctrl {
312 unsigned int cm0ioctl; 344 unsigned int cm0ioctl;
313 unsigned int cm1ioctl; 345 unsigned int cm1ioctl;
314 unsigned int cm2ioctl; 346 unsigned int cm2ioctl;
315 unsigned int resv2[12]; 347 unsigned int resv2[12];
316 unsigned int dt0ioctl; 348 unsigned int dt0ioctl;
317 unsigned int dt1ioctl; 349 unsigned int dt1ioctl;
318 unsigned int dt2ioctrl; 350 unsigned int dt2ioctrl;
319 unsigned int dt3ioctrl; 351 unsigned int dt3ioctrl;
320 unsigned int resv3[4]; 352 unsigned int resv3[4];
321 unsigned int emif_sdram_config_ext; 353 unsigned int emif_sdram_config_ext;
322 }; 354 };
323 355
324 struct ctrl_ioregs { 356 struct ctrl_ioregs {
325 unsigned int cm0ioctl; 357 unsigned int cm0ioctl;
326 unsigned int cm1ioctl; 358 unsigned int cm1ioctl;
327 unsigned int cm2ioctl; 359 unsigned int cm2ioctl;
328 unsigned int dt0ioctl; 360 unsigned int dt0ioctl;
329 unsigned int dt1ioctl; 361 unsigned int dt1ioctl;
330 unsigned int dt2ioctrl; 362 unsigned int dt2ioctrl;
331 unsigned int dt3ioctrl; 363 unsigned int dt3ioctrl;
332 unsigned int emif_sdram_config_ext; 364 unsigned int emif_sdram_config_ext;
333 }; 365 };
334 366
335 /** 367 /**
336 * Configure DDR io control registers 368 * Configure DDR io control registers
337 */ 369 */
338 void config_io_ctrl(const struct ctrl_ioregs *ioregs); 370 void config_io_ctrl(const struct ctrl_ioregs *ioregs);
339 371
340 struct ddr_ctrl { 372 struct ddr_ctrl {
341 unsigned int ddrioctrl; 373 unsigned int ddrioctrl;
342 unsigned int resv1[325]; 374 unsigned int resv1[325];
343 unsigned int ddrckectrl; 375 unsigned int ddrckectrl;
344 }; 376 };
345 377
346 void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs, 378 void config_ddr(unsigned int pll, const struct ctrl_ioregs *ioregs,
347 const struct ddr_data *data, const struct cmd_control *ctrl, 379 const struct ddr_data *data, const struct cmd_control *ctrl,
348 const struct emif_regs *regs, int nr); 380 const struct emif_regs *regs, int nr);
349 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size); 381 void emif_get_ext_phy_ctrl_const_regs(const u32 **regs, u32 *size);
350 382
351 #endif /* _DDR_DEFS_H */ 383 #endif /* _DDR_DEFS_H */
352 384
board/embedian/smarct335x/board.c
Diff comments   View file @ 4bac48b
1 /* 1 /*
2 * board.c 2 * board.c
3 * 3 *
4 * Board functions for TI AM335X based boards 4 * Board functions for TI AM335X based boards
5 * 5 *
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
7 * 7 *
8 * SPDX-License-Identifier: GPL-2.0+ 8 * SPDX-License-Identifier: GPL-2.0+
9 */ 9 */
10 10
11 #include <common.h> 11 #include <common.h>
12 #include <errno.h> 12 #include <errno.h>
13 #include <spl.h> 13 #include <spl.h>
14 #include <asm/arch/cpu.h> 14 #include <asm/arch/cpu.h>
15 #include <asm/arch/hardware.h> 15 #include <asm/arch/hardware.h>
16 #include <asm/arch/omap.h> 16 #include <asm/arch/omap.h>
17 #include <asm/arch/ddr_defs.h> 17 #include <asm/arch/ddr_defs.h>
18 #include <asm/arch/clock.h> 18 #include <asm/arch/clock.h>
19 #include <asm/arch/gpio.h> 19 #include <asm/arch/gpio.h>
20 #include <asm/arch/mmc_host_def.h> 20 #include <asm/arch/mmc_host_def.h>
21 #include <asm/arch/sys_proto.h> 21 #include <asm/arch/sys_proto.h>
22 #include <asm/arch/mem.h> 22 #include <asm/arch/mem.h>
23 #include <asm/io.h> 23 #include <asm/io.h>
24 #include <asm/emif.h> 24 #include <asm/emif.h>
25 #include <asm/gpio.h> 25 #include <asm/gpio.h>
26 #include <i2c.h> 26 #include <i2c.h>
27 #include <miiphy.h> 27 #include <miiphy.h>
28 #include <cpsw.h> 28 #include <cpsw.h>
29 #include <power/tps65217.h> 29 #include <power/tps65217.h>
30 #include <power/tps65910.h> 30 #include <power/tps65910.h>
31 #include <environment.h> 31 #include <environment.h>
32 #include <watchdog.h> 32 #include <watchdog.h>
33 #include "board.h" 33 #include "board.h"
34 34
35 DECLARE_GLOBAL_DATA_PTR; 35 DECLARE_GLOBAL_DATA_PTR;
36 36
37 /* GPIO that controls power to DDR on EVM-SK */ 37 /* GPIO that controls power to DDR on EVM-SK */
38 #define GPIO_DDR_VTT_EN 7 38 #define GPIO_DDR_VTT_EN 7
39 39
40 /* GPIO that controls power of LCD backlight */ 40 /* GPIO that controls power of LCD backlight */
41 #define GPIO_LCD_BKLT_EN 54 41 #define GPIO_LCD_BKLT_EN 54
42 42
43 /* GPIO that controls LCD backlight PWM */ 43 /* GPIO that controls LCD backlight PWM */
44 #define GPIO_LCD_PWM_EN 7 44 #define GPIO_LCD_PWM_EN 7
45 45
46 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 46 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
47 47
48 /* 48 /*
49 * Read header information from EEPROM into global structure. 49 * Read header information from EEPROM into global structure.
50 */ 50 */
51 static int read_eeprom(struct am335x_baseboard_id *header) 51 static int read_eeprom(struct am335x_baseboard_id *header)
52 { 52 {
53 /* Check if baseboard eeprom is available */ 53 /* Check if baseboard eeprom is available */
54 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { 54 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
55 puts("Could not probe the EEPROM; something fundamentally " 55 puts("Could not probe the EEPROM; something fundamentally "
56 "wrong on the I2C bus.\n"); 56 "wrong on the I2C bus.\n");
57 return -ENODEV; 57 return -ENODEV;
58 } 58 }
59 59
60 /* read the eeprom using i2c */ 60 /* read the eeprom using i2c */
61 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header, 61 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
62 sizeof(struct am335x_baseboard_id))) { 62 sizeof(struct am335x_baseboard_id))) {
63 puts("Could not read the EEPROM; something fundamentally" 63 puts("Could not read the EEPROM; something fundamentally"
64 " wrong on the I2C bus.\n"); 64 " wrong on the I2C bus.\n");
65 return -EIO; 65 return -EIO;
66 } 66 }
67 67
68 if (header->magic != 0xEE3355AA) { 68 if (header->magic != 0xEE3355AA) {
69 /* 69 /*
70 * read the eeprom using i2c again, 70 * read the eeprom using i2c again,
71 * but use only a 1 byte address 71 * but use only a 1 byte address
72 */ 72 */
73 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header, 73 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
74 sizeof(struct am335x_baseboard_id))) { 74 sizeof(struct am335x_baseboard_id))) {
75 puts("Could not read the EEPROM; something " 75 puts("Could not read the EEPROM; something "
76 "fundamentally wrong on the I2C bus.\n"); 76 "fundamentally wrong on the I2C bus.\n");
77 return -EIO; 77 return -EIO;
78 } 78 }
79 79
80 if (header->magic != 0xEE3355AA) { 80 if (header->magic != 0xEE3355AA) {
81 printf("Incorrect magic number (0x%x) in EEPROM\n", 81 printf("Incorrect magic number (0x%x) in EEPROM\n",
82 header->magic); 82 header->magic);
83 return -EINVAL; 83 return -EINVAL;
84 } 84 }
85 } 85 }
86 86
87 return 0; 87 return 0;
88 } 88 }
89 89
90 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) 90 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
91 static const struct ddr_data ddr2_data = { 91 static const struct ddr_data ddr2_data = {
92 .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) | 92 .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
93 (MT47H128M16RT25E_RD_DQS<<20) | 93 (MT47H128M16RT25E_RD_DQS<<20) |
94 (MT47H128M16RT25E_RD_DQS<<10) | 94 (MT47H128M16RT25E_RD_DQS<<10) |
95 (MT47H128M16RT25E_RD_DQS<<0)), 95 (MT47H128M16RT25E_RD_DQS<<0)),
96 .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) | 96 .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
97 (MT47H128M16RT25E_WR_DQS<<20) | 97 (MT47H128M16RT25E_WR_DQS<<20) |
98 (MT47H128M16RT25E_WR_DQS<<10) | 98 (MT47H128M16RT25E_WR_DQS<<10) |
99 (MT47H128M16RT25E_WR_DQS<<0)), 99 (MT47H128M16RT25E_WR_DQS<<0)),
100 .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) | 100 .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
101 (MT47H128M16RT25E_PHY_WRLVL<<20) | 101 (MT47H128M16RT25E_PHY_WRLVL<<20) |
102 (MT47H128M16RT25E_PHY_WRLVL<<10) | 102 (MT47H128M16RT25E_PHY_WRLVL<<10) |
103 (MT47H128M16RT25E_PHY_WRLVL<<0)), 103 (MT47H128M16RT25E_PHY_WRLVL<<0)),
104 .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) | 104 .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
105 (MT47H128M16RT25E_PHY_GATELVL<<20) | 105 (MT47H128M16RT25E_PHY_GATELVL<<20) |
106 (MT47H128M16RT25E_PHY_GATELVL<<10) | 106 (MT47H128M16RT25E_PHY_GATELVL<<10) |
107 (MT47H128M16RT25E_PHY_GATELVL<<0)), 107 (MT47H128M16RT25E_PHY_GATELVL<<0)),
108 .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) | 108 .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
109 (MT47H128M16RT25E_PHY_FIFO_WE<<20) | 109 (MT47H128M16RT25E_PHY_FIFO_WE<<20) |
110 (MT47H128M16RT25E_PHY_FIFO_WE<<10) | 110 (MT47H128M16RT25E_PHY_FIFO_WE<<10) |
111 (MT47H128M16RT25E_PHY_FIFO_WE<<0)), 111 (MT47H128M16RT25E_PHY_FIFO_WE<<0)),
112 .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) | 112 .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
113 (MT47H128M16RT25E_PHY_WR_DATA<<20) | 113 (MT47H128M16RT25E_PHY_WR_DATA<<20) |
114 (MT47H128M16RT25E_PHY_WR_DATA<<10) | 114 (MT47H128M16RT25E_PHY_WR_DATA<<10) |
115 (MT47H128M16RT25E_PHY_WR_DATA<<0)), 115 (MT47H128M16RT25E_PHY_WR_DATA<<0)),
116 }; 116 };
117 117
118 static const struct cmd_control ddr2_cmd_ctrl_data = { 118 static const struct cmd_control ddr2_cmd_ctrl_data = {
119 .cmd0csratio = MT47H128M16RT25E_RATIO, 119 .cmd0csratio = MT47H128M16RT25E_RATIO,
120 .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT, 120 .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
121 121
122 .cmd1csratio = MT47H128M16RT25E_RATIO, 122 .cmd1csratio = MT47H128M16RT25E_RATIO,
123 .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT, 123 .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
124 124
125 .cmd2csratio = MT47H128M16RT25E_RATIO, 125 .cmd2csratio = MT47H128M16RT25E_RATIO,
126 .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT, 126 .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
127 }; 127 };
128 128
129 static const struct emif_regs ddr2_emif_reg_data = { 129 static const struct emif_regs ddr2_emif_reg_data = {
130 .sdram_config = MT47H128M16RT25E_EMIF_SDCFG, 130 .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
131 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF, 131 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
132 .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1, 132 .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
133 .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2, 133 .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
134 .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3, 134 .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
135 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY, 135 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
136 }; 136 };
137 137
138 static const struct ddr_data ddr3_data = { 138 static const struct ddr_data ddr3_data = {
139 .datardsratio0 = MT41J128MJT125_RD_DQS, 139 .datardsratio0 = MT41J128MJT125_RD_DQS,
140 .datawdsratio0 = MT41J128MJT125_WR_DQS, 140 .datawdsratio0 = MT41J128MJT125_WR_DQS,
141 .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE, 141 .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
142 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA, 142 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
143 }; 143 };
144 144
145 static const struct ddr_data ddr3_beagleblack_data = { 145 static const struct ddr_data ddr3_beagleblack_data = {
146 .datardsratio0 = MT41K256M16HA125E_RD_DQS, 146 .datardsratio0 = MT41K256M16HA125E_RD_DQS,
147 .datawdsratio0 = MT41K256M16HA125E_WR_DQS, 147 .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
148 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, 148 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
149 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, 149 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
150 }; 150 };
151 151
152 static const struct ddr_data ddr3_smarct335x_data = { 152 static const struct ddr_data ddr3_smarct335x_data = {
153 .datardsratio0 = MT41K256M16HA125E_RD_DQS, 153 .datardsratio0 = K4B4G1646EBYK0_RD_DQS,
154 .datawdsratio0 = MT41K256M16HA125E_WR_DQS, 154 .datawdsratio0 = K4B4G1646EBYK0_WR_DQS,
155 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, 155 .datafwsratio0 = K4B4G1646EBYK0_PHY_FIFO_WE,
156 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, 156 .datawrsratio0 = K4B4G1646EBYK0_PHY_WR_DATA,
157 }; 157 };
158 158
159 static const struct ddr_data ddr3_smarct335x80_data = {
160 .datardsratio0 = MT41K256M16HA125ITE_RD_DQS,
161 .datawdsratio0 = MT41K256M16HA125ITE_WR_DQS,
162 .datafwsratio0 = MT41K256M16HA125ITE_PHY_FIFO_WE,
163 .datawrsratio0 = MT41K256M16HA125ITE_PHY_WR_DATA,
164 };
165
159 static const struct ddr_data ddr3_evm_data = { 166 static const struct ddr_data ddr3_evm_data = {
160 .datardsratio0 = MT41J512M8RH125_RD_DQS, 167 .datardsratio0 = MT41J512M8RH125_RD_DQS,
161 .datawdsratio0 = MT41J512M8RH125_WR_DQS, 168 .datawdsratio0 = MT41J512M8RH125_WR_DQS,
162 .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE, 169 .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
163 .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA, 170 .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
164 }; 171 };
165 172
166 static const struct cmd_control ddr3_cmd_ctrl_data = { 173 static const struct cmd_control ddr3_cmd_ctrl_data = {
167 .cmd0csratio = MT41J128MJT125_RATIO, 174 .cmd0csratio = MT41J128MJT125_RATIO,
168 .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT, 175 .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
169 176
170 .cmd1csratio = MT41J128MJT125_RATIO, 177 .cmd1csratio = MT41J128MJT125_RATIO,
171 .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT, 178 .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
172 179
173 .cmd2csratio = MT41J128MJT125_RATIO, 180 .cmd2csratio = MT41J128MJT125_RATIO,
174 .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT, 181 .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
175 }; 182 };
176 183
177 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = { 184 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
178 .cmd0csratio = MT41K256M16HA125E_RATIO, 185 .cmd0csratio = MT41K256M16HA125E_RATIO,
179 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 186 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
180 187
181 .cmd1csratio = MT41K256M16HA125E_RATIO, 188 .cmd1csratio = MT41K256M16HA125E_RATIO,
182 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 189 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
183 190
184 .cmd2csratio = MT41K256M16HA125E_RATIO, 191 .cmd2csratio = MT41K256M16HA125E_RATIO,
185 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 192 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
186 }; 193 };
187 194
188 static const struct cmd_control ddr3_smarct335x_cmd_ctrl_data = { 195 static const struct cmd_control ddr3_smarct335x_cmd_ctrl_data = {
189 .cmd0csratio = MT41K256M16HA125E_RATIO, 196 .cmd0csratio = K4B4G1646EBYK0_RATIO,
190 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 197 .cmd0iclkout = K4B4G1646EBYK0_INVERT_CLKOUT,
191 198
192 .cmd1csratio = MT41K256M16HA125E_RATIO, 199 .cmd1csratio = K4B4G1646EBYK0_RATIO,
193 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 200 .cmd1iclkout = K4B4G1646EBYK0_INVERT_CLKOUT,
194 201
195 .cmd2csratio = MT41K256M16HA125E_RATIO, 202 .cmd2csratio = K4B4G1646EBYK0_RATIO,
196 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 203 .cmd2iclkout = K4B4G1646EBYK0_INVERT_CLKOUT,
197 }; 204 };
198 205
206 static const struct cmd_control ddr3_smarct335x80_cmd_ctrl_data = {
207 .cmd0csratio = MT41K256M16HA125ITE_RATIO,
208 .cmd0iclkout = MT41K256M16HA125ITE_INVERT_CLKOUT,
209
210 .cmd1csratio = MT41K256M16HA125ITE_RATIO,
211 .cmd1iclkout = MT41K256M16HA125ITE_INVERT_CLKOUT,
212
213 .cmd2csratio = MT41K256M16HA125ITE_RATIO,
214 .cmd2iclkout = MT41K256M16HA125ITE_INVERT_CLKOUT,
215 };
216
199 static const struct cmd_control ddr3_evm_cmd_ctrl_data = { 217 static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
200 .cmd0csratio = MT41J512M8RH125_RATIO, 218 .cmd0csratio = MT41J512M8RH125_RATIO,
201 .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT, 219 .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
202 220
203 .cmd1csratio = MT41J512M8RH125_RATIO, 221 .cmd1csratio = MT41J512M8RH125_RATIO,
204 .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT, 222 .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
205 223
206 .cmd2csratio = MT41J512M8RH125_RATIO, 224 .cmd2csratio = MT41J512M8RH125_RATIO,
207 .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT, 225 .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
208 }; 226 };
209 227
210 static struct emif_regs ddr3_emif_reg_data = { 228 static struct emif_regs ddr3_emif_reg_data = {
211 .sdram_config = MT41J128MJT125_EMIF_SDCFG, 229 .sdram_config = MT41J128MJT125_EMIF_SDCFG,
212 .ref_ctrl = MT41J128MJT125_EMIF_SDREF, 230 .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
213 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1, 231 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
214 .sdram_tim2 = MT41J128MJT125_EMIF_TIM2, 232 .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
215 .sdram_tim3 = MT41J128MJT125_EMIF_TIM3, 233 .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
216 .zq_config = MT41J128MJT125_ZQ_CFG, 234 .zq_config = MT41J128MJT125_ZQ_CFG,
217 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY | 235 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
218 PHY_EN_DYN_PWRDN, 236 PHY_EN_DYN_PWRDN,
219 }; 237 };
220 238
221 static struct emif_regs ddr3_beagleblack_emif_reg_data = { 239 static struct emif_regs ddr3_beagleblack_emif_reg_data = {
222 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, 240 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
223 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, 241 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
224 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, 242 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
225 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, 243 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
226 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, 244 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
227 .zq_config = MT41K256M16HA125E_ZQ_CFG, 245 .zq_config = MT41K256M16HA125E_ZQ_CFG,
228 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, 246 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
229 }; 247 };
230 248
231 static struct emif_regs ddr3_smarct335x_emif_reg_data = { 249 static struct emif_regs ddr3_smarct335x_emif_reg_data = {
232 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, 250 .sdram_config = K4B4G1646EBYK0_EMIF_SDCFG,
233 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, 251 .ref_ctrl = K4B4G1646EBYK0_EMIF_SDREF,
234 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, 252 .sdram_tim1 = K4B4G1646EBYK0_EMIF_TIM1,
235 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, 253 .sdram_tim2 = K4B4G1646EBYK0_EMIF_TIM2,
236 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, 254 .sdram_tim3 = K4B4G1646EBYK0_EMIF_TIM3,
237 .zq_config = MT41K256M16HA125E_ZQ_CFG, 255 .zq_config = K4B4G1646EBYK0_ZQ_CFG,
238 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, 256 .emif_ddr_phy_ctlr_1 = K4B4G1646EBYK0_EMIF_READ_LATENCY,
239 }; 257 };
240 258
259 static struct emif_regs ddr3_smarct335x80_emif_reg_data = {
260 .sdram_config = MT41K256M16HA125ITE_EMIF_SDCFG,
261 .ref_ctrl = MT41K256M16HA125ITE_EMIF_SDREF,
262 .sdram_tim1 = MT41K256M16HA125ITE_EMIF_TIM1,
263 .sdram_tim2 = MT41K256M16HA125ITE_EMIF_TIM2,
264 .sdram_tim3 = MT41K256M16HA125ITE_EMIF_TIM3,
265 .zq_config = MT41K256M16HA125ITE_ZQ_CFG,
266 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125ITE_EMIF_READ_LATENCY,
267 };
268
241 static struct emif_regs ddr3_evm_emif_reg_data = { 269 static struct emif_regs ddr3_evm_emif_reg_data = {
242 .sdram_config = MT41J512M8RH125_EMIF_SDCFG, 270 .sdram_config = MT41J512M8RH125_EMIF_SDCFG,
243 .ref_ctrl = MT41J512M8RH125_EMIF_SDREF, 271 .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
244 .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1, 272 .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
245 .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2, 273 .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
246 .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3, 274 .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
247 .zq_config = MT41J512M8RH125_ZQ_CFG, 275 .zq_config = MT41J512M8RH125_ZQ_CFG,
248 .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY | 276 .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
249 PHY_EN_DYN_PWRDN, 277 PHY_EN_DYN_PWRDN,
250 }; 278 };
251 279
252 #ifdef CONFIG_SPL_OS_BOOT 280 #ifdef CONFIG_SPL_OS_BOOT
253 int spl_start_uboot(void) 281 int spl_start_uboot(void)
254 { 282 {
255 /* break into full u-boot on 'c' */ 283 /* break into full u-boot on 'c' */
256 return (serial_tstc() && serial_getc() == 'c'); 284 return (serial_tstc() && serial_getc() == 'c');
257 } 285 }
258 #endif 286 #endif
259 287
260 #define OSC (V_OSCK/1000000) 288 #define OSC (V_OSCK/1000000)
261 const struct dpll_params dpll_ddr = { 289 const struct dpll_params dpll_ddr = {
262 266, OSC-1, 1, -1, -1, -1, -1}; 290 266, OSC-1, 1, -1, -1, -1, -1};
263 const struct dpll_params dpll_ddr_evm_sk = { 291 const struct dpll_params dpll_ddr_evm_sk = {
264 303, OSC-1, 1, -1, -1, -1, -1}; 292 303, OSC-1, 1, -1, -1, -1, -1};
265 const struct dpll_params dpll_ddr_bone_black = { 293 const struct dpll_params dpll_ddr_bone_black = {
266 400, OSC-1, 1, -1, -1, -1, -1}; 294 400, OSC-1, 1, -1, -1, -1, -1};
267 const struct dpll_params dpll_ddr_smarc_t335x = { 295 const struct dpll_params dpll_ddr_smarc_t335x = {
268 400, OSC-1, 1, -1, -1, -1, -1}; 296 400, OSC-1, 1, -1, -1, -1, -1};
269 297
270 void am33xx_spl_board_init(void) 298 void am33xx_spl_board_init(void)
271 { 299 {
272 struct am335x_baseboard_id header; 300 struct am335x_baseboard_id header;
273 int mpu_vdd; 301 int mpu_vdd;
274 302
275 if (read_eeprom(&header) < 0) 303 if (read_eeprom(&header) < 0)
276 puts("Could not get board ID.\n"); 304 puts("Could not get board ID.\n");
277 305
278 /* Get the frequency */ 306 /* Get the frequency */
279 dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); 307 dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
280 308
281 if (board_is_bone(&header) || board_is_bone_lt(&header) || board_is_smarc_t335x(&header) || board_is_smarc_t335x_1g(&header)) { 309 if (board_is_bone(&header) || board_is_bone_lt(&header) || board_is_smarc_t335x(&header) || board_is_smarc_t335x_80(&header) || board_is_smarc_t335x_1g(&header)) {
282 /* BeagleBone and SMARC T335X PMIC Code */ 310 /* BeagleBone and SMARC T335X PMIC Code */
283 int usb_cur_lim; 311 int usb_cur_lim;
284 312
285 /* 313 /*
286 * Only perform PMIC configurations if board rev > A1 314 * Only perform PMIC configurations if board rev > A1
287 * on Beaglebone White 315 * on Beaglebone White
288 */ 316 */
289 if (board_is_bone(&header) && !strncmp(header.version, 317 if (board_is_bone(&header) && !strncmp(header.version,
290 "00A1", 4)) 318 "00A1", 4))
291 return; 319 return;
292 320
293 if (i2c_probe(TPS65217_CHIP_PM)) 321 if (i2c_probe(TPS65217_CHIP_PM))
294 return; 322 return;
295 323
296 /* 324 /*
297 * On Beaglebone White we need to ensure we have AC power 325 * On Beaglebone White we need to ensure we have AC power
298 * before increasing the frequency. 326 * before increasing the frequency.
299 */ 327 */
300 if (board_is_bone(&header)) { 328 if (board_is_bone(&header)) {
301 uchar pmic_status_reg; 329 uchar pmic_status_reg;
302 if (tps65217_reg_read(TPS65217_STATUS, 330 if (tps65217_reg_read(TPS65217_STATUS,
303 &pmic_status_reg)) 331 &pmic_status_reg))
304 return; 332 return;
305 if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) { 333 if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
306 puts("No AC power, disabling frequency switch\n"); 334 puts("No AC power, disabling frequency switch\n");
307 return; 335 return;
308 } 336 }
309 } 337 }
310 338
311 /* 339 /*
312 * Override what we have detected since we know if we have 340 * Override what we have detected since we know if we have
313 * a Beaglebone Black or SMARC T335X 1G they support 1GHz. 341 * a Beaglebone Black or SMARC T335X 1G they support 1GHz.
314 */ 342 */
315 if ((board_is_bone_lt(&header) || board_is_smarc_t335x_1g(&header))) 343 if ((board_is_bone_lt(&header) || board_is_smarc_t335x_1g(&header)))
316 dpll_mpu_opp100.m = MPUPLL_M_1000; 344 dpll_mpu_opp100.m = MPUPLL_M_1000;
317 345
318 /* 346 /*
319 * Increase USB current limit to 1300mA or 1800mA and set 347 * Increase USB current limit to 1300mA or 1800mA and set
320 * the MPU voltage controller as needed. 348 * the MPU voltage controller as needed.
321 */ 349 */
322 if (dpll_mpu_opp100.m == MPUPLL_M_1000) { 350 if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
323 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; 351 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
324 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV; 352 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
325 } else { 353 } else {
326 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; 354 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
327 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV; 355 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
328 } 356 }
329 357
330 if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, 358 if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
331 TPS65217_POWER_PATH, 359 TPS65217_POWER_PATH,
332 usb_cur_lim, 360 usb_cur_lim,
333 TPS65217_USB_INPUT_CUR_LIMIT_MASK)) 361 TPS65217_USB_INPUT_CUR_LIMIT_MASK))
334 puts("tps65217_reg_write failure\n"); 362 puts("tps65217_reg_write failure\n");
335 363
336 /* Set DCDC3 (CORE) voltage to 1.125V */ 364 /* Set DCDC3 (CORE) voltage to 1.125V */
337 if (tps65217_voltage_update(TPS65217_DEFDCDC3, 365 if (tps65217_voltage_update(TPS65217_DEFDCDC3,
338 TPS65217_DCDC_VOLT_SEL_1125MV)) { 366 TPS65217_DCDC_VOLT_SEL_1125MV)) {
339 puts("tps65217_voltage_update failure\n"); 367 puts("tps65217_voltage_update failure\n");
340 return; 368 return;
341 } 369 }
342 370
343 /* Set CORE Frequencies to OPP100 */ 371 /* Set CORE Frequencies to OPP100 */
344 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); 372 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
345 373
346 /* Set DCDC2 (MPU) voltage */ 374 /* Set DCDC2 (MPU) voltage */
347 if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) { 375 if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
348 puts("tps65217_voltage_update failure\n"); 376 puts("tps65217_voltage_update failure\n");
349 return; 377 return;
350 } 378 }
351 379
352 /* 380 /*
353 * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone. 381 * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
354 * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black and SMARC T335X. 382 * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black and SMARC T335X.
355 */ 383 */
356 if (board_is_bone(&header)) { 384 if (board_is_bone(&header)) {
357 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, 385 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
358 TPS65217_DEFLS1, 386 TPS65217_DEFLS1,
359 TPS65217_LDO_VOLTAGE_OUT_3_3, 387 TPS65217_LDO_VOLTAGE_OUT_3_3,
360 TPS65217_LDO_MASK)) 388 TPS65217_LDO_MASK))
361 puts("tps65217_reg_write failure\n"); 389 puts("tps65217_reg_write failure\n");
362 } else { 390 } else {
363 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, 391 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
364 TPS65217_DEFLS1, 392 TPS65217_DEFLS1,
365 TPS65217_LDO_VOLTAGE_OUT_1_8, 393 TPS65217_LDO_VOLTAGE_OUT_1_8,
366 TPS65217_LDO_MASK)) 394 TPS65217_LDO_MASK))
367 puts("tps65217_reg_write failure\n"); 395 puts("tps65217_reg_write failure\n");
368 } 396 }
369 397
370 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, 398 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
371 TPS65217_DEFLS2, 399 TPS65217_DEFLS2,
372 TPS65217_LDO_VOLTAGE_OUT_3_3, 400 TPS65217_LDO_VOLTAGE_OUT_3_3,
373 TPS65217_LDO_MASK)) 401 TPS65217_LDO_MASK))
374 puts("tps65217_reg_write failure\n"); 402 puts("tps65217_reg_write failure\n");
375 } else { 403 } else {
376 int sil_rev; 404 int sil_rev;
377 405
378 /* 406 /*
379 * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all 407 * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all
380 * MPU frequencies we support we use a CORE voltage of 408 * MPU frequencies we support we use a CORE voltage of
381 * 1.1375V. For MPU voltage we need to switch based on 409 * 1.1375V. For MPU voltage we need to switch based on
382 * the frequency we are running at. 410 * the frequency we are running at.
383 */ 411 */
384 if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) 412 if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
385 return; 413 return;
386 414
387 /* 415 /*
388 * Depending on MPU clock and PG we will need a different 416 * Depending on MPU clock and PG we will need a different
389 * VDD to drive at that speed. 417 * VDD to drive at that speed.
390 */ 418 */
391 sil_rev = readl(&cdev->deviceid) >> 28; 419 sil_rev = readl(&cdev->deviceid) >> 28;
392 mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, 420 mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
393 dpll_mpu_opp100.m); 421 dpll_mpu_opp100.m);
394 422
395 /* Tell the TPS65910 to use i2c */ 423 /* Tell the TPS65910 to use i2c */
396 tps65910_set_i2c_control(); 424 tps65910_set_i2c_control();
397 425
398 /* First update MPU voltage. */ 426 /* First update MPU voltage. */
399 if (tps65910_voltage_update(MPU, mpu_vdd)) 427 if (tps65910_voltage_update(MPU, mpu_vdd))
400 return; 428 return;
401 429
402 /* Second, update the CORE voltage. */ 430 /* Second, update the CORE voltage. */
403 if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3)) 431 if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
404 return; 432 return;
405 433
406 /* Set CORE Frequencies to OPP100 */ 434 /* Set CORE Frequencies to OPP100 */
407 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); 435 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
408 } 436 }
409 437
410 /* Set MPU Frequency to what we detected now that voltages are set */ 438 /* Set MPU Frequency to what we detected now that voltages are set */
411 do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); 439 do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
412 } 440 }
413 441
414 const struct dpll_params *get_dpll_ddr_params(void) 442 const struct dpll_params *get_dpll_ddr_params(void)
415 { 443 {
416 struct am335x_baseboard_id header; 444 struct am335x_baseboard_id header;
417 445
418 enable_i2c0_pin_mux(); 446 enable_i2c0_pin_mux();
419 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE); 447 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
420 if (read_eeprom(&header) < 0) 448 if (read_eeprom(&header) < 0)
421 puts("Could not get board ID.\n"); 449 puts("Could not get board ID.\n");
422 450
423 if (board_is_evm_sk(&header)) 451 if (board_is_evm_sk(&header))
424 return &dpll_ddr_evm_sk; 452 return &dpll_ddr_evm_sk;
425 else if (board_is_bone_lt(&header)) 453 else if (board_is_bone_lt(&header))
426 return &dpll_ddr_bone_black; 454 return &dpll_ddr_bone_black;
427 else if (board_is_smarc_t335x(&header) || board_is_smarc_t335x_1g(&header)) 455 else if (board_is_smarc_t335x(&header) || board_is_smarc_t335x_80(&header) || board_is_smarc_t335x_1g(&header))
428 return &dpll_ddr_smarc_t335x; 456 return &dpll_ddr_smarc_t335x;
429 else if (board_is_evm_15_or_later(&header)) 457 else if (board_is_evm_15_or_later(&header))
430 return &dpll_ddr_evm_sk; 458 return &dpll_ddr_evm_sk;
431 else 459 else
432 return &dpll_ddr; 460 return &dpll_ddr;
433 } 461 }
434 462
435 void set_uart_mux_conf(void) 463 void set_uart_mux_conf(void)
436 { 464 {
437 #ifdef CONFIG_SERIAL1 465 #ifdef CONFIG_SERIAL1
438 enable_uart0_pin_mux(); 466 enable_uart0_pin_mux();
439 #endif /* CONFIG_SERIAL1 */ 467 #endif /* CONFIG_SERIAL1 */
440 #ifdef CONFIG_SERIAL2 468 #ifdef CONFIG_SERIAL2
441 enable_uart1_pin_mux(); 469 enable_uart1_pin_mux();
442 #endif /* CONFIG_SERIAL2 */ 470 #endif /* CONFIG_SERIAL2 */
443 #ifdef CONFIG_SERIAL3 471 #ifdef CONFIG_SERIAL3
444 enable_uart2_pin_mux(); 472 enable_uart2_pin_mux();
445 #endif /* CONFIG_SERIAL3 */ 473 #endif /* CONFIG_SERIAL3 */
446 #ifdef CONFIG_SERIAL4 474 #ifdef CONFIG_SERIAL4
447 enable_uart3_pin_mux(); 475 enable_uart3_pin_mux();
448 #endif /* CONFIG_SERIAL4 */ 476 #endif /* CONFIG_SERIAL4 */
449 #ifdef CONFIG_SERIAL5 477 #ifdef CONFIG_SERIAL5
450 enable_uart4_pin_mux(); 478 enable_uart4_pin_mux();
451 #endif /* CONFIG_SERIAL5 */ 479 #endif /* CONFIG_SERIAL5 */
452 #ifdef CONFIG_SERIAL6 480 #ifdef CONFIG_SERIAL6
453 enable_uart5_pin_mux(); 481 enable_uart5_pin_mux();
454 #endif /* CONFIG_SERIAL6 */ 482 #endif /* CONFIG_SERIAL6 */
455 } 483 }
456 484
457 void set_mux_conf_regs(void) 485 void set_mux_conf_regs(void)
458 { 486 {
459 __maybe_unused struct am335x_baseboard_id header; 487 __maybe_unused struct am335x_baseboard_id header;
460 488
461 if (read_eeprom(&header) < 0) 489 if (read_eeprom(&header) < 0)
462 puts("Could not get board ID.\n"); 490 puts("Could not get board ID.\n");
463 491
464 enable_board_pin_mux(&header); 492 enable_board_pin_mux(&header);
465 } 493 }
466 494
467 const struct ctrl_ioregs ioregs_evmsk = { 495 const struct ctrl_ioregs ioregs_evmsk = {
468 .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE, 496 .cm0ioctl = MT41J128MJT125_IOCTRL_VALUE,
469 .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE, 497 .cm1ioctl = MT41J128MJT125_IOCTRL_VALUE,
470 .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE, 498 .cm2ioctl = MT41J128MJT125_IOCTRL_VALUE,
471 .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE, 499 .dt0ioctl = MT41J128MJT125_IOCTRL_VALUE,
472 .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE, 500 .dt1ioctl = MT41J128MJT125_IOCTRL_VALUE,
473 }; 501 };
474 502
475 const struct ctrl_ioregs ioregs_bonelt = { 503 const struct ctrl_ioregs ioregs_bonelt = {
476 .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 504 .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
477 .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 505 .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
478 .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 506 .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
479 .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 507 .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
480 .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 508 .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
481 }; 509 };
482 510
483 const struct ctrl_ioregs ioregs_smarct335x = { 511 const struct ctrl_ioregs ioregs_smarct335x = {
484 .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 512 .cm0ioctl = K4B4G1646EBYK0_IOCTRL_VALUE,
485 .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 513 .cm1ioctl = K4B4G1646EBYK0_IOCTRL_VALUE,
486 .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 514 .cm2ioctl = K4B4G1646EBYK0_IOCTRL_VALUE,
487 .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 515 .dt0ioctl = K4B4G1646EBYK0_IOCTRL_VALUE,
488 .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 516 .dt1ioctl = K4B4G1646EBYK0_IOCTRL_VALUE,
489 }; 517 };
490 518
519 const struct ctrl_ioregs ioregs_smarct335x80 = {
520 .cm0ioctl = MT41K256M16HA125ITE_IOCTRL_VALUE,
521 .cm1ioctl = MT41K256M16HA125ITE_IOCTRL_VALUE,
522 .cm2ioctl = MT41K256M16HA125ITE_IOCTRL_VALUE,
523 .dt0ioctl = MT41K256M16HA125ITE_IOCTRL_VALUE,
524 .dt1ioctl = MT41K256M16HA125ITE_IOCTRL_VALUE,
525 };
526
491 const struct ctrl_ioregs ioregs_evm15 = { 527 const struct ctrl_ioregs ioregs_evm15 = {
492 .cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE, 528 .cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
493 .cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE, 529 .cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
494 .cm2ioctl = MT41J512M8RH125_IOCTRL_VALUE, 530 .cm2ioctl = MT41J512M8RH125_IOCTRL_VALUE,
495 .dt0ioctl = MT41J512M8RH125_IOCTRL_VALUE, 531 .dt0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
496 .dt1ioctl = MT41J512M8RH125_IOCTRL_VALUE, 532 .dt1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
497 }; 533 };
498 534
499 const struct ctrl_ioregs ioregs = { 535 const struct ctrl_ioregs ioregs = {
500 .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 536 .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
501 .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 537 .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
502 .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 538 .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
503 .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 539 .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
504 .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE, 540 .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
505 }; 541 };
506 542
507 void sdram_init(void) 543 void sdram_init(void)
508 { 544 {
509 __maybe_unused struct am335x_baseboard_id header; 545 __maybe_unused struct am335x_baseboard_id header;
510 546
511 if (read_eeprom(&header) < 0) 547 if (read_eeprom(&header) < 0)
512 puts("Could not get board ID.\n"); 548 puts("Could not get board ID.\n");
513 549
514 if (board_is_evm_sk(&header)) { 550 if (board_is_evm_sk(&header)) {
515 /* 551 /*
516 * EVM SK 1.2A and later use gpio0_7 to enable DDR3. 552 * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
517 * This is safe enough to do on older revs. 553 * This is safe enough to do on older revs.
518 */ 554 */
519 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); 555 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
520 gpio_direction_output(GPIO_DDR_VTT_EN, 1); 556 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
521 } 557 }
522 558
523 if (board_is_evm_sk(&header)) 559 if (board_is_evm_sk(&header))
524 config_ddr(303, &ioregs_evmsk, &ddr3_data, 560 config_ddr(303, &ioregs_evmsk, &ddr3_data,
525 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); 561 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
526 else if (board_is_bone_lt(&header)) 562 else if (board_is_bone_lt(&header))
527 config_ddr(400, &ioregs_bonelt, 563 config_ddr(400, &ioregs_bonelt,
528 &ddr3_beagleblack_data, 564 &ddr3_beagleblack_data,
529 &ddr3_beagleblack_cmd_ctrl_data, 565 &ddr3_beagleblack_cmd_ctrl_data,
530 &ddr3_beagleblack_emif_reg_data, 0); 566 &ddr3_beagleblack_emif_reg_data, 0);
531 else if (board_is_smarc_t335x(&header) || board_is_smarc_t335x_1g(&header)) { 567 else if (board_is_smarc_t335x(&header) || board_is_smarc_t335x_1g(&header)) {
532 /* 568 /*
533 * SMARC T335X rev. 00B0 and later use gpio0_7 as LCD backlight PWM and gpio1_22 as LCD backlight enable. 569 * SMARC T335X rev. 00B0 and later use gpio0_7 as LCD backlight PWM and gpio1_22 as LCD backlight enable.
534 * This is safe enough to do on older revs. 570 * This is safe enough to do on older revs.
535 */ 571 */
536 gpio_request(GPIO_LCD_BKLT_EN, "lcd_bklt_en"); 572 gpio_request(GPIO_LCD_BKLT_EN, "lcd_bklt_en");
537 gpio_direction_output(GPIO_LCD_BKLT_EN, 1); 573 gpio_direction_output(GPIO_LCD_BKLT_EN, 1);
538 gpio_request(GPIO_LCD_PWM_EN, "lcd_pwm_en"); 574 gpio_request(GPIO_LCD_PWM_EN, "lcd_pwm_en");
539 gpio_direction_output(GPIO_LCD_PWM_EN, 1); 575 gpio_direction_output(GPIO_LCD_PWM_EN, 1);
540 config_ddr(400, &ioregs_smarct335x, 576 config_ddr(400, &ioregs_smarct335x,
541 &ddr3_smarct335x_data, 577 &ddr3_smarct335x_data,
542 &ddr3_smarct335x_cmd_ctrl_data, 578 &ddr3_smarct335x_cmd_ctrl_data,
543 &ddr3_smarct335x_emif_reg_data, 0); 579 &ddr3_smarct335x_emif_reg_data, 0);
544 puts("Set DDR3 to 800MHz.\n"); 580 udelay(1600);
545 } 581 }
582 else if (board_is_smarc_t335x_80(&header)) {
583 /*
584 * SMARC T335X rev. 00B0 and later use gpio0_7 as LCD backlight PWM and gpio1_22 as LCD backlight enable.
585 * This is safe enough to do on older revs.
586 */
587 gpio_request(GPIO_LCD_BKLT_EN, "lcd_bklt_en");
588 gpio_direction_output(GPIO_LCD_BKLT_EN, 1);
589 gpio_request(GPIO_LCD_PWM_EN, "lcd_pwm_en");
590 gpio_direction_output(GPIO_LCD_PWM_EN, 1);
591 config_ddr(400, &ioregs_smarct335x80,
592 &ddr3_smarct335x80_data,
593 &ddr3_smarct335x80_cmd_ctrl_data,
594 &ddr3_smarct335x80_emif_reg_data, 0);
595 udelay(1200);
596 }
546 else if (board_is_evm_15_or_later(&header)) 597 else if (board_is_evm_15_or_later(&header))
547 config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data, 598 config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data,
548 &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0); 599 &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
549 else 600 else
550 config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data, 601 config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
551 &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0); 602 &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
552 } 603 }
553 #endif 604 #endif
554 605
555 /* 606 /*
556 * Basic board specific setup. Pinmux has been handled already. 607 * Basic board specific setup. Pinmux has been handled already.
557 */ 608 */
558 int board_init(void) 609 int board_init(void)
559 { 610 {
560 #if defined(CONFIG_HW_WATCHDOG) 611 #if defined(CONFIG_HW_WATCHDOG)
561 hw_watchdog_init(); 612 hw_watchdog_init();
562 #endif 613 #endif
563 614
564 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 615 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
565 #if defined(CONFIG_NOR) || defined(CONFIG_NAND) 616 #if defined(CONFIG_NOR) || defined(CONFIG_NAND)
566 gpmc_init(); 617 gpmc_init();
567 #endif 618 #endif
568 return 0; 619 return 0;
569 } 620 }
570 621
571 #ifdef CONFIG_BOARD_LATE_INIT 622 #ifdef CONFIG_BOARD_LATE_INIT
572 int board_late_init(void) 623 int board_late_init(void)
573 { 624 {
574 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 625 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
575 char safe_string[HDR_NAME_LEN + 1]; 626 char safe_string[HDR_NAME_LEN + 1];
576 struct am335x_baseboard_id header; 627 struct am335x_baseboard_id header;
577 628
578 if (read_eeprom(&header) < 0) 629 if (read_eeprom(&header) < 0)
579 puts("Could not get board ID.\n"); 630 puts("Could not get board ID.\n");
580 631
581 /* Now set variables based on the header. */ 632 /* Now set variables based on the header. */
582 strncpy(safe_string, (char *)header.name, sizeof(header.name)); 633 strncpy(safe_string, (char *)header.name, sizeof(header.name));
583 safe_string[sizeof(header.name)] = 0; 634 safe_string[sizeof(header.name)] = 0;
584 setenv("board_name", safe_string); 635 setenv("board_name", safe_string);
585 636
586 strncpy(safe_string, (char *)header.version, sizeof(header.version)); 637 strncpy(safe_string, (char *)header.version, sizeof(header.version));
587 safe_string[sizeof(header.version)] = 0; 638 safe_string[sizeof(header.version)] = 0;
588 setenv("board_rev", safe_string); 639 setenv("board_rev", safe_string);
589 #endif 640 #endif
590 641
591 return 0; 642 return 0;
592 } 643 }
593 #endif 644 #endif
594 645
595 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ 646 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
596 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) 647 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
597 static void cpsw_control(int enabled) 648 static void cpsw_control(int enabled)
598 { 649 {
599 /* VTP can be added here */ 650 /* VTP can be added here */
600 651
601 return; 652 return;
602 } 653 }
603 654
604 static struct cpsw_slave_data cpsw_slaves[] = { 655 static struct cpsw_slave_data cpsw_slaves[] = {
605 { 656 {
606 .slave_reg_ofs = 0x208, 657 .slave_reg_ofs = 0x208,
607 .sliver_reg_ofs = 0xd80, 658 .sliver_reg_ofs = 0xd80,
608 .phy_addr = 0, 659 .phy_addr = 0,
609 }, 660 },
610 { 661 {
611 .slave_reg_ofs = 0x308, 662 .slave_reg_ofs = 0x308,
612 .sliver_reg_ofs = 0xdc0, 663 .sliver_reg_ofs = 0xdc0,
613 .phy_addr = 1, 664 .phy_addr = 1,
614 }, 665 },
615 }; 666 };
616 667
617 static struct cpsw_platform_data cpsw_data = { 668 static struct cpsw_platform_data cpsw_data = {
618 .mdio_base = CPSW_MDIO_BASE, 669 .mdio_base = CPSW_MDIO_BASE,
619 .cpsw_base = CPSW_BASE, 670 .cpsw_base = CPSW_BASE,
620 .mdio_div = 0xff, 671 .mdio_div = 0xff,
621 .channels = 8, 672 .channels = 8,
622 .cpdma_reg_ofs = 0x800, 673 .cpdma_reg_ofs = 0x800,
623 .slaves = 1, 674 .slaves = 1,
624 .slave_data = cpsw_slaves, 675 .slave_data = cpsw_slaves,
625 .ale_reg_ofs = 0xd00, 676 .ale_reg_ofs = 0xd00,
626 .ale_entries = 1024, 677 .ale_entries = 1024,
627 .host_port_reg_ofs = 0x108, 678 .host_port_reg_ofs = 0x108,
628 .hw_stats_reg_ofs = 0x900, 679 .hw_stats_reg_ofs = 0x900,
629 .bd_ram_ofs = 0x2000, 680 .bd_ram_ofs = 0x2000,
630 .mac_control = (1 << 5), 681 .mac_control = (1 << 5),
631 .control = cpsw_control, 682 .control = cpsw_control,
632 .host_port_num = 0, 683 .host_port_num = 0,
633 .version = CPSW_CTRL_VERSION_2, 684 .version = CPSW_CTRL_VERSION_2,
634 }; 685 };
635 #endif 686 #endif
636 687
637 /* 688 /*
638 * This function will: 689 * This function will:
639 * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr 690 * Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
640 * in the environment 691 * in the environment
641 * Perform fixups to the PHY present on certain boards. We only need this 692 * Perform fixups to the PHY present on certain boards. We only need this
642 * function in: 693 * function in:
643 * - SPL with either CPSW or USB ethernet support 694 * - SPL with either CPSW or USB ethernet support
644 * - Full U-Boot, with either CPSW or USB ethernet 695 * - Full U-Boot, with either CPSW or USB ethernet
645 * Build in only these cases to avoid warnings about unused variables 696 * Build in only these cases to avoid warnings about unused variables
646 * when we build an SPL that has neither option but full U-Boot will. 697 * when we build an SPL that has neither option but full U-Boot will.
647 */ 698 */
648 #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \ 699 #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \
649 && defined(CONFIG_SPL_BUILD)) || \ 700 && defined(CONFIG_SPL_BUILD)) || \
650 ((defined(CONFIG_DRIVER_TI_CPSW) || \ 701 ((defined(CONFIG_DRIVER_TI_CPSW) || \
651 defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \ 702 defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
652 !defined(CONFIG_SPL_BUILD)) 703 !defined(CONFIG_SPL_BUILD))
653 int board_eth_init(bd_t *bis) 704 int board_eth_init(bd_t *bis)
654 { 705 {
655 int rv, n = 0; 706 int rv, n = 0;
656 uint8_t mac_addr[6]; 707 uint8_t mac_addr[6];
657 uint32_t mac_hi, mac_lo; 708 uint32_t mac_hi, mac_lo;
658 __maybe_unused struct am335x_baseboard_id header; 709 __maybe_unused struct am335x_baseboard_id header;
659 710
660 /* try reading mac address from efuse */ 711 /* try reading mac address from efuse */
661 mac_lo = readl(&cdev->macid0l); 712 mac_lo = readl(&cdev->macid0l);
662 mac_hi = readl(&cdev->macid0h); 713 mac_hi = readl(&cdev->macid0h);
663 mac_addr[0] = mac_hi & 0xFF; 714 mac_addr[0] = mac_hi & 0xFF;
664 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 715 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
665 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 716 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
666 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 717 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
667 mac_addr[4] = mac_lo & 0xFF; 718 mac_addr[4] = mac_lo & 0xFF;
668 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 719 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
669 720
670 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ 721 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
671 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) 722 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
672 if (!getenv("ethaddr")) { 723 if (!getenv("ethaddr")) {
673 printf("<ethaddr> not set. Validating first E-fuse MAC\n"); 724 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
674 725
675 if (is_valid_ether_addr(mac_addr)) 726 if (is_valid_ether_addr(mac_addr))
676 eth_setenv_enetaddr("ethaddr", mac_addr); 727 eth_setenv_enetaddr("ethaddr", mac_addr);
677 } 728 }
678 729
679 #ifdef CONFIG_DRIVER_TI_CPSW 730 #ifdef CONFIG_DRIVER_TI_CPSW
680 731
681 mac_lo = readl(&cdev->macid1l); 732 mac_lo = readl(&cdev->macid1l);
682 mac_hi = readl(&cdev->macid1h); 733 mac_hi = readl(&cdev->macid1h);
683 mac_addr[0] = mac_hi & 0xFF; 734 mac_addr[0] = mac_hi & 0xFF;
684 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 735 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
685 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 736 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
686 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 737 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
687 mac_addr[4] = mac_lo & 0xFF; 738 mac_addr[4] = mac_lo & 0xFF;
688 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 739 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
689 740
690 if (!getenv("eth1addr")) { 741 if (!getenv("eth1addr")) {
691 if (is_valid_ether_addr(mac_addr)) 742 if (is_valid_ether_addr(mac_addr))
692 eth_setenv_enetaddr("eth1addr", mac_addr); 743 eth_setenv_enetaddr("eth1addr", mac_addr);
693 } 744 }
694 745
695 if (read_eeprom(&header) < 0) 746 if (read_eeprom(&header) < 0)
696 puts("Could not get board ID.\n"); 747 puts("Could not get board ID.\n");
697 748
698 if (board_is_bone(&header) || board_is_bone_lt(&header) || 749 if (board_is_bone(&header) || board_is_bone_lt(&header) ||
699 board_is_idk(&header)) { 750 board_is_idk(&header)) {
700 writel(MII_MODE_ENABLE, &cdev->miisel); 751 writel(MII_MODE_ENABLE, &cdev->miisel);
701 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = 752 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
702 PHY_INTERFACE_MODE_MII; 753 PHY_INTERFACE_MODE_MII;
703 } else if (board_is_smarc_t335x(&header) || board_is_smarc_t335x_1g(&header)) { 754 } else if (board_is_smarc_t335x(&header) || board_is_smarc_t335x_80(&header) || board_is_smarc_t335x_1g(&header)) {
704 writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel); 755 writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
705 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = 756 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
706 PHY_INTERFACE_MODE_RMII; 757 PHY_INTERFACE_MODE_RMII;
707 } else { 758 } else {
708 writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel); 759 writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
709 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = 760 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
710 PHY_INTERFACE_MODE_RGMII; 761 PHY_INTERFACE_MODE_RGMII;
711 } 762 }
712 763
713 rv = cpsw_register(&cpsw_data); 764 rv = cpsw_register(&cpsw_data);
714 if (rv < 0) 765 if (rv < 0)
715 printf("Error %d registering CPSW switch\n", rv); 766 printf("Error %d registering CPSW switch\n", rv);
716 else 767 else
717 n += rv; 768 n += rv;
718 #endif 769 #endif
719 770
720 /* 771 /*
721 * 772 *
722 * CPSW RGMII Internal Delay Mode is not supported in all PVT 773 * CPSW RGMII Internal Delay Mode is not supported in all PVT
723 * operating points. So we must set the TX clock delay feature 774 * operating points. So we must set the TX clock delay feature
724 * in the AR8051 PHY. Since we only support a single ethernet 775 * in the AR8051 PHY. Since we only support a single ethernet
725 * device in U-Boot, we only do this for the first instance. 776 * device in U-Boot, we only do this for the first instance.
726 */ 777 */
727 #define AR8051_PHY_DEBUG_ADDR_REG 0x1d 778 #define AR8051_PHY_DEBUG_ADDR_REG 0x1d
728 #define AR8051_PHY_DEBUG_DATA_REG 0x1e 779 #define AR8051_PHY_DEBUG_DATA_REG 0x1e
729 #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5 780 #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
730 #define AR8051_RGMII_TX_CLK_DLY 0x100 781 #define AR8051_RGMII_TX_CLK_DLY 0x100
731 782
732 if (board_is_evm_sk(&header) || board_is_gp_evm(&header)) { 783 if (board_is_evm_sk(&header) || board_is_gp_evm(&header)) {
733 const char *devname; 784 const char *devname;
734 devname = miiphy_get_current_dev(); 785 devname = miiphy_get_current_dev();
735 786
736 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG, 787 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
737 AR8051_DEBUG_RGMII_CLK_DLY_REG); 788 AR8051_DEBUG_RGMII_CLK_DLY_REG);
738 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG, 789 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
739 AR8051_RGMII_TX_CLK_DLY); 790 AR8051_RGMII_TX_CLK_DLY);
740 } 791 }
741 #endif 792 #endif
742 #if defined(CONFIG_USB_ETHER) && \ 793 #if defined(CONFIG_USB_ETHER) && \
743 (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT)) 794 (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
744 if (is_valid_ether_addr(mac_addr)) 795 if (is_valid_ether_addr(mac_addr))
745 eth_setenv_enetaddr("usbnet_devaddr", mac_addr); 796 eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
746 797
747 rv = usb_eth_initialize(bis); 798 rv = usb_eth_initialize(bis);
748 if (rv < 0) 799 if (rv < 0)
749 printf("Error %d registering USB_ETHER\n", rv); 800 printf("Error %d registering USB_ETHER\n", rv);
750 else 801 else
751 n += rv; 802 n += rv;
752 #endif 803 #endif
753 return n; 804 return n;
754 } 805 }
755 #endif 806 #endif
756 807
board/embedian/smarct335x/board.h
Diff comments   View file @ 4bac48b
1 /* 1 /*
2 * board.h 2 * board.h
3 * 3 *
4 * TI AM335x boards information header 4 * TI AM335x boards information header
5 * 5 *
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
7 * 7 *
8 * SPDX-License-Identifier: GPL-2.0+ 8 * SPDX-License-Identifier: GPL-2.0+
9 */ 9 */
10 10
11 #ifndef _BOARD_H_ 11 #ifndef _BOARD_H_
12 #define _BOARD_H_ 12 #define _BOARD_H_
13 13
14 /* 14 /*
15 * TI AM335x parts define a system EEPROM that defines certain sub-fields. 15 * TI AM335x parts define a system EEPROM that defines certain sub-fields.
16 * We use these fields to in turn see what board we are on, and what 16 * We use these fields to in turn see what board we are on, and what
17 * that might require us to set or not set. 17 * that might require us to set or not set.
18 */ 18 */
19 #define HDR_NO_OF_MAC_ADDR 3 19 #define HDR_NO_OF_MAC_ADDR 3
20 #define HDR_ETH_ALEN 6 20 #define HDR_ETH_ALEN 6
21 #define HDR_NAME_LEN 8 21 #define HDR_NAME_LEN 8
22 22
23 struct am335x_baseboard_id { 23 struct am335x_baseboard_id {
24 unsigned int magic; 24 unsigned int magic;
25 char name[HDR_NAME_LEN]; 25 char name[HDR_NAME_LEN];
26 char version[4]; 26 char version[4];
27 char serial[12]; 27 char serial[12];
28 char config[32]; 28 char config[32];
29 char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN]; 29 char mac_addr[HDR_NO_OF_MAC_ADDR][HDR_ETH_ALEN];
30 }; 30 };
31 31
32 static inline int board_is_bone(struct am335x_baseboard_id *header) 32 static inline int board_is_bone(struct am335x_baseboard_id *header)
33 { 33 {
34 return !strncmp(header->name, "A335BONE", HDR_NAME_LEN); 34 return !strncmp(header->name, "A335BONE", HDR_NAME_LEN);
35 } 35 }
36 36
37 static inline int board_is_bone_lt(struct am335x_baseboard_id *header) 37 static inline int board_is_bone_lt(struct am335x_baseboard_id *header)
38 { 38 {
39 return !strncmp(header->name, "A335BNLT", HDR_NAME_LEN); 39 return !strncmp(header->name, "A335BNLT", HDR_NAME_LEN);
40 } 40 }
41 41
42 static inline int board_is_smarc_t335x(struct am335x_baseboard_id *header) 42 static inline int board_is_smarc_t335x(struct am335x_baseboard_id *header)
43 { 43 {
44 return !strncmp(header->name, "SMARCT33", HDR_NAME_LEN); 44 return !strncmp(header->name, "SMARCT33", HDR_NAME_LEN);
45 } 45 }
46 46
47 static inline int board_is_smarc_t335x_80(struct am335x_baseboard_id *header)
48 {
49 return !strncmp(header->name, "SMARCT80", HDR_NAME_LEN);
50 }
51
47 static inline int board_is_smarc_t335x_1g(struct am335x_baseboard_id *header) 52 static inline int board_is_smarc_t335x_1g(struct am335x_baseboard_id *header)
48 { 53 {
49 return !strncmp(header->name, "SMARCT1G", HDR_NAME_LEN); 54 return !strncmp(header->name, "SMARCT1G", HDR_NAME_LEN);
50 } 55 }
51 56
52 static inline int board_is_evm_sk(struct am335x_baseboard_id *header) 57 static inline int board_is_evm_sk(struct am335x_baseboard_id *header)
53 { 58 {
54 return !strncmp("A335X_SK", header->name, HDR_NAME_LEN); 59 return !strncmp("A335X_SK", header->name, HDR_NAME_LEN);
55 } 60 }
56 61
57 static inline int board_is_idk(struct am335x_baseboard_id *header) 62 static inline int board_is_idk(struct am335x_baseboard_id *header)
58 { 63 {
59 return !strncmp(header->config, "SKU#02", 6); 64 return !strncmp(header->config, "SKU#02", 6);
60 } 65 }
61 66
62 static inline int board_is_gp_evm(struct am335x_baseboard_id *header) 67 static inline int board_is_gp_evm(struct am335x_baseboard_id *header)
63 { 68 {
64 return !strncmp("A33515BB", header->name, HDR_NAME_LEN); 69 return !strncmp("A33515BB", header->name, HDR_NAME_LEN);
65 } 70 }
66 71
67 static inline int board_is_evm_15_or_later(struct am335x_baseboard_id *header) 72 static inline int board_is_evm_15_or_later(struct am335x_baseboard_id *header)
68 { 73 {
69 return (board_is_gp_evm(header) && 74 return (board_is_gp_evm(header) &&
70 strncmp("1.5", header->version, 3) <= 0); 75 strncmp("1.5", header->version, 3) <= 0);
71 } 76 }
72 77
73 /* 78 /*
74 * We have three pin mux functions that must exist. We must be able to enable 79 * We have three pin mux functions that must exist. We must be able to enable
75 * uart0, for initial output and i2c0 to read the main EEPROM. We then have a 80 * uart0, for initial output and i2c0 to read the main EEPROM. We then have a
76 * main pinmux function that can be overridden to enable all other pinmux that 81 * main pinmux function that can be overridden to enable all other pinmux that
77 * is required on the board. 82 * is required on the board.
78 */ 83 */
79 void enable_uart0_pin_mux(void); 84 void enable_uart0_pin_mux(void);
80 void enable_uart1_pin_mux(void); 85 void enable_uart1_pin_mux(void);
81 void enable_uart2_pin_mux(void); 86 void enable_uart2_pin_mux(void);
82 void enable_uart3_pin_mux(void); 87 void enable_uart3_pin_mux(void);
83 void enable_uart4_pin_mux(void); 88 void enable_uart4_pin_mux(void);
84 void enable_uart5_pin_mux(void); 89 void enable_uart5_pin_mux(void);
85 void enable_i2c0_pin_mux(void); 90 void enable_i2c0_pin_mux(void);
86 void enable_board_pin_mux(struct am335x_baseboard_id *header); 91 void enable_board_pin_mux(struct am335x_baseboard_id *header);
87 #endif 92 #endif
88 93
board/embedian/smarct335x/mux.c
Diff comments   View file @ 4bac48b
1 /* 1 /*
2 * mux.c 2 * mux.c
3 * 3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ 4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
5 * 5 *
6 * This program is free software; you can redistribute it and/or 6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as 7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2. 8 * published by the Free Software Foundation version 2.
9 * 9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty 11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 */ 14 */
15 15
16 #include <common.h> 16 #include <common.h>
17 #include <asm/arch/sys_proto.h> 17 #include <asm/arch/sys_proto.h>
18 #include <asm/arch/hardware.h> 18 #include <asm/arch/hardware.h>
19 #include <asm/arch/mux.h> 19 #include <asm/arch/mux.h>
20 #include <asm/io.h> 20 #include <asm/io.h>
21 #include <i2c.h> 21 #include <i2c.h>
22 #include "board.h" 22 #include "board.h"
23 23
24 static struct module_pin_mux uart0_pin_mux[] = { 24 static struct module_pin_mux uart0_pin_mux[] = {
25 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ 25 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
26 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ 26 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
27 {-1}, 27 {-1},
28 }; 28 };
29 29
30 static struct module_pin_mux uart1_pin_mux[] = { 30 static struct module_pin_mux uart1_pin_mux[] = {
31 {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */ 31 {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
32 {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */ 32 {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
33 {-1}, 33 {-1},
34 }; 34 };
35 35
36 static struct module_pin_mux uart2_pin_mux[] = { 36 static struct module_pin_mux uart2_pin_mux[] = {
37 {OFFSET(mii1_txclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */ 37 {OFFSET(mii1_txclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
38 {OFFSET(mii1_rxclk), (MODE(1) | PULLUDEN)}, /* UART2_TXD */ 38 {OFFSET(mii1_rxclk), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
39 {-1}, 39 {-1},
40 }; 40 };
41 41
42 static struct module_pin_mux uart3_pin_mux[] = { 42 static struct module_pin_mux uart3_pin_mux[] = {
43 {OFFSET(mii1_rxd3), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */ 43 {OFFSET(mii1_rxd3), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
44 {OFFSET(mii1_rxd2), (MODE(1) | PULLUDEN)}, /* UART3_TXD */ 44 {OFFSET(mii1_rxd2), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
45 {-1}, 45 {-1},
46 }; 46 };
47 47
48 static struct module_pin_mux uart4_pin_mux[] = { 48 static struct module_pin_mux uart4_pin_mux[] = {
49 {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */ 49 {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
50 {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */ 50 {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */
51 {-1}, 51 {-1},
52 }; 52 };
53 53
54 static struct module_pin_mux uart5_pin_mux[] = { 54 static struct module_pin_mux uart5_pin_mux[] = {
55 {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */ 55 {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */
56 {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */ 56 {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */
57 {-1}, 57 {-1},
58 }; 58 };
59 59
60 static struct module_pin_mux mmc0_pin_mux[] = { 60 static struct module_pin_mux mmc0_pin_mux[] = {
61 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ 61 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
62 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ 62 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
63 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ 63 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
64 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ 64 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
65 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ 65 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
66 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ 66 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
67 {OFFSET(gpmc_a2), (MODE(7) | RXACTIVE)}, /* MMC0_WP */ 67 {OFFSET(gpmc_a2), (MODE(7) | RXACTIVE)}, /* MMC0_WP */
68 {OFFSET(gpmc_a1), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ 68 {OFFSET(gpmc_a1), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
69 {-1}, 69 {-1},
70 }; 70 };
71 71
72 static struct module_pin_mux mmc0_no_cd_pin_mux[] = { 72 static struct module_pin_mux mmc0_no_cd_pin_mux[] = {
73 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ 73 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
74 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ 74 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
75 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ 75 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
76 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ 76 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
77 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ 77 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
78 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ 78 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
79 {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */ 79 {OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
80 {-1}, 80 {-1},
81 }; 81 };
82 82
83 static struct module_pin_mux mmc0_pin_mux_sk_evm[] = { 83 static struct module_pin_mux mmc0_pin_mux_sk_evm[] = {
84 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ 84 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
85 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ 85 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
86 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ 86 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
87 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ 87 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
88 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ 88 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
89 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ 89 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
90 {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ 90 {OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
91 {-1}, 91 {-1},
92 }; 92 };
93 93
94 static struct module_pin_mux mmc1_pin_mux[] = { 94 static struct module_pin_mux mmc1_pin_mux[] = {
95 {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */ 95 {OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
96 {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */ 96 {OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
97 {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */ 97 {OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
98 {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */ 98 {OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
99 {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */ 99 {OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
100 {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */ 100 {OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
101 {-1}, 101 {-1},
102 }; 102 };
103 103
104 static struct module_pin_mux i2c0_pin_mux[] = { 104 static struct module_pin_mux i2c0_pin_mux[] = {
105 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | 105 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
106 PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ 106 PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
107 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | 107 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
108 PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ 108 PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
109 {-1}, 109 {-1},
110 }; 110 };
111 111
112 static struct module_pin_mux i2c1_pin_mux[] = { 112 static struct module_pin_mux i2c1_pin_mux[] = {
113 {OFFSET(uart1_rxd), (MODE(3) | RXACTIVE | 113 {OFFSET(uart1_rxd), (MODE(3) | RXACTIVE |
114 PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ 114 PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
115 {OFFSET(uart1_txd), (MODE(3) | RXACTIVE | 115 {OFFSET(uart1_txd), (MODE(3) | RXACTIVE |
116 PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ 116 PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
117 {-1}, 117 {-1},
118 }; 118 };
119 119
120 static struct module_pin_mux spi0_pin_mux[] = { 120 static struct module_pin_mux spi0_pin_mux[] = {
121 {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_SCLK */ 121 {OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_SCLK */
122 {OFFSET(spi0_d0), (MODE(0) | RXACTIVE | 122 {OFFSET(spi0_d0), (MODE(0) | RXACTIVE |
123 PULLUDEN | PULLUP_EN)}, /* SPI0_D0 */ 123 PULLUDEN | PULLUP_EN)}, /* SPI0_D0 */
124 {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_D1 */ 124 {OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN)}, /* SPI0_D1 */
125 {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | 125 {OFFSET(spi0_cs0), (MODE(0) | RXACTIVE |
126 PULLUDEN | PULLUP_EN)}, /* SPI0_CS0 */ 126 PULLUDEN | PULLUP_EN)}, /* SPI0_CS0 */
127 {-1}, 127 {-1},
128 }; 128 };
129 129
130 static struct module_pin_mux gpio0_7_pin_mux[] = { 130 static struct module_pin_mux gpio0_7_pin_mux[] = {
131 {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)}, /* GPIO0_7 */ 131 {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)}, /* GPIO0_7 */
132 {-1}, 132 {-1},
133 }; 133 };
134 134
135 static struct module_pin_mux smarc_gpio_pin_mux[] = { 135 static struct module_pin_mux smarc_gpio_pin_mux[] = {
136 {OFFSET(gpmc_a7), (MODE(7) | PULLUDEN | PULLUP_EN)}, /* GPIO1_23, LCD VDD_EN */ 136 {OFFSET(gpmc_a7), (MODE(7) | PULLUDEN | PULLUP_EN)}, /* GPIO1_23, LCD VDD_EN */
137 {OFFSET(gpmc_a6), (MODE(7) | PULLUDEN | PULLUP_EN)}, /* GPIO1_22, LCD Backlight Enable */ 137 {OFFSET(gpmc_a6), (MODE(7) | PULLUDEN | PULLUP_EN)}, /* GPIO1_22, LCD Backlight Enable */
138 {OFFSET(gpmc_a3), (MODE(7) | PULLUDEN | PULLUP_EN)}, /* GPIO1_19, MMC0_PWREN Enable*/ 138 {OFFSET(gpmc_a3), (MODE(7) | PULLUDEN | PULLUP_EN)}, /* GPIO1_19, MMC0_PWREN Enable*/
139 {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)}, /* GPIO0_7, LCD_BKLT_PWM */ 139 {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)}, /* GPIO0_7, LCD_BKLT_PWM */
140 /* By SMARC Spec. GPIO0-5 is recommended for use as outputs and GPIO6-11 is recommended for use of inputs */ 140 /* By SMARC Spec. GPIO0-5 is recommended for use as outputs and GPIO6-11 is recommended for use of inputs */
141 {OFFSET(mii1_rxdv), MODE(7)}, /* GPIO3_4, GPIO0 */ 141 {OFFSET(mii1_rxdv), MODE(7)}, /* GPIO3_4, GPIO0 */
142 {OFFSET(gpmc_be0n_cle), MODE(7)}, /* GPIO2_5, GPIO1 */ 142 {OFFSET(gpmc_be0n_cle), MODE(7)}, /* GPIO2_5, GPIO1 */
143 {OFFSET(gpmc_a9), MODE(7)}, /* GPIO1_25, GPIO2 */ 143 {OFFSET(gpmc_a9), MODE(7)}, /* GPIO1_25, GPIO2 */
144 {OFFSET(gpmc_a8), MODE(7)}, /* GPIO1_24, GPIO3 */ 144 {OFFSET(gpmc_a8), MODE(7)}, /* GPIO1_24, GPIO3 */
145 {OFFSET(gpmc_wen), MODE(7)}, /* GPIO2_4, GPIO4 */ 145 {OFFSET(gpmc_wen), MODE(7)}, /* GPIO2_4, GPIO4 */
146 {OFFSET(gpmc_oen_ren), MODE(7)}, /* GPIO2_3, GPIO5 */ 146 {OFFSET(gpmc_oen_ren), MODE(7)}, /* GPIO2_3, GPIO5 */
147 {OFFSET(gpmc_be1n), MODE(7) | RXACTIVE}, /* GPIO1_28, GPIO6 */ 147 {OFFSET(gpmc_be1n), MODE(7) | RXACTIVE}, /* GPIO1_28, GPIO6 */
148 {OFFSET(gpmc_csn0), MODE(7) | RXACTIVE}, /* GPIO1_29, GPIO7 */ 148 {OFFSET(gpmc_csn0), MODE(7) | RXACTIVE}, /* GPIO1_29, GPIO7 */
149 {OFFSET(gpmc_csn3), MODE(7) | RXACTIVE}, /* GPIO2_0, GPIO8 */ 149 {OFFSET(gpmc_csn3), MODE(7) | RXACTIVE}, /* GPIO2_0, GPIO8 */
150 {OFFSET(gpmc_clk), MODE(7) | RXACTIVE}, /* GPIO2_1, GPIO9 */ 150 {OFFSET(gpmc_clk), MODE(7) | RXACTIVE}, /* GPIO2_1, GPIO9 */
151 {OFFSET(emu0), MODE(7)}, /* GPIO3_7, GPIO10 for Buzzer */ 151 {OFFSET(emu0), MODE(7)}, /* GPIO3_7, GPIO10 for Buzzer */
152 {OFFSET(emu1), MODE(7) | RXACTIVE}, /* GPIO3_8, GPIO11 */ 152 {OFFSET(emu1), MODE(7) | RXACTIVE}, /* GPIO3_8, GPIO11 */
153 /* i2c1 (pin37 and pin38 on P1 connector) in SBC-SMART-MEN is set as GPIOs*/ 153 /* i2c1 (pin37 and pin38 on P1 connector) in SBC-SMART-MEN is set as GPIOs*/
154 {OFFSET(uart1_txd), MODE(7)}, /* uart1_txd.gpio0_15 */ 154 {OFFSET(uart1_txd), MODE(7)}, /* uart1_txd.gpio0_15 */
155 {OFFSET(uart1_rxd), MODE(7)}, /* uart1_rxd.gpio0_14 */ 155 {OFFSET(uart1_rxd), MODE(7)}, /* uart1_rxd.gpio0_14 */
156 {-1}, 156 {-1},
157 }; 157 };
158 158
159 /* Module pin mux for LCDC */ 159 /* Module pin mux for LCDC */
160 static struct module_pin_mux lcdc_pin_mux[] = { 160 static struct module_pin_mux lcdc_pin_mux[] = {
161 {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /*lcd_data0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT*/ 161 {OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /*lcd_data0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT*/
162 {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, 162 {OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)},
163 {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, 163 {OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)},
164 {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, 164 {OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)},
165 {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, 165 {OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)},
166 {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, 166 {OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)},
167 {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, 167 {OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)},
168 {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, 168 {OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)},
169 {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, 169 {OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)},
170 {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, 170 {OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)},
171 {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, 171 {OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)},
172 {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, 172 {OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)},
173 {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, 173 {OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)},
174 {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, 174 {OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)},
175 {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, 175 {OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)},
176 {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, 176 {OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)},
177 // new signals 177 // new signals
178 {OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)}, 178 {OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)},
179 {OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)}, 179 {OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)},
180 {OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)}, 180 {OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)},
181 {OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)}, 181 {OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)},
182 {OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)}, 182 {OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)},
183 {OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)}, 183 {OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)},
184 {OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)}, 184 {OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)},
185 {OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)}, 185 {OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)},
186 // 186 //
187 {OFFSET(lcd_vsync), (MODE(0) | PULLUDEN)}, 187 {OFFSET(lcd_vsync), (MODE(0) | PULLUDEN)},
188 {OFFSET(lcd_hsync), (MODE(0) | PULLUDEN)}, 188 {OFFSET(lcd_hsync), (MODE(0) | PULLUDEN)},
189 {OFFSET(lcd_pclk), (MODE(0) | PULLUDEN)}, 189 {OFFSET(lcd_pclk), (MODE(0) | PULLUDEN)},
190 {OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDEN)}, 190 {OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDEN)},
191 {-1}, 191 {-1},
192 }; 192 };
193 193
194 static struct module_pin_mux rgmii1_pin_mux[] = { 194 static struct module_pin_mux rgmii1_pin_mux[] = {
195 {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */ 195 {OFFSET(mii1_txen), MODE(2)}, /* RGMII1_TCTL */
196 {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */ 196 {OFFSET(mii1_rxdv), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */
197 {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */ 197 {OFFSET(mii1_txd3), MODE(2)}, /* RGMII1_TD3 */
198 {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */ 198 {OFFSET(mii1_txd2), MODE(2)}, /* RGMII1_TD2 */
199 {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */ 199 {OFFSET(mii1_txd1), MODE(2)}, /* RGMII1_TD1 */
200 {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */ 200 {OFFSET(mii1_txd0), MODE(2)}, /* RGMII1_TD0 */
201 {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */ 201 {OFFSET(mii1_txclk), MODE(2)}, /* RGMII1_TCLK */
202 {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */ 202 {OFFSET(mii1_rxclk), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */
203 {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */ 203 {OFFSET(mii1_rxd3), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */
204 {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */ 204 {OFFSET(mii1_rxd2), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */
205 {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */ 205 {OFFSET(mii1_rxd1), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */
206 {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */ 206 {OFFSET(mii1_rxd0), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */
207 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ 207 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
208 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ 208 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
209 {-1}, 209 {-1},
210 }; 210 };
211 211
212 static struct module_pin_mux rmii1_pin_mux[] = { 212 static struct module_pin_mux rmii1_pin_mux[] = {
213 {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS */ 213 {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RMII1_CRS */
214 {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */ 214 {OFFSET(mii1_rxerr), MODE(1) | RXACTIVE}, /* RMII1_RXERR */
215 {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */ 215 {OFFSET(mii1_txen), MODE(1)}, /* RMII1_TXEN */
216 {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */ 216 {OFFSET(mii1_txd1), MODE(1)}, /* RMII1_TXD1 */
217 {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */ 217 {OFFSET(mii1_txd0), MODE(1)}, /* RMII1_TXD0 */
218 {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */ 218 {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RMII1_RXD1 */
219 {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */ 219 {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RMII1_RXD0 */
220 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ 220 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
221 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ 221 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
222 {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */ 222 {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RMII1_REFCLK */
223 {-1}, 223 {-1},
224 }; 224 };
225 225
226 static struct module_pin_mux rmii2_pin_mux[] = { 226 static struct module_pin_mux rmii2_pin_mux[] = {
227 {OFFSET(gpmc_wait0), MODE(3) | RXACTIVE}, /* RMII2_CRS */ 227 {OFFSET(gpmc_wait0), MODE(3) | RXACTIVE}, /* RMII2_CRS */
228 {OFFSET(gpmc_wpn), MODE(3) | RXACTIVE}, /* RMII2_RXERR */ 228 {OFFSET(gpmc_wpn), MODE(3) | RXACTIVE}, /* RMII2_RXERR */
229 {OFFSET(gpmc_a0), MODE(3)}, /* RMII2_TXEN */ 229 {OFFSET(gpmc_a0), MODE(3)}, /* RMII2_TXEN */
230 {OFFSET(gpmc_a4), MODE(3)}, /* RMII2_TXD1 */ 230 {OFFSET(gpmc_a4), MODE(3)}, /* RMII2_TXD1 */
231 {OFFSET(gpmc_a5), MODE(3)}, /* RMII2_TXD0 */ 231 {OFFSET(gpmc_a5), MODE(3)}, /* RMII2_TXD0 */
232 {OFFSET(gpmc_a10), MODE(3) | RXACTIVE}, /* RMII2_RXD1 */ 232 {OFFSET(gpmc_a10), MODE(3) | RXACTIVE}, /* RMII2_RXD1 */
233 {OFFSET(gpmc_a11), MODE(3) | RXACTIVE}, /* RMII2_RXD0 */ 233 {OFFSET(gpmc_a11), MODE(3) | RXACTIVE}, /* RMII2_RXD0 */
234 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ 234 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
235 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ 235 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
236 {OFFSET(mii1_col), MODE(1) | RXACTIVE}, /* RMII2_REFCLK */ 236 {OFFSET(mii1_col), MODE(1) | RXACTIVE}, /* RMII2_REFCLK */
237 {-1}, 237 {-1},
238 }; 238 };
239 239
240 static struct module_pin_mux mii1_pin_mux[] = { 240 static struct module_pin_mux mii1_pin_mux[] = {
241 {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */ 241 {OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
242 {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */ 242 {OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
243 {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */ 243 {OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
244 {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */ 244 {OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
245 {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */ 245 {OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
246 {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */ 246 {OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
247 {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */ 247 {OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
248 {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */ 248 {OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
249 {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */ 249 {OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
250 {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */ 250 {OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
251 {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */ 251 {OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
252 {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */ 252 {OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
253 {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */ 253 {OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
254 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */ 254 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN}, /* MDIO_DATA */
255 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ 255 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
256 {-1}, 256 {-1},
257 }; 257 };
258 258
259 static struct module_pin_mux nand_pin_mux[] = { 259 static struct module_pin_mux nand_pin_mux[] = {
260 {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ 260 {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
261 {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ 261 {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
262 {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ 262 {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
263 {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ 263 {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
264 {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ 264 {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
265 {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ 265 {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
266 {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ 266 {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
267 {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ 267 {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
268 {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ 268 {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
269 {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ 269 {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
270 {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ 270 {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
271 {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ 271 {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
272 {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ 272 {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
273 {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ 273 {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
274 {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ 274 {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
275 {-1}, 275 {-1},
276 }; 276 };
277 277
278 #if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT) 278 #if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT)
279 static struct module_pin_mux bone_norcape_pin_mux[] = { 279 static struct module_pin_mux bone_norcape_pin_mux[] = {
280 {OFFSET(lcd_data0), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A0 */ 280 {OFFSET(lcd_data0), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A0 */
281 {OFFSET(lcd_data1), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A1 */ 281 {OFFSET(lcd_data1), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A1 */
282 {OFFSET(lcd_data2), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A2 */ 282 {OFFSET(lcd_data2), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A2 */
283 {OFFSET(lcd_data3), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A3 */ 283 {OFFSET(lcd_data3), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A3 */
284 {OFFSET(lcd_data4), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A4 */ 284 {OFFSET(lcd_data4), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A4 */
285 {OFFSET(lcd_data5), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A5 */ 285 {OFFSET(lcd_data5), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A5 */
286 {OFFSET(lcd_data6), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A6 */ 286 {OFFSET(lcd_data6), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A6 */
287 {OFFSET(lcd_data7), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A7 */ 287 {OFFSET(lcd_data7), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A7 */
288 {OFFSET(lcd_vsync), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A8 */ 288 {OFFSET(lcd_vsync), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A8 */
289 {OFFSET(lcd_hsync), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A9 */ 289 {OFFSET(lcd_hsync), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A9 */
290 {OFFSET(lcd_pclk), MODE(1)| PULLUDEN | RXACTIVE}, /* NOR_A10 */ 290 {OFFSET(lcd_pclk), MODE(1)| PULLUDEN | RXACTIVE}, /* NOR_A10 */
291 {OFFSET(lcd_ac_bias_en), MODE(1)| PULLUDEN | RXACTIVE}, /* NOR_A11 */ 291 {OFFSET(lcd_ac_bias_en), MODE(1)| PULLUDEN | RXACTIVE}, /* NOR_A11 */
292 {OFFSET(lcd_data8), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A12 */ 292 {OFFSET(lcd_data8), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A12 */
293 {OFFSET(lcd_data9), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A13 */ 293 {OFFSET(lcd_data9), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A13 */
294 {OFFSET(lcd_data10), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A14 */ 294 {OFFSET(lcd_data10), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A14 */
295 {OFFSET(lcd_data11), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A15 */ 295 {OFFSET(lcd_data11), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A15 */
296 {OFFSET(lcd_data12), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A16 */ 296 {OFFSET(lcd_data12), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A16 */
297 {OFFSET(lcd_data13), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A17 */ 297 {OFFSET(lcd_data13), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A17 */
298 {OFFSET(lcd_data14), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A18 */ 298 {OFFSET(lcd_data14), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A18 */
299 {OFFSET(lcd_data15), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A19 */ 299 {OFFSET(lcd_data15), MODE(1) | PULLUDEN | RXACTIVE}, /* NOR_A19 */
300 {OFFSET(gpmc_ad0), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD0 */ 300 {OFFSET(gpmc_ad0), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD0 */
301 {OFFSET(gpmc_ad1), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD1 */ 301 {OFFSET(gpmc_ad1), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD1 */
302 {OFFSET(gpmc_ad2), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD2 */ 302 {OFFSET(gpmc_ad2), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD2 */
303 {OFFSET(gpmc_ad3), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD3 */ 303 {OFFSET(gpmc_ad3), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD3 */
304 {OFFSET(gpmc_ad4), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD4 */ 304 {OFFSET(gpmc_ad4), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD4 */
305 {OFFSET(gpmc_ad5), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD5 */ 305 {OFFSET(gpmc_ad5), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD5 */
306 {OFFSET(gpmc_ad6), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD6 */ 306 {OFFSET(gpmc_ad6), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD6 */
307 {OFFSET(gpmc_ad7), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD7 */ 307 {OFFSET(gpmc_ad7), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD7 */
308 {OFFSET(gpmc_ad8), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD8 */ 308 {OFFSET(gpmc_ad8), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD8 */
309 {OFFSET(gpmc_ad9), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD9 */ 309 {OFFSET(gpmc_ad9), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD9 */
310 {OFFSET(gpmc_ad10), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD10 */ 310 {OFFSET(gpmc_ad10), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD10 */
311 {OFFSET(gpmc_ad11), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD11 */ 311 {OFFSET(gpmc_ad11), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD11 */
312 {OFFSET(gpmc_ad12), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD12 */ 312 {OFFSET(gpmc_ad12), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD12 */
313 {OFFSET(gpmc_ad13), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD13 */ 313 {OFFSET(gpmc_ad13), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD13 */
314 {OFFSET(gpmc_ad14), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD14 */ 314 {OFFSET(gpmc_ad14), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD14 */
315 {OFFSET(gpmc_ad15), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD15 */ 315 {OFFSET(gpmc_ad15), MODE(0) | PULLUDEN | RXACTIVE}, /* NOR_AD15 */
316 316
317 {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN) | RXACTIVE}, /* NOR_CE */ 317 {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN) | RXACTIVE}, /* NOR_CE */
318 {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN) | RXACTIVE}, /* NOR_ADVN_ALE */ 318 {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN) | RXACTIVE}, /* NOR_ADVN_ALE */
319 {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN | RXACTIVE)},/* NOR_OE */ 319 {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN | RXACTIVE)},/* NOR_OE */
320 {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN | RXACTIVE)},/* NOR_BE0N_CLE */ 320 {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN | RXACTIVE)},/* NOR_BE0N_CLE */
321 {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN | RXACTIVE)}, /* NOR_WEN */ 321 {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN | RXACTIVE)}, /* NOR_WEN */
322 {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUDEN)}, /* NOR WAIT */ 322 {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUDEN)}, /* NOR WAIT */
323 {-1}, 323 {-1},
324 }; 324 };
325 #endif 325 #endif
326 326
327 #if defined(CONFIG_NOR_BOOT) 327 #if defined(CONFIG_NOR_BOOT)
328 static struct module_pin_mux norboot_pin_mux[] = { 328 static struct module_pin_mux norboot_pin_mux[] = {
329 {OFFSET(lcd_data1), MODE(1) | PULLUDDIS}, 329 {OFFSET(lcd_data1), MODE(1) | PULLUDDIS},
330 {OFFSET(lcd_data2), MODE(1) | PULLUDDIS}, 330 {OFFSET(lcd_data2), MODE(1) | PULLUDDIS},
331 {OFFSET(lcd_data3), MODE(1) | PULLUDDIS}, 331 {OFFSET(lcd_data3), MODE(1) | PULLUDDIS},
332 {OFFSET(lcd_data4), MODE(1) | PULLUDDIS}, 332 {OFFSET(lcd_data4), MODE(1) | PULLUDDIS},
333 {OFFSET(lcd_data5), MODE(1) | PULLUDDIS}, 333 {OFFSET(lcd_data5), MODE(1) | PULLUDDIS},
334 {OFFSET(lcd_data6), MODE(1) | PULLUDDIS}, 334 {OFFSET(lcd_data6), MODE(1) | PULLUDDIS},
335 {OFFSET(lcd_data7), MODE(1) | PULLUDDIS}, 335 {OFFSET(lcd_data7), MODE(1) | PULLUDDIS},
336 {OFFSET(lcd_data8), MODE(1) | PULLUDDIS}, 336 {OFFSET(lcd_data8), MODE(1) | PULLUDDIS},
337 {OFFSET(lcd_data9), MODE(1) | PULLUDDIS}, 337 {OFFSET(lcd_data9), MODE(1) | PULLUDDIS},
338 {-1}, 338 {-1},
339 }; 339 };
340 340
341 void enable_norboot_pin_mux(void) 341 void enable_norboot_pin_mux(void)
342 { 342 {
343 configure_module_pin_mux(norboot_pin_mux); 343 configure_module_pin_mux(norboot_pin_mux);
344 } 344 }
345 #endif 345 #endif
346 346
347 void enable_uart0_pin_mux(void) 347 void enable_uart0_pin_mux(void)
348 { 348 {
349 configure_module_pin_mux(uart0_pin_mux); 349 configure_module_pin_mux(uart0_pin_mux);
350 } 350 }
351 351
352 void enable_uart1_pin_mux(void) 352 void enable_uart1_pin_mux(void)
353 { 353 {
354 configure_module_pin_mux(uart1_pin_mux); 354 configure_module_pin_mux(uart1_pin_mux);
355 } 355 }
356 356
357 void enable_uart2_pin_mux(void) 357 void enable_uart2_pin_mux(void)
358 { 358 {
359 configure_module_pin_mux(uart2_pin_mux); 359 configure_module_pin_mux(uart2_pin_mux);
360 } 360 }
361 361
362 void enable_uart3_pin_mux(void) 362 void enable_uart3_pin_mux(void)
363 { 363 {
364 configure_module_pin_mux(uart3_pin_mux); 364 configure_module_pin_mux(uart3_pin_mux);
365 } 365 }
366 366
367 void enable_uart4_pin_mux(void) 367 void enable_uart4_pin_mux(void)
368 { 368 {
369 configure_module_pin_mux(uart4_pin_mux); 369 configure_module_pin_mux(uart4_pin_mux);
370 } 370 }
371 371
372 void enable_uart5_pin_mux(void) 372 void enable_uart5_pin_mux(void)
373 { 373 {
374 configure_module_pin_mux(uart5_pin_mux); 374 configure_module_pin_mux(uart5_pin_mux);
375 } 375 }
376 376
377 void enable_i2c0_pin_mux(void) 377 void enable_i2c0_pin_mux(void)
378 { 378 {
379 configure_module_pin_mux(i2c0_pin_mux); 379 configure_module_pin_mux(i2c0_pin_mux);
380 } 380 }
381 381
382 /* 382 /*
383 * The AM335x GP EVM, if daughter card(s) are connected, can have 8 383 * The AM335x GP EVM, if daughter card(s) are connected, can have 8
384 * different profiles. These profiles determine what peripherals are 384 * different profiles. These profiles determine what peripherals are
385 * valid and need pinmux to be configured. 385 * valid and need pinmux to be configured.
386 */ 386 */
387 #define PROFILE_NONE 0x0 387 #define PROFILE_NONE 0x0
388 #define PROFILE_0 (1 << 0) 388 #define PROFILE_0 (1 << 0)
389 #define PROFILE_1 (1 << 1) 389 #define PROFILE_1 (1 << 1)
390 #define PROFILE_2 (1 << 2) 390 #define PROFILE_2 (1 << 2)
391 #define PROFILE_3 (1 << 3) 391 #define PROFILE_3 (1 << 3)
392 #define PROFILE_4 (1 << 4) 392 #define PROFILE_4 (1 << 4)
393 #define PROFILE_5 (1 << 5) 393 #define PROFILE_5 (1 << 5)
394 #define PROFILE_6 (1 << 6) 394 #define PROFILE_6 (1 << 6)
395 #define PROFILE_7 (1 << 7) 395 #define PROFILE_7 (1 << 7)
396 #define PROFILE_MASK 0x7 396 #define PROFILE_MASK 0x7
397 #define PROFILE_ALL 0xFF 397 #define PROFILE_ALL 0xFF
398 398
399 /* CPLD registers */ 399 /* CPLD registers */
400 #define I2C_CPLD_ADDR 0x35 400 #define I2C_CPLD_ADDR 0x35
401 #define CFG_REG 0x10 401 #define CFG_REG 0x10
402 402
403 static unsigned short detect_daughter_board_profile(void) 403 static unsigned short detect_daughter_board_profile(void)
404 { 404 {
405 unsigned short val; 405 unsigned short val;
406 406
407 if (i2c_probe(I2C_CPLD_ADDR)) 407 if (i2c_probe(I2C_CPLD_ADDR))
408 return PROFILE_NONE; 408 return PROFILE_NONE;
409 409
410 if (i2c_read(I2C_CPLD_ADDR, CFG_REG, 1, (unsigned char *)(&val), 2)) 410 if (i2c_read(I2C_CPLD_ADDR, CFG_REG, 1, (unsigned char *)(&val), 2))
411 return PROFILE_NONE; 411 return PROFILE_NONE;
412 412
413 return (1 << (val & PROFILE_MASK)); 413 return (1 << (val & PROFILE_MASK));
414 } 414 }
415 415
416 void enable_board_pin_mux(struct am335x_baseboard_id *header) 416 void enable_board_pin_mux(struct am335x_baseboard_id *header)
417 { 417 {
418 /* Do board-specific muxes. */ 418 /* Do board-specific muxes. */
419 if (board_is_bone(header)) { 419 if (board_is_bone(header)) {
420 /* Beaglebone pinmux */ 420 /* Beaglebone pinmux */
421 configure_module_pin_mux(i2c1_pin_mux); 421 configure_module_pin_mux(i2c1_pin_mux);
422 configure_module_pin_mux(mii1_pin_mux); 422 configure_module_pin_mux(mii1_pin_mux);
423 configure_module_pin_mux(mmc0_pin_mux); 423 configure_module_pin_mux(mmc0_pin_mux);
424 #ifndef CONFIG_NOR 424 #ifndef CONFIG_NOR
425 configure_module_pin_mux(mmc1_pin_mux); 425 configure_module_pin_mux(mmc1_pin_mux);
426 #endif 426 #endif
427 #if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT) 427 #if defined(CONFIG_NOR) && !defined(CONFIG_NOR_BOOT)
428 configure_module_pin_mux(bone_norcape_pin_mux); 428 configure_module_pin_mux(bone_norcape_pin_mux);
429 #endif 429 #endif
430 } else if (board_is_gp_evm(header)) { 430 } else if (board_is_gp_evm(header)) {
431 /* General Purpose EVM */ 431 /* General Purpose EVM */
432 unsigned short profile = detect_daughter_board_profile(); 432 unsigned short profile = detect_daughter_board_profile();
433 configure_module_pin_mux(rgmii1_pin_mux); 433 configure_module_pin_mux(rgmii1_pin_mux);
434 configure_module_pin_mux(mmc0_pin_mux); 434 configure_module_pin_mux(mmc0_pin_mux);
435 /* In profile #2 i2c1 and spi0 conflict. */ 435 /* In profile #2 i2c1 and spi0 conflict. */
436 if (profile & ~PROFILE_2) 436 if (profile & ~PROFILE_2)
437 configure_module_pin_mux(i2c1_pin_mux); 437 configure_module_pin_mux(i2c1_pin_mux);
438 /* Profiles 2 & 3 don't have NAND */ 438 /* Profiles 2 & 3 don't have NAND */
439 if (profile & ~(PROFILE_2 | PROFILE_3)) 439 if (profile & ~(PROFILE_2 | PROFILE_3))
440 configure_module_pin_mux(nand_pin_mux); 440 configure_module_pin_mux(nand_pin_mux);
441 else if (profile == PROFILE_2) { 441 else if (profile == PROFILE_2) {
442 configure_module_pin_mux(mmc1_pin_mux); 442 configure_module_pin_mux(mmc1_pin_mux);
443 configure_module_pin_mux(spi0_pin_mux); 443 configure_module_pin_mux(spi0_pin_mux);
444 } 444 }
445 } else if (board_is_idk(header)) { 445 } else if (board_is_idk(header)) {
446 /* 446 /*
447 * Industrial Motor Control (IDK) 447 * Industrial Motor Control (IDK)
448 * note: IDK console is on UART3 by default. 448 * note: IDK console is on UART3 by default.
449 * So u-boot mus be build with CONFIG_SERIAL4 and 449 * So u-boot mus be build with CONFIG_SERIAL4 and
450 * CONFIG_CONS_INDEX=4 450 * CONFIG_CONS_INDEX=4
451 */ 451 */
452 configure_module_pin_mux(mii1_pin_mux); 452 configure_module_pin_mux(mii1_pin_mux);
453 configure_module_pin_mux(mmc0_no_cd_pin_mux); 453 configure_module_pin_mux(mmc0_no_cd_pin_mux);
454 } else if (board_is_evm_sk(header)) { 454 } else if (board_is_evm_sk(header)) {
455 /* Starter Kit EVM */ 455 /* Starter Kit EVM */
456 configure_module_pin_mux(i2c1_pin_mux); 456 configure_module_pin_mux(i2c1_pin_mux);
457 configure_module_pin_mux(gpio0_7_pin_mux); 457 configure_module_pin_mux(gpio0_7_pin_mux);
458 configure_module_pin_mux(rgmii1_pin_mux); 458 configure_module_pin_mux(rgmii1_pin_mux);
459 configure_module_pin_mux(mmc0_pin_mux_sk_evm); 459 configure_module_pin_mux(mmc0_pin_mux_sk_evm);
460 } else if (board_is_bone_lt(header)) { 460 } else if (board_is_bone_lt(header)) {
461 /* Beaglebone LT pinmux */ 461 /* Beaglebone LT pinmux */
462 configure_module_pin_mux(i2c1_pin_mux); 462 configure_module_pin_mux(i2c1_pin_mux);
463 configure_module_pin_mux(mii1_pin_mux); 463 configure_module_pin_mux(mii1_pin_mux);
464 configure_module_pin_mux(mmc0_pin_mux); 464 configure_module_pin_mux(mmc0_pin_mux);
465 configure_module_pin_mux(mmc1_pin_mux); 465 configure_module_pin_mux(mmc1_pin_mux);
466 } else if (!strncmp(header->name, "SMARCT33", HDR_NAME_LEN)) { 466 } else if (!strncmp(header->name, "SMARCT33", HDR_NAME_LEN)) {
467 /* SMARC T335X pinmux */ 467 /* SMARC T335X pinmux */
468 /* i2c1 (pin37 and pin38 on P1 connector) in SBC-SMART-MEN is set as GPIOs*/ 468 /* i2c1 (pin37 and pin38 on P1 connector) in SBC-SMART-MEN is set as GPIOs*/
469 /* configure_module_pin_mux(i2c1_pin_mux);*/ 469 /* configure_module_pin_mux(i2c1_pin_mux);*/
470 configure_module_pin_mux(mmc0_pin_mux); 470 configure_module_pin_mux(mmc0_pin_mux);
471 configure_module_pin_mux(mmc1_pin_mux); 471 configure_module_pin_mux(mmc1_pin_mux);
472 configure_module_pin_mux(uart3_pin_mux); 472 configure_module_pin_mux(uart3_pin_mux);
473 configure_module_pin_mux(rmii1_pin_mux); 473 configure_module_pin_mux(rmii1_pin_mux);
474 configure_module_pin_mux(rmii2_pin_mux); 474 configure_module_pin_mux(rmii2_pin_mux);
475 configure_module_pin_mux(smarc_gpio_pin_mux); 475 configure_module_pin_mux(smarc_gpio_pin_mux);
476 configure_module_pin_mux(spi0_pin_mux); 476 configure_module_pin_mux(spi0_pin_mux);
477 configure_module_pin_mux(lcdc_pin_mux); 477 configure_module_pin_mux(lcdc_pin_mux);
478 } else if (!strncmp(header->name, "SMARCT80", HDR_NAME_LEN)) {
479 /* SMARC T335X 80 pinmux */
480 configure_module_pin_mux(i2c1_pin_mux);
481 configure_module_pin_mux(mmc0_pin_mux);
482 configure_module_pin_mux(mmc1_pin_mux);
483 configure_module_pin_mux(uart3_pin_mux);
484 configure_module_pin_mux(rmii1_pin_mux);
485 configure_module_pin_mux(rmii2_pin_mux);
486 configure_module_pin_mux(smarc_gpio_pin_mux);
487 configure_module_pin_mux(spi0_pin_mux);
488 configure_module_pin_mux(lcdc_pin_mux);
478 } else if (!strncmp(header->name, "SMARCT1G", HDR_NAME_LEN)) { 489 } else if (!strncmp(header->name, "SMARCT1G", HDR_NAME_LEN)) {
479 /* SMARC T335X 1G pinmux */ 490 /* SMARC T335X 1G pinmux */
480 configure_module_pin_mux(i2c1_pin_mux); 491 configure_module_pin_mux(i2c1_pin_mux);
481 configure_module_pin_mux(mmc0_pin_mux); 492 configure_module_pin_mux(mmc0_pin_mux);
482 configure_module_pin_mux(mmc1_pin_mux); 493 configure_module_pin_mux(mmc1_pin_mux);
483 configure_module_pin_mux(uart3_pin_mux); 494 configure_module_pin_mux(uart3_pin_mux);
484 configure_module_pin_mux(rmii1_pin_mux); 495 configure_module_pin_mux(rmii1_pin_mux);
485 configure_module_pin_mux(rmii2_pin_mux); 496 configure_module_pin_mux(rmii2_pin_mux);
486 configure_module_pin_mux(smarc_gpio_pin_mux); 497 configure_module_pin_mux(smarc_gpio_pin_mux);
487 configure_module_pin_mux(spi0_pin_mux); 498 configure_module_pin_mux(spi0_pin_mux);
488 configure_module_pin_mux(lcdc_pin_mux); 499 configure_module_pin_mux(lcdc_pin_mux);
489 } else { 500 } else {
490 puts("Unknown board, cannot configure pinmux."); 501 puts("Unknown board, cannot configure pinmux.");
491 hang(); 502 hang();
492 } 503 }
493 } 504 }
494 505
include/configs/smarct335x_evm.h
Diff comments   View file @ 4bac48b
1 /* 1 /*
2 * am335x_evm.h 2 * am335x_evm.h
3 * 3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ 4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
5 * 5 *
6 * This program is free software; you can redistribute it and/or 6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as 7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2. 8 * published by the Free Software Foundation version 2.
9 * 9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty 11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 */ 14 */
15 15
16 #ifndef __CONFIG_SMARCT335X_EVM_H 16 #ifndef __CONFIG_SMARCT335X_EVM_H
17 #define __CONFIG_SMARCT335X_EVM_H 17 #define __CONFIG_SMARCT335X_EVM_H
18 18
19 #include <configs/embedian_am335x_common.h> 19 #include <configs/embedian_am335x_common.h>
20 20
21 #define MACH_TYPE_SMARCT335XEVM 3600 /* Until the next sync */ 21 #define MACH_TYPE_SMARCT335XEVM 3600 /* Until the next sync */
22 #define CONFIG_MACH_TYPE MACH_TYPE_SMARCT335XEVM 22 #define CONFIG_MACH_TYPE MACH_TYPE_SMARCT335XEVM
23 #define CONFIG_BOARD_LATE_INIT 23 #define CONFIG_BOARD_LATE_INIT
24 24
25 /* Clock Defines */ 25 /* Clock Defines */
26 #define V_OSCK 24000000 /* Clock output from T2 */ 26 #define V_OSCK 24000000 /* Clock output from T2 */
27 #define V_SCLK (V_OSCK) 27 #define V_SCLK (V_OSCK)
28 28
29 /* Custom script for NOR */ 29 /* Custom script for NOR */
30 #define CONFIG_SYS_LDSCRIPT "board/embedian/smarct335x/u-boot.lds" 30 #define CONFIG_SYS_LDSCRIPT "board/embedian/smarct335x/u-boot.lds"
31 31
32 /* Always 128 KiB env size */ 32 /* Always 128 KiB env size */
33 #define CONFIG_ENV_SIZE (128 << 10) 33 #define CONFIG_ENV_SIZE (128 << 10)
34 34
35 /* Enhance our eMMC support / experience. */ 35 /* Enhance our eMMC support / experience. */
36 #define CONFIG_CMD_GPT 36 #define CONFIG_CMD_GPT
37 #define CONFIG_EFI_PARTITION 37 #define CONFIG_EFI_PARTITION
38 #define CONFIG_PARTITION_UUIDS 38 #define CONFIG_PARTITION_UUIDS
39 #define CONFIG_CMD_PART 39 #define CONFIG_CMD_PART
40 40
41 #ifdef CONFIG_NAND 41 #ifdef CONFIG_NAND
42 #define NANDARGS \ 42 #define NANDARGS \
43 "mtdids=" MTDIDS_DEFAULT "\0" \ 43 "mtdids=" MTDIDS_DEFAULT "\0" \
44 "mtdparts=" MTDPARTS_DEFAULT "\0" \ 44 "mtdparts=" MTDPARTS_DEFAULT "\0" \
45 "nandargs=setenv bootargs console=${console} " \ 45 "nandargs=setenv bootargs console=${console} " \
46 "${optargs} " \ 46 "${optargs} " \
47 "root=${nandroot} " \ 47 "root=${nandroot} " \
48 "rootfstype=${nandrootfstype}\0" \ 48 "rootfstype=${nandrootfstype}\0" \
49 "nandroot=ubi0:rootfs rw ubi.mtd=7,2048\0" \ 49 "nandroot=ubi0:rootfs rw ubi.mtd=7,2048\0" \
50 "nandrootfstype=ubifs rootwait=1\0" \ 50 "nandrootfstype=ubifs rootwait=1\0" \
51 "nandboot=echo Booting from nand ...; " \ 51 "nandboot=echo Booting from nand ...; " \
52 "run nandargs; " \ 52 "run nandargs; " \
53 "nand read ${fdtaddr} u-boot-spl-os; " \ 53 "nand read ${fdtaddr} u-boot-spl-os; " \
54 "nand read ${loadaddr} kernel; " \ 54 "nand read ${loadaddr} kernel; " \
55 "bootz ${loadaddr} - ${fdtaddr}\0" 55 "bootz ${loadaddr} - ${fdtaddr}\0"
56 #else 56 #else
57 #define NANDARGS "" 57 #define NANDARGS ""
58 #endif 58 #endif
59 59
60 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 60 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
61 61
62 #ifndef CONFIG_SPL_BUILD 62 #ifndef CONFIG_SPL_BUILD
63 #define CONFIG_EXTRA_ENV_SETTINGS \ 63 #define CONFIG_EXTRA_ENV_SETTINGS \
64 "hostname=smarct335x\0" \ 64 "hostname=smarct335x\0" \
65 "loadaddr=0x82000000\0" \ 65 "loadaddr=0x82000000\0" \
66 "fdtaddr=0x88000000\0" \ 66 "fdtaddr=0x88000000\0" \
67 "fdt_high=0xffffffff\0" \ 67 "fdt_high=0xffffffff\0" \
68 "boot_fdt=try\0" \ 68 "boot_fdt=try\0" \
69 "rdaddr=0x88080000\0" \ 69 "rdaddr=0x88080000\0" \
70 "bootpart=0:1\0" \ 70 "bootpart=0:1\0" \
71 "bootdir=\0" \ 71 "bootdir=\0" \
72 "fdtdir=/dtbs\0" \ 72 "fdtdir=/dtbs\0" \
73 "bootfile=zImage\0" \ 73 "bootfile=zImage\0" \
74 "fdtfile=undefined\0" \ 74 "fdtfile=undefined\0" \
75 "console=ttyO3,115200n8\0" \ 75 "console=ttyO3,115200n8\0" \
76 "partitions=" \ 76 "partitions=" \
77 "uuid_disk=${uuid_gpt_disk};" \ 77 "uuid_disk=${uuid_gpt_disk};" \
78 "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \ 78 "name=rootfs,start=2MiB,size=-,uuid=${uuid_gpt_rootfs}\0" \
79 "optargs=\0" \ 79 "optargs=\0" \
80 "mmcdev=0\0" \ 80 "mmcdev=0\0" \
81 "mmcpart=1\0" \ 81 "mmcpart=1\0" \
82 "mmcroot=/dev/mmcblk0p2 ro fixrtc\0" \ 82 "mmcroot=/dev/mmcblk0p2 ro fixrtc\0" \
83 "mmcrootfstype=ext4 rootwait\0" \ 83 "mmcrootfstype=ext4 rootwait\0" \
84 "rootpath=/export/rootfs\0" \ 84 "rootpath=/export/rootfs\0" \
85 "nfsopts=nolock\0" \ 85 "nfsopts=nolock\0" \
86 "static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \ 86 "static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \
87 "::off\0" \ 87 "::off\0" \
88 "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \ 88 "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \
89 "ramrootfstype=ext2\0" \ 89 "ramrootfstype=ext2\0" \
90 "mmcargs=setenv bootargs console=${console} " \ 90 "mmcargs=setenv bootargs console=${console} " \
91 "${optargs} " \ 91 "${optargs} " \
92 "root=${mmcroot} " \ 92 "root=${mmcroot} " \
93 "rootfstype=${mmcrootfstype}\0" \ 93 "rootfstype=${mmcrootfstype}\0" \
94 "spiroot=/dev/mtdblock4 rw\0" \ 94 "spiroot=/dev/mtdblock4 rw\0" \
95 "spirootfstype=jffs2\0" \ 95 "spirootfstype=jffs2\0" \
96 "spisrcaddr=0xe0000\0" \ 96 "spisrcaddr=0xe0000\0" \
97 "spiimgsize=0x362000\0" \ 97 "spiimgsize=0x362000\0" \
98 "spibusno=0\0" \ 98 "spibusno=0\0" \
99 "spiargs=setenv bootargs console=${console} " \ 99 "spiargs=setenv bootargs console=${console} " \
100 "${optargs} " \ 100 "${optargs} " \
101 "root=${spiroot} " \ 101 "root=${spiroot} " \
102 "rootfstype=${spirootfstype}\0" \ 102 "rootfstype=${spirootfstype}\0" \
103 "netargs=setenv bootargs console=${console} " \ 103 "netargs=setenv bootargs console=${console} " \
104 "${optargs} " \ 104 "${optargs} " \
105 "root=/dev/nfs " \ 105 "root=/dev/nfs " \
106 "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \ 106 "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \
107 "ip=dhcp\0" \ 107 "ip=dhcp\0" \
108 "bootenv=uEnv.txt\0" \ 108 "bootenv=uEnv.txt\0" \
109 "loadbootenv=load mmc ${bootpart} ${loadaddr} ${bootenv}\0" \ 109 "loadbootenv=load mmc ${bootpart} ${loadaddr} ${bootenv}\0" \
110 "importbootenv=echo Importing environment from mmc ...; " \ 110 "importbootenv=echo Importing environment from mmc ...; " \
111 "env import -t $loadaddr $filesize\0" \ 111 "env import -t $loadaddr $filesize\0" \
112 "ramargs=setenv bootargs console=${console} " \ 112 "ramargs=setenv bootargs console=${console} " \
113 "${optargs} " \ 113 "${optargs} " \
114 "root=${ramroot} " \ 114 "root=${ramroot} " \
115 "rootfstype=${ramrootfstype}\0" \ 115 "rootfstype=${ramrootfstype}\0" \
116 "loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \ 116 "loadramdisk=load mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
117 "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \ 117 "loadimage=load mmc ${bootpart} ${loadaddr} ${bootdir}/${bootfile}\0" \
118 "loadfdt=load mmc ${bootpart} ${fdtaddr} ${fdtdir}/${fdtfile}\0" \ 118 "loadfdt=load mmc ${bootpart} ${fdtaddr} ${fdtdir}/${fdtfile}\0" \
119 "mmcloados=run mmcargs; " \ 119 "mmcloados=run mmcargs; " \
120 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ 120 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
121 "if run loadfdt; then " \ 121 "if run loadfdt; then " \
122 "bootz ${loadaddr} - ${fdtaddr}; " \ 122 "bootz ${loadaddr} - ${fdtaddr}; " \
123 "else " \ 123 "else " \
124 "if test ${boot_fdt} = try; then " \ 124 "if test ${boot_fdt} = try; then " \
125 "bootz; " \ 125 "bootz; " \
126 "else " \ 126 "else " \
127 "echo WARN: Cannot load the DT; " \ 127 "echo WARN: Cannot load the DT; " \
128 "fi; " \ 128 "fi; " \
129 "fi; " \ 129 "fi; " \
130 "else " \ 130 "else " \
131 "bootz; " \ 131 "bootz; " \
132 "fi;\0" \ 132 "fi;\0" \
133 "mmcboot=mmc dev ${mmcdev}; " \ 133 "mmcboot=mmc dev ${mmcdev}; " \
134 "if mmc rescan; then " \ 134 "if mmc rescan; then " \
135 "gpio set 51; " \ 135 "gpio set 51; " \
136 "echo SD/MMC found on device ${mmcdev};" \ 136 "echo SD/MMC found on device ${mmcdev};" \
137 "if run loadbootenv; then " \ 137 "if run loadbootenv; then " \
138 "gpio set 54;" \ 138 "gpio set 54;" \
139 "gpio set 55;" \ 139 "gpio set 55;" \
140 "echo Loaded environment from ${bootenv};" \ 140 "echo Loaded environment from ${bootenv};" \
141 "run importbootenv;" \ 141 "run importbootenv;" \
142 "gpio set 7;" \ 142 "gpio set 7;" \
143 "fi;" \ 143 "fi;" \
144 "if test -n $cape; then " \ 144 "if test -n $cape; then " \
145 "if test -e mmc ${bootpart} ${fdtdir}/$fdtbase-$cape.dtb; then " \ 145 "if test -e mmc ${bootpart} ${fdtdir}/$fdtbase-$cape.dtb; then " \
146 "setenv fdtfile $fdtbase-$cape.dtb; " \ 146 "setenv fdtfile $fdtbase-$cape.dtb; " \
147 "fi; " \ 147 "fi; " \
148 "echo using: $fdtfile...; " \ 148 "echo using: $fdtfile...; " \
149 "fi; " \ 149 "fi; " \
150 "echo Checking if uenvcmd is set ...;" \ 150 "echo Checking if uenvcmd is set ...;" \
151 "if test -n $uenvcmd; then " \ 151 "if test -n $uenvcmd; then " \
152 "echo Running uenvcmd ...;" \ 152 "echo Running uenvcmd ...;" \
153 "run uenvcmd;" \ 153 "run uenvcmd;" \
154 "fi;" \ 154 "fi;" \
155 "echo; echo uenvcmd was not defined in uEnv.txt ...; echo trying eMMC (SMARC T335X) ...; echo;"\ 155 "echo; echo uenvcmd was not defined in uEnv.txt ...; echo trying eMMC (SMARC T335X) ...; echo;"\
156 "fi;\0" \ 156 "fi;\0" \
157 "mmc_classic_boot=echo Booting from mmc${mmcdev} ...; " \ 157 "mmc_classic_boot=echo Booting from mmc${mmcdev} ...; " \
158 "run mmcargs; " \ 158 "run mmcargs; " \
159 "bootz ${loadaddr}\0" \ 159 "bootz ${loadaddr}\0" \
160 "spiboot=echo Booting from spi ...; " \ 160 "spiboot=echo Booting from spi ...; " \
161 "run spiargs; " \ 161 "run spiargs; " \
162 "sf probe ${spibusno}:0; " \ 162 "sf probe ${spibusno}:0; " \
163 "sf read ${loadaddr} ${spisrcaddr} ${spiimgsize}; " \ 163 "sf read ${loadaddr} ${spisrcaddr} ${spiimgsize}; " \
164 "bootz ${loadaddr}\0" \ 164 "bootz ${loadaddr}\0" \
165 "netboot=echo Booting from network ...; " \ 165 "netboot=echo Booting from network ...; " \
166 "setenv autoload no; " \ 166 "setenv autoload no; " \
167 "dhcp; " \ 167 "dhcp; " \
168 "tftp ${loadaddr} ${bootfile}; " \ 168 "tftp ${loadaddr} ${bootfile}; " \
169 "tftp ${fdtaddr} ${fdtfile}; " \ 169 "tftp ${fdtaddr} ${fdtfile}; " \
170 "run netargs; " \ 170 "run netargs; " \
171 "bootz ${loadaddr} - ${fdtaddr}\0" \ 171 "bootz ${loadaddr} - ${fdtaddr}\0" \
172 "ramboot=echo Booting from ramdisk ...; " \ 172 "ramboot=echo Booting from ramdisk ...; " \
173 "run ramargs; " \ 173 "run ramargs; " \
174 "bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \ 174 "bootz ${loadaddr} ${rdaddr} ${fdtaddr}\0" \
175 "findfdt="\ 175 "findfdt="\
176 "if test $board_name = A335BONE; then " \ 176 "if test $board_name = A335BONE; then " \
177 "setenv fdtfile am335x-bone.dtb; setenv fdtbase am335x-bone; fi; " \ 177 "setenv fdtfile am335x-bone.dtb; setenv fdtbase am335x-bone; fi; " \
178 "if test $board_name = A335BNLT; then " \ 178 "if test $board_name = A335BNLT; then " \
179 "setenv fdtfile am335x-boneblack.dtb; setenv fdtbase am335x-boneblack; fi; " \ 179 "setenv fdtfile am335x-boneblack.dtb; setenv fdtbase am335x-boneblack; fi; " \
180 "if test $board_name = SMARCT33; then " \ 180 "if test $board_name = SMARCT33; then " \
181 "setenv fdtfile am335x-smarct335x.dtb; setenv fdtbase am335x-smarct335x.dtb; fi; " \ 181 "setenv fdtfile am335x-smarct335x.dtb; setenv fdtbase am335x-smarct335x.dtb; fi; " \
182 "if test $board_name = SMARCT80; then " \
183 "setenv fdtfile am335x-smarct335x.dtb; setenv fdtbase am335x-smarct335x.dtb; fi; " \
182 "if test $board_name = SMARCT1G; then " \ 184 "if test $board_name = SMARCT1G; then " \
183 "setenv fdtfile am335x-smarct335x.dtb; setenv fdtbase am335x-smarct335x.dtb; fi; " \ 185 "setenv fdtfile am335x-smarct335x.dtb; setenv fdtbase am335x-smarct335x.dtb; fi; " \
184 "if test $board_name = A33515BB; then " \ 186 "if test $board_name = A33515BB; then " \
185 "setenv fdtfile am335x-evm.dtb; fi; " \ 187 "setenv fdtfile am335x-evm.dtb; fi; " \
186 "if test $board_name = A335X_SK; then " \ 188 "if test $board_name = A335X_SK; then " \
187 "setenv fdtfile am335x-evmsk.dtb; fi; " \ 189 "setenv fdtfile am335x-evmsk.dtb; fi; " \
188 "if test $fdtfile = undefined; then " \ 190 "if test $fdtfile = undefined; then " \
189 "echo WARNING: Could not determine device tree to use; fi; \0" \ 191 "echo WARNING: Could not determine device tree to use; fi; \0" \
190 NANDARGS \ 192 NANDARGS \
191 DFUARGS 193 DFUARGS
192 #endif 194 #endif
193 195
194 #define CONFIG_BOOTCOMMAND \ 196 #define CONFIG_BOOTCOMMAND \
195 "gpio set 51; " \ 197 "gpio set 51; " \
196 "i2c mw 0x24 1 0x3e; " \ 198 "i2c mw 0x24 1 0x3e; " \
197 "run findfdt; " \ 199 "run findfdt; " \
198 "run mmcboot;" \ 200 "run mmcboot;" \
199 "gpio set 7; " \ 201 "gpio set 7; " \
200 "gpio set 55; " \ 202 "gpio set 55; " \
201 "gpio set 54; " \ 203 "gpio set 54; " \
202 "setenv mmcdev 1; " \ 204 "setenv mmcdev 1; " \
203 "setenv bootpart 1:1; " \ 205 "setenv bootpart 1:1; " \
204 "run mmcboot;" \ 206 "run mmcboot;" \
205 207
206 /* NS16550 Configuration */ 208 /* NS16550 Configuration */
207 #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */ 209 #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* Base EVM has UART0 */
208 #define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ 210 #define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */
209 #define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */ 211 #define CONFIG_SYS_NS16550_COM3 0x48024000 /* UART2 */
210 #define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */ 212 #define CONFIG_SYS_NS16550_COM4 0x481a6000 /* UART3 */
211 #define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */ 213 #define CONFIG_SYS_NS16550_COM5 0x481a8000 /* UART4 */
212 #define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */ 214 #define CONFIG_SYS_NS16550_COM6 0x481aa000 /* UART5 */
213 #define CONFIG_BAUDRATE 115200 215 #define CONFIG_BAUDRATE 115200
214 216
215 #define CONFIG_CMD_EEPROM 217 #define CONFIG_CMD_EEPROM
216 #define CONFIG_ENV_EEPROM_IS_ON_I2C 218 #define CONFIG_ENV_EEPROM_IS_ON_I2C
217 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ 219 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
218 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 220 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
219 #define CONFIG_SYS_I2C_MULTI_EEPROMS 221 #define CONFIG_SYS_I2C_MULTI_EEPROMS
220 222
221 /* PMIC support */ 223 /* PMIC support */
222 #define CONFIG_POWER_TPS65217 224 #define CONFIG_POWER_TPS65217
223 #define CONFIG_POWER_TPS65910 225 #define CONFIG_POWER_TPS65910
224 226
225 /* SPL */ 227 /* SPL */
226 #ifndef CONFIG_NOR_BOOT 228 #ifndef CONFIG_NOR_BOOT
227 #define CONFIG_SPL_POWER_SUPPORT 229 #define CONFIG_SPL_POWER_SUPPORT
228 #define CONFIG_SPL_YMODEM_SUPPORT 230 #define CONFIG_SPL_YMODEM_SUPPORT
229 231
230 /* Bootcount using the RTC block */ 232 /* Bootcount using the RTC block */
231 #define CONFIG_BOOTCOUNT_LIMIT 233 #define CONFIG_BOOTCOUNT_LIMIT
232 #define CONFIG_BOOTCOUNT_AM33XX 234 #define CONFIG_BOOTCOUNT_AM33XX
233 235
234 /* USB gadget RNDIS */ 236 /* USB gadget RNDIS */
235 #define CONFIG_SPL_MUSB_NEW_SUPPORT 237 #define CONFIG_SPL_MUSB_NEW_SUPPORT
236 238
237 /* General network SPL, both CPSW and USB gadget RNDIS */ 239 /* General network SPL, both CPSW and USB gadget RNDIS */
238 #define CONFIG_SPL_NET_SUPPORT 240 #define CONFIG_SPL_NET_SUPPORT
239 #define CONFIG_SPL_ENV_SUPPORT 241 #define CONFIG_SPL_ENV_SUPPORT
240 #define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL" 242 #define CONFIG_SPL_NET_VCI_STRING "AM335x U-Boot SPL"
241 243
242 /* SPI flash. */ 244 /* SPI flash. */
243 #define CONFIG_SPL_SPI_SUPPORT 245 #define CONFIG_SPL_SPI_SUPPORT
244 #define CONFIG_SPL_SPI_FLASH_SUPPORT 246 #define CONFIG_SPL_SPI_FLASH_SUPPORT
245 #define CONFIG_SPL_SPI_LOAD 247 #define CONFIG_SPL_SPI_LOAD
246 #define CONFIG_SPL_SPI_BUS 0 248 #define CONFIG_SPL_SPI_BUS 0
247 #define CONFIG_SPL_SPI_CS 0 249 #define CONFIG_SPL_SPI_CS 0
248 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 250 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
249 251
250 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds" 252 #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
251 253
252 #ifdef CONFIG_NAND 254 #ifdef CONFIG_NAND
253 #define CONFIG_NAND_OMAP_GPMC 255 #define CONFIG_NAND_OMAP_GPMC
254 #define CONFIG_NAND_OMAP_ELM 256 #define CONFIG_NAND_OMAP_ELM
255 #define CONFIG_SYS_NAND_5_ADDR_CYCLE 257 #define CONFIG_SYS_NAND_5_ADDR_CYCLE
256 #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ 258 #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
257 CONFIG_SYS_NAND_PAGE_SIZE) 259 CONFIG_SYS_NAND_PAGE_SIZE)
258 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 260 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
259 #define CONFIG_SYS_NAND_OOBSIZE 64 261 #define CONFIG_SYS_NAND_OOBSIZE 64
260 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) 262 #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
261 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS 263 #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
262 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ 264 #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
263 10, 11, 12, 13, 14, 15, 16, 17, \ 265 10, 11, 12, 13, 14, 15, 16, 17, \
264 18, 19, 20, 21, 22, 23, 24, 25, \ 266 18, 19, 20, 21, 22, 23, 24, 25, \
265 26, 27, 28, 29, 30, 31, 32, 33, \ 267 26, 27, 28, 29, 30, 31, 32, 33, \
266 34, 35, 36, 37, 38, 39, 40, 41, \ 268 34, 35, 36, 37, 38, 39, 40, 41, \
267 42, 43, 44, 45, 46, 47, 48, 49, \ 269 42, 43, 44, 45, 46, 47, 48, 49, \
268 50, 51, 52, 53, 54, 55, 56, 57, } 270 50, 51, 52, 53, 54, 55, 56, 57, }
269 271
270 #define CONFIG_SYS_NAND_ECCSIZE 512 272 #define CONFIG_SYS_NAND_ECCSIZE 512
271 #define CONFIG_SYS_NAND_ECCBYTES 14 273 #define CONFIG_SYS_NAND_ECCBYTES 14
272 #define CONFIG_SYS_NAND_ONFI_DETECTION 274 #define CONFIG_SYS_NAND_ONFI_DETECTION
273 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW 275 #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW
274 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE 276 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
275 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 277 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
276 #endif 278 #endif
277 #endif 279 #endif
278 280
279 /* 281 /*
280 * For NOR boot, we must set this to the start of where NOR is mapped 282 * For NOR boot, we must set this to the start of where NOR is mapped
281 * in memory. 283 * in memory.
282 */ 284 */
283 #ifdef CONFIG_NOR_BOOT 285 #ifdef CONFIG_NOR_BOOT
284 #define CONFIG_SYS_TEXT_BASE 0x08000000 286 #define CONFIG_SYS_TEXT_BASE 0x08000000
285 #endif 287 #endif
286 288
287 /* 289 /*
288 * USB configuration. We enable MUSB support, both for host and for 290 * USB configuration. We enable MUSB support, both for host and for
289 * gadget. We set USB0 as peripheral and USB1 as host, based on the 291 * gadget. We set USB0 as peripheral and USB1 as host, based on the
290 * board schematic and physical port wired to each. Then for host we 292 * board schematic and physical port wired to each. Then for host we
291 * add mass storage support and for gadget we add both RNDIS ethernet 293 * add mass storage support and for gadget we add both RNDIS ethernet
292 * and DFU. 294 * and DFU.
293 */ 295 */
294 #define CONFIG_USB_MUSB_DSPS 296 #define CONFIG_USB_MUSB_DSPS
295 #define CONFIG_ARCH_MISC_INIT 297 #define CONFIG_ARCH_MISC_INIT
296 #define CONFIG_MUSB_GADGET 298 #define CONFIG_MUSB_GADGET
297 #define CONFIG_MUSB_PIO_ONLY 299 #define CONFIG_MUSB_PIO_ONLY
298 #define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT 300 #define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT
299 #define CONFIG_USB_GADGET 301 #define CONFIG_USB_GADGET
300 #define CONFIG_USBDOWNLOAD_GADGET 302 #define CONFIG_USBDOWNLOAD_GADGET
301 #define CONFIG_USB_GADGET_DUALSPEED 303 #define CONFIG_USB_GADGET_DUALSPEED
302 #define CONFIG_USB_GADGET_VBUS_DRAW 2 304 #define CONFIG_USB_GADGET_VBUS_DRAW 2
303 #define CONFIG_MUSB_HOST 305 #define CONFIG_MUSB_HOST
304 #define CONFIG_AM335X_USB0 306 #define CONFIG_AM335X_USB0
305 #define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL 307 #define CONFIG_AM335X_USB0_MODE MUSB_PERIPHERAL
306 #define CONFIG_AM335X_USB1 308 #define CONFIG_AM335X_USB1
307 #define CONFIG_AM335X_USB1_MODE MUSB_HOST 309 #define CONFIG_AM335X_USB1_MODE MUSB_HOST
308 310
309 #ifdef CONFIG_MUSB_HOST 311 #ifdef CONFIG_MUSB_HOST
310 #define CONFIG_CMD_USB 312 #define CONFIG_CMD_USB
311 #define CONFIG_USB_STORAGE 313 #define CONFIG_USB_STORAGE
312 #endif 314 #endif
313 315
314 #ifdef CONFIG_MUSB_GADGET 316 #ifdef CONFIG_MUSB_GADGET
315 #define CONFIG_USB_ETHER 317 #define CONFIG_USB_ETHER
316 #define CONFIG_USB_ETH_RNDIS 318 #define CONFIG_USB_ETH_RNDIS
317 #define CONFIG_USBNET_HOST_ADDR "de:ad:be:af:00:00" 319 #define CONFIG_USBNET_HOST_ADDR "de:ad:be:af:00:00"
318 320
319 /* USB TI's IDs */ 321 /* USB TI's IDs */
320 #define CONFIG_G_DNL_VENDOR_NUM 0x0403 322 #define CONFIG_G_DNL_VENDOR_NUM 0x0403
321 #define CONFIG_G_DNL_PRODUCT_NUM 0xBD00 323 #define CONFIG_G_DNL_PRODUCT_NUM 0xBD00
322 #define CONFIG_G_DNL_MANUFACTURER "Texas Instruments" 324 #define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
323 #endif /* CONFIG_MUSB_GADGET */ 325 #endif /* CONFIG_MUSB_GADGET */
324 326
325 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT) 327 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_USBETH_SUPPORT)
326 /* disable host part of MUSB in SPL */ 328 /* disable host part of MUSB in SPL */
327 #undef CONFIG_MUSB_HOST 329 #undef CONFIG_MUSB_HOST
328 /* disable EFI partitions and partition UUID support */ 330 /* disable EFI partitions and partition UUID support */
329 #undef CONFIG_PARTITION_UUIDS 331 #undef CONFIG_PARTITION_UUIDS
330 #undef CONFIG_EFI_PARTITION 332 #undef CONFIG_EFI_PARTITION
331 /* 333 /*
332 * Disable CPSW SPL support so we fit within the 101KiB limit. 334 * Disable CPSW SPL support so we fit within the 101KiB limit.
333 */ 335 */
334 #undef CONFIG_SPL_ETH_SUPPORT 336 #undef CONFIG_SPL_ETH_SUPPORT
335 #endif 337 #endif
336 338
337 /* USB Device Firmware Update support */ 339 /* USB Device Firmware Update support */
338 #define CONFIG_DFU_FUNCTION 340 #define CONFIG_DFU_FUNCTION
339 #define CONFIG_DFU_MMC 341 #define CONFIG_DFU_MMC
340 #define CONFIG_CMD_DFU 342 #define CONFIG_CMD_DFU
341 #define DFU_ALT_INFO_MMC \ 343 #define DFU_ALT_INFO_MMC \
342 "dfu_alt_info_mmc=" \ 344 "dfu_alt_info_mmc=" \
343 "boot part 0 1;" \ 345 "boot part 0 1;" \
344 "rootfs part 0 2;" \ 346 "rootfs part 0 2;" \
345 "MLO fat 0 1;" \ 347 "MLO fat 0 1;" \
346 "MLO.raw mmc 100 100;" \ 348 "MLO.raw mmc 100 100;" \
347 "u-boot.img.raw mmc 300 400;" \ 349 "u-boot.img.raw mmc 300 400;" \
348 "spl-os-args.raw mmc 80 80;" \ 350 "spl-os-args.raw mmc 80 80;" \
349 "spl-os-image.raw mmc 900 2000;" \ 351 "spl-os-image.raw mmc 900 2000;" \
350 "spl-os-args fat 0 1;" \ 352 "spl-os-args fat 0 1;" \
351 "spl-os-image fat 0 1;" \ 353 "spl-os-image fat 0 1;" \
352 "u-boot.img fat 0 1;" \ 354 "u-boot.img fat 0 1;" \
353 "uEnv.txt fat 0 1\0" 355 "uEnv.txt fat 0 1\0"
354 #ifdef CONFIG_NAND 356 #ifdef CONFIG_NAND
355 #define CONFIG_DFU_NAND 357 #define CONFIG_DFU_NAND
356 #define DFU_ALT_INFO_NAND \ 358 #define DFU_ALT_INFO_NAND \
357 "dfu_alt_info_nand=" \ 359 "dfu_alt_info_nand=" \
358 "SPL part 0 1;" \ 360 "SPL part 0 1;" \
359 "SPL.backup1 part 0 2;" \ 361 "SPL.backup1 part 0 2;" \
360 "SPL.backup2 part 0 3;" \ 362 "SPL.backup2 part 0 3;" \
361 "SPL.backup3 part 0 4;" \ 363 "SPL.backup3 part 0 4;" \
362 "u-boot part 0 5;" \ 364 "u-boot part 0 5;" \
363 "u-boot-spl-os part 0 6;" \ 365 "u-boot-spl-os part 0 6;" \
364 "kernel part 0 8;" \ 366 "kernel part 0 8;" \
365 "rootfs part 0 9\0" 367 "rootfs part 0 9\0"
366 #else 368 #else
367 #define DFU_ALT_INFO_NAND "" 369 #define DFU_ALT_INFO_NAND ""
368 #endif 370 #endif
369 #define CONFIG_DFU_RAM 371 #define CONFIG_DFU_RAM
370 #define DFU_ALT_INFO_RAM \ 372 #define DFU_ALT_INFO_RAM \
371 "dfu_alt_info_ram=" \ 373 "dfu_alt_info_ram=" \
372 "kernel ram 0x80200000 0xD80000;" \ 374 "kernel ram 0x80200000 0xD80000;" \
373 "fdt ram 0x80F80000 0x80000;" \ 375 "fdt ram 0x80F80000 0x80000;" \
374 "ramdisk ram 0x81000000 0x4000000\0" 376 "ramdisk ram 0x81000000 0x4000000\0"
375 #define DFUARGS \ 377 #define DFUARGS \
376 "dfu_alt_info_emmc=rawemmc mmc 0 3751936\0" \ 378 "dfu_alt_info_emmc=rawemmc mmc 0 3751936\0" \
377 DFU_ALT_INFO_MMC \ 379 DFU_ALT_INFO_MMC \
378 DFU_ALT_INFO_RAM \ 380 DFU_ALT_INFO_RAM \
379 DFU_ALT_INFO_NAND 381 DFU_ALT_INFO_NAND
380 382
381 /* 383 /*
382 * Default to using SPI for environment, etc. 384 * Default to using SPI for environment, etc.
383 * 0x000000 - 0x020000 : SPL (128KiB) 385 * 0x000000 - 0x020000 : SPL (128KiB)
384 * 0x020000 - 0x0A0000 : U-Boot (512KiB) 386 * 0x020000 - 0x0A0000 : U-Boot (512KiB)
385 * 0x0A0000 - 0x0BFFFF : First copy of U-Boot Environment (128KiB) 387 * 0x0A0000 - 0x0BFFFF : First copy of U-Boot Environment (128KiB)
386 * 0x0C0000 - 0x0DFFFF : Second copy of U-Boot Environment (128KiB) 388 * 0x0C0000 - 0x0DFFFF : Second copy of U-Boot Environment (128KiB)
387 * 0x0E0000 - 0x442000 : Linux Kernel 389 * 0x0E0000 - 0x442000 : Linux Kernel
388 * 0x442000 - 0x800000 : Userland 390 * 0x442000 - 0x800000 : Userland
389 */ 391 */
390 #if defined(CONFIG_SPI_BOOT) 392 #if defined(CONFIG_SPI_BOOT)
391 #define CONFIG_ENV_IS_IN_SPI_FLASH 393 #define CONFIG_ENV_IS_IN_SPI_FLASH
392 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 394 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
393 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED 395 #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
394 #define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */ 396 #define CONFIG_ENV_SECT_SIZE (4 << 10) /* 4 KB sectors */
395 #define CONFIG_ENV_OFFSET (768 << 10) /* 768 KiB in */ 397 #define CONFIG_ENV_OFFSET (768 << 10) /* 768 KiB in */
396 #define CONFIG_ENV_OFFSET_REDUND (896 << 10) /* 896 KiB in */ 398 #define CONFIG_ENV_OFFSET_REDUND (896 << 10) /* 896 KiB in */
397 #define MTDIDS_DEFAULT "nor0=m25p80-flash.0" 399 #define MTDIDS_DEFAULT "nor0=m25p80-flash.0"
398 #define MTDPARTS_DEFAULT "mtdparts=m25p80-flash.0:128k(SPL)," \ 400 #define MTDPARTS_DEFAULT "mtdparts=m25p80-flash.0:128k(SPL)," \
399 "512k(u-boot),128k(u-boot-env1)," \ 401 "512k(u-boot),128k(u-boot-env1)," \
400 "128k(u-boot-env2),3464k(kernel)," \ 402 "128k(u-boot-env2),3464k(kernel)," \
401 "-(rootfs)" 403 "-(rootfs)"
402 #elif defined(CONFIG_EMMC_BOOT) 404 #elif defined(CONFIG_EMMC_BOOT)
403 #undef CONFIG_SPL_OS_BOOT 405 #undef CONFIG_SPL_OS_BOOT
404 #undef CONFIG_ENV_IS_NOWHERE 406 #undef CONFIG_ENV_IS_NOWHERE
405 #define CONFIG_ENV_IS_IN_MMC 407 #define CONFIG_ENV_IS_IN_MMC
406 #define CONFIG_SYS_MMC_ENV_DEV 1 408 #define CONFIG_SYS_MMC_ENV_DEV 1
407 #define CONFIG_SYS_MMC_ENV_PART 2 409 #define CONFIG_SYS_MMC_ENV_PART 2
408 #define CONFIG_ENV_OFFSET 0x0 410 #define CONFIG_ENV_OFFSET 0x0
409 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) 411 #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
410 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT 412 #define CONFIG_SYS_REDUNDAND_ENVIRONMENT
411 #endif 413 #endif
412 414
413 /* SPI flash. */ 415 /* SPI flash. */
414 #define CONFIG_CMD_SF 416 #define CONFIG_CMD_SF
415 #define CONFIG_SPI_FLASH 417 #define CONFIG_SPI_FLASH
416 #define CONFIG_SPI_FLASH_WINBOND 418 #define CONFIG_SPI_FLASH_WINBOND
417 #define CONFIG_SF_DEFAULT_SPEED 24000000 419 #define CONFIG_SF_DEFAULT_SPEED 24000000
418 420
419 /* Network. */ 421 /* Network. */
420 #define CONFIG_PHY_GIGE 422 #define CONFIG_PHY_GIGE
421 #define CONFIG_PHYLIB 423 #define CONFIG_PHYLIB
422 #define CONFIG_PHY_SMSC 424 #define CONFIG_PHY_SMSC
423 425
424 /* NAND support */ 426 /* NAND support */
425 #ifdef CONFIG_NAND 427 #ifdef CONFIG_NAND
426 #define CONFIG_CMD_NAND 428 #define CONFIG_CMD_NAND
427 #if !defined(CONFIG_SPI_BOOT) && !defined(CONFIG_NOR_BOOT) 429 #if !defined(CONFIG_SPI_BOOT) && !defined(CONFIG_NOR_BOOT)
428 #define MTDIDS_DEFAULT "nand0=omap2-nand.0" 430 #define MTDIDS_DEFAULT "nand0=omap2-nand.0"
429 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:128k(SPL)," \ 431 #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:128k(SPL)," \
430 "128k(SPL.backup1)," \ 432 "128k(SPL.backup1)," \
431 "128k(SPL.backup2)," \ 433 "128k(SPL.backup2)," \
432 "128k(SPL.backup3),1792k(u-boot)," \ 434 "128k(SPL.backup3),1792k(u-boot)," \
433 "128k(u-boot-spl-os)," \ 435 "128k(u-boot-spl-os)," \
434 "128k(u-boot-env),5m(kernel),-(rootfs)" 436 "128k(u-boot-env),5m(kernel),-(rootfs)"
435 #define CONFIG_ENV_IS_IN_NAND 437 #define CONFIG_ENV_IS_IN_NAND
436 #define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */ 438 #define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */
437 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 439 #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
438 #endif 440 #endif
439 #endif 441 #endif
440 442
441 /* 443 /*
442 * NOR Size = 16 MiB 444 * NOR Size = 16 MiB
443 * Number of Sectors/Blocks = 128 445 * Number of Sectors/Blocks = 128
444 * Sector Size = 128 KiB 446 * Sector Size = 128 KiB
445 * Word length = 16 bits 447 * Word length = 16 bits
446 * Default layout: 448 * Default layout:
447 * 0x000000 - 0x07FFFF : U-Boot (512 KiB) 449 * 0x000000 - 0x07FFFF : U-Boot (512 KiB)
448 * 0x080000 - 0x09FFFF : First copy of U-Boot Environment (128 KiB) 450 * 0x080000 - 0x09FFFF : First copy of U-Boot Environment (128 KiB)
449 * 0x0A0000 - 0x0BFFFF : Second copy of U-Boot Environment (128 KiB) 451 * 0x0A0000 - 0x0BFFFF : Second copy of U-Boot Environment (128 KiB)
450 * 0x0C0000 - 0x4BFFFF : Linux Kernel (4 MiB) 452 * 0x0C0000 - 0x4BFFFF : Linux Kernel (4 MiB)
451 * 0x4C0000 - 0xFFFFFF : Userland (11 MiB + 256 KiB) 453 * 0x4C0000 - 0xFFFFFF : Userland (11 MiB + 256 KiB)
452 */ 454 */
453 #if defined(CONFIG_NOR) 455 #if defined(CONFIG_NOR)
454 #undef CONFIG_SYS_NO_FLASH 456 #undef CONFIG_SYS_NO_FLASH
455 #define CONFIG_CMD_FLASH 457 #define CONFIG_CMD_FLASH
456 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 458 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
457 #define CONFIG_SYS_FLASH_PROTECTION 459 #define CONFIG_SYS_FLASH_PROTECTION
458 #define CONFIG_SYS_FLASH_CFI 460 #define CONFIG_SYS_FLASH_CFI
459 #define CONFIG_FLASH_CFI_DRIVER 461 #define CONFIG_FLASH_CFI_DRIVER
460 #define CONFIG_FLASH_CFI_MTD 462 #define CONFIG_FLASH_CFI_MTD
461 #define CONFIG_SYS_MAX_FLASH_SECT 128 463 #define CONFIG_SYS_MAX_FLASH_SECT 128
462 #define CONFIG_SYS_MAX_FLASH_BANKS 1 464 #define CONFIG_SYS_MAX_FLASH_BANKS 1
463 #define CONFIG_SYS_FLASH_BASE (0x08000000) 465 #define CONFIG_SYS_FLASH_BASE (0x08000000)
464 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 466 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
465 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 467 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
466 /* Reduce SPL size by removing unlikey targets */ 468 /* Reduce SPL size by removing unlikey targets */
467 #undef CONFIG_SPL_SPI_SUPPORT 469 #undef CONFIG_SPL_SPI_SUPPORT
468 #ifdef CONFIG_NOR_BOOT 470 #ifdef CONFIG_NOR_BOOT
469 #define CONFIG_ENV_IS_IN_FLASH 471 #define CONFIG_ENV_IS_IN_FLASH
470 #define CONFIG_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ 472 #define CONFIG_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
471 #define CONFIG_ENV_OFFSET (512 << 10) /* 512 KiB */ 473 #define CONFIG_ENV_OFFSET (512 << 10) /* 512 KiB */
472 #define CONFIG_ENV_OFFSET_REDUND (768 << 10) /* 768 KiB */ 474 #define CONFIG_ENV_OFFSET_REDUND (768 << 10) /* 768 KiB */
473 #define MTDIDS_DEFAULT "nor0=physmap-flash.0" 475 #define MTDIDS_DEFAULT "nor0=physmap-flash.0"
474 #define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:" \ 476 #define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:" \
475 "512k(u-boot)," \ 477 "512k(u-boot)," \
476 "128k(u-boot-env1)," \ 478 "128k(u-boot-env1)," \
477 "128k(u-boot-env2)," \ 479 "128k(u-boot-env2)," \
478 "4m(kernel),-(rootfs)" 480 "4m(kernel),-(rootfs)"
479 #endif 481 #endif
480 #endif /* NOR support */ 482 #endif /* NOR support */
481 483
482 #endif /* ! __CONFIG_SMARCT335X_EVM_H */ 484 #endif /* ! __CONFIG_SMARCT335X_EVM_H */
483 485