Commit 4bac48b2c7178eb56ea2e53d7a57086802a1560b

Authored by Eric Lee
1 parent ba71de91c1

Add SMARCT80 Board support

Showing 5 changed files with 127 additions and 26 deletions Side-by-side Diff

arch/arm/include/asm/arch-am33xx/ddr_defs.h
... ... @@ -112,6 +112,38 @@
112 112 #define MT41K256M16HA125E_PHY_FIFO_WE 0x94
113 113 #define MT41K256M16HA125E_IOCTRL_VALUE 0x18B
114 114  
  115 +/* Samsung K4B4G1646E-BYK0 */
  116 +#define K4B4G1646EBYK0_EMIF_READ_LATENCY 0x100007
  117 +#define K4B4G1646EBYK0_EMIF_TIM1 0x0AAAE51B
  118 +#define K4B4G1646EBYK0_EMIF_TIM2 0x267B7FDA
  119 +#define K4B4G1646EBYK0_EMIF_TIM3 0x501F877F
  120 +#define K4B4G1646EBYK0_EMIF_SDCFG 0x61C05332
  121 +#define K4B4G1646EBYK0_EMIF_SDREF 0xC30
  122 +#define K4B4G1646EBYK0_ZQ_CFG 0x50074BE4
  123 +#define K4B4G1646EBYK0_RATIO 0x80
  124 +#define K4B4G1646EBYK0_INVERT_CLKOUT 0x0
  125 +#define K4B4G1646EBYK0_RD_DQS 0x3B
  126 +#define K4B4G1646EBYK0_WR_DQS 0x4A
  127 +#define K4B4G1646EBYK0_PHY_WR_DATA 0x83
  128 +#define K4B4G1646EBYK0_PHY_FIFO_WE 0xA4
  129 +#define K4B4G1646EBYK0_IOCTRL_VALUE 0x18B
  130 +
  131 +/* Micron MT41K256M16HA-125ITE */
  132 +#define MT41K256M16HA125ITE_EMIF_READ_LATENCY 0x100007
  133 +#define MT41K256M16HA125ITE_EMIF_TIM1 0x0AAAE51B
  134 +#define MT41K256M16HA125ITE_EMIF_TIM2 0x267B7FDA
  135 +#define MT41K256M16HA125ITE_EMIF_TIM3 0x501F877F
  136 +#define MT41K256M16HA125ITE_EMIF_SDCFG 0x61C05332
  137 +#define MT41K256M16HA125ITE_EMIF_SDREF 0xC30
  138 +#define MT41K256M16HA125ITE_ZQ_CFG 0x50074BE4
  139 +#define MT41K256M16HA125ITE_RATIO 0x80
  140 +#define MT41K256M16HA125ITE_INVERT_CLKOUT 0x0
  141 +#define MT41K256M16HA125ITE_RD_DQS 0x3D
  142 +#define MT41K256M16HA125ITE_WR_DQS 0x4B
  143 +#define MT41K256M16HA125ITE_PHY_WR_DATA 0x7F
  144 +#define MT41K256M16HA125ITE_PHY_FIFO_WE 0x9D
  145 +#define MT41K256M16HA125ITE_IOCTRL_VALUE 0x18B
  146 +
115 147 /* Micron MT41J512M8RH-125 on EVM v1.5 */
116 148 #define MT41J512M8RH125_EMIF_READ_LATENCY 0x100006
117 149 #define MT41J512M8RH125_EMIF_TIM1 0x0888A39B
board/embedian/smarct335x/board.c
... ... @@ -150,12 +150,19 @@
150 150 };
151 151  
152 152 static const struct ddr_data ddr3_smarct335x_data = {
153   - .datardsratio0 = MT41K256M16HA125E_RD_DQS,
154   - .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
155   - .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
156   - .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  153 + .datardsratio0 = K4B4G1646EBYK0_RD_DQS,
  154 + .datawdsratio0 = K4B4G1646EBYK0_WR_DQS,
  155 + .datafwsratio0 = K4B4G1646EBYK0_PHY_FIFO_WE,
  156 + .datawrsratio0 = K4B4G1646EBYK0_PHY_WR_DATA,
157 157 };
158 158  
  159 +static const struct ddr_data ddr3_smarct335x80_data = {
  160 + .datardsratio0 = MT41K256M16HA125ITE_RD_DQS,
  161 + .datawdsratio0 = MT41K256M16HA125ITE_WR_DQS,
  162 + .datafwsratio0 = MT41K256M16HA125ITE_PHY_FIFO_WE,
  163 + .datawrsratio0 = MT41K256M16HA125ITE_PHY_WR_DATA,
  164 +};
  165 +
159 166 static const struct ddr_data ddr3_evm_data = {
160 167 .datardsratio0 = MT41J512M8RH125_RD_DQS,
161 168 .datawdsratio0 = MT41J512M8RH125_WR_DQS,
162 169  
163 170  
164 171  
... ... @@ -186,16 +193,27 @@
186 193 };
187 194  
188 195 static const struct cmd_control ddr3_smarct335x_cmd_ctrl_data = {
189   - .cmd0csratio = MT41K256M16HA125E_RATIO,
190   - .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  196 + .cmd0csratio = K4B4G1646EBYK0_RATIO,
  197 + .cmd0iclkout = K4B4G1646EBYK0_INVERT_CLKOUT,
191 198  
192   - .cmd1csratio = MT41K256M16HA125E_RATIO,
193   - .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  199 + .cmd1csratio = K4B4G1646EBYK0_RATIO,
  200 + .cmd1iclkout = K4B4G1646EBYK0_INVERT_CLKOUT,
194 201  
195   - .cmd2csratio = MT41K256M16HA125E_RATIO,
196   - .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  202 + .cmd2csratio = K4B4G1646EBYK0_RATIO,
  203 + .cmd2iclkout = K4B4G1646EBYK0_INVERT_CLKOUT,
197 204 };
198 205  
  206 +static const struct cmd_control ddr3_smarct335x80_cmd_ctrl_data = {
  207 + .cmd0csratio = MT41K256M16HA125ITE_RATIO,
  208 + .cmd0iclkout = MT41K256M16HA125ITE_INVERT_CLKOUT,
  209 +
  210 + .cmd1csratio = MT41K256M16HA125ITE_RATIO,
  211 + .cmd1iclkout = MT41K256M16HA125ITE_INVERT_CLKOUT,
  212 +
  213 + .cmd2csratio = MT41K256M16HA125ITE_RATIO,
  214 + .cmd2iclkout = MT41K256M16HA125ITE_INVERT_CLKOUT,
  215 +};
  216 +
199 217 static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
200 218 .cmd0csratio = MT41J512M8RH125_RATIO,
201 219 .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
202 220  
... ... @@ -229,15 +247,25 @@
229 247 };
230 248  
231 249 static struct emif_regs ddr3_smarct335x_emif_reg_data = {
232   - .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
233   - .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
234   - .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
235   - .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
236   - .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
237   - .zq_config = MT41K256M16HA125E_ZQ_CFG,
238   - .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
  250 + .sdram_config = K4B4G1646EBYK0_EMIF_SDCFG,
  251 + .ref_ctrl = K4B4G1646EBYK0_EMIF_SDREF,
  252 + .sdram_tim1 = K4B4G1646EBYK0_EMIF_TIM1,
  253 + .sdram_tim2 = K4B4G1646EBYK0_EMIF_TIM2,
  254 + .sdram_tim3 = K4B4G1646EBYK0_EMIF_TIM3,
  255 + .zq_config = K4B4G1646EBYK0_ZQ_CFG,
  256 + .emif_ddr_phy_ctlr_1 = K4B4G1646EBYK0_EMIF_READ_LATENCY,
239 257 };
240 258  
  259 +static struct emif_regs ddr3_smarct335x80_emif_reg_data = {
  260 + .sdram_config = MT41K256M16HA125ITE_EMIF_SDCFG,
  261 + .ref_ctrl = MT41K256M16HA125ITE_EMIF_SDREF,
  262 + .sdram_tim1 = MT41K256M16HA125ITE_EMIF_TIM1,
  263 + .sdram_tim2 = MT41K256M16HA125ITE_EMIF_TIM2,
  264 + .sdram_tim3 = MT41K256M16HA125ITE_EMIF_TIM3,
  265 + .zq_config = MT41K256M16HA125ITE_ZQ_CFG,
  266 + .emif_ddr_phy_ctlr_1 = MT41K256M16HA125ITE_EMIF_READ_LATENCY,
  267 +};
  268 +
241 269 static struct emif_regs ddr3_evm_emif_reg_data = {
242 270 .sdram_config = MT41J512M8RH125_EMIF_SDCFG,
243 271 .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
... ... @@ -278,7 +306,7 @@
278 306 /* Get the frequency */
279 307 dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
280 308  
281   - if (board_is_bone(&header) || board_is_bone_lt(&header) || board_is_smarc_t335x(&header) || board_is_smarc_t335x_1g(&header)) {
  309 + if (board_is_bone(&header) || board_is_bone_lt(&header) || board_is_smarc_t335x(&header) || board_is_smarc_t335x_80(&header) || board_is_smarc_t335x_1g(&header)) {
282 310 /* BeagleBone and SMARC T335X PMIC Code */
283 311 int usb_cur_lim;
284 312  
... ... @@ -424,7 +452,7 @@
424 452 return &dpll_ddr_evm_sk;
425 453 else if (board_is_bone_lt(&header))
426 454 return &dpll_ddr_bone_black;
427   - else if (board_is_smarc_t335x(&header) || board_is_smarc_t335x_1g(&header))
  455 + else if (board_is_smarc_t335x(&header) || board_is_smarc_t335x_80(&header) || board_is_smarc_t335x_1g(&header))
428 456 return &dpll_ddr_smarc_t335x;
429 457 else if (board_is_evm_15_or_later(&header))
430 458 return &dpll_ddr_evm_sk;
431 459  
... ... @@ -481,13 +509,21 @@
481 509 };
482 510  
483 511 const struct ctrl_ioregs ioregs_smarct335x = {
484   - .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
485   - .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
486   - .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
487   - .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
488   - .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  512 + .cm0ioctl = K4B4G1646EBYK0_IOCTRL_VALUE,
  513 + .cm1ioctl = K4B4G1646EBYK0_IOCTRL_VALUE,
  514 + .cm2ioctl = K4B4G1646EBYK0_IOCTRL_VALUE,
  515 + .dt0ioctl = K4B4G1646EBYK0_IOCTRL_VALUE,
  516 + .dt1ioctl = K4B4G1646EBYK0_IOCTRL_VALUE,
489 517 };
490 518  
  519 +const struct ctrl_ioregs ioregs_smarct335x80 = {
  520 + .cm0ioctl = MT41K256M16HA125ITE_IOCTRL_VALUE,
  521 + .cm1ioctl = MT41K256M16HA125ITE_IOCTRL_VALUE,
  522 + .cm2ioctl = MT41K256M16HA125ITE_IOCTRL_VALUE,
  523 + .dt0ioctl = MT41K256M16HA125ITE_IOCTRL_VALUE,
  524 + .dt1ioctl = MT41K256M16HA125ITE_IOCTRL_VALUE,
  525 +};
  526 +
491 527 const struct ctrl_ioregs ioregs_evm15 = {
492 528 .cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
493 529 .cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
494 530  
... ... @@ -541,8 +577,23 @@
541 577 &ddr3_smarct335x_data,
542 578 &ddr3_smarct335x_cmd_ctrl_data,
543 579 &ddr3_smarct335x_emif_reg_data, 0);
544   - puts("Set DDR3 to 800MHz.\n");
  580 + udelay(1600);
545 581 }
  582 + else if (board_is_smarc_t335x_80(&header)) {
  583 + /*
  584 + * SMARC T335X rev. 00B0 and later use gpio0_7 as LCD backlight PWM and gpio1_22 as LCD backlight enable.
  585 + * This is safe enough to do on older revs.
  586 + */
  587 + gpio_request(GPIO_LCD_BKLT_EN, "lcd_bklt_en");
  588 + gpio_direction_output(GPIO_LCD_BKLT_EN, 1);
  589 + gpio_request(GPIO_LCD_PWM_EN, "lcd_pwm_en");
  590 + gpio_direction_output(GPIO_LCD_PWM_EN, 1);
  591 + config_ddr(400, &ioregs_smarct335x80,
  592 + &ddr3_smarct335x80_data,
  593 + &ddr3_smarct335x80_cmd_ctrl_data,
  594 + &ddr3_smarct335x80_emif_reg_data, 0);
  595 + udelay(1200);
  596 + }
546 597 else if (board_is_evm_15_or_later(&header))
547 598 config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data,
548 599 &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
... ... @@ -700,7 +751,7 @@
700 751 writel(MII_MODE_ENABLE, &cdev->miisel);
701 752 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
702 753 PHY_INTERFACE_MODE_MII;
703   - } else if (board_is_smarc_t335x(&header) || board_is_smarc_t335x_1g(&header)) {
  754 + } else if (board_is_smarc_t335x(&header) || board_is_smarc_t335x_80(&header) || board_is_smarc_t335x_1g(&header)) {
704 755 writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
705 756 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
706 757 PHY_INTERFACE_MODE_RMII;
board/embedian/smarct335x/board.h
... ... @@ -44,6 +44,11 @@
44 44 return !strncmp(header->name, "SMARCT33", HDR_NAME_LEN);
45 45 }
46 46  
  47 +static inline int board_is_smarc_t335x_80(struct am335x_baseboard_id *header)
  48 +{
  49 + return !strncmp(header->name, "SMARCT80", HDR_NAME_LEN);
  50 +}
  51 +
47 52 static inline int board_is_smarc_t335x_1g(struct am335x_baseboard_id *header)
48 53 {
49 54 return !strncmp(header->name, "SMARCT1G", HDR_NAME_LEN);
board/embedian/smarct335x/mux.c
... ... @@ -475,6 +475,17 @@
475 475 configure_module_pin_mux(smarc_gpio_pin_mux);
476 476 configure_module_pin_mux(spi0_pin_mux);
477 477 configure_module_pin_mux(lcdc_pin_mux);
  478 + } else if (!strncmp(header->name, "SMARCT80", HDR_NAME_LEN)) {
  479 + /* SMARC T335X 80 pinmux */
  480 + configure_module_pin_mux(i2c1_pin_mux);
  481 + configure_module_pin_mux(mmc0_pin_mux);
  482 + configure_module_pin_mux(mmc1_pin_mux);
  483 + configure_module_pin_mux(uart3_pin_mux);
  484 + configure_module_pin_mux(rmii1_pin_mux);
  485 + configure_module_pin_mux(rmii2_pin_mux);
  486 + configure_module_pin_mux(smarc_gpio_pin_mux);
  487 + configure_module_pin_mux(spi0_pin_mux);
  488 + configure_module_pin_mux(lcdc_pin_mux);
478 489 } else if (!strncmp(header->name, "SMARCT1G", HDR_NAME_LEN)) {
479 490 /* SMARC T335X 1G pinmux */
480 491 configure_module_pin_mux(i2c1_pin_mux);
include/configs/smarct335x_evm.h
... ... @@ -179,6 +179,8 @@
179 179 "setenv fdtfile am335x-boneblack.dtb; setenv fdtbase am335x-boneblack; fi; " \
180 180 "if test $board_name = SMARCT33; then " \
181 181 "setenv fdtfile am335x-smarct335x.dtb; setenv fdtbase am335x-smarct335x.dtb; fi; " \
  182 + "if test $board_name = SMARCT80; then " \
  183 + "setenv fdtfile am335x-smarct335x.dtb; setenv fdtbase am335x-smarct335x.dtb; fi; " \
182 184 "if test $board_name = SMARCT1G; then " \
183 185 "setenv fdtfile am335x-smarct335x.dtb; setenv fdtbase am335x-smarct335x.dtb; fi; " \
184 186 "if test $board_name = A33515BB; then " \