MLK-18147-2 mx6sabreauto/sabresd: Update mx6dq/dqp/dl/s sabre boards codes

Porting the mx6dq/dqp/dl/s sabresd and sabreauto codes from v2018.03 The major change is moving back to non-SPL mode for sabre boards. which means all old things like DCD, plugin are added back for each platform. This inherits the way used in v2018.03 Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 3a3a0f07c85b0ae86b18709445206db0310c3b63) (cherry picked from commit 90b86014f70f44db3b18e96b2643a57a0a6f92a3) (cherry picked from commit 2660660f213e117c3445ba6f18e78d44df1683bc) (cherry picked from commit 7e4494e316fd48aad0cee22f45722147ff1f6dcd) (cherry picked from commit b29f22f4314bc67305e1533ba21ddaa67aa8df49)

MLK-18147-2 mx6sabreauto/sabresd: Update mx6dq/dqp/dl/s sabre boards codes
Porting the mx6dq/dqp/dl/s sabresd and sabreauto codes from v2018.03 The major change is moving back to non-SPL mode for sabre boards. which means all old things like DCD, plugin are added back for each platform. This inherits the way used in v2018.03 Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 3a3a0f07c85b0ae86b18709445206db0310c3b63) (cherry picked from commit 90b86014f70f44db3b18e96b2643a57a0a6f92a3) (cherry picked from commit 2660660f213e117c3445ba6f18e78d44df1683bc) (cherry picked from commit 7e4494e316fd48aad0cee22f45722147ff1f6dcd) (cherry picked from commit b29f22f4314bc67305e1533ba21ddaa67aa8df49)
Ye Li
1 parent 2e50d048bf
Showing 19 changed files with 4085 additions and 232 deletions Side-by-side Diff
arch/arm/mach-imx/mx6/Kconfig
board/freescale/mx6sabreauto/Kconfig
board/freescale/mx6sabreauto/imximage.cfg
board/freescale/mx6sabreauto/mx6dl.cfg
board/freescale/mx6sabreauto/mx6qp.cfg
board/freescale/mx6sabreauto/mx6sabreauto.c
board/freescale/mx6sabreauto/mx6solo.cfg
board/freescale/mx6sabreauto/plugin.S
board/freescale/mx6sabresd/Kconfig
board/freescale/mx6sabresd/mx6dlsabresd.cfg
board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg
board/freescale/mx6sabresd/mx6qp.cfg
board/freescale/mx6sabresd/mx6sabresd.c
board/freescale/mx6sabresd/mx6solo_4x_mt41j128.cfg
board/freescale/mx6sabresd/plugin.S
include/configs/mx6sabre_common.h
include/configs/mx6sabreauto.h
include/configs/mx6sabresd.h
scripts/config_whitelist.txt
@@ -125,6 +125,30 @@
 	help
 	  Set "Y" to enable the bee commands
  
+config TARGET_MX6SABREAUTO_COMMON
+    bool
+    select BOARD_LATE_INIT
+    select DM
+    select DM_THERMAL
+    select IMX_THERMAL
+    select BOARD_EARLY_INIT_F
+    select NXP_BOARD_REVISION
+    imply CMD_DM
+    select FSL_CAAM
+    select ARCH_MISC_INIT
+
+config TARGET_MX6SABRESD_COMMON
+    bool
+    select BOARD_LATE_INIT
+    select DM
+    select DM_THERMAL
+    select IMX_THERMAL
+    select BOARD_EARLY_INIT_F
+    select NXP_BOARD_REVISION
+    imply CMD_DM
+    select FSL_CAAM
+    select ARCH_MISC_INIT
+
 choice
 	prompt "MX6 board select"
 	optional
@@ -387,6 +411,46 @@
 	imply CMD_DM
 	select FSL_CAAM
 	select ARCH_MISC_INIT
+
+config TARGET_MX6QSABREAUTO
+    bool "mx6qsabreauto"
+    select TARGET_MX6SABREAUTO_COMMON
+    depends on MX6Q
+
+config TARGET_MX6QPSABREAUTO
+    bool "mx6qpsabreauto"
+    select TARGET_MX6SABREAUTO_COMMON
+    depends on MX6QP
+
+config TARGET_MX6DLSABREAUTO
+    bool "mx6dlsabreauto"
+    select TARGET_MX6SABREAUTO_COMMON
+    depends on MX6DL
+
+config TARGET_MX6SOLOSABREAUTO
+    bool "mx6solosabreauto"
+    select TARGET_MX6SABREAUTO_COMMON
+    depends on MX6S
+
+config TARGET_MX6QSABRESD
+	bool "mx6qsabresd"
+    select TARGET_MX6SABRESD_COMMON
+    depends on MX6Q
+
+config TARGET_MX6QPSABRESD
+	bool "mx6qpsabresd"
+    select TARGET_MX6SABRESD_COMMON
+    depends on MX6QP
+
+config TARGET_MX6DLSABRESD
+	bool "mx6dlsabresd"
+    select TARGET_MX6SABRESD_COMMON
+    depends on MX6DL
+
+config TARGET_MX6SOLOSABRESD
+	bool "mx6solosabresd"
+    select TARGET_MX6SABRESD_COMMON
+    depends on MX6S
  
 config TARGET_MX6SLEVK
 	bool "mx6slevk"
-if TARGET_MX6SABREAUTO
+if TARGET_MX6SABREAUTO || TARGET_MX6SABREAUTO_COMMON
  
 config SYS_BOARD
 	default "mx6sabreauto"
@@ -9,5 +9,13 @@
 config SYS_CONFIG_NAME
 	default "mx6sabreauto"
  
+config SYS_TEXT_BASE
+    default 0x17800000
+
+config NOR
+	bool "Support for NOR flash"
+	help
+	  The i.MX SoC supports having a NOR flash connected to the WEIM.
+	  Need to set this for NOR_BOOT.
 endif
+/*
+ * Copyright (C) 2012-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of spi, sd, eimnor, nand, sata:
+ * spinor: flash_offset: 0x0400
+ * nand:   flash_offset: 0x0400
+ * sata:   flash_offset: 0x0400
+ * sd/mmc: flash_offset: 0x0400
+ * eimnor: flash_offset: 0x1000
+ */
+
+#if defined(CONFIG_NOR_BOOT)
+BOOT_FROM	nor
+#else /* others has the same flash_offset as sd */
+BOOT_FROM	sd
+#endif
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN board/freescale/mx6sabreauto/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+DATA 4 0x020e0798 0x000C0000
+DATA 4 0x020e0758 0x00000000
+DATA 4 0x020e0588 0x00000030
+DATA 4 0x020e0594 0x00000030
+DATA 4 0x020e056c 0x00000030
+DATA 4 0x020e0578 0x00000030
+DATA 4 0x020e074c 0x00000030
+DATA 4 0x020e057c 0x00000030
+DATA 4 0x020e058c 0x00000000
+DATA 4 0x020e059c 0x00000030
+DATA 4 0x020e05a0 0x00000030
+DATA 4 0x020e078c 0x00000030
+DATA 4 0x020e0750 0x00020000
+DATA 4 0x020e05a8 0x00000028
+DATA 4 0x020e05b0 0x00000028
+DATA 4 0x020e0524 0x00000028
+DATA 4 0x020e051c 0x00000028
+DATA 4 0x020e0518 0x00000028
+DATA 4 0x020e050c 0x00000028
+DATA 4 0x020e05b8 0x00000028
+DATA 4 0x020e05c0 0x00000028
+DATA 4 0x020e0774 0x00020000
+DATA 4 0x020e0784 0x00000028
+DATA 4 0x020e0788 0x00000028
+DATA 4 0x020e0794 0x00000028
+DATA 4 0x020e079c 0x00000028
+DATA 4 0x020e07a0 0x00000028
+DATA 4 0x020e07a4 0x00000028
+DATA 4 0x020e07a8 0x00000028
+DATA 4 0x020e0748 0x00000028
+DATA 4 0x020e05ac 0x00000028
+DATA 4 0x020e05b4 0x00000028
+DATA 4 0x020e0528 0x00000028
+DATA 4 0x020e0520 0x00000028
+DATA 4 0x020e0514 0x00000028
+DATA 4 0x020e0510 0x00000028
+DATA 4 0x020e05bc 0x00000028
+DATA 4 0x020e05c4 0x00000028
+DATA 4 0x021b0800 0xa1390003
+DATA 4 0x021b080c 0x001F001F
+DATA 4 0x021b0810 0x001F001F
+DATA 4 0x021b480c 0x001F001F
+DATA 4 0x021b4810 0x001F001F
+DATA 4 0x021b083c 0x43260335
+DATA 4 0x021b0840 0x031A030B
+DATA 4 0x021b483c 0x4323033B
+DATA 4 0x021b4840 0x0323026F
+DATA 4 0x021b0848 0x483D4545
+DATA 4 0x021b4848 0x44433E48
+DATA 4 0x021b0850 0x41444840
+DATA 4 0x021b4850 0x4835483E
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+DATA 4 0x021b481c 0x33333333
+DATA 4 0x021b4820 0x33333333
+DATA 4 0x021b4824 0x33333333
+DATA 4 0x021b4828 0x33333333
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b48b8 0x00000800
+DATA 4 0x021b0004 0x00020036
+DATA 4 0x021b0008 0x09444040
+DATA 4 0x021b000c 0x8A8F7955
+DATA 4 0x021b0010 0xFF328F64
+DATA 4 0x021b0014 0x01FF00DB
+DATA 4 0x021b0018 0x00001740
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b002c 0x000026d2
+DATA 4 0x021b0030 0x008F1023
+DATA 4 0x021b0040 0x00000047
+DATA 4 0x021b0000 0x841A0000
+DATA 4 0x021b001c 0x04088032
+DATA 4 0x021b001c 0x00008033
+DATA 4 0x021b001c 0x00048031
+DATA 4 0x021b001c 0x09408030
+DATA 4 0x021b001c 0x04008040
+DATA 4 0x021b0020 0x00005800
+DATA 4 0x021b0818 0x00011117
+DATA 4 0x021b4818 0x00011117
+DATA 4 0x021b0004 0x00025576
+DATA 4 0x021b0404 0x00011006
+DATA 4 0x021b001c 0x00000000
+
+/* set the default clock gate to save power */
+DATA 4 0x020c4068 0x00C03F3F
+DATA 4 0x020c406c 0x0030FC03
+DATA 4 0x020c4070 0x0FFFF000
+DATA 4 0x020c4074 0x3FF00000
+DATA 4 0x020c4078 0xFFFFF300
+DATA 4 0x020c407c 0x0F0000F3
+DATA 4 0x020c4080 0x00000FFF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4 0x020e0010 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4 0x020e0018 0x007F007F
+DATA 4 0x020e001c 0x007F007F
+#endif
+/*
+ * Copyright (C) 2013-2016 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of spi, sd, eimnor, nand, sata:
+ * spinor: flash_offset: 0x0400
+ * nand:   flash_offset: 0x0400
+ * sata:   flash_offset: 0x0400
+ * sd/mmc: flash_offset: 0x0400
+ * eimnor: flash_offset: 0x1000
+ */
+
+#if defined(CONFIG_NOR_BOOT)
+BOOT_FROM       nor
+#else /* others has the same flash_offset as sd */
+BOOT_FROM       sd
+#endif
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN board/freescale/mx6sabreauto/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+DATA 4 0x020e0774 0x000C0000
+DATA 4 0x020e0754 0x00000000
+DATA 4 0x020e04ac 0x00000030
+DATA 4 0x020e04b0 0x00000030
+DATA 4 0x020e0464 0x00000030
+DATA 4 0x020e0490 0x00000030
+DATA 4 0x020e074c 0x00000030
+DATA 4 0x020e0494 0x00000030
+DATA 4 0x020e04a0 0x00000000
+DATA 4 0x020e04b4 0x00000030
+DATA 4 0x020e04b8 0x00000030
+DATA 4 0x020e076c 0x00000030
+DATA 4 0x020e0750 0x00020000
+DATA 4 0x020e04bc 0x00000028
+DATA 4 0x020e04c0 0x00000028
+DATA 4 0x020e04c4 0x00000028
+DATA 4 0x020e04c8 0x00000028
+DATA 4 0x020e04cc 0x00000028
+DATA 4 0x020e04d0 0x00000028
+DATA 4 0x020e04d4 0x00000028
+DATA 4 0x020e04d8 0x00000028
+DATA 4 0x020e0760 0x00020000
+DATA 4 0x020e0764 0x00000028
+DATA 4 0x020e0770 0x00000028
+DATA 4 0x020e0778 0x00000028
+DATA 4 0x020e077c 0x00000028
+DATA 4 0x020e0780 0x00000028
+DATA 4 0x020e0784 0x00000028
+DATA 4 0x020e078c 0x00000028
+DATA 4 0x020e0748 0x00000028
+DATA 4 0x020e0470 0x00000028
+DATA 4 0x020e0474 0x00000028
+DATA 4 0x020e0478 0x00000028
+DATA 4 0x020e047c 0x00000028
+DATA 4 0x020e0480 0x00000028
+DATA 4 0x020e0484 0x00000028
+DATA 4 0x020e0488 0x00000028
+DATA 4 0x020e048c 0x00000028
+DATA 4 0x021b0800 0xa1390003
+DATA 4 0x021b080c 0x001F001F
+DATA 4 0x021b0810 0x001F001F
+DATA 4 0x021b480c 0x001F001F
+DATA 4 0x021b4810 0x001F001F
+DATA 4 0x021b083c 0x42190217
+DATA 4 0x021b0840 0x017B017B
+DATA 4 0x021b483c 0x4176017B
+DATA 4 0x021b4840 0x015F016C
+DATA 4 0x021b0848 0x4C4C4D4C
+DATA 4 0x021b4848 0x4A4D4C48
+DATA 4 0x021b0850 0x3F3F3F40
+DATA 4 0x021b4850 0x3538382E
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+DATA 4 0x021b481c 0x33333333
+DATA 4 0x021b4820 0x33333333
+DATA 4 0x021b4824 0x33333333
+DATA 4 0x021b4828 0x33333333
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b48b8 0x00000800
+DATA 4 0x021b0004 0x00020025
+DATA 4 0x021b0008 0x00333030
+DATA 4 0x021b000c 0x676B5313
+DATA 4 0x021b0010 0xB66E8B63
+DATA 4 0x021b0014 0x01FF00DB
+DATA 4 0x021b0018 0x00001740
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b002c 0x000026d2
+DATA 4 0x021b0030 0x006B1023
+DATA 4 0x021b0040 0x00000047
+DATA 4 0x021b0000 0x841A0000
+DATA 4 0x021b001c 0x04008032
+DATA 4 0x021b001c 0x00008033
+DATA 4 0x021b001c 0x00048031
+DATA 4 0x021b001c 0x05208030
+DATA 4 0x021b001c 0x04008040
+DATA 4 0x021b0020 0x00005800
+DATA 4 0x021b0818 0x00011117
+DATA 4 0x021b4818 0x00011117
+DATA 4 0x021b0004 0x00025565
+DATA 4 0x021b0404 0x00011006
+DATA 4 0x021b001c 0x00000000
+
+/* set the default clock gate to save power */
+DATA 4 0x020c4068 0x00C03F3F
+DATA 4 0x020c406c 0x0030FC03
+DATA 4 0x020c4070 0x0FFFF000
+DATA 4 0x020c4074 0x3FF00000
+DATA 4 0x020c4078 0xFFFFF300
+DATA 4 0x020c407c 0x0F0000C3
+DATA 4 0x020c4080 0x00000FFF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4 0x020e0010 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4 0x020e0018 0x007F007F
+DATA 4 0x020e001c 0x007F007F
+#endif
+/*
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+/* image version */
+
+#include <config.h>
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of spi, sd, eimnor, nand, sata:
+ * spinor: flash_offset: 0x0400
+ * nand:   flash_offset: 0x0400
+ * sata:   flash_offset: 0x0400
+ * sd/mmc: flash_offset: 0x0400
+ * eimnor: flash_offset: 0x1000
+ */
+
+#if defined(CONFIG_NOR_BOOT)
+BOOT_FROM       nor
+#else /* others has the same flash_offset as sd */
+BOOT_FROM       sd
+#endif
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN board/freescale/mx6sabreauto/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+DATA 4 0x020e0798 0x000C0000
+DATA 4 0x020e0758 0x00000000
+DATA 4 0x020e0588 0x00000030
+DATA 4 0x020e0594 0x00000030
+DATA 4 0x020e056c 0x00000030
+DATA 4 0x020e0578 0x00000030
+DATA 4 0x020e074c 0x00000030
+DATA 4 0x020e057c 0x00000030
+DATA 4 0x020e058c 0x00000000
+DATA 4 0x020e059c 0x00000030
+DATA 4 0x020e05a0 0x00000030
+DATA 4 0x020e078c 0x00000030
+DATA 4 0x020e0750 0x00020000
+DATA 4 0x020e05a8 0x00000030
+DATA 4 0x020e05b0 0x00000030
+DATA 4 0x020e0524 0x00000030
+DATA 4 0x020e051c 0x00000030
+DATA 4 0x020e0518 0x00000030
+DATA 4 0x020e050c 0x00000030
+DATA 4 0x020e05b8 0x00000030
+DATA 4 0x020e05c0 0x00000030
+DATA 4 0x020e0774 0x00020000
+DATA 4 0x020e0784 0x00000030
+DATA 4 0x020e0788 0x00000030
+DATA 4 0x020e0794 0x00000030
+DATA 4 0x020e079c 0x00000030
+DATA 4 0x020e07a0 0x00000030
+DATA 4 0x020e07a4 0x00000030
+DATA 4 0x020e07a8 0x00000030
+DATA 4 0x020e0748 0x00000030
+DATA 4 0x020e05ac 0x00000030
+DATA 4 0x020e05b4 0x00000030
+DATA 4 0x020e0528 0x00000030
+DATA 4 0x020e0520 0x00000030
+DATA 4 0x020e0514 0x00000030
+DATA 4 0x020e0510 0x00000030
+DATA 4 0x020e05bc 0x00000030
+DATA 4 0x020e05c4 0x00000030
+DATA 4 0x021b0800 0xa1390003
+DATA 4 0x021b080c 0x001b001e
+DATA 4 0x021b0810 0x002e0029
+DATA 4 0x021b480c 0x001b002a
+DATA 4 0x021b4810 0x0019002c
+DATA 4 0x021b083c 0x43240334
+DATA 4 0x021b0840 0x0324031a
+DATA 4 0x021b483c 0x43340344
+DATA 4 0x021b4840 0x03280276
+DATA 4 0x021b0848 0x44383A3E
+DATA 4 0x021b4848 0x3C3C3846
+DATA 4 0x021b0850 0x2e303230
+DATA 4 0x021b4850 0x38283E34
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+DATA 4 0x021b481c 0x33333333
+DATA 4 0x021b4820 0x33333333
+DATA 4 0x021b4824 0x33333333
+DATA 4 0x021b4828 0x33333333
+DATA 4 0x021b08c0 0x24912249
+DATA 4 0x021b48c0 0x24914289
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b48b8 0x00000800
+DATA 4 0x021b0004 0x00020036
+DATA 4 0x021b0008 0x24444040
+DATA 4 0x021b000c 0x898E7955
+DATA 4 0x021b0010 0xFF320F64
+DATA 4 0x021b0014 0x01FF00DB
+DATA 4 0x021b0018 0x00001740
+DATA 4 0x021b001c 0x00008000
+
+DATA 4 0x021b002c 0x000026d2
+DATA 4 0x021b0030 0x008E1023
+DATA 4 0x021b0040 0x00000047
+DATA 4 0x021b0400 0x14420000
+DATA 4 0x021b0000 0x841A0000
+DATA 4 0x021b0890 0x00400C58
+DATA 4 0x00bb0008 0x00000000
+DATA 4 0x00bb000c 0x2891E41A
+DATA 4 0x00bb0038 0x00000564
+DATA 4 0x00bb0014 0x00000040
+DATA 4 0x00bb0028 0x00000020
+DATA 4 0x00bb002c 0x00000020
+DATA 4 0x021b001c 0x04088032
+DATA 4 0x021b001c 0x00008033
+DATA 4 0x021b001c 0x00048031
+DATA 4 0x021b001c 0x09408030
+DATA 4 0x021b001c 0x04008040
+DATA 4 0x021b0020 0x00005800
+DATA 4 0x021b0818 0x00011117
+DATA 4 0x021b4818 0x00011117
+DATA 4 0x021b0004 0x00025576
+DATA 4 0x021b0404 0x00011006
+DATA 4 0x021b001c 0x00000000
+/* set the default clock gate to save power */
+DATA 4, 0x020c4068, 0x00C03F3F
+DATA 4, 0x020c406c, 0x0030FC03
+DATA 4, 0x020c4070, 0x0FFFF000
+DATA 4, 0x020c4074, 0x3FF00000
+DATA 4, 0x020c4078, 0xFFFFF300
+DATA 4, 0x020c407c, 0x0F0000F3
+DATA 4, 0x020c4080, 0x00000FFF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, 0x020e0010, 0xF00000CF
+/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
+DATA 4, 0x020e0018, 0x77177717
+DATA 4, 0x020e001c, 0x77177717
+#endif
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
  *
  * Author: Fabio Estevam <fabio.estevam@freescale.com>
  */
@@ -36,6 +37,16 @@
 #include <power/pfuze100_pmic.h>
 #include "../common/pfuze.h"
  
+#ifdef CONFIG_SATA
+#include <asm/mach-imx/sata.h>
+#endif
+#ifdef CONFIG_FSL_FASTBOOT
+#include <fsl_fastboot.h>
+#ifdef CONFIG_ANDROID_RECOVERY
+#include <recovery.h>
+#endif
+#endif /*CONFIG_FSL_FASTBOOT*/
+
 DECLARE_GLOBAL_DATA_PTR;
  
 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
@@ -46,6 +57,11 @@
 	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  
+/*Need more drive strength for SD1 slot on base board*/
+#define USDHC1_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |            \
+	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |               \
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  
  
@@ -60,10 +76,18 @@
  
 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  
+#define SPI_PAD_CTRL (PAD_CTL_HYS |				\
+	PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
+
 #define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |          \
 	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
 	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST)
  
+#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
 #define I2C_PMIC	1
  
 int dram_init(void)
  
  
  
  
  
  
  
  
  
@@ -78,65 +102,40 @@
 	IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 };
  
-
+#ifdef CONFIG_SYS_I2C_LEGACY
 /* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
-static struct i2c_pads_info mx6q_i2c_pad_info1 = {
+static struct i2c_pads_info i2c_pad_info1 = {
 	.scl = {
-		.i2c_mode = MX6Q_PAD_EIM_EB2__I2C2_SCL | PC,
-		.gpio_mode = MX6Q_PAD_EIM_EB2__GPIO2_IO30 | PC,
+		.i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
+		.gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
 		.gp = IMX_GPIO_NR(2, 30)
 	},
 	.sda = {
-		.i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
-		.gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
+		.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
+		.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 		.gp = IMX_GPIO_NR(4, 13)
 	}
 };
  
-static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
-	.scl = {
-		.i2c_mode = MX6DL_PAD_EIM_EB2__I2C2_SCL | PC,
-		.gpio_mode = MX6DL_PAD_EIM_EB2__GPIO2_IO30 | PC,
-		.gp = IMX_GPIO_NR(2, 30)
-	},
-	.sda = {
-		.i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
-		.gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
-		.gp = IMX_GPIO_NR(4, 13)
-	}
-};
-
 #ifndef CONFIG_SYS_FLASH_CFI
 /*
  * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
  * Compass Sensor, Accelerometer, Res Touch
  */
-static struct i2c_pads_info mx6q_i2c_pad_info2 = {
+static struct i2c_pads_info i2c_pad_info2 = {
 	.scl = {
-		.i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
-		.gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
+		.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
+		.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
 		.gp = IMX_GPIO_NR(1, 3)
 	},
 	.sda = {
-		.i2c_mode = MX6Q_PAD_EIM_D18__I2C3_SDA | PC,
-		.gpio_mode = MX6Q_PAD_EIM_D18__GPIO3_IO18 | PC,
+		.i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
+		.gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
 		.gp = IMX_GPIO_NR(3, 18)
 	}
 };
-
-static struct i2c_pads_info mx6dl_i2c_pad_info2 = {
-	.scl = {
-		.i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
-		.gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
-		.gp = IMX_GPIO_NR(1, 3)
-	},
-	.sda = {
-		.i2c_mode = MX6DL_PAD_EIM_D18__I2C3_SDA | PC,
-		.gpio_mode = MX6DL_PAD_EIM_D18__GPIO3_IO18 | PC,
-		.gp = IMX_GPIO_NR(3, 18)
-	}
-};
 #endif
+#endif
  
 static iomux_v3_cfg_t const i2c3_pads[] = {
 	IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04	| MUX_PAD_CTRL(NO_PAD_CTRL)),
@@ -245,6 +244,26 @@
 #endif
  
  
+static void setup_iomux_uart(void)
+{
+	SETUP_IOMUX_PADS(uart4_pads);
+}
+
+#ifdef CONFIG_FSL_ESDHC_IMX
+#if !CONFIG_IS_ENABLED(DM_MMC)
+static iomux_v3_cfg_t const usdhc1_pads[] = {
+	/*To avoid pin conflict with NAND, set usdhc1 to 4 pins*/
+	IOMUX_PADS(PAD_SD1_CLK__SD1_CLK	| MUX_PAD_CTRL(USDHC1_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_CMD__SD1_CMD	| MUX_PAD_CTRL(USDHC1_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0	| MUX_PAD_CTRL(USDHC1_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1	| MUX_PAD_CTRL(USDHC1_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2	| MUX_PAD_CTRL(USDHC1_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3	| MUX_PAD_CTRL(USDHC1_PAD_CTRL)),
+
+	/*CD pin*/
+	IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
 static iomux_v3_cfg_t const usdhc3_pads[] = {
 	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK		| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD		| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
  
  
  
  
  
@@ -260,30 +279,71 @@
 	IOMUX_PADS(PAD_NANDF_CS2__GPIO6_IO15	| MUX_PAD_CTRL(NO_PAD_CTRL)),
 };
  
-static void setup_iomux_uart(void)
-{
-	SETUP_IOMUX_PADS(uart4_pads);
-}
+#define USDHC1_CD_GPIO	IMX_GPIO_NR(1, 1)
+#define USDHC3_CD_GPIO	IMX_GPIO_NR(6, 15)
  
-#ifdef CONFIG_FSL_ESDHC_IMX
-static struct fsl_esdhc_cfg usdhc_cfg[1] = {
+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
+	{USDHC1_BASE_ADDR, 0, 4},
 	{USDHC3_BASE_ADDR},
 };
  
 int board_mmc_getcd(struct mmc *mmc)
 {
-	gpio_direction_input(IMX_GPIO_NR(6, 15));
-	return !gpio_get_value(IMX_GPIO_NR(6, 15));
+	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
+	int ret = 0;
+
+	switch (cfg->esdhc_base) {
+	case USDHC1_BASE_ADDR:
+		gpio_direction_input(USDHC1_CD_GPIO);
+		ret = !gpio_get_value(USDHC1_CD_GPIO);
+		break;
+	case USDHC3_BASE_ADDR:
+		gpio_direction_input(USDHC3_CD_GPIO);
+		ret = !gpio_get_value(USDHC3_CD_GPIO);
+		break;
+	}
+
+	return ret;
 }
  
 int board_mmc_init(struct bd_info *bis)
 {
-	SETUP_IOMUX_PADS(usdhc3_pads);
+	int i;
  
-	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+	/*
+	* According to the board_mmc_init() the following map is done:
+	* (U-boot device node)    (Physical Port)
+	* mmc0				USDHC1
+	* mmc1				USDHC3
+	*/
+	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
+		switch (i) {
+		case 0:
+			SETUP_IOMUX_PADS(usdhc1_pads);
+			gpio_request(USDHC1_CD_GPIO, "usdhc1 cd");
+			gpio_direction_input(USDHC1_CD_GPIO);
+			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+			break;
+		case 1:
+			SETUP_IOMUX_PADS(usdhc3_pads);
+			gpio_request(USDHC3_CD_GPIO, "usdhc3 cd");
+			gpio_direction_input(USDHC3_CD_GPIO);
+			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+			break;
+		default:
+			printf("Warning: you configured more USDHC controllers"
+				"(%d) than supported by the board\n", i + 1);
+			return 0;
+			}
+
+		if (fsl_esdhc_initialize(bis, &usdhc_cfg[i]))
+			printf("Warning: failed to initialize mmc dev %d\n", i);
+	}
+
+	return 0;
 }
 #endif
+#endif
  
 #ifdef CONFIG_NAND_MXS
 static iomux_v3_cfg_t gpmi_pads[] = {
@@ -321,6 +381,24 @@
 }
 #endif
  
+static void setup_fec(void)
+{
+	int ret;
+
+	if (is_mx6dqp()) {
+		/*
+		 * select ENET MAC0 TX clock from PLL
+		 */
+		imx_iomux_set_gpr_register(5, 9, 1, 1);
+	} else {
+		imx_iomux_set_gpr_register(1, 21, 1, 1);
+	}
+
+	ret = enable_fec_anatop_clock(0, ENET_125MHZ);
+	if (ret)
+		printf("Error fec anatop clock settings!\n");
+}
+
 #ifdef CONFIG_REVISION_TAG
 u32 get_board_rev(void)
 {
@@ -403,7 +481,7 @@
 	.bus	= -1,
 	.addr	= 0,
 	.pixfmt	= IPU_PIX_FMT_RGB24,
-	.detect	= detect_hdmi,
+	.detect	= NULL,
 	.enable	= do_enable_hdmi,
 	.mode	= {
 		.name           = "HDMI",
@@ -428,8 +506,22 @@
  
 static void setup_iomux_backlight(void)
 {
-	gpio_request(IMX_GPIO_NR(2, 9), "backlight");
-	gpio_direction_output(IMX_GPIO_NR(2, 9), 1);
+	int ret;
+	struct gpio_desc desc;
+
+	ret = dm_gpio_lookup_name("GPIO2_9", &desc);
+	if (ret) {
+		printf("%s lookup GPIO2_9 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	ret = dm_gpio_request(&desc, "backlight");
+	if (ret) {
+		printf("%s request backlight failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
 	SETUP_IOMUX_PADS(backlight_pads);
 }
  
@@ -497,6 +589,24 @@
 	return 1;
 }
  
+#ifdef CONFIG_MXC_SPI
+iomux_v3_cfg_t const ecspi1_pads[] = {
+	IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19  | MUX_PAD_CTRL(NO_PAD_CTRL)),
+	/* Steer logic */
+	IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04  | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+void setup_spinor(void)
+{
+	SETUP_IOMUX_PADS(ecspi1_pads);
+
+	gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
+}
+#endif
+
 int board_early_init_f(void)
 {
 	setup_iomux_uart();
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
@@ -513,65 +623,281 @@
  
 int board_init(void)
 {
+	int ret;
+	struct gpio_desc desc;
+
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  
+#ifdef CONFIG_SYS_I2C_LEGACY
 	/* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
-	if (is_mx6dq() || is_mx6dqp())
-		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
-	else
-		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
-	/* I2C 3 Steer */
-	gpio_request(IMX_GPIO_NR(5, 4), "steer logic");
-	gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
-	SETUP_IOMUX_PADS(i2c3_pads);
+	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 #ifndef CONFIG_SYS_FLASH_CFI
-	if (is_mx6dq() || is_mx6dqp())
-		setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2);
-	else
-		setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2);
+	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 #endif
-	gpio_request(IMX_GPIO_NR(1, 15), "expander en");
-	gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
+#endif
+
+	/* I2C 3 Steer */
+	ret = dm_gpio_lookup_name("GPIO5_4", &desc);
+	if (ret) {
+		printf("%s lookup GPIO5_4 failed ret = %d\n", __func__, ret);
+		return -ENODEV;
+	}
+	ret = dm_gpio_request(&desc, "steer logic");
+	if (ret) {
+		printf("%s request steer logic failed ret = %d\n", __func__, ret);
+		return -ENODEV;
+	}
+	dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+	SETUP_IOMUX_PADS(i2c3_pads);
+
+	ret = dm_gpio_lookup_name("GPIO1_15", &desc);
+	if (ret) {
+		printf("%s lookup GPIO1_15 failed ret = %d\n", __func__, ret);
+		return -ENODEV;
+	}
+	ret = dm_gpio_request(&desc, "expander en");
+	if (ret) {
+		printf("%s request steer logic failed ret = %d\n", __func__, ret);
+		return -ENODEV;
+	}
+	dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
 	SETUP_IOMUX_PADS(port_exp);
  
 #ifdef CONFIG_VIDEO_IPUV3
 	setup_display();
 #endif
  
+#ifdef CONFIG_MXC_SPI
+	setup_spinor();
+#endif
+
+#ifdef CONFIG_SATA
+	setup_sata();
+#endif
+
 #ifdef CONFIG_MTD_NOR_FLASH
 	setup_iomux_eimnor();
 #endif
-	return 0;
-}
  
-#ifdef CONFIG_MXC_SPI
-int board_spi_cs_gpio(unsigned bus, unsigned cs)
-{
-	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
-}
+#ifdef CONFIG_FEC_MXC
+	setup_fec();
 #endif
  
+	return 0;
+}
+
+#ifdef CONFIG_POWER_LEGACY
 int power_init_board(void)
 {
-	struct pmic *p;
+	struct pmic *pfuze;
 	unsigned int value;
+	int ret;
  
-	p = pfuze_common_init(I2C_PMIC);
-	if (!p)
+	pfuze = pfuze_common_init(I2C_PMIC);
+	if (!pfuze)
 		return -ENODEV;
  
+	if (is_mx6dqp())
+		ret = pfuze_mode_init(pfuze, APS_APS);
+	else
+		ret = pfuze_mode_init(pfuze, APS_PFM);
+
+	if (ret < 0)
+		return ret;
+
 	if (is_mx6dqp()) {
+		/* set SW1C staby volatage 1.075V*/
+		pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &value);
+		value &= ~0x3f;
+		value |= 0x1f;
+		pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, value);
+
+		/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
+		pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &value);
+		value &= ~0xc0;
+		value |= 0x40;
+		pmic_reg_write(pfuze, PFUZE100_SW1CCONF, value);
+
 		/* set SW2 staby volatage 0.975V*/
-		pmic_reg_read(p, PFUZE100_SW2STBY, &value);
+		pmic_reg_read(pfuze, PFUZE100_SW2STBY, &value);
 		value &= ~0x3f;
 		value |= 0x17;
-		pmic_reg_write(p, PFUZE100_SW2STBY, value);
+		pmic_reg_write(pfuze, PFUZE100_SW2STBY, value);
+
+		/* set SW2/VDDARM step ramp up time to from 16us to 4us/25mV */
+		pmic_reg_read(pfuze, PFUZE100_SW2CONF, &value);
+		value &= ~0xc0;
+		value |= 0x40;
+		pmic_reg_write(pfuze, PFUZE100_SW2CONF, value);
+	} else {
+		/* set SW1AB staby volatage 0.975V*/
+		pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, &value);
+		value &= ~0x3f;
+		value |= 0x1b;
+		pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, value);
+
+		/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+		pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, &value);
+		value &= ~0xc0;
+		value |= 0x40;
+		pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, value);
+
+		/* set SW1C staby volatage 0.975V*/
+		pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &value);
+		value &= ~0x3f;
+		value |= 0x1b;
+		pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, value);
+
+		/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
+		pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &value);
+		value &= ~0xc0;
+		value |= 0x40;
+		pmic_reg_write(pfuze, PFUZE100_SW1CCONF, value);
 	}
  
-	return pfuze_mode_init(p, APS_PFM);
+	return 0;
 }
+#elif defined(CONFIG_DM_PMIC_PFUZE100)
+int power_init_board(void)
+{
+	struct udevice *dev;
+	unsigned int reg;
+	int ret;
  
+	dev = pfuze_common_init();
+	if (!dev)
+		return -ENODEV;
+
+	if (is_mx6dqp())
+		ret = pfuze_mode_init(dev, APS_APS);
+	else
+		ret = pfuze_mode_init(dev, APS_PFM);
+	if (ret < 0)
+		return ret;
+
+	if (is_mx6dqp()) {
+		/* set SW1C staby volatage 1.075V*/
+		reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY);
+		reg &= ~0x3f;
+		reg |= 0x1f;
+		pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg);
+
+		/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
+		reg = pmic_reg_read(dev, PFUZE100_SW1CCONF);
+		reg &= ~0xc0;
+		reg |= 0x40;
+		pmic_reg_write(dev, PFUZE100_SW1CCONF, reg);
+
+		/* set SW2/VDDARM staby volatage 0.975V*/
+		reg = pmic_reg_read(dev, PFUZE100_SW2STBY);
+		reg &= ~0x3f;
+		reg |= 0x17;
+		pmic_reg_write(dev, PFUZE100_SW2STBY, reg);
+
+		/* set SW2/VDDARM step ramp up time to from 16us to 4us/25mV */
+		reg = pmic_reg_read(dev, PFUZE100_SW2CONF);
+		reg &= ~0xc0;
+		reg |= 0x40;
+		pmic_reg_write(dev, PFUZE100_SW2CONF, reg);
+	} else {
+		/* set SW1AB staby volatage 0.975V*/
+		reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY);
+		reg &= ~0x3f;
+		reg |= 0x1b;
+		pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg);
+
+		/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+		reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF);
+		reg &= ~0xc0;
+		reg |= 0x40;
+		pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg);
+
+		/* set SW1C staby volatage 0.975V*/
+		reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY);
+		reg &= ~0x3f;
+		reg |= 0x1b;
+		pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg);
+
+		/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
+		reg = pmic_reg_read(dev, PFUZE100_SW1CCONF);
+		reg &= ~0xc0;
+		reg |= 0x40;
+		pmic_reg_write(dev, PFUZE100_SW1CCONF, reg);
+	}
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_LDO_BYPASS_CHECK
+#ifdef CONFIG_POWER_LEGACY
+void ldo_mode_set(int ldo_bypass)
+{
+	unsigned int value;
+	struct pmic *p = pmic_get("PFUZE100");
+
+	if (!p) {
+		printf("No PMIC found!\n");
+		return;
+	}
+
+	/* increase VDDARM/VDDSOC to support 1.2G chip */
+	if (check_1_2G()) {
+		ldo_bypass = 0;	/* ldo_enable on 1.2G chip */
+		printf("1.2G chip, increase VDDARM_IN/VDDSOC_IN\n");
+
+		if (is_mx6dqp()) {
+			/* increase VDDARM to 1.425V */
+			pmic_reg_read(p, PFUZE100_SW2VOL, &value);
+			value &= ~0x3f;
+			value |= 0x29;
+			pmic_reg_write(p, PFUZE100_SW2VOL, value);
+		} else {
+			/* increase VDDARM to 1.425V */
+			pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
+			value &= ~0x3f;
+			value |= 0x2d;
+			pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
+		}
+		/* increase VDDSOC to 1.425V */
+		pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
+		value &= ~0x3f;
+		value |= 0x2d;
+		pmic_reg_write(p, PFUZE100_SW1CVOL, value);
+	}
+}
+#elif defined(CONFIG_DM_PMIC_PFUZE100)
+void ldo_mode_set(int ldo_bypass)
+{
+	struct udevice *dev;
+	int ret;
+
+	ret = pmic_get("pfuze100@8", &dev);
+	if (ret == -ENODEV) {
+		printf("No PMIC found!\n");
+		return;
+	}
+
+	/* increase VDDARM/VDDSOC to support 1.2G chip */
+	if (check_1_2G()) {
+		ldo_bypass = 0; /* ldo_enable on 1.2G chip */
+		printf("1.2G chip, increase VDDARM_IN/VDDSOC_IN\n");
+
+		if (is_mx6dqp()) {
+			/* increase VDDARM to 1.425V */
+			pmic_clrsetbits(dev, PFUZE100_SW2VOL, 0x3f, 0x29);
+		} else {
+			/* increase VDDARM to 1.425V */
+			pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, 0x2d);
+		}
+		/* increase VDDSOC to 1.425V */
+		pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, 0x2d);
+	}
+}
+#endif
+#endif
+
 #ifdef CONFIG_CMD_BMODE
 static const struct boot_mode board_boot_modes[] = {
 	/* 4 bit bus width */
@@ -627,6 +953,49 @@
 	return 0;
 }
 #endif
+
+#ifdef CONFIG_FSL_FASTBOOT
+#ifdef CONFIG_ANDROID_RECOVERY
+
+iomux_v3_cfg_t const recovery_key_pads[] = {
+	IOMUX_PADS(PAD_DISP0_DAT20__GPIO5_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+int is_recovery_key_pressing(void)
+{
+	int button_pressed = 0;
+	int ret;
+	struct gpio_desc desc;
+
+	/* Check Recovery Combo Button press or not. */
+	SETUP_IOMUX_PADS(recovery_key_pads);
+
+	ret = dm_gpio_lookup_name("GPIO5_14", &desc);
+	if (ret) {
+		printf("%s lookup GPIO5_14 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	ret = dm_gpio_request(&desc, "volume_dn_key");
+	if (ret) {
+		printf("%s request volume_dn_key failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN);
+
+	if (dm_gpio_get_value(&desc) == 0) { /* VOL_DN key is low assert */
+		button_pressed = 1;
+		printf("Recovery key pressed\n");
+	}
+
+	return  button_pressed;
+}
+
+#endif /*CONFIG_ANDROID_RECOVERY*/
+
+#endif /*CONFIG_FSL_FASTBOOT*/
+
  
 #ifdef CONFIG_SPL_BUILD
 #include <asm/arch/mx6-ddr.h>
+/*
+ * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of spi, sd, eimnor, nand, sata:
+ * spinor: flash_offset: 0x0400
+ * nand:   flash_offset: 0x0400
+ * sata:   flash_offset: 0x0400
+ * sd/mmc: flash_offset: 0x0400
+ * eimnor: flash_offset: 0x1000
+ */
+
+#if defined(CONFIG_NOR_BOOT)
+BOOT_FROM       nor
+#else /* others has the same flash_offset as sd */
+BOOT_FROM       sd
+#endif
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx6sabreauto/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+DATA 4, 0x020e0774, 0x000C0000
+DATA 4, 0x020e0754, 0x00000000
+DATA 4, 0x020e04ac, 0x00000030
+DATA 4, 0x020e04b0, 0x00000030
+DATA 4, 0x020e0464, 0x00000030
+DATA 4, 0x020e0490, 0x00000030
+DATA 4, 0x020e074c, 0x00000030
+DATA 4, 0x020e0494, 0x00000030
+DATA 4, 0x020e04a0, 0x00000000
+DATA 4, 0x020e04b4, 0x00000030
+DATA 4, 0x020e04b8, 0x00000030
+DATA 4, 0x020e076c, 0x00000030
+DATA 4, 0x020e0750, 0x00020000
+DATA 4, 0x020e04bc, 0x00000028
+DATA 4, 0x020e04c0, 0x00000028
+DATA 4, 0x020e04c4, 0x00000028
+DATA 4, 0x020e04c8, 0x00000028
+DATA 4, 0x020e0760, 0x00020000
+DATA 4, 0x020e0764, 0x00000028
+DATA 4, 0x020e0770, 0x00000028
+DATA 4, 0x020e0778, 0x00000028
+DATA 4, 0x020e077c, 0x00000028
+DATA 4, 0x020e0470, 0x00000028
+DATA 4, 0x020e0474, 0x00000028
+DATA 4, 0x020e0478, 0x00000028
+DATA 4, 0x020e047c, 0x00000028
+DATA 4, 0x021b0800, 0xa1390003
+DATA 4, 0x021b080c, 0x001F001F
+DATA 4, 0x021b0810, 0x001F001F
+DATA 4, 0x021b083c, 0x421C0216
+DATA 4, 0x021b0840, 0x017B017A
+DATA 4, 0x021b0848, 0x4B4A4E4C
+DATA 4, 0x021b0850, 0x3F3F3334
+DATA 4, 0x021b081c, 0x33333333
+DATA 4, 0x021b0820, 0x33333333
+DATA 4, 0x021b0824, 0x33333333
+DATA 4, 0x021b0828, 0x33333333
+DATA 4, 0x021b08b8, 0x00000800
+DATA 4, 0x021b0004, 0x00020025
+DATA 4, 0x021b0008, 0x00333030
+DATA 4, 0x021b000c, 0x676B5313
+DATA 4, 0x021b0010, 0xB66E8B63
+DATA 4, 0x021b0014, 0x01FF00DB
+DATA 4, 0x021b0018, 0x00001740
+DATA 4, 0x021b001c, 0x00008000
+DATA 4, 0x021b002c, 0x000026d2
+DATA 4, 0x021b0030, 0x006B1023
+DATA 4, 0x021b0040, 0x00000027
+DATA 4, 0x021b0000, 0x84190000
+DATA 4, 0x021b001c, 0x04008032
+DATA 4, 0x021b001c, 0x00008033
+DATA 4, 0x021b001c, 0x00048031
+DATA 4, 0x021b001c, 0x05208030
+DATA 4, 0x021b001c, 0x04008040
+DATA 4, 0x021b0020, 0x00005800
+DATA 4, 0x021b0818, 0x00011117
+DATA 4, 0x021b0004, 0x00025565
+DATA 4, 0x021b0404, 0x00011006
+DATA 4, 0x021b001c, 0x00000000
+
+/* set the default clock gate to save power */
+DATA 4, 0x020c4068, 0x00C03F3F
+DATA 4, 0x020c406c, 0x0030FC03
+DATA 4, 0x020c4070, 0x0FFFF000
+DATA 4, 0x020c4074, 0x3FF00000
+DATA 4, 0x020c4078, 0xFFFFF300
+DATA 4, 0x020c407c, 0x0F0000C3
+DATA 4, 0x020c4080, 0x00000FFF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, 0x020e0010, 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, 0x020e0018, 0x007F007F
+DATA 4, 0x020e001c, 0x007F007F
+#endif
+/*
+ * Copyright (C) 2012-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+
+/* DDR script */
+.macro imx6dqpsabreauto_ddr_setting
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0x000c0000
+	str r1, [r0, #0x798]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x758]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x588]
+	str r1, [r0, #0x594]
+	str r1, [r0, #0x56c]
+	str r1, [r0, #0x578]
+	str r1, [r0, #0x74c]
+	str r1, [r0, #0x57c]
+
+	ldr r1, =0x00000000
+	str r1, [r0, #0x58c]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x59c]
+	str r1, [r0, #0x5a0]
+	str r1, [r0, #0x78c]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x750]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x5a8]
+	str r1, [r0, #0x5b0]
+	str r1, [r0, #0x524]
+	str r1, [r0, #0x51c]
+	str r1, [r0, #0x518]
+	str r1, [r0, #0x50c]
+	str r1, [r0, #0x5b8]
+	str r1, [r0, #0x5c0]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x774]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x784]
+	str r1, [r0, #0x788]
+	str r1, [r0, #0x794]
+	str r1, [r0, #0x79c]
+	str r1, [r0, #0x7a0]
+	str r1, [r0, #0x7a4]
+	str r1, [r0, #0x7a8]
+	str r1, [r0, #0x748]
+	str r1, [r0, #0x5ac]
+	str r1, [r0, #0x5b4]
+	str r1, [r0, #0x528]
+	str r1, [r0, #0x520]
+	str r1, [r0, #0x514]
+	str r1, [r0, #0x510]
+	str r1, [r0, #0x5bc]
+	str r1, [r0, #0x5c4]
+
+	ldr r0, =MMDC_P0_BASE_ADDR
+	ldr r2, =0xa1390003
+	str r2, [r0, #0x800]
+
+	ldr r2, =0x001b001e
+	str r2, [r0, #0x80c]
+	ldr r2, =0x002e0029
+	str r2, [r0, #0x810]
+	ldr r1, =MMDC_P1_BASE_ADDR
+	ldr r2, =0x001b002a
+	str r2, [r1, #0x80c]
+	ldr r2, =0x0019002c
+	str r2, [r1, #0x810]
+
+	ldr r2, =0x43240334
+	str r2, [r0, #0x83c]
+	ldr r2, =0x0324031a
+	str r2, [r0, #0x840]
+
+	ldr r2, =0x43340344
+	str r2, [r1, #0x83c]
+	ldr r2, =0x03280276
+	str r2, [r1, #0x840]
+
+	ldr r2, =0x44383A3E
+	str r2, [r0, #0x848]
+	ldr r2, =0x3C3C3846
+	str r2, [r1, #0x848]
+
+	ldr r2, =0x2e303230
+	str r2, [r0, #0x850]
+	ldr r2, =0x38283E34
+	str r2, [r1, #0x850]
+
+	ldr r2, =0x33333333
+	str r2, [r0, #0x81c]
+	str r2, [r0, #0x820]
+	str r2, [r0, #0x824]
+	str r2, [r0, #0x828]
+	str r2, [r1, #0x81c]
+	str r2, [r1, #0x820]
+	str r2, [r1, #0x824]
+	str r2, [r1, #0x828]
+
+	ldr r2, =0x24912249
+	str r2, [r0, #0x8c0]
+	ldr r2, =0x24914289
+	str r2, [r1, #0x8c0]
+
+	ldr r2, =0x00000800
+	str r2, [r0, #0x8b8]
+	str r2, [r1, #0x8b8]
+
+	ldr r2, =0x00020036
+	str r2, [r0, #0x004]
+	ldr r2, =0x24444040
+	str r2, [r0, #0x008]
+
+	ldr r2, =0x898E7955
+	str r2, [r0, #0x00c]
+	ldr r2, =0xFF320F64
+	str r2, [r0, #0x010]
+
+	ldr r2, =0x01FF00DB
+	str r2, [r0, #0x014]
+	ldr r2, =0x00001740
+	str r2, [r0, #0x018]
+
+	ldr r2, =0x00008000
+	str r2, [r0, #0x01c]
+	ldr r2, =0x000026d2
+	str r2, [r0, #0x02c]
+	ldr r2, =0x008E1023
+	str r2, [r0, #0x030]
+	ldr r2, =0x00000047
+	str r2, [r0, #0x040]
+
+	ldr r2, =0x14420000
+	str r2, [r0, #0x400]
+	ldr r2, =0x841A0000
+	str r2, [r0, #0x000]
+
+	ldr r2, =0x00400C58
+	str r2, [r0, #0x890]
+
+	ldr r3, =0x00bb0000
+	ldr r2, =0x00000000
+	str r2, [r3, #0x008]
+	ldr r2, =0x2891E41A
+	str r2, [r3, #0x00c]
+	ldr r2, =0x00000564
+	str r2, [r3, #0x038]
+	ldr r2, =0x00000040
+	str r2, [r3, #0x014]
+	ldr r2, =0x00000020
+	str r2, [r3, #0x028]
+	str r2, [r3, #0x02c]
+
+	ldr r2, =0x04088032
+	str r2, [r0, #0x01c]
+	ldr r2, =0x00008033
+	str r2, [r0, #0x01c]
+	ldr r2, =0x00048031
+	str r2, [r0, #0x01c]
+	ldr r2, =0x09408030
+	str r2, [r0, #0x01c]
+	ldr r2, =0x04008040
+	str r2, [r0, #0x01c]
+
+	ldr r2, =0x00005800
+	str r2, [r0, #0x020]
+	ldr r2, =0x00011117
+	str r2, [r0, #0x818]
+	str r2, [r1, #0x818]
+	ldr r2, =0x00025576
+	str r2, [r0, #0x004]
+	ldr r2, =0x00011006
+	str r2, [r0, #0x404]
+	ldr r2, =0x00000000
+	str r2, [r0, #0x01c]
+.endm
+
+.macro imx6dqsabreauto_ddr_setting
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0x000c0000
+	str r1, [r0, #0x798]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x758]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x588]
+	str r1, [r0, #0x594]
+	str r1, [r0, #0x56c]
+	str r1, [r0, #0x578]
+	str r1, [r0, #0x74c]
+	str r1, [r0, #0x57c]
+
+	ldr r1, =0x00000000
+	str r1, [r0, #0x58c]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x59c]
+	str r1, [r0, #0x5a0]
+	str r1, [r0, #0x78c]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x750]
+
+	ldr r1, =0x00000028
+	str r1, [r0, #0x5a8]
+	str r1, [r0, #0x5b0]
+	str r1, [r0, #0x524]
+	str r1, [r0, #0x51c]
+	str r1, [r0, #0x518]
+	str r1, [r0, #0x50c]
+	str r1, [r0, #0x5b8]
+	str r1, [r0, #0x5c0]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x774]
+
+	ldr r1, =0x00000028
+	str r1, [r0, #0x784]
+	str r1, [r0, #0x788]
+	str r1, [r0, #0x794]
+	str r1, [r0, #0x79c]
+	str r1, [r0, #0x7a0]
+	str r1, [r0, #0x7a4]
+	str r1, [r0, #0x7a8]
+	str r1, [r0, #0x748]
+	str r1, [r0, #0x5ac]
+	str r1, [r0, #0x5b4]
+	str r1, [r0, #0x528]
+	str r1, [r0, #0x520]
+	str r1, [r0, #0x514]
+	str r1, [r0, #0x510]
+	str r1, [r0, #0x5bc]
+	str r1, [r0, #0x5c4]
+
+	ldr r0, =MMDC_P0_BASE_ADDR
+	ldr r2, =0xa1390003
+	str r2, [r0, #0x800]
+
+	ldr r2, =0x001F001F
+	str r2, [r0, #0x80c]
+	str r2, [r0, #0x810]
+	ldr r1, =MMDC_P1_BASE_ADDR
+	str r2, [r1, #0x80c]
+	str r2, [r1, #0x810]
+
+	ldr r2, =0x43260335
+	str r2, [r0, #0x83c]
+	ldr r2, =0x031A030B
+	str r2, [r0, #0x840]
+
+	ldr r2, =0x4323033B
+	str r2, [r1, #0x83c]
+	ldr r2, =0x0323026F
+	str r2, [r1, #0x840]
+
+	ldr r2, =0x483D4545
+	str r2, [r0, #0x848]
+	ldr r2, =0x44433E48
+	str r2, [r1, #0x848]
+
+	ldr r2, =0x41444840
+	str r2, [r0, #0x850]
+	ldr r2, =0x4835483E
+	str r2, [r1, #0x850]
+
+	ldr r2, =0x33333333
+	str r2, [r0, #0x81c]
+	str r2, [r0, #0x820]
+	str r2, [r0, #0x824]
+	str r2, [r0, #0x828]
+	str r2, [r1, #0x81c]
+	str r2, [r1, #0x820]
+	str r2, [r1, #0x824]
+	str r2, [r1, #0x828]
+
+	ldr r2, =0x00000800
+	str r2, [r0, #0x8b8]
+	str r2, [r1, #0x8b8]
+
+	ldr r2, =0x00020036
+	str r2, [r0, #0x004]
+	ldr r2, =0x09444040
+	str r2, [r0, #0x008]
+
+	ldr r2, =0x8A8F7955
+	str r2, [r0, #0x00c]
+	ldr r2, =0xFF328F64
+	str r2, [r0, #0x010]
+
+	ldr r2, =0x01FF00DB
+	str r2, [r0, #0x014]
+	ldr r2, =0x00001740
+	str r2, [r0, #0x018]
+
+	ldr r2, =0x00008000
+	str r2, [r0, #0x01c]
+	ldr r2, =0x000026d2
+	str r2, [r0, #0x02c]
+	ldr r2, =0x008F1023
+	str r2, [r0, #0x030]
+	ldr r2, =0x00000047
+	str r2, [r0, #0x040]
+
+	ldr r2, =0x841A0000
+	str r2, [r0, #0x000]
+
+	ldr r2, =0x04088032
+	str r2, [r0, #0x01c]
+	ldr r2, =0x00008033
+	str r2, [r0, #0x01c]
+	ldr r2, =0x00048031
+	str r2, [r0, #0x01c]
+	ldr r2, =0x09408030
+	str r2, [r0, #0x01c]
+	ldr r2, =0x04008040
+	str r2, [r0, #0x01c]
+
+	ldr r2, =0x00005800
+	str r2, [r0, #0x020]
+	ldr r2, =0x00011117
+	str r2, [r0, #0x818]
+	str r2, [r1, #0x818]
+	ldr r2, =0x00025576
+	str r2, [r0, #0x004]
+	ldr r2, =0x00011006
+	str r2, [r0, #0x404]
+	ldr r2, =0x00000000
+	str r2, [r0, #0x01c]
+.endm
+
+.macro imx6dlsabreauto_ddr_setting
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0x000c0000
+	str r1, [r0, #0x774]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x754]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x4ac]
+	str r1, [r0, #0x4b0]
+	str r1, [r0, #0x464]
+	str r1, [r0, #0x490]
+	str r1, [r0, #0x74c]
+	str r1, [r0, #0x494]
+
+	ldr r1, =0x00000000
+	str r1, [r0, #0x4a0]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x4b4]
+	str r1, [r0, #0x4b8]
+	str r1, [r0, #0x76c]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x750]
+
+	ldr r1, =0x00000028
+	str r1, [r0, #0x4bc]
+	str r1, [r0, #0x4c0]
+	str r1, [r0, #0x4c4]
+	str r1, [r0, #0x4c8]
+	str r1, [r0, #0x4cc]
+	str r1, [r0, #0x4d0]
+	str r1, [r0, #0x4d4]
+	str r1, [r0, #0x4d8]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x760]
+
+	ldr r1, =0x00000028
+	str r1, [r0, #0x764]
+	str r1, [r0, #0x770]
+	str r1, [r0, #0x778]
+	str r1, [r0, #0x77c]
+	str r1, [r0, #0x780]
+	str r1, [r0, #0x784]
+	str r1, [r0, #0x78c]
+	str r1, [r0, #0x748]
+	str r1, [r0, #0x470]
+	str r1, [r0, #0x474]
+	str r1, [r0, #0x478]
+	str r1, [r0, #0x47c]
+	str r1, [r0, #0x480]
+	str r1, [r0, #0x484]
+	str r1, [r0, #0x488]
+	str r1, [r0, #0x48c]
+
+	ldr r0, =MMDC_P0_BASE_ADDR
+	ldr r2, =0xa1390003
+	str r2, [r0, #0x800]
+
+	ldr r2, =0x001f001f
+	str r2, [r0, #0x80c]
+	str r2, [r0, #0x810]
+	ldr r1, =MMDC_P1_BASE_ADDR
+	str r2, [r1, #0x80c]
+	str r2, [r1, #0x810]
+
+	ldr r2, =0x42190217
+	str r2, [r0, #0x83c]
+	ldr r2, =0x017b017b
+	str r2, [r0, #0x840]
+
+	ldr r2, =0x4176017b
+	str r2, [r1, #0x83c]
+	ldr r2, =0x015f016c
+	str r2, [r1, #0x840]
+
+	ldr r2, =0x4c4c4d4c
+	str r2, [r0, #0x848]
+	ldr r2, =0x4a4d4c48
+	str r2, [r1, #0x848]
+
+	ldr r2, =0x3f3f3f40
+	str r2, [r0, #0x850]
+	ldr r2, =0x3538382e
+	str r2, [r1, #0x850]
+
+	ldr r2, =0x33333333
+	str r2, [r0, #0x81c]
+	str r2, [r0, #0x820]
+	str r2, [r0, #0x824]
+	str r2, [r0, #0x828]
+	str r2, [r1, #0x81c]
+	str r2, [r1, #0x820]
+	str r2, [r1, #0x824]
+	str r2, [r1, #0x828]
+
+	ldr r2, =0x00000800
+	str r2, [r0, #0x8b8]
+	str r2, [r1, #0x8b8]
+
+	ldr r2, =0x00020025
+	str r2, [r0, #0x004]
+	ldr r2, =0x00333030
+	str r2, [r0, #0x008]
+
+	ldr r2, =0x676b5313
+	str r2, [r0, #0x00c]
+	ldr r2, =0xb66e8b63
+	str r2, [r0, #0x010]
+
+	ldr r2, =0x01ff00db
+	str r2, [r0, #0x014]
+	ldr r2, =0x00001740
+	str r2, [r0, #0x018]
+
+	ldr r2, =0x00008000
+	str r2, [r0, #0x01c]
+	ldr r2, =0x000026d2
+	str r2, [r0, #0x02c]
+	ldr r2, =0x006b1023
+	str r2, [r0, #0x030]
+	ldr r2, =0x00000047
+	str r2, [r0, #0x040]
+
+	ldr r2, =0x841a0000
+	str r2, [r0, #0x000]
+
+	ldr r2, =0x04008032
+	str r2, [r0, #0x01c]
+	ldr r2, =0x00008033
+	str r2, [r0, #0x01c]
+	ldr r2, =0x00048031
+	str r2, [r0, #0x01c]
+	ldr r2, =0x05208030
+	str r2, [r0, #0x01c]
+	ldr r2, =0x04008040
+	str r2, [r0, #0x01c]
+
+	ldr r2, =0x00005800
+	str r2, [r0, #0x020]
+	ldr r2, =0x00011117
+	str r2, [r0, #0x818]
+	str r2, [r1, #0x818]
+	ldr r2, =0x00025565
+	str r2, [r0, #0x004]
+	ldr r2, =0x00011006
+	str r2, [r0, #0x404]
+	ldr r2, =0x00000000
+	str r2, [r0, #0x01c]
+.endm
+
+.macro imx6solosabreauto_ddr_setting
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0x000c0000
+	str r1, [r0, #0x774]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x754]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x4ac]
+	str r1, [r0, #0x4b0]
+	str r1, [r0, #0x464]
+	str r1, [r0, #0x490]
+	str r1, [r0, #0x74c]
+	str r1, [r0, #0x494]
+
+	ldr r1, =0x00000000
+	str r1, [r0, #0x4a0]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x4b4]
+	str r1, [r0, #0x4b8]
+	str r1, [r0, #0x76c]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x750]
+
+	ldr r1, =0x00000028
+	str r1, [r0, #0x4bc]
+	str r1, [r0, #0x4c0]
+	str r1, [r0, #0x4c4]
+	str r1, [r0, #0x4c8]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x760]
+
+	ldr r1, =0x00000028
+	str r1, [r0, #0x764]
+	str r1, [r0, #0x770]
+	str r1, [r0, #0x778]
+	str r1, [r0, #0x77c]
+	str r1, [r0, #0x470]
+	str r1, [r0, #0x474]
+	str r1, [r0, #0x478]
+	str r1, [r0, #0x47c]
+
+	ldr r0, =MMDC_P0_BASE_ADDR
+	ldr r2, =0xa1390003
+	str r2, [r0, #0x800]
+
+	ldr r2, =0x001F001F
+	str r2, [r0, #0x80c]
+	str r2, [r0, #0x810]
+
+	ldr r2, =0x421C0216
+	str r2, [r0, #0x83c]
+	ldr r2, =0x017B017A
+	str r2, [r0, #0x840]
+
+	ldr r2, =0x4B4A4E4C
+	str r2, [r0, #0x848]
+
+	ldr r2, =0x3F3F3334
+	str r2, [r0, #0x850]
+
+	ldr r2, =0x33333333
+	str r2, [r0, #0x81c]
+	str r2, [r0, #0x820]
+	str r2, [r0, #0x824]
+	str r2, [r0, #0x828]
+
+	ldr r2, =0x00000800
+	str r2, [r0, #0x8b8]
+
+	ldr r2, =0x00020025
+	str r2, [r0, #0x004]
+	ldr r2, =0x00333030
+	str r2, [r0, #0x008]
+
+	ldr r2, =0x676B5313
+	str r2, [r0, #0x00c]
+	ldr r2, =0xB66E8B63
+	str r2, [r0, #0x010]
+
+	ldr r2, =0x01FF00DB
+	str r2, [r0, #0x014]
+	ldr r2, =0x00001740
+	str r2, [r0, #0x018]
+
+	ldr r2, =0x00008000
+	str r2, [r0, #0x01c]
+	ldr r2, =0x000026d2
+	str r2, [r0, #0x02c]
+	ldr r2, =0x006B1023
+	str r2, [r0, #0x030]
+	ldr r2, =0x00000027
+	str r2, [r0, #0x040]
+
+	ldr r2, =0x84190000
+	str r2, [r0, #0x000]
+
+	ldr r2, =0x04008032
+	str r2, [r0, #0x01c]
+	ldr r2, =0x00008033
+	str r2, [r0, #0x01c]
+	ldr r2, =0x00048031
+	str r2, [r0, #0x01c]
+	ldr r2, =0x05208030
+	str r2, [r0, #0x01c]
+	ldr r2, =0x04008040
+	str r2, [r0, #0x01c]
+
+	ldr r2, =0x00005800
+	str r2, [r0, #0x020]
+	ldr r2, =0x00011117
+	str r2, [r0, #0x818]
+	ldr r2, =0x00025565
+	str r2, [r0, #0x004]
+	ldr r2, =0x00011006
+	str r2, [r0, #0x404]
+	ldr r2, =0x00000000
+	str r2, [r0, #0x01c]
+.endm
+
+.macro imx6_clock_gating
+	ldr r0, =CCM_BASE_ADDR
+	ldr r1, =0x00C03F3F
+	str r1, [r0, #0x068]
+	ldr r1, =0x0030FC03
+	str r1, [r0, #0x06c]
+	ldr r1, =0x0FFFF000
+	str r1, [r0, #0x070]
+	ldr r1, =0x3FF00000
+	str r1, [r0, #0x074]
+	ldr r1, =0xFFFFF300
+	str r1, [r0, #0x078]
+	ldr r1, =0x0F0000C3
+	str r1, [r0, #0x07c]
+	ldr r1, =0x00000FFF
+	str r1, [r0, #0x080]
+.endm
+
+.macro imx6_qos_setting
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0xF00000CF
+	str r1, [r0, #0x10]
+
+#if defined(CONFIG_MX6QP)
+	ldr r1, =0x77177717
+	str r1, [r0, #0x18]
+	str r1, [r0, #0x1c]
+#else
+	ldr r1, =0x007F007F
+	str r1, [r0, #0x18]
+	str r1, [r0, #0x1c]
+#endif
+.endm
+
+.macro imx6_ddr_setting
+#if defined (CONFIG_MX6S)
+	imx6solosabreauto_ddr_setting
+#elif defined (CONFIG_MX6DL)
+	imx6dlsabreauto_ddr_setting
+#elif defined (CONFIG_MX6QP)
+	imx6dqpsabreauto_ddr_setting
+#elif defined (CONFIG_MX6Q)
+	imx6dqsabreauto_ddr_setting
+#else
+	#error "SOC not configured"
+#endif
+.endm
+
+/* include the common plugin code here */
+#include <asm/arch/mx6_plugin.S>
-if TARGET_MX6SABRESD
+if TARGET_MX6SABRESD || TARGET_MX6SABRESD_COMMON
  
 config SYS_BOARD
 	default "mx6sabresd"
@@ -8,6 +8,9 @@
  
 config SYS_CONFIG_NAME
 	default "mx6sabresd"
+
+config SYS_TEXT_BASE
+    default 0x17800000
  
 endif
+/*
+ * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <config.h>
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+
+BOOT_FROM	sd
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN board/freescale/mx6sabresd/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *	Addr-type register length (1,2 or 4 bytes)
+ *	Address	  absolute address of the register
+ *	value	  value to be stored in the register
+ */
+DATA 4	0x020e0774 0x000C0000
+DATA 4	0x020e0754 0x00000000
+DATA 4	0x020e04ac 0x00000030
+DATA 4	0x020e04b0 0x00000030
+DATA 4	0x020e0464 0x00000030
+DATA 4	0x020e0490 0x00000030
+DATA 4	0x020e074c 0x00000030
+DATA 4	0x020e0494 0x00000030
+DATA 4	0x020e04a0 0x00000000
+DATA 4	0x020e04b4 0x00000030
+DATA 4	0x020e04b8 0x00000030
+DATA 4	0x020e076c 0x00000030
+DATA 4	0x020e0750 0x00020000
+DATA 4	0x020e04bc 0x00000030
+DATA 4	0x020e04c0 0x00000030
+DATA 4	0x020e04c4 0x00000030
+DATA 4	0x020e04c8 0x00000030
+DATA 4	0x020e04cc 0x00000030
+DATA 4	0x020e04d0 0x00000030
+DATA 4	0x020e04d4 0x00000030
+DATA 4	0x020e04d8 0x00000030
+DATA 4	0x020e0760 0x00020000
+DATA 4	0x020e0764 0x00000030
+DATA 4	0x020e0770 0x00000030
+DATA 4	0x020e0778 0x00000030
+DATA 4	0x020e077c 0x00000030
+DATA 4	0x020e0780 0x00000030
+DATA 4	0x020e0784 0x00000030
+DATA 4	0x020e078c 0x00000030
+DATA 4	0x020e0748 0x00000030
+DATA 4	0x020e0470 0x00000030
+DATA 4	0x020e0474 0x00000030
+DATA 4	0x020e0478 0x00000030
+DATA 4	0x020e047c 0x00000030
+DATA 4	0x020e0480 0x00000030
+DATA 4	0x020e0484 0x00000030
+DATA 4	0x020e0488 0x00000030
+DATA 4	0x020e048c 0x00000030
+DATA 4	0x021b0800 0xa1390003
+DATA 4	0x021b080c 0x001F001F
+DATA 4	0x021b0810 0x001F001F
+DATA 4	0x021b480c 0x001F001F
+DATA 4	0x021b4810 0x001F001F
+DATA 4	0x021b083c 0x4220021F
+DATA 4	0x021b0840 0x0207017E
+DATA 4	0x021b483c 0x4201020C
+DATA 4	0x021b4840 0x01660172
+DATA 4	0x021b0848 0x4A4D4E4D
+DATA 4	0x021b4848 0x4A4F5049
+DATA 4	0x021b0850 0x3F3C3D31
+DATA 4	0x021b4850 0x3238372B
+DATA 4	0x021b081c 0x33333333
+DATA 4	0x021b0820 0x33333333
+DATA 4	0x021b0824 0x33333333
+DATA 4	0x021b0828 0x33333333
+DATA 4	0x021b481c 0x33333333
+DATA 4	0x021b4820 0x33333333
+DATA 4	0x021b4824 0x33333333
+DATA 4	0x021b4828 0x33333333
+DATA 4	0x021b08b8 0x00000800
+DATA 4	0x021b48b8 0x00000800
+DATA 4	0x021b0004 0x0002002D
+DATA 4	0x021b0008 0x00333030
+DATA 4	0x021b000c 0x3F435313
+DATA 4	0x021b0010 0xB66E8B63
+DATA 4	0x021b0014 0x01FF00DB
+DATA 4	0x021b0018 0x00001740
+DATA 4	0x021b001c 0x00008000
+DATA 4	0x021b002c 0x000026d2
+DATA 4	0x021b0030 0x00431023
+DATA 4	0x021b0040 0x00000027
+DATA 4	0x021b0000 0x831A0000
+DATA 4	0x021b001c 0x04008032
+DATA 4	0x021b001c 0x00008033
+DATA 4	0x021b001c 0x00048031
+DATA 4	0x021b001c 0x05208030
+DATA 4 0x021b001c 0x04008040
+DATA 4	0x021b0020 0x00005800
+DATA 4	0x021b0818 0x00011117
+DATA 4	0x021b4818 0x00011117
+DATA 4	0x021b0004 0x0002556D
+DATA 4	0x021b0404 0x00011006
+DATA 4	0x021b001c 0x00000000
+
+/* set the default clock gate to save power */
+DATA 4 0x020c4068 0x00C03F3F
+DATA 4 0x020c406c 0x0030FC03
+DATA 4 0x020c4070 0x0FFFF000
+DATA 4 0x020c4074 0x3FF00000
+DATA 4 0x020c4078 0x00FFF300
+DATA 4 0x020c407c 0x0F0000C3
+DATA 4 0x020c4080 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4 0x020e0010 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4 0x020e0018 0x007F007F
+DATA 4 0x020e001c 0x007F007F
+#endif
+/*
+ * Copyright (C) 2011-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ * Jason Liu <r64343@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <config.h>
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM      sd
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN board/freescale/mx6sabresd/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *      Addr-type register length (1,2 or 4 bytes)
+ *      Address   absolute address of the register
+ *      value     value to be stored in the register
+ */
+DATA 4 0x020e0798 0x000C0000
+DATA 4 0x020e0758 0x00000000
+DATA 4 0x020e0588 0x00000030
+DATA 4 0x020e0594 0x00000030
+DATA 4 0x020e056c 0x00000030
+DATA 4 0x020e0578 0x00000030
+DATA 4 0x020e074c 0x00000030
+DATA 4 0x020e057c 0x00000030
+DATA 4 0x020e058c 0x00000000
+DATA 4 0x020e059c 0x00000030
+DATA 4 0x020e05a0 0x00000030
+DATA 4 0x020e078c 0x00000030
+DATA 4 0x020e0750 0x00020000
+DATA 4 0x020e05a8 0x00000030
+DATA 4 0x020e05b0 0x00000030
+DATA 4 0x020e0524 0x00000030
+DATA 4 0x020e051c 0x00000030
+DATA 4 0x020e0518 0x00000030
+DATA 4 0x020e050c 0x00000030
+DATA 4 0x020e05b8 0x00000030
+DATA 4 0x020e05c0 0x00000030
+DATA 4 0x020e0774 0x00020000
+DATA 4 0x020e0784 0x00000030
+DATA 4 0x020e0788 0x00000030
+DATA 4 0x020e0794 0x00000030
+DATA 4 0x020e079c 0x00000030
+DATA 4 0x020e07a0 0x00000030
+DATA 4 0x020e07a4 0x00000030
+DATA 4 0x020e07a8 0x00000030
+DATA 4 0x020e0748 0x00000030
+DATA 4 0x020e05ac 0x00000030
+DATA 4 0x020e05b4 0x00000030
+DATA 4 0x020e0528 0x00000030
+DATA 4 0x020e0520 0x00000030
+DATA 4 0x020e0514 0x00000030
+DATA 4 0x020e0510 0x00000030
+DATA 4 0x020e05bc 0x00000030
+DATA 4 0x020e05c4 0x00000030
+DATA 4 0x021b0800 0xa1390003
+DATA 4 0x021b080c 0x001F001F
+DATA 4 0x021b0810 0x001F001F
+DATA 4 0x021b480c 0x001F001F
+DATA 4 0x021b4810 0x001F001F
+DATA 4 0x021b083c 0x43270338
+DATA 4 0x021b0840 0x03200314
+DATA 4 0x021b483c 0x431A032F
+DATA 4 0x021b4840 0x03200263
+DATA 4 0x021b0848 0x4B434748
+DATA 4 0x021b4848 0x4445404C
+DATA 4 0x021b0850 0x38444542
+DATA 4 0x021b4850 0x4935493A
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+DATA 4 0x021b481c 0x33333333
+DATA 4 0x021b4820 0x33333333
+DATA 4 0x021b4824 0x33333333
+DATA 4 0x021b4828 0x33333333
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b48b8 0x00000800
+DATA 4 0x021b0004 0x00020036
+DATA 4 0x021b0008 0x09444040
+DATA 4 0x021b000c 0x555A7975
+DATA 4 0x021b0010 0xFF538F64
+DATA 4 0x021b0014 0x01FF00DB
+DATA 4 0x021b0018 0x00001740
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b002c 0x000026d2
+DATA 4 0x021b0030 0x005A1023
+DATA 4 0x021b0040 0x00000027
+DATA 4 0x021b0000 0x831A0000
+DATA 4 0x021b001c 0x04088032
+DATA 4 0x021b001c 0x00008033
+DATA 4 0x021b001c 0x00048031
+DATA 4 0x021b001c 0x09408030
+DATA 4 0x021b001c 0x04008040
+DATA 4 0x021b0020 0x00005800
+DATA 4 0x021b0818 0x00011117
+DATA 4 0x021b4818 0x00011117
+DATA 4 0x021b0004 0x00025576
+DATA 4 0x021b0404 0x00011006
+DATA 4 0x021b001c 0x00000000
+
+/* set the default clock gate to save power */
+DATA 4 0x020c4068 0x00C03F3F
+DATA 4 0x020c406c 0x0030FC03
+DATA 4 0x020c4070 0x0FFFF000
+DATA 4 0x020c4074 0x3FF00000
+DATA 4 0x020c4078 0x00FFF300
+DATA 4 0x020c407c 0x0F0000F3
+DATA 4 0x020c4080 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4 0x020e0010 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4 0x020e0018 0x007F007F
+DATA 4 0x020e001c 0x007F007F
+
+/*
+ * Setup CCM_CCOSR register as follows:
+ *
+ * cko1_en  = 1	   --> CKO1 enabled
+ * cko1_div = 111  --> divide by 8
+ * cko1_sel = 1011 --> ahb_clk_root
+ *
+ * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
+ */
+DATA 4 0x020c4060 0x000000fb
+#endif
+/*
+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <config.h>
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM      sd
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN	board/freescale/mx6sabresd/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *      Addr-type register length (1,2 or 4 bytes)
+ *      Address   absolute address of the register
+ *      value     value to be stored in the register
+ */
+DATA 4, 0x020e0798, 0x000c0000
+DATA 4, 0x020e0758, 0x00000000
+DATA 4, 0x020e0588, 0x00000030
+DATA 4, 0x020e0594, 0x00000030
+DATA 4, 0x020e056c, 0x00000030
+DATA 4, 0x020e0578, 0x00000030
+DATA 4, 0x020e074c, 0x00000030
+DATA 4, 0x020e057c, 0x00000030
+DATA 4, 0x020e058c, 0x00000000
+DATA 4, 0x020e059c, 0x00000030
+DATA 4, 0x020e05a0, 0x00000030
+DATA 4, 0x020e078c, 0x00000030
+DATA 4, 0x020e0750, 0x00020000
+DATA 4, 0x020e05a8, 0x00000030
+DATA 4, 0x020e05b0, 0x00000030
+DATA 4, 0x020e0524, 0x00000030
+DATA 4, 0x020e051c, 0x00000030
+DATA 4, 0x020e0518, 0x00000030
+DATA 4, 0x020e050c, 0x00000030
+DATA 4, 0x020e05b8, 0x00000030
+DATA 4, 0x020e05c0, 0x00000030
+
+DATA 4, 0x020e0534, 0x00018200
+DATA 4, 0x020e0538, 0x00008000
+DATA 4, 0x020e053c, 0x00018200
+DATA 4, 0x020e0540, 0x00018200
+DATA 4, 0x020e0544, 0x00018200
+DATA 4, 0x020e0548, 0x00018200
+DATA 4, 0x020e054c, 0x00018200
+DATA 4, 0x020e0550, 0x00018200
+
+DATA 4, 0x020e0774, 0x00020000
+DATA 4, 0x020e0784, 0x00000030
+DATA 4, 0x020e0788, 0x00000030
+DATA 4, 0x020e0794, 0x00000030
+DATA 4, 0x020e079c, 0x00000030
+DATA 4, 0x020e07a0, 0x00000030
+DATA 4, 0x020e07a4, 0x00000030
+DATA 4, 0x020e07a8, 0x00000030
+DATA 4, 0x020e0748, 0x00000030
+DATA 4, 0x020e05ac, 0x00000030
+DATA 4, 0x020e05b4, 0x00000030
+DATA 4, 0x020e0528, 0x00000030
+DATA 4, 0x020e0520, 0x00000030
+DATA 4, 0x020e0514, 0x00000030
+DATA 4, 0x020e0510, 0x00000030
+DATA 4, 0x020e05bc, 0x00000030
+DATA 4, 0x020e05c4, 0x00000030
+DATA 4, 0x021b0800, 0xa1390003
+DATA 4, 0x021b080c, 0x001b001e
+DATA 4, 0x021b0810, 0x002e0029
+DATA 4, 0x021b480c, 0x001b002a
+DATA 4, 0x021b4810, 0x0019002c
+DATA 4, 0x021b083c, 0x43240334
+DATA 4, 0x021b0840, 0x0324031a
+DATA 4, 0x021b483c, 0x43340344
+DATA 4, 0x021b4840, 0x03280276
+DATA 4, 0x021b0848, 0x44383A3E
+DATA 4, 0x021b4848, 0x3C3C3846
+DATA 4, 0x021b0850, 0x2e303230
+DATA 4, 0x021b4850, 0x38283E34
+DATA 4, 0x021b081c, 0x33333333
+DATA 4, 0x021b0820, 0x33333333
+DATA 4, 0x021b0824, 0x33333333
+DATA 4, 0x021b0828, 0x33333333
+DATA 4, 0x021b481c, 0x33333333
+DATA 4, 0x021b4820, 0x33333333
+DATA 4, 0x021b4824, 0x33333333
+DATA 4, 0x021b4828, 0x33333333
+DATA 4, 0x021b08c0, 0x24912489
+DATA 4, 0x021b48c0, 0x24914452
+DATA 4, 0x021b08b8, 0x00000800
+DATA 4, 0x021b48b8, 0x00000800
+DATA 4, 0x021b0004, 0x00020036
+DATA 4, 0x021b0008, 0x24444040
+DATA 4, 0x021b000c, 0x555A7955
+DATA 4, 0x021b0010, 0xFF320F64
+DATA 4, 0x021b0014, 0x01ff00db
+DATA 4, 0x021b0018, 0x00011740
+DATA 4, 0x021b001c, 0x00008000
+DATA 4, 0x021b002c, 0x000026d2
+DATA 4, 0x021b0030, 0x005A1023
+DATA 4, 0x021b0040, 0x00000027
+DATA 4, 0x021b0400, 0x14420000
+DATA 4, 0x021b0000, 0x831A0000
+DATA 4, 0x021b0890, 0x00400C58
+DATA 4, 0x00bb0008, 0x00000000
+DATA 4, 0x00bb000c, 0x2891E41A
+DATA 4, 0x00bb0038, 0x00000564
+DATA 4, 0x00bb0014, 0x00000040
+DATA 4, 0x00bb0028, 0x00000020
+DATA 4, 0x00bb002c, 0x00000020
+DATA 4, 0x021b001c, 0x04088032
+DATA 4, 0x021b001c, 0x00008033
+DATA 4, 0x021b001c, 0x00048031
+DATA 4, 0x021b001c, 0x09408030
+DATA 4, 0x021b001c, 0x04008040
+DATA 4, 0x021b0020, 0x00005800
+DATA 4, 0x021b0818, 0x00011117
+DATA 4, 0x021b4818, 0x00011117
+DATA 4, 0x021b0004, 0x00025576
+DATA 4, 0x021b0404, 0x00011006
+DATA 4, 0x021b001c, 0x00000000
+
+/* set the default clock gate to save power */
+DATA 4, 0x020c4068, 0x00C03F3F
+DATA 4, 0x020c406c, 0x0030FC03
+DATA 4, 0x020c4070, 0x0FFFF000
+DATA 4, 0x020c4074, 0x3FF00000
+DATA 4, 0x020c4078, 0x00FFF300
+DATA 4, 0x020c407c, 0x0F0000F3
+DATA 4, 0x020c4080, 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, 0x020e0010, 0xF00000CF
+/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
+DATA 4, 0x020e0018, 0x77177717
+DATA 4, 0x020e001c, 0x77177717
+#endif
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright (C) 2012-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
  *
  * Author: Fabio Estevam <fabio.estevam@freescale.com>
  */
@@ -16,6 +17,7 @@
 #include <asm/mach-imx/spi.h>
 #include <env.h>
 #include <linux/errno.h>
+#include <linux/delay.h>
 #include <asm/gpio.h>
 #include <asm/mach-imx/mxc_i2c.h>
 #include <asm/mach-imx/iomux-v3.h>
@@ -35,6 +37,20 @@
 #include "../common/pfuze.h"
 #include <usb.h>
 #include <usb/ehci-ci.h>
+#include <asm/arch/mx6-ddr.h>
+#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)
+#include <lcd.h>
+#include <mxc_epdc_fb.h>
+#endif
+#ifdef CONFIG_SATA
+#include <asm/mach-imx/sata.h>
+#endif
+#ifdef CONFIG_FSL_FASTBOOT
+#include <fsl_fastboot.h>
+#ifdef CONFIG_ANDROID_RECOVERY
+#include <recovery.h>
+#endif
+#endif /*CONFIG_FSL_FASTBOOT*/
  
 DECLARE_GLOBAL_DATA_PTR;
  
  
@@ -53,12 +69,18 @@
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
 	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  
+#define EPDC_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_SPEED_MED |	\
+	PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |		\
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+
 #define I2C_PMIC	1
  
 #define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
  
-#define DISP0_PWR_EN	IMX_GPIO_NR(1, 21)
-
 #define KEY_VOL_UP	IMX_GPIO_NR(1, 4)
  
 int dram_init(void)
@@ -72,47 +94,7 @@
 	IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
 };
  
-static iomux_v3_cfg_t const usdhc2_pads[] = {
-	IOMUX_PADS(PAD_SD2_CLK__SD2_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD2_CMD__SD2_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02	| MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
-};
-
-static iomux_v3_cfg_t const usdhc3_pads[] = {
-	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00    | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
-};
-
-static iomux_v3_cfg_t const usdhc4_pads[] = {
-	IOMUX_PADS(PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-	IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
-};
-
+#ifdef CONFIG_MXC_SPI
 static iomux_v3_cfg_t const ecspi1_pads[] = {
 	IOMUX_PADS(PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 	IOMUX_PADS(PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
@@ -120,6 +102,12 @@
 	IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 };
  
+static void setup_spi(void)
+{
+	SETUP_IOMUX_PADS(ecspi1_pads);
+}
+#endif
+
 static iomux_v3_cfg_t const rgb_pads[] = {
 	IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL)),
 	IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
  
@@ -158,9 +146,20 @@
  
 static void enable_backlight(void)
 {
+	struct gpio_desc desc;
+	int ret;
+
 	SETUP_IOMUX_PADS(bl_pads);
-	gpio_request(DISP0_PWR_EN, "Display Power Enable");
-	gpio_direction_output(DISP0_PWR_EN, 1);
+
+	ret = dm_gpio_lookup_name("GPIO1_21", &desc);
+	if (ret)
+		return;
+
+	ret = dm_gpio_request(&desc, "Display Power Enable");
+	if (ret)
+		return;
+
+	dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
 }
  
 static void enable_rgb(struct display_info_t const *dev)
  
  
  
  
  
  
  
@@ -174,36 +173,34 @@
 	enable_backlight();
 }
  
-static struct i2c_pads_info mx6q_i2c_pad_info1 = {
+#ifdef CONFIG_SYS_I2C_LEGACY
+static struct i2c_pads_info i2c_pad_info1 = {
 	.scl = {
-		.i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
-		.gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
+		.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
+		.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
 		.gp = IMX_GPIO_NR(4, 12)
 	},
 	.sda = {
-		.i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
-		.gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
+		.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
+		.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
 		.gp = IMX_GPIO_NR(4, 13)
 	}
 };
+#endif
  
-static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
-	.scl = {
-		.i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
-		.gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
-		.gp = IMX_GPIO_NR(4, 12)
-	},
-	.sda = {
-		.i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
-		.gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
-		.gp = IMX_GPIO_NR(4, 13)
-	}
+#ifdef CONFIG_PCIE_IMX
+iomux_v3_cfg_t const pcie_pads[] = {
+	IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),	/* POWER */
+	IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL)),	/* RESET */
 };
  
-static void setup_spi(void)
+static void setup_pcie(void)
 {
-	SETUP_IOMUX_PADS(ecspi1_pads);
+	SETUP_IOMUX_PADS(pcie_pads);
+	gpio_request(CONFIG_PCIE_IMX_POWER_GPIO, "PCIE Power Enable");
+	gpio_request(CONFIG_PCIE_IMX_PERST_GPIO, "PCIE Reset");
 }
+#endif
  
 iomux_v3_cfg_t const di0_pads[] = {
 	IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK),	/* DISP0_CLK */
  
@@ -216,7 +213,97 @@
 	SETUP_IOMUX_PADS(uart1_pads);
 }
  
+#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)
+static iomux_v3_cfg_t const epdc_enable_pads[] = {
+	IOMUX_PADS(PAD_EIM_A16__EPDC_DATA00	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA10__EPDC_DATA01	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA12__EPDC_DATA02	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA11__EPDC_DATA03	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_LBA__EPDC_DATA04	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_EB2__EPDC_DATA05	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_CS0__EPDC_DATA06	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_RW__EPDC_DATA07	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A21__EPDC_GDCLK	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A22__EPDC_GDSP	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A23__EPDC_GDOE	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A24__EPDC_GDRL	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D31__EPDC_SDCLK_P	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D27__EPDC_SDOE	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA1__EPDC_SDLE	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_EB1__EPDC_SDSHR	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA2__EPDC_BDR0	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA4__EPDC_SDCE0	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA5__EPDC_SDCE1	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_DA6__EPDC_SDCE2	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+};
+
+static iomux_v3_cfg_t const epdc_disable_pads[] = {
+	IOMUX_PADS(PAD_EIM_A16__GPIO2_IO22),
+	IOMUX_PADS(PAD_EIM_DA10__GPIO3_IO10),
+	IOMUX_PADS(PAD_EIM_DA12__GPIO3_IO12),
+	IOMUX_PADS(PAD_EIM_DA11__GPIO3_IO11),
+	IOMUX_PADS(PAD_EIM_LBA__GPIO2_IO27),
+	IOMUX_PADS(PAD_EIM_EB2__GPIO2_IO30),
+	IOMUX_PADS(PAD_EIM_CS0__GPIO2_IO23),
+	IOMUX_PADS(PAD_EIM_RW__GPIO2_IO26),
+	IOMUX_PADS(PAD_EIM_A21__GPIO2_IO17),
+	IOMUX_PADS(PAD_EIM_A22__GPIO2_IO16),
+	IOMUX_PADS(PAD_EIM_A23__GPIO6_IO06),
+	IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04),
+	IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31),
+	IOMUX_PADS(PAD_EIM_D27__GPIO3_IO27),
+	IOMUX_PADS(PAD_EIM_DA1__GPIO3_IO01),
+	IOMUX_PADS(PAD_EIM_EB1__GPIO2_IO29),
+	IOMUX_PADS(PAD_EIM_DA2__GPIO3_IO02),
+	IOMUX_PADS(PAD_EIM_DA4__GPIO3_IO04),
+	IOMUX_PADS(PAD_EIM_DA5__GPIO3_IO05),
+	IOMUX_PADS(PAD_EIM_DA6__GPIO3_IO06),
+};
+#endif
+
 #ifdef CONFIG_FSL_ESDHC_IMX
+#if !CONFIG_IS_ENABLED(DM_MMC)
+static iomux_v3_cfg_t const usdhc2_pads[] = {
+	IOMUX_PADS(PAD_SD2_CLK__SD2_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_CMD__SD2_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7	| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02	| MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
+};
+
+static iomux_v3_cfg_t const usdhc3_pads[] = {
+	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00    | MUX_PAD_CTRL(NO_PAD_CTRL)), /* CD */
+};
+
+static iomux_v3_cfg_t const usdhc4_pads[] = {
+	IOMUX_PADS(PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+	IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+};
+
 struct fsl_esdhc_cfg usdhc_cfg[3] = {
 	{USDHC2_BASE_ADDR},
 	{USDHC3_BASE_ADDR},
@@ -226,11 +313,6 @@
 #define USDHC2_CD_GPIO	IMX_GPIO_NR(2, 2)
 #define USDHC3_CD_GPIO	IMX_GPIO_NR(2, 0)
  
-int board_mmc_get_env_dev(int devno)
-{
-	return devno - 1;
-}
-
 int board_mmc_getcd(struct mmc *mmc)
 {
 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  
  
  
@@ -288,21 +370,28 @@
 	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
 }
 #endif
+#endif
  
 static int ar8031_phy_fixup(struct phy_device *phydev)
 {
 	unsigned short val;
  
 	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+	if (!is_mx6dqp()) {
+		phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+		phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+		phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
  
-	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
-	val &= 0xffe3;
-	val |= 0x18;
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+		val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+		val &= 0xffe3;
+		val |= 0x18;
+		phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+	}
  
+	/* set the IO voltage to 1.8v */
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
+	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
+
 	/* introduce tx clock delay */
 	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
@@ -322,6 +411,227 @@
 	return 0;
 }
  
+#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)
+vidinfo_t panel_info = {
+	.vl_refresh = 85,
+	.vl_col = 800,
+	.vl_row = 600,
+	.vl_pixclock = 26666667,
+	.vl_left_margin = 8,
+	.vl_right_margin = 100,
+	.vl_upper_margin = 4,
+	.vl_lower_margin = 8,
+	.vl_hsync = 4,
+	.vl_vsync = 1,
+	.vl_sync = 0,
+	.vl_mode = 0,
+	.vl_flag = 0,
+	.vl_bpix = 3,
+	.cmap = 0,
+};
+
+struct epdc_timing_params panel_timings = {
+	.vscan_holdoff = 4,
+	.sdoed_width = 10,
+	.sdoed_delay = 20,
+	.sdoez_width = 10,
+	.sdoez_delay = 20,
+	.gdclk_hp_offs = 419,
+	.gdsp_offs = 20,
+	.gdoe_offs = 0,
+	.gdclk_offs = 5,
+	.num_ce = 1,
+};
+
+static iomux_v3_cfg_t const epdc_pwr_ctrl_pads[] = {
+	IOMUX_PADS(PAD_EIM_A17__GPIO2_IO21	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D17__GPIO3_IO17	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_D20__GPIO3_IO20	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+	IOMUX_PADS(PAD_EIM_A18__GPIO2_IO20	| MUX_PAD_CTRL(EPDC_PAD_CTRL)),
+};
+
+struct gpio_desc epd_pwrstat_desc;
+struct gpio_desc epd_vcom_desc;
+struct gpio_desc epd_wakeup_desc;
+struct gpio_desc epd_pwr_ctl0_desc;
+
+static void setup_epdc_power(void)
+{
+	int ret;
+
+	SETUP_IOMUX_PADS(epdc_pwr_ctrl_pads);
+
+	/* Setup epdc voltage */
+
+	/* EIM_A17 - GPIO2[21] for PWR_GOOD status */
+	/* Set as input */
+	ret = dm_gpio_lookup_name("GPIO2_21", &epd_pwrstat_desc);
+	if (ret) {
+		printf("%s lookup GPIO2_21 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	ret = dm_gpio_request(&epd_pwrstat_desc, "EPDC PWRSTAT");
+	if (ret) {
+		printf("%s request EPDC PWRSTAT failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	dm_gpio_set_dir_flags(&epd_pwrstat_desc, GPIOD_IS_IN);
+
+	/* EIM_D17 - GPIO3[17] for VCOM control */
+	/* Set as output */
+	ret = dm_gpio_lookup_name("GPIO3_17", &epd_vcom_desc);
+	if (ret) {
+		printf("%s lookup GPIO3_17 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	ret = dm_gpio_request(&epd_vcom_desc, "EPDC VCOM0");
+	if (ret) {
+		printf("%s request EPDC VCOM0 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	dm_gpio_set_dir_flags(&epd_vcom_desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+
+	/* EIM_D20 - GPIO3[20] for EPD PMIC WAKEUP */
+	/* Set as output */
+	ret = dm_gpio_lookup_name("GPIO3_20", &epd_wakeup_desc);
+	if (ret) {
+		printf("%s lookup GPIO3_20 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	ret = dm_gpio_request(&epd_wakeup_desc, "EPDC PWR WAKEUP");
+	if (ret) {
+		printf("%s request EPDC PWR WAKEUP failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	dm_gpio_set_dir_flags(&epd_wakeup_desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+
+	/* EIM_A18 - GPIO2[20] for EPD PWR CTL0 */
+	/* Set as output */
+	ret = dm_gpio_lookup_name("GPIO2_20", &epd_pwr_ctl0_desc);
+	if (ret) {
+		printf("%s lookup GPIO2_20 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	ret = dm_gpio_request(&epd_pwr_ctl0_desc, "EPDC PWR CTRL0");
+	if (ret) {
+		printf("%s request EPDC PWR CTRL0 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	dm_gpio_set_dir_flags(&epd_pwr_ctl0_desc, GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
+}
+
+static void epdc_enable_pins(void)
+{
+	/* epdc iomux settings */
+	SETUP_IOMUX_PADS(epdc_enable_pads);
+}
+
+static void epdc_disable_pins(void)
+{
+	/* Configure MUX settings for EPDC pins to GPIO */
+	SETUP_IOMUX_PADS(epdc_disable_pads);
+}
+
+static void setup_epdc(void)
+{
+	unsigned int reg;
+	struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+	/*** Set pixel clock rates for EPDC ***/
+
+	/* EPDC AXI clk (IPU2_CLK) from PFD_400M, set to 396/2 = 198MHz */
+	reg = readl(&ccm_regs->cscdr3);
+	reg &= ~0x7C000;
+	reg |= (1 << 16) | (1 << 14);
+	writel(reg, &ccm_regs->cscdr3);
+
+	/* EPDC AXI clk enable */
+	reg = readl(&ccm_regs->CCGR3);
+	reg |= 0x00C0;
+	writel(reg, &ccm_regs->CCGR3);
+
+	/* EPDC PIX clk (IPU2_DI1_CLK) from PLL5, set to 650/4/6 = ~27MHz */
+	reg = readl(&ccm_regs->cscdr2);
+	reg &= ~0x3FE00;
+	reg |= (2 << 15) | (5 << 12);
+	writel(reg, &ccm_regs->cscdr2);
+
+	/* PLL5 enable (defaults to 650) */
+	reg = readl(&ccm_regs->analog_pll_video);
+	reg &= ~((1 << 16) | (1 << 12));
+	reg |= (1 << 13);
+	writel(reg, &ccm_regs->analog_pll_video);
+
+	/* EPDC PIX clk enable */
+	reg = readl(&ccm_regs->CCGR3);
+	reg |= 0x0C00;
+	writel(reg, &ccm_regs->CCGR3);
+
+	panel_info.epdc_data.wv_modes.mode_init = 0;
+	panel_info.epdc_data.wv_modes.mode_du = 1;
+	panel_info.epdc_data.wv_modes.mode_gc4 = 3;
+	panel_info.epdc_data.wv_modes.mode_gc8 = 2;
+	panel_info.epdc_data.wv_modes.mode_gc16 = 2;
+	panel_info.epdc_data.wv_modes.mode_gc32 = 2;
+
+	panel_info.epdc_data.epdc_timings = panel_timings;
+
+	setup_epdc_power();
+}
+
+void epdc_power_on(void)
+{
+	unsigned int reg;
+	struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR;
+
+	/* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */
+	dm_gpio_set_value(&epd_pwr_ctl0_desc, 1);
+	udelay(1000);
+
+	/* Enable epdc signal pin */
+	epdc_enable_pins();
+
+	/* Set PMIC Wakeup to high - enable Display power */
+	dm_gpio_set_value(&epd_wakeup_desc, 1);
+
+	/* Wait for PWRGOOD == 1 */
+	while (1) {
+		reg = readl(&gpio_regs->gpio_psr);
+		if (!(reg & (1 << 21)))
+			break;
+
+		udelay(100);
+	}
+
+	/* Enable VCOM */
+	dm_gpio_set_value(&epd_vcom_desc, 1);
+
+	udelay(500);
+}
+
+void epdc_power_off(void)
+{
+	/* Set PMIC Wakeup to low - disable Display power */
+	dm_gpio_set_value(&epd_wakeup_desc, 0);
+
+	/* Disable VCOM */
+	dm_gpio_set_value(&epd_vcom_desc, 0);
+
+	epdc_disable_pins();
+
+	/* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */
+	dm_gpio_set_value(&epd_pwr_ctl0_desc, 0);
+}
+#endif
+
 #if defined(CONFIG_VIDEO_IPUV3)
 static void disable_lvds(struct display_info_t const *dev)
 {
@@ -365,7 +675,7 @@
 	.bus	= -1,
 	.addr	= 0,
 	.pixfmt	= IPU_PIX_FMT_RGB24,
-	.detect	= detect_hdmi,
+	.detect	= NULL,
 	.enable	= do_enable_hdmi,
 	.mode	= {
 		.name           = "HDMI",
  
  
  
@@ -469,20 +779,46 @@
 	return 1;
 }
  
+static void setup_fec(void)
+{
+	if (is_mx6dqp()) {
+		int ret;
+
+		/* select ENET MAC0 TX clock from PLL */
+		imx_iomux_set_gpr_register(5, 9, 1, 1);
+		ret = enable_fec_anatop_clock(0, ENET_125MHZ);
+		if (ret)
+		    printf("Error fec anatop clock settings!\n");
+	}
+}
+
 #ifdef CONFIG_USB_EHCI_MX6
-static void setup_usb(void)
+int board_ehci_hcd_init(int port)
 {
-	/*
-	 * set daisy chain for otg_pin_id on 6q.
-	 * for 6dl, this bit is reserved
-	 */
-	imx_iomux_set_gpr_register(1, 13, 1, 0);
+	switch (port) {
+	case 0:
+		/*
+		  * Set daisy chain for otg_pin_id on 6q.
+		 *  For 6dl, this bit is reserved.
+		 */
+		imx_iomux_set_gpr_register(1, 13, 1, 0);
+		break;
+	case 1:
+		break;
+	default:
+		printf("MXC USB port %d not yet supported\n", port);
+		return -EINVAL;
+	}
+	return 0;
 }
 #endif
  
 int board_early_init_f(void)
 {
 	setup_iomux_uart();
+#if defined(CONFIG_VIDEO_IPUV3)
+	setup_display();
+#endif
  
 	return 0;
 }
  
  
  
  
  
  
  
  
  
  
  
  
  
@@ -495,56 +831,394 @@
 #ifdef CONFIG_MXC_SPI
 	setup_spi();
 #endif
-	if (is_mx6dq() || is_mx6dqp())
-		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
-	else
-		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
-#if defined(CONFIG_VIDEO_IPUV3)
-	setup_display();
+
+#ifdef CONFIG_SYS_I2C_LEGACY
+	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 #endif
-#ifdef CONFIG_USB_EHCI_MX6
-	setup_usb();
+
+#ifdef CONFIG_PCIE_IMX
+	setup_pcie();
 #endif
  
+#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)
+	setup_epdc();
+#endif
+
+#ifdef CONFIG_SATA
+	setup_sata();
+#endif
+
+#ifdef CONFIG_FEC_MXC
+	setup_fec();
+#endif
+
 	return 0;
 }
  
+#ifdef CONFIG_POWER_LEGACY
 int power_init_board(void)
 {
-	struct pmic *p;
+	struct pmic *pfuze;
 	unsigned int reg;
 	int ret;
  
-	p = pfuze_common_init(I2C_PMIC);
-	if (!p)
+	pfuze = pfuze_common_init(I2C_PMIC);
+	if (!pfuze)
 		return -ENODEV;
  
-	ret = pfuze_mode_init(p, APS_PFM);
+	if (is_mx6dqp())
+		ret = pfuze_mode_init(pfuze, APS_APS);
+	else
+		ret = pfuze_mode_init(pfuze, APS_PFM);
+
 	if (ret < 0)
 		return ret;
+	/* VGEN3 and VGEN5 corrected on i.mx6qp board */
+	if (!is_mx6dqp()) {
+		/* Increase VGEN3 from 2.5 to 2.8V */
+		pmic_reg_read(pfuze, PFUZE100_VGEN3VOL, &reg);
+		reg &= ~LDO_VOL_MASK;
+		reg |= LDOB_2_80V;
+		pmic_reg_write(pfuze, PFUZE100_VGEN3VOL, reg);
  
-	/* Increase VGEN3 from 2.5 to 2.8V */
-	pmic_reg_read(p, PFUZE100_VGEN3VOL, &reg);
-	reg &= ~LDO_VOL_MASK;
-	reg |= LDOB_2_80V;
-	pmic_reg_write(p, PFUZE100_VGEN3VOL, reg);
+		/* Increase VGEN5 from 2.8 to 3V */
+		pmic_reg_read(pfuze, PFUZE100_VGEN5VOL, &reg);
+		reg &= ~LDO_VOL_MASK;
+		reg |= LDOB_3_00V;
+		pmic_reg_write(pfuze, PFUZE100_VGEN5VOL, reg);
+	}
  
-	/* Increase VGEN5 from 2.8 to 3V */
-	pmic_reg_read(p, PFUZE100_VGEN5VOL, &reg);
-	reg &= ~LDO_VOL_MASK;
-	reg |= LDOB_3_00V;
-	pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
+	if (is_mx6dqp()) {
+		/* set SW1C staby volatage 1.075V*/
+		pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &reg);
+		reg &= ~0x3f;
+		reg |= 0x1f;
+		pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg);
  
+		/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
+		pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &reg);
+		reg &= ~0xc0;
+		reg |= 0x40;
+		pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg);
+
+		/* set SW2/VDDARM staby volatage 0.975V*/
+		pmic_reg_read(pfuze, PFUZE100_SW2STBY, &reg);
+		reg &= ~0x3f;
+		reg |= 0x17;
+		pmic_reg_write(pfuze, PFUZE100_SW2STBY, reg);
+
+		/* set SW2/VDDARM step ramp up time to from 16us to 4us/25mV */
+		pmic_reg_read(pfuze, PFUZE100_SW2CONF, &reg);
+		reg &= ~0xc0;
+		reg |= 0x40;
+		pmic_reg_write(pfuze, PFUZE100_SW2CONF, reg);
+	} else {
+		/* set SW1AB staby volatage 0.975V*/
+		pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, &reg);
+		reg &= ~0x3f;
+		reg |= 0x1b;
+		pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, reg);
+
+		/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+		pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, &reg);
+		reg &= ~0xc0;
+		reg |= 0x40;
+		pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, reg);
+
+		/* set SW1C staby volatage 0.975V*/
+		pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &reg);
+		reg &= ~0x3f;
+		reg |= 0x1b;
+		pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, reg);
+
+		/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
+		pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &reg);
+		reg &= ~0xc0;
+		reg |= 0x40;
+		pmic_reg_write(pfuze, PFUZE100_SW1CCONF, reg);
+	}
+
 	return 0;
 }
  
-#ifdef CONFIG_MXC_SPI
-int board_spi_cs_gpio(unsigned bus, unsigned cs)
+#elif defined(CONFIG_DM_PMIC_PFUZE100)
+int power_init_board(void)
 {
-	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
+	struct udevice *dev;
+	unsigned int reg;
+	int ret;
+
+	dev = pfuze_common_init();
+	if (!dev)
+		return -ENODEV;
+
+	if (is_mx6dqp())
+		ret = pfuze_mode_init(dev, APS_APS);
+	else
+		ret = pfuze_mode_init(dev, APS_PFM);
+	if (ret < 0)
+		return ret;
+
+	/* VGEN3 and VGEN5 corrected on i.mx6qp board */
+	if (!is_mx6dqp()) {
+		/* Increase VGEN3 from 2.5 to 2.8V */
+		reg = pmic_reg_read(dev, PFUZE100_VGEN3VOL);
+		reg &= ~LDO_VOL_MASK;
+		reg |= LDOB_2_80V;
+		pmic_reg_write(dev, PFUZE100_VGEN3VOL, reg);
+
+		/* Increase VGEN5 from 2.8 to 3V */
+		reg = pmic_reg_read(dev, PFUZE100_VGEN5VOL);
+		reg &= ~LDO_VOL_MASK;
+		reg |= LDOB_3_00V;
+		pmic_reg_write(dev, PFUZE100_VGEN5VOL, reg);
+	}
+
+	if (is_mx6dqp()) {
+		/* set SW1C staby volatage 1.075V*/
+		reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY);
+		reg &= ~0x3f;
+		reg |= 0x1f;
+		pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg);
+
+		/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
+		reg = pmic_reg_read(dev, PFUZE100_SW1CCONF);
+		reg &= ~0xc0;
+		reg |= 0x40;
+		pmic_reg_write(dev, PFUZE100_SW1CCONF, reg);
+
+		/* set SW2/VDDARM staby volatage 0.975V*/
+		reg = pmic_reg_read(dev, PFUZE100_SW2STBY);
+		reg &= ~0x3f;
+		reg |= 0x17;
+		pmic_reg_write(dev, PFUZE100_SW2STBY, reg);
+
+		/* set SW2/VDDARM step ramp up time to from 16us to 4us/25mV */
+		reg = pmic_reg_read(dev, PFUZE100_SW2CONF);
+		reg &= ~0xc0;
+		reg |= 0x40;
+		pmic_reg_write(dev, PFUZE100_SW2CONF, reg);
+	} else {
+		/* set SW1AB staby volatage 0.975V*/
+		reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY);
+		reg &= ~0x3f;
+		reg |= 0x1b;
+		pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg);
+
+		/* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+		reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF);
+		reg &= ~0xc0;
+		reg |= 0x40;
+		pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg);
+
+		/* set SW1C staby volatage 0.975V*/
+		reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY);
+		reg &= ~0x3f;
+		reg |= 0x1b;
+		pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg);
+
+		/* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
+		reg = pmic_reg_read(dev, PFUZE100_SW1CCONF);
+		reg &= ~0xc0;
+		reg |= 0x40;
+		pmic_reg_write(dev, PFUZE100_SW1CCONF, reg);
+	}
+
+	return 0;
 }
 #endif
  
+#ifdef CONFIG_LDO_BYPASS_CHECK
+#ifdef CONFIG_POWER_LEGACY
+void ldo_mode_set(int ldo_bypass)
+{
+	unsigned int value;
+	int is_400M;
+	unsigned char vddarm;
+	struct pmic *p = pmic_get("PFUZE100");
+
+	if (!p) {
+		printf("No PMIC found!\n");
+		return;
+	}
+
+	/* increase VDDARM/VDDSOC to support 1.2G chip */
+	if (check_1_2G()) {
+		ldo_bypass = 0;	/* ldo_enable on 1.2G chip */
+		printf("1.2G chip, increase VDDARM_IN/VDDSOC_IN\n");
+		if (is_mx6dqp()) {
+			/* increase VDDARM to 1.425V */
+			pmic_reg_read(p, PFUZE100_SW2VOL, &value);
+			value &= ~0x3f;
+			value |= 0x29;
+			pmic_reg_write(p, PFUZE100_SW2VOL, value);
+		} else {
+			/* increase VDDARM to 1.425V */
+			pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
+			value &= ~0x3f;
+			value |= 0x2d;
+			pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
+		}
+		/* increase VDDSOC to 1.425V */
+		pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
+		value &= ~0x3f;
+		value |= 0x2d;
+		pmic_reg_write(p, PFUZE100_SW1CVOL, value);
+	}
+	/* switch to ldo_bypass mode , boot on 800Mhz */
+	if (ldo_bypass) {
+		prep_anatop_bypass();
+		if (is_mx6dqp()) {
+			/* decrease VDDARM for 400Mhz DQP:1.1V*/
+			pmic_reg_read(p, PFUZE100_SW2VOL, &value);
+			value &= ~0x3f;
+			value |= 0x1c;
+			pmic_reg_write(p, PFUZE100_SW2VOL, value);
+		} else {
+			/* decrease VDDARM for 400Mhz DQ:1.1V, DL:1.275V */
+			pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
+			value &= ~0x3f;
+			if (is_mx6dl())
+				value |= 0x27;
+			else
+				value |= 0x20;
+
+			pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
+		}
+		/* increase VDDSOC to 1.3V */
+		pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
+		value &= ~0x3f;
+		value |= 0x28;
+		pmic_reg_write(p, PFUZE100_SW1CVOL, value);
+
+		/*
+		 * MX6Q/DQP:
+		 * VDDARM:1.15V@800M; VDDSOC:1.175V@800M
+		 * VDDARM:0.975V@400M; VDDSOC:1.175V@400M
+		 * MX6DL:
+		 * VDDARM:1.175V@800M; VDDSOC:1.175V@800M
+		 * VDDARM:1.15V@400M; VDDSOC:1.175V@400M
+		 */
+		is_400M = set_anatop_bypass(2);
+		if (is_mx6dqp()) {
+			pmic_reg_read(p, PFUZE100_SW2VOL, &value);
+			value &= ~0x3f;
+			if (is_400M)
+				value |= 0x17;
+			else
+				value |= 0x1e;
+			pmic_reg_write(p, PFUZE100_SW2VOL, value);
+		}
+
+		if (is_400M) {
+			if (is_mx6dl())
+				vddarm = 0x22;
+			else
+				vddarm = 0x1b;
+		} else {
+			if (is_mx6dl())
+				vddarm = 0x23;
+			else
+				vddarm = 0x22;
+		}
+		pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
+		value &= ~0x3f;
+		value |= vddarm;
+		pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
+
+		/* decrease VDDSOC to 1.175V */
+		pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
+		value &= ~0x3f;
+		value |= 0x23;
+		pmic_reg_write(p, PFUZE100_SW1CVOL, value);
+
+		finish_anatop_bypass();
+		printf("switch to ldo_bypass mode!\n");
+	}
+}
+#elif defined(CONFIG_DM_PMIC_PFUZE100)
+void ldo_mode_set(int ldo_bypass)
+{
+	int is_400M;
+	unsigned char vddarm;
+	struct udevice *dev;
+	int ret;
+
+	ret = pmic_get("pfuze100@8", &dev);
+	if (ret == -ENODEV) {
+		printf("No PMIC found!\n");
+		return;
+	}
+
+	/* increase VDDARM/VDDSOC to support 1.2G chip */
+	if (check_1_2G()) {
+		ldo_bypass = 0; /* ldo_enable on 1.2G chip */
+		printf("1.2G chip, increase VDDARM_IN/VDDSOC_IN\n");
+		if (is_mx6dqp()) {
+			/* increase VDDARM to 1.425V */
+			pmic_clrsetbits(dev, PFUZE100_SW2VOL, 0x3f, 0x29);
+		} else {
+			/* increase VDDARM to 1.425V */
+			pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, 0x2d);
+		}
+		/* increase VDDSOC to 1.425V */
+		pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, 0x2d);
+	}
+	/* switch to ldo_bypass mode , boot on 800Mhz */
+	if (ldo_bypass) {
+		prep_anatop_bypass();
+		if (is_mx6dqp()) {
+			/* decrease VDDARM for 400Mhz DQP:1.1V*/
+			pmic_clrsetbits(dev, PFUZE100_SW2VOL, 0x3f, 0x1c);
+		} else {
+			/* decrease VDDARM for 400Mhz DQ:1.1V, DL:1.275V */
+			if (is_mx6dl())
+				pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, 0x27);
+			else
+				pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, 0x20);
+		}
+		/* increase VDDSOC to 1.3V */
+		pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, 0x28);
+
+		/*
+		 * MX6Q/DQP:
+		 * VDDARM:1.15V@800M; VDDSOC:1.175V@800M
+		 * VDDARM:0.975V@400M; VDDSOC:1.175V@400M
+		 * MX6DL:
+		 * VDDARM:1.175V@800M; VDDSOC:1.175V@800M
+		 * VDDARM:1.15V@400M; VDDSOC:1.175V@400M
+		 */
+		is_400M = set_anatop_bypass(2);
+		if (is_mx6dqp()) {
+			if (is_400M)
+				pmic_clrsetbits(dev, PFUZE100_SW2VOL, 0x3f, 0x17);
+			else
+				pmic_clrsetbits(dev, PFUZE100_SW2VOL, 0x3f, 0x1e);
+		}
+
+		if (is_400M) {
+			if (is_mx6dl())
+				vddarm = 0x22;
+			else
+				vddarm = 0x1b;
+		} else {
+			if (is_mx6dl())
+				vddarm = 0x23;
+			else
+				vddarm = 0x22;
+		}
+		pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, vddarm);
+
+		/* decrease VDDSOC to 1.175V */
+		pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, 0x23);
+
+		finish_anatop_bypass();
+		printf("switch to ldo_bypass mode!\n");
+	}
+}
+#endif
+#endif
+
 #ifdef CONFIG_CMD_BMODE
 static const struct boot_mode board_boot_modes[] = {
 	/* 4 bit bus width */
@@ -575,6 +1249,49 @@
  
 	return 0;
 }
+
+#ifdef CONFIG_FSL_FASTBOOT
+#ifdef CONFIG_ANDROID_RECOVERY
+
+#define GPIO_VOL_DN_KEY IMX_GPIO_NR(1, 5)
+iomux_v3_cfg_t const recovery_key_pads[] = {
+	IOMUX_PADS(PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+};
+
+int is_recovery_key_pressing(void)
+{
+	int button_pressed = 0;
+	int ret;
+	struct gpio_desc desc;
+
+	/* Check Recovery Combo Button press or not. */
+	SETUP_IOMUX_PADS(recovery_key_pads);
+
+	ret = dm_gpio_lookup_name("GPIO1_5", &desc);
+	if (ret) {
+		printf("%s lookup GPIO1_5 failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	ret = dm_gpio_request(&desc, "volume_dn_key");
+	if (ret) {
+		printf("%s request volume_dn_key failed ret = %d\n", __func__, ret);
+		return;
+	}
+
+	dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN);
+
+	if (dm_gpio_get_value(&desc) == 0) { /* VOL_DN key is low assert */
+		button_pressed = 1;
+		printf("Recovery key pressed\n");
+	}
+
+	return  button_pressed;
+}
+
+#endif /*CONFIG_ANDROID_RECOVERY*/
+
+#endif /*CONFIG_FSL_FASTBOOT*/
  
 #ifdef CONFIG_SPL_BUILD
 #include <asm/arch/mx6-ddr.h>
+/*
+ * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ * Jason Liu <r64343@freescale.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+#include <config.h>
+
+/* image version */
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM      sd
+
+#ifdef CONFIG_USE_IMXIMG_PLUGIN
+/*PLUGIN    plugin-binary-file    IRAM_FREE_START_ADDR*/
+PLUGIN board/freescale/mx6sabresd/plugin.bin 0x00907000
+#else
+
+#ifdef CONFIG_IMX_HAB
+CSF CONFIG_CSF_SIZE
+#endif
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *      Addr-type register length (1,2 or 4 bytes)
+ *      Address   absolute address of the register
+ *      value     value to be stored in the register
+ */
+DATA 4, 0x020e0774, 0x000C0000
+DATA 4, 0x020e0754, 0x00000000
+DATA 4, 0x020e04ac, 0x00000030
+DATA 4, 0x020e04b0, 0x00000030
+DATA 4, 0x020e0464, 0x00000030
+DATA 4, 0x020e0490, 0x00000030
+DATA 4, 0x020e074c, 0x00000030
+DATA 4, 0x020e0494, 0x00000030
+DATA 4, 0x020e04a0, 0x00000000
+DATA 4, 0x020e04b4, 0x00000030
+DATA 4, 0x020e04b8, 0x00000030
+DATA 4, 0x020e076c, 0x00000030
+DATA 4, 0x020e0750, 0x00020000
+DATA 4, 0x020e04bc, 0x00000030
+DATA 4, 0x020e04c0, 0x00000030
+DATA 4, 0x020e04c4, 0x00000030
+DATA 4, 0x020e04c8, 0x00000030
+DATA 4, 0x020e0760, 0x00020000
+DATA 4, 0x020e0764, 0x00000030
+DATA 4, 0x020e0770, 0x00000030
+DATA 4, 0x020e0778, 0x00000030
+DATA 4, 0x020e077c, 0x00000030
+DATA 4, 0x020e0470, 0x00000030
+DATA 4, 0x020e0474, 0x00000030
+DATA 4, 0x020e0478, 0x00000030
+DATA 4, 0x020e047c, 0x00000030
+DATA 4, 0x021b0800, 0xa1390003
+DATA 4, 0x021b080c, 0x001F001F
+DATA 4, 0x021b0810, 0x001F001F
+DATA 4, 0x021b083c, 0x42190219
+DATA 4, 0x021b0840, 0x017B0177
+DATA 4, 0x021b0848, 0x4B4D4E4D
+DATA 4, 0x021b0850, 0x3F3E2D36
+DATA 4, 0x021b081c, 0x33333333
+DATA 4, 0x021b0820, 0x33333333
+DATA 4, 0x021b0824, 0x33333333
+DATA 4, 0x021b0828, 0x33333333
+DATA 4, 0x021b08b8, 0x00000800
+DATA 4, 0x021b0004, 0x0002002D
+DATA 4, 0x021b0008, 0x00333030
+DATA 4, 0x021b000c, 0x3F435313
+DATA 4, 0x021b0010, 0xB66E8B63
+DATA 4, 0x021b0014, 0x01FF00DB
+DATA 4, 0x021b0018, 0x00001740
+DATA 4, 0x021b001c, 0x00008000
+DATA 4, 0x021b002c, 0x000026d2
+DATA 4, 0x021b0030, 0x00431023
+DATA 4, 0x021b0040, 0x00000017
+DATA 4, 0x021b0000, 0x83190000
+DATA 4, 0x021b001c, 0x04008032
+DATA 4, 0x021b001c, 0x00008033
+DATA 4, 0x021b001c, 0x00048031
+DATA 4, 0x021b001c, 0x05208030
+DATA 4, 0x021b001c, 0x04008040
+DATA 4, 0x021b0020, 0x00005800
+DATA 4, 0x021b0818, 0x00011117
+DATA 4, 0x021b0004, 0x0002556D
+DATA 4, 0x021b0404, 0x00011006
+DATA 4, 0x021b001c, 0x00000000
+
+/* set the default clock gate to save power */
+DATA 4, 0x020c4068, 0x00C03F3F
+DATA 4, 0x020c406c, 0x0030FC03
+DATA 4, 0x020c4070, 0x0FFFF000
+DATA 4, 0x020c4074, 0x3FF00000
+DATA 4, 0x020c4078, 0x00FFF300
+DATA 4, 0x020c407c, 0x0F0000C3
+DATA 4, 0x020c4080, 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4, 0x020e0010, 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4, 0x020e0018, 0x007F007F
+DATA 4, 0x020e001c, 0x007F007F
+#endif
+/*
+ * Copyright (C) 2012-2016 Freescale Semiconductor, Inc.
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <config.h>
+
+/* DDR script */
+.macro imx6dqpsabresd_ddr_setting
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0x000c0000
+	str r1, [r0, #0x798]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x758]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x588]
+	str r1, [r0, #0x594]
+	str r1, [r0, #0x56c]
+	str r1, [r0, #0x578]
+	str r1, [r0, #0x74c]
+	str r1, [r0, #0x57c]
+
+	ldr r1, =0x00000000
+	str r1, [r0, #0x58c]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x59c]
+	str r1, [r0, #0x5a0]
+	str r1, [r0, #0x78c]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x750]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x5a8]
+	str r1, [r0, #0x5b0]
+	str r1, [r0, #0x524]
+	str r1, [r0, #0x51c]
+	str r1, [r0, #0x518]
+	str r1, [r0, #0x50c]
+	str r1, [r0, #0x5b8]
+	str r1, [r0, #0x5c0]
+
+	ldr r1, =0x00018200
+	str r1, [r0, #0x534]
+	ldr r1, =0x00008000
+	str r1, [r0, #0x538]
+	ldr r1, =0x00018200
+	str r1, [r0, #0x53c]
+	str r1, [r0, #0x540]
+	str r1, [r0, #0x544]
+	str r1, [r0, #0x548]
+	str r1, [r0, #0x54c]
+	str r1, [r0, #0x550]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x774]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x784]
+	str r1, [r0, #0x788]
+	str r1, [r0, #0x794]
+	str r1, [r0, #0x79c]
+	str r1, [r0, #0x7a0]
+	str r1, [r0, #0x7a4]
+	str r1, [r0, #0x7a8]
+	str r1, [r0, #0x748]
+	str r1, [r0, #0x5ac]
+	str r1, [r0, #0x5b4]
+	str r1, [r0, #0x528]
+	str r1, [r0, #0x520]
+	str r1, [r0, #0x514]
+	str r1, [r0, #0x510]
+	str r1, [r0, #0x5bc]
+	str r1, [r0, #0x5c4]
+
+	ldr r0, =MMDC_P0_BASE_ADDR
+	ldr r2, =0xa1390003
+	str r2, [r0, #0x800]
+
+	ldr r2, =0x001b001e
+	str r2, [r0, #0x80c]
+	ldr r2, =0x002e0029
+	str r2, [r0, #0x810]
+
+	ldr r1, =MMDC_P1_BASE_ADDR
+	ldr r2, =0x001b002a
+	str r2, [r1, #0x80c]
+	ldr r2, =0x0019002c
+	str r2, [r1, #0x810]
+
+	ldr r2, =0x43240334
+	str r2, [r0, #0x83c]
+	ldr r2, =0x0324031a
+	str r2, [r0, #0x840]
+
+	ldr r2, =0x43340344
+	str r2, [r1, #0x83c]
+	ldr r2, =0x03280276
+	str r2, [r1, #0x840]
+
+	ldr r2, =0x44383A3E
+	str r2, [r0, #0x848]
+	ldr r2, =0x3C3C3846
+	str r2, [r1, #0x848]
+
+	ldr r2, =0x2e303230
+	str r2, [r0, #0x850]
+	ldr r2, =0x38283E34
+	str r2, [r1, #0x850]
+
+	ldr r2, =0x33333333
+	str r2, [r0, #0x81c]
+	str r2, [r0, #0x820]
+	str r2, [r0, #0x824]
+	str r2, [r0, #0x828]
+	str r2, [r1, #0x81c]
+	str r2, [r1, #0x820]
+	str r2, [r1, #0x824]
+	str r2, [r1, #0x828]
+
+	ldr r2, =0x24912489
+	str r2, [r0, #0x8c0]
+	ldr r2, =0x24914452
+	str r2, [r1, #0x8c0]
+
+	ldr r2, =0x00000800
+	str r2, [r0, #0x8b8]
+	str r2, [r1, #0x8b8]
+
+	ldr r2, =0x00020036
+	str r2, [r0, #0x004]
+	ldr r2, =0x24444040
+	str r2, [r0, #0x008]
+
+	ldr r2, =0x555A7955
+	str r2, [r0, #0x00c]
+	ldr r2, =0xFF320F64
+	str r2, [r0, #0x010]
+
+	ldr r2, =0x01FF00DB
+	str r2, [r0, #0x014]
+	ldr r2, =0x00011740
+	str r2, [r0, #0x018]
+
+	ldr r2, =0x00008000
+	str r2, [r0, #0x01c]
+	ldr r2, =0x000026d2
+	str r2, [r0, #0x02c]
+	ldr r2, =0x005A1023
+	str r2, [r0, #0x030]
+	ldr r2, =0x00000027
+	str r2, [r0, #0x040]
+
+	ldr r2, =0x14420000
+	str r2, [r0, #0x400]
+
+	ldr r2, =0x831A0000
+	str r2, [r0, #0x000]
+
+	ldr r2, =0x00400C58
+	str r2, [r0, #0x890]
+
+	ldr r3, =0x00bb0000
+	ldr r2, =0x00000000
+	str r2, [r3, #0x008]
+	ldr r2, =0x2891E41A
+	str r2, [r3, #0x00C]
+	ldr r2, =0x00000564
+	str r2, [r3, #0x038]
+	ldr r2, =0x00000040
+	str r2, [r3, #0x014]
+	ldr r2, =0x00000020
+	str r2, [r3, #0x028]
+	ldr r2, =0x00000020
+	str r2, [r3, #0x02c]
+
+	ldr r2, =0x04088032
+	str r2, [r0, #0x01c]
+	ldr r2, =0x00008033
+	str r2, [r0, #0x01c]
+	ldr r2, =0x00048031
+	str r2, [r0, #0x01c]
+	ldr r2, =0x09408030
+	str r2, [r0, #0x01c]
+	ldr r2, =0x04008040
+	str r2, [r0, #0x01c]
+
+	ldr r2, =0x00005800
+	str r2, [r0, #0x020]
+	ldr r2, =0x00011117
+	str r2, [r0, #0x818]
+	str r2, [r1, #0x818]
+	ldr r2, =0x00025576
+	str r2, [r0, #0x004]
+	ldr r2, =0x00011006
+	str r2, [r0, #0x404]
+	ldr r2, =0x00000000
+	str r2, [r0, #0x01c]
+.endm
+
+.macro imx6dqsabresd_ddr_setting
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0x000c0000
+	str r1, [r0, #0x798]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x758]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x588]
+	str r1, [r0, #0x594]
+	str r1, [r0, #0x56c]
+	str r1, [r0, #0x578]
+	str r1, [r0, #0x74c]
+	str r1, [r0, #0x57c]
+
+	ldr r1, =0x00000000
+	str r1, [r0, #0x58c]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x59c]
+	str r1, [r0, #0x5a0]
+	str r1, [r0, #0x78c]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x750]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x5a8]
+	str r1, [r0, #0x5b0]
+	str r1, [r0, #0x524]
+	str r1, [r0, #0x51c]
+	str r1, [r0, #0x518]
+	str r1, [r0, #0x50c]
+	str r1, [r0, #0x5b8]
+	str r1, [r0, #0x5c0]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x774]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x784]
+	str r1, [r0, #0x788]
+	str r1, [r0, #0x794]
+	str r1, [r0, #0x79c]
+	str r1, [r0, #0x7a0]
+	str r1, [r0, #0x7a4]
+	str r1, [r0, #0x7a8]
+	str r1, [r0, #0x748]
+	str r1, [r0, #0x5ac]
+	str r1, [r0, #0x5b4]
+	str r1, [r0, #0x528]
+	str r1, [r0, #0x520]
+	str r1, [r0, #0x514]
+	str r1, [r0, #0x510]
+	str r1, [r0, #0x5bc]
+	str r1, [r0, #0x5c4]
+
+	ldr r0, =MMDC_P0_BASE_ADDR
+	ldr r2, =0xa1390003
+	str r2, [r0, #0x800]
+
+	ldr r2, =0x001F001F
+	str r2, [r0, #0x80c]
+	str r2, [r0, #0x810]
+	ldr r1, =MMDC_P1_BASE_ADDR
+	str r2, [r1, #0x80c]
+	str r2, [r1, #0x810]
+
+	ldr r2, =0x43270338
+	str r2, [r0, #0x83c]
+	ldr r2, =0x03200314
+	str r2, [r0, #0x840]
+
+	ldr r2, =0x431A032F
+	str r2, [r1, #0x83c]
+	ldr r2, =0x03200263
+	str r2, [r1, #0x840]
+
+	ldr r2, =0x4B434748
+	str r2, [r0, #0x848]
+	ldr r2, =0x4445404C
+	str r2, [r1, #0x848]
+
+	ldr r2, =0x38444542
+	str r2, [r0, #0x850]
+	ldr r2, =0x4935493A
+	str r2, [r1, #0x850]
+
+	ldr r2, =0x33333333
+	str r2, [r0, #0x81c]
+	str r2, [r0, #0x820]
+	str r2, [r0, #0x824]
+	str r2, [r0, #0x828]
+	str r2, [r1, #0x81c]
+	str r2, [r1, #0x820]
+	str r2, [r1, #0x824]
+	str r2, [r1, #0x828]
+
+	ldr r2, =0x00000800
+	str r2, [r0, #0x8b8]
+	str r2, [r1, #0x8b8]
+
+	ldr r2, =0x00020036
+	str r2, [r0, #0x004]
+	ldr r2, =0x09444040
+	str r2, [r0, #0x008]
+
+	ldr r2, =0x555A7975
+	str r2, [r0, #0x00c]
+	ldr r2, =0xFF538F64
+	str r2, [r0, #0x010]
+
+	ldr r2, =0x01FF00DB
+	str r2, [r0, #0x014]
+	ldr r2, =0x00001740
+	str r2, [r0, #0x018]
+
+	ldr r2, =0x00008000
+	str r2, [r0, #0x01c]
+	ldr r2, =0x000026d2
+	str r2, [r0, #0x02c]
+	ldr r2, =0x005A1023
+	str r2, [r0, #0x030]
+	ldr r2, =0x00000027
+	str r2, [r0, #0x040]
+
+	ldr r2, =0x831A0000
+	str r2, [r0, #0x000]
+
+	ldr r2, =0x04088032
+	str r2, [r0, #0x01c]
+	ldr r2, =0x00008033
+	str r2, [r0, #0x01c]
+	ldr r2, =0x00048031
+	str r2, [r0, #0x01c]
+	ldr r2, =0x09408030
+	str r2, [r0, #0x01c]
+	ldr r2, =0x04008040
+	str r2, [r0, #0x01c]
+
+	ldr r2, =0x00005800
+	str r2, [r0, #0x020]
+	ldr r2, =0x00011117
+	str r2, [r0, #0x818]
+	str r2, [r1, #0x818]
+	ldr r2, =0x00025576
+	str r2, [r0, #0x004]
+	ldr r2, =0x00011006
+	str r2, [r0, #0x404]
+	ldr r2, =0x00000000
+	str r2, [r0, #0x01c]
+.endm
+
+.macro imx6dlsabresd_ddr_setting
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0x000c0000
+	str r1, [r0, #0x774]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x754]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x4ac]
+	str r1, [r0, #0x4b0]
+	str r1, [r0, #0x464]
+	str r1, [r0, #0x490]
+	str r1, [r0, #0x74c]
+	str r1, [r0, #0x494]
+
+	ldr r1, =0x00000000
+	str r1, [r0, #0x4a0]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x4b4]
+	str r1, [r0, #0x4b8]
+	str r1, [r0, #0x76c]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x750]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x4bc]
+	str r1, [r0, #0x4c0]
+	str r1, [r0, #0x4c4]
+	str r1, [r0, #0x4c8]
+	str r1, [r0, #0x4cc]
+	str r1, [r0, #0x4d0]
+	str r1, [r0, #0x4d4]
+	str r1, [r0, #0x4d8]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x760]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x764]
+	str r1, [r0, #0x770]
+	str r1, [r0, #0x778]
+	str r1, [r0, #0x77c]
+	str r1, [r0, #0x780]
+	str r1, [r0, #0x784]
+	str r1, [r0, #0x78c]
+	str r1, [r0, #0x748]
+	str r1, [r0, #0x470]
+	str r1, [r0, #0x474]
+	str r1, [r0, #0x478]
+	str r1, [r0, #0x47c]
+	str r1, [r0, #0x480]
+	str r1, [r0, #0x484]
+	str r1, [r0, #0x488]
+	str r1, [r0, #0x48c]
+
+	ldr r0, =MMDC_P0_BASE_ADDR
+	ldr r2, =0xa1390003
+	str r2, [r0, #0x800]
+
+	ldr r2, =0x001f001f
+	str r2, [r0, #0x80c]
+	str r2, [r0, #0x810]
+	ldr r1, =MMDC_P1_BASE_ADDR
+	str r2, [r1, #0x80c]
+	str r2, [r1, #0x810]
+
+	ldr r2, =0x4220021F
+	str r2, [r0, #0x83c]
+	ldr r2, =0x0207017E
+	str r2, [r0, #0x840]
+
+	ldr r2, =0x4201020C
+	str r2, [r1, #0x83c]
+	ldr r2, =0x01660172
+	str r2, [r1, #0x840]
+
+	ldr r2, =0x4A4D4E4D
+	str r2, [r0, #0x848]
+	ldr r2, =0x4A4F5049
+	str r2, [r1, #0x848]
+
+	ldr r2, =0x3F3C3D31
+	str r2, [r0, #0x850]
+	ldr r2, =0x3238372B
+	str r2, [r1, #0x850]
+
+	ldr r2, =0x33333333
+	str r2, [r0, #0x81c]
+	str r2, [r0, #0x820]
+	str r2, [r0, #0x824]
+	str r2, [r0, #0x828]
+	str r2, [r1, #0x81c]
+	str r2, [r1, #0x820]
+	str r2, [r1, #0x824]
+	str r2, [r1, #0x828]
+
+	ldr r2, =0x00000800
+	str r2, [r0, #0x8b8]
+	str r2, [r1, #0x8b8]
+
+	ldr r2, =0x0002002D
+	str r2, [r0, #0x004]
+	ldr r2, =0x00333030
+	str r2, [r0, #0x008]
+
+	ldr r2, =0x3F435313
+	str r2, [r0, #0x00c]
+	ldr r2, =0xB66E8B63
+	str r2, [r0, #0x010]
+
+	ldr r2, =0x01FF00DB
+	str r2, [r0, #0x014]
+	ldr r2, =0x00001740
+	str r2, [r0, #0x018]
+
+	ldr r2, =0x00008000
+	str r2, [r0, #0x01c]
+	ldr r2, =0x000026d2
+	str r2, [r0, #0x02c]
+	ldr r2, =0x00431023
+	str r2, [r0, #0x030]
+	ldr r2, =0x00000027
+	str r2, [r0, #0x040]
+
+	ldr r2, =0x831A0000
+	str r2, [r0, #0x000]
+
+	ldr r2, =0x04008032
+	str r2, [r0, #0x01c]
+	ldr r2, =0x00008033
+	str r2, [r0, #0x01c]
+	ldr r2, =0x00048031
+	str r2, [r0, #0x01c]
+	ldr r2, =0x05208030
+	str r2, [r0, #0x01c]
+	ldr r2, =0x04008040
+	str r2, [r0, #0x01c]
+
+	ldr r2, =0x00005800
+	str r2, [r0, #0x020]
+	ldr r2, =0x00011117
+	str r2, [r0, #0x818]
+	str r2, [r1, #0x818]
+	ldr r2, =0x0002556D
+	str r2, [r0, #0x004]
+	ldr r2, =0x00011006
+	str r2, [r0, #0x404]
+	ldr r2, =0x00000000
+	str r2, [r0, #0x01c]
+.endm
+
+.macro imx6solosabresd_ddr_setting
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0x000c0000
+	str r1, [r0, #0x774]
+	ldr r1, =0x00000000
+	str r1, [r0, #0x754]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x4ac]
+	str r1, [r0, #0x4b0]
+	str r1, [r0, #0x464]
+	str r1, [r0, #0x490]
+	str r1, [r0, #0x74c]
+	str r1, [r0, #0x494]
+
+	ldr r1, =0x00000000
+	str r1, [r0, #0x4a0]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x4b4]
+	str r1, [r0, #0x4b8]
+	str r1, [r0, #0x76c]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x750]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x4bc]
+	str r1, [r0, #0x4c0]
+	str r1, [r0, #0x4c4]
+	str r1, [r0, #0x4c8]
+
+	ldr r1, =0x00020000
+	str r1, [r0, #0x760]
+
+	ldr r1, =0x00000030
+	str r1, [r0, #0x764]
+	str r1, [r0, #0x770]
+	str r1, [r0, #0x778]
+	str r1, [r0, #0x77c]
+	str r1, [r0, #0x470]
+	str r1, [r0, #0x474]
+	str r1, [r0, #0x478]
+	str r1, [r0, #0x47c]
+
+	ldr r0, =MMDC_P0_BASE_ADDR
+	ldr r2, =0xa1390003
+	str r2, [r0, #0x800]
+
+	ldr r2, =0x001F001F
+	str r2, [r0, #0x80c]
+	str r2, [r0, #0x810]
+
+	ldr r2, =0x42190219
+	str r2, [r0, #0x83c]
+	ldr r2, =0x017B0177
+	str r2, [r0, #0x840]
+
+	ldr r2, =0x4B4D4E4D
+	str r2, [r0, #0x848]
+
+	ldr r2, =0x3F3E2D36
+	str r2, [r0, #0x850]
+
+	ldr r2, =0x33333333
+	str r2, [r0, #0x81c]
+	str r2, [r0, #0x820]
+	str r2, [r0, #0x824]
+	str r2, [r0, #0x828]
+
+	ldr r2, =0x00000800
+	str r2, [r0, #0x8b8]
+
+	ldr r2, =0x0002002D
+	str r2, [r0, #0x004]
+	ldr r2, =0x00333030
+	str r2, [r0, #0x008]
+
+	ldr r2, =0x3F435313
+	str r2, [r0, #0x00c]
+	ldr r2, =0xB66E8B63
+	str r2, [r0, #0x010]
+
+	ldr r2, =0x01FF00DB
+	str r2, [r0, #0x014]
+	ldr r2, =0x00001740
+	str r2, [r0, #0x018]
+
+	ldr r2, =0x00008000
+	str r2, [r0, #0x01c]
+	ldr r2, =0x000026d2
+	str r2, [r0, #0x02c]
+	ldr r2, =0x00431023
+	str r2, [r0, #0x030]
+	ldr r2, =0x00000017
+	str r2, [r0, #0x040]
+
+	ldr r2, =0x83190000
+	str r2, [r0, #0x000]
+
+	ldr r2, =0x04008032
+	str r2, [r0, #0x01c]
+	ldr r2, =0x00008033
+	str r2, [r0, #0x01c]
+	ldr r2, =0x00048031
+	str r2, [r0, #0x01c]
+	ldr r2, =0x05208030
+	str r2, [r0, #0x01c]
+	ldr r2, =0x04008040
+	str r2, [r0, #0x01c]
+
+	ldr r2, =0x00005800
+	str r2, [r0, #0x020]
+	ldr r2, =0x00011117
+	str r2, [r0, #0x818]
+	ldr r2, =0x0002556D
+	str r2, [r0, #0x004]
+	ldr r2, =0x00011006
+	str r2, [r0, #0x404]
+	ldr r2, =0x00000000
+	str r2, [r0, #0x01c]
+.endm
+.macro imx6_clock_gating
+	ldr r0, =CCM_BASE_ADDR
+	ldr r1, =0x00C03F3F
+	str r1, [r0, #0x068]
+	ldr r1, =0x0030FC03
+	str r1, [r0, #0x06c]
+	ldr r1, =0x0FFFF000
+	str r1, [r0, #0x070]
+	ldr r1, =0x3FF00000
+	str r1, [r0, #0x074]
+	ldr r1, =0x00FFF300
+	str r1, [r0, #0x078]
+	ldr r1, =0x0F0000C3
+	str r1, [r0, #0x07c]
+	ldr r1, =0x000003FF
+	str r1, [r0, #0x080]
+.endm
+
+.macro imx6_qos_setting
+	ldr r0, =IOMUXC_BASE_ADDR
+	ldr r1, =0xF00000CF
+	str r1, [r0, #0x10]
+
+#if defined(CONFIG_MX6QP)
+	ldr r1, =0x77177717
+	str r1, [r0, #0x18]
+	str r1, [r0, #0x1c]
+#else
+	ldr r1, =0x007F007F
+	str r1, [r0, #0x18]
+	str r1, [r0, #0x1c]
+#endif
+.endm
+
+.macro imx6_ddr_setting
+#if defined (CONFIG_MX6S)
+	imx6solosabresd_ddr_setting
+#elif defined (CONFIG_MX6DL)
+	imx6dlsabresd_ddr_setting
+#elif defined (CONFIG_MX6QP)
+	imx6dqpsabresd_ddr_setting
+#elif defined (CONFIG_MX6Q)
+	imx6dqsabresd_ddr_setting
+#else
+	#error "SOC not configured"
+#endif
+
+.endm
+
+/* include the common plugin code here */
+#include <asm/arch/mx6_plugin.S>
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright 2018 NXP
  *
  * Configuration settings for the Freescale i.MX6Q SabreSD board.
  */
@@ -15,6 +16,39 @@
 /* MMC Configs */
 #define CONFIG_SYS_FSL_ESDHC_ADDR      0
  
+#define CONFIG_FEC_MXC
+#define CONFIG_FEC_XCV_TYPE		RGMII
+#define CONFIG_ETHPRIME			"eth0"
+
+#define CONFIG_PHY_ATHEROS
+
+#ifdef CONFIG_MX6S
+#define SYS_NOSMP "nosmp"
+#else
+#define SYS_NOSMP
+#endif
+
+#ifdef CONFIG_NAND_BOOT
+#define MFG_NAND_PARTITION "mtdparts=8000000.nor:1m(boot),-(rootfs)\\;gpmi-nand:64m(nandboot),16m(nandkernel),16m(nanddtb),16m(nandtee),-(nandrootfs) "
+#else
+#define MFG_NAND_PARTITION ""
+#endif
+
+#define CONFIG_MFG_ENV_SETTINGS \
+	"mfgtool_args=setenv bootargs console=" CONSOLE_DEV ",115200 " \
+		"rdinit=/linuxrc " \
+		"g_mass_storage.stall=0 g_mass_storage.removable=1 " \
+		"g_mass_storage.file=/fat g_mass_storage.ro=1 " \
+		"g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
+		"g_mass_storage.iSerialNumber=\"\" "\
+		"enable_wait_mode=off "\
+		MFG_NAND_PARTITION \
+		"\0" \
+		"initrd_addr=0x12C00000\0" \
+		"initrd_high=0xffffffff\0" \
+		"bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
+
+
 #ifdef CONFIG_SUPPORT_EMMC_BOOT
 #define EMMC_ENV \
 	"emmcdev=2\0" \
  
  
@@ -35,10 +69,75 @@
 #define EMMC_ENV ""
 #endif
  
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+#if defined(CONFIG_NAND_BOOT)
+	/*
+	 * The dts also enables the WEIN NOR which is mtd0.
+	 * So the partions' layout for NAND is:
+	 *     mtd1: 16M      (uboot)
+	 *     mtd2: 16M      (kernel)
+	 *     mtd3: 16M      (dtb)
+	 *     mtd4: left     (rootfs)
+	 */
 #define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS \
+	"fdt_addr=0x18000000\0" \
+	"fdt_high=0xffffffff\0"	  \
+	"console=" CONSOLE_DEV "\0" \
+	"bootargs=console=" CONSOLE_DEV ",115200 ubi.mtd=6 "  \
+		"root=ubi0:nandrootfs rootfstype=ubifs "		     \
+		MFG_NAND_PARTITION \
+		"\0" \
+	"bootcmd=nand read ${loadaddr} 0x4000000 0xc00000;"\
+		"nand read ${fdt_addr} 0x5000000 0x100000;"\
+		"bootz ${loadaddr} - ${fdt_addr}\0"
+
+#elif defined(CONFIG_SATA_BOOT)
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+		CONFIG_MFG_ENV_SETTINGS \
+		"image=zImage\0" \
+		"fdt_file=undefined\0" \
+		"fdt_addr=0x18000000\0" \
+		"fdt_high=0xffffffff\0"   \
+		"findfdt="\
+			"if test $fdt_file = undefined; then " \
+				"if test $board_name = SABREAUTO && test $board_rev = MX6QP; then " \
+					"setenv fdt_file imx6qp-sabreauto.dtb; fi; " \
+				"if test $board_name = SABREAUTO && test $board_rev = MX6Q; then " \
+					"setenv fdt_file imx6q-sabreauto.dtb; fi; " \
+				"if test $board_name = SABREAUTO && test $board_rev = MX6DL; then " \
+					"setenv fdt_file imx6dl-sabreauto.dtb; fi; " \
+				"if test $board_name = SABRESD && test $board_rev = MX6QP; then " \
+					"setenv fdt_file imx6qp-sabresd.dtb; fi; " \
+				"if test $board_name = SABRESD && test $board_rev = MX6Q; then " \
+					"setenv fdt_file imx6q-sabresd.dtb; fi; " \
+				"if test $board_name = SABRESD && test $board_rev = MX6DL; then " \
+					"setenv fdt_file imx6dl-sabresd.dtb; fi; " \
+				"if test $fdt_file = undefined; then " \
+					"echo WARNING: Could not determine dtb to use; " \
+				"fi; " \
+			"fi;\0" \
+		"findtee="\
+		"bootargs=console=" CONSOLE_DEV ",115200 \0"\
+		"bootargs_sata=setenv bootargs ${bootargs} " \
+			"root=/dev/sda2 rootwait rw \0" \
+		"bootcmd_sata=run bootargs_sata; sata init; " \
+			"run findfdt;" \
+			"fatload sata 0:1 ${loadaddr} ${image}; " \
+			"fatload sata 0:1 ${fdt_addr} ${fdt_file}; " \
+			"bootz ${loadaddr} - ${fdt_addr} \0" \
+		"bootcmd=run bootcmd_sata \0"
+
+#else
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	CONFIG_MFG_ENV_SETTINGS \
+	"epdc_waveform=epdc_splash.bin\0" \
 	"script=boot.scr\0" \
 	"image=zImage\0" \
-	"fdtfile=undefinedfile=undefined\0" \" \
+	"fdt_file=undefinedfile=undefined\0" \" \
 	"fdt_addr=0x18000000\0" \
 	"boot_fdt=try\0" \
 	"ip_dyn=yes\0" \
@@ -53,6 +152,8 @@
 	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
 	"mmcpart=1\0" \
 	"finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
+	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+	"mmcautodetect=yes\0" \
 	"update_sd_firmware=" \
 		"if test ${ip_dyn} = yes; then " \
 			"setenv get_cmd dhcp; " \
@@ -67,8 +168,9 @@
 			"fi; "	\
 		"fi\0" \
 	EMMC_ENV	  \
-	"mmcargs=setenv bootargs console=${console},${baudrate} " \
-		"root=PARTUUID=${uuid} rootwait rw\0" \
+	"smp=" SYS_NOSMP "\0"\
+	"mmcargs=setenv bootargs console=${console},${baudrate} ${smp} " \
+		"root=${mmcroot}\0" \
 	"loadbootscript=" \
 		"load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script} || " \
 		"load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${script};\0" \
  
@@ -76,10 +178,9 @@
 		"source\0" \
 	"loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} || " \
 		"load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${image}\0" \
-	"loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdtfile} || " \
-		"load mmc ${mmcdev}:${mmcpart} ${fdt_addr} boot/${fdtfile}\0" \
+	"loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file} || " \
+		"load mmc ${mmcdev}:${mmcpart} ${fdt_addr} boot/${fdt_file}\0" \
 	"mmcboot=echo Booting from mmc ...; " \
-		"run finduuid; " \
 		"run mmcargs; " \
 		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
 			"if run loadfdt; then " \
@@ -94,7 +195,7 @@
 		"else " \
 			"bootz; " \
 		"fi;\0" \
-	"netargs=setenv bootargs console=${console},${baudrate} " \
+	"netargs=setenv bootargs console=${console},${baudrate} ${smp} " \
 		"root=/dev/nfs " \
 		"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
 	"netboot=echo Booting from net ...; " \
@@ -106,7 +207,7 @@
 		"fi; " \
 		"${get_cmd} ${image}; " \
 		"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
-			"if ${get_cmd} ${fdt_addr} ${fdtfile}; then " \
+			"if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
 				"bootz ${loadaddr} - ${fdt_addr}; " \
 			"else " \
 				"if test ${boot_fdt} = try; then " \
  
  
  
  
  
  
  
@@ -119,23 +220,25 @@
 			"bootz; " \
 		"fi;\0" \
 		"findfdt="\
-			"if test $fdtfile = undefined; then " \
+			"if test $fdt_file = undefined; then " \
 				"if test $board_name = SABREAUTO && test $board_rev = MX6QP; then " \
-					"setenv fdtfile imx6qp-sabreauto.dtb; fi; " \
+					"setenv fdt_file imx6qp-sabreauto.dtb; fi; " \
 				"if test $board_name = SABREAUTO && test $board_rev = MX6Q; then " \
-					"setenv fdtfile imx6q-sabreauto.dtb; fi; " \
+					"setenv fdt_file imx6q-sabreauto.dtb; fi; " \
 				"if test $board_name = SABREAUTO && test $board_rev = MX6DL; then " \
-					"setenv fdtfile imx6dl-sabreauto.dtb; fi; " \
+					"setenv fdt_file imx6dl-sabreauto.dtb; fi; " \
 				"if test $board_name = SABRESD && test $board_rev = MX6QP; then " \
-					"setenv fdtfile imx6qp-sabresd.dtb; fi; " \
+					"setenv fdt_file imx6qp-sabresd.dtb; fi; " \
 				"if test $board_name = SABRESD && test $board_rev = MX6Q; then " \
-					"setenv fdtfile imx6q-sabresd.dtb; fi; " \
+					"setenv fdt_file imx6q-sabresd.dtb; fi; " \
 				"if test $board_name = SABRESD && test $board_rev = MX6DL; then " \
-					"setenv fdtfile imx6dl-sabresd.dtb; fi; " \
-				"if test $fdtfile = undefined; then " \
+					"setenv fdt_file imx6dl-sabresd.dtb; fi; " \
+				"if test $fdt_file = undefined; then " \
 					"echo WARNING: Could not determine dtb to use; fi; " \
 			"fi;\0" \
  
+#endif
+
 #define CONFIG_ARP_TIMEOUT     200UL
  
 /* Physical Memory Map */
  
  
  
@@ -150,14 +253,54 @@
 #define CONFIG_SYS_INIT_SP_ADDR \
 	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  
-/* Environment organization */
+#ifdef CONFIG_SATA
+#define CONFIG_DWC_AHSATA
+#define CONFIG_SYS_SATA_MAX_DEVICE	1
+#define CONFIG_DWC_AHSATA_PORT_ID	0
+#define CONFIG_DWC_AHSATA_BASE_ADDR	SATA_ARB_BASE_ADDR
+#define CONFIG_LBA48
+#define CONFIG_LIBATA
+#endif
  
+#ifdef CONFIG_MTD_NOR_FLASH
+#define CONFIG_SYS_FLASH_BASE           WEIM_ARB_BASE_ADDR
+#define CONFIG_SYS_FLASH_SECT_SIZE      (128 * 1024)
+#define CONFIG_SYS_MAX_FLASH_SECT 256   /* max number of sectors on one chip */
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
+#endif
+
+#ifdef CONFIG_NAND_MXS
+
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define CONFIG_SYS_NAND_BASE           0x40000000
+#define CONFIG_SYS_NAND_USE_FLASH_BBT
+
+/* DMA stuff, needed for GPMI/MXS NAND support */
+#endif
+
+#if defined(CONFIG_ENV_IS_IN_SATA)
+#define CONFIG_SYS_SATA_ENV_DEV		0
+#define CONFIG_SYS_DCACHE_OFF /* remove when sata driver support cache */
+#endif
+
+
+/* PMIC */
+#ifndef CONFIG_DM_PMIC
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
+#endif
+
 /* Framebuffer */
 #define CONFIG_VIDEO_BMP_LOGO
 #define CONFIG_IMX_HDMI
 #define CONFIG_IMX_VIDEO_SKIP
  
+#if defined(CONFIG_ANDROID_SUPPORT)
+#include "mx6sabreandroid_common.h"
+#else
 #define CONFIG_USBD_HS
  
+#endif /* CONFIG_ANDROID_SUPPORT */
 #endif                         /* __MX6QSABRE_COMMON_CONFIG_H */
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright 2018 NXP
  *
  * Configuration settings for the Freescale i.MX6Q SabreAuto board.
  */
  
  
  
  
@@ -14,18 +15,31 @@
  
 #define CONFIG_MXC_UART_BASE	UART4_BASE
 #define CONSOLE_DEV		"ttymxc3"
+#define CONFIG_MMCROOT		"/dev/mmcblk2p2"  /* SDHC3 */
+#define PHYS_SDRAM_SIZE		(2u * 1024 * 1024 * 1024)
+#ifdef CONFIG_MX6S
+#undef PHYS_SDRAM_SIZE
+#define PHYS_SDRAM_SIZE		(1u * 1024 * 1024 * 1024)
+#endif
  
+#include "mx6sabre_common.h"
+
+#define CONFIG_SYS_FSL_USDHC_NUM	2
+
+/*Since the pin conflicts on EIM D18, disable the USB host if the NOR flash is enabled */
+#ifdef CONFIG_USB
 /* USB Configs */
 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET	/* For OTG port */
 #define CONFIG_MXC_USB_PORTSC	(PORT_PTS_UTMI | PORT_PTS_PTW)
 #define CONFIG_MXC_USB_FLAGS	0
  
+#if !defined(CONFIG_DM_PCA953X) && defined(CONFIG_SYS_I2C)
 #define CONFIG_PCA953X
 #define CONFIG_SYS_I2C_PCA953X_WIDTH	{ {0x30, 8}, {0x32, 8}, {0x34, 8} }
+#endif
+#endif
  
-#include "mx6sabre_common.h"
-
 /* Falcon Mode */
 #ifdef CONFIG_SPL_OS_BOOT
 #define CONFIG_SPL_FS_LOAD_ARGS_NAME	"args"
@@ -36,26 +50,6 @@
 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR  0x800   /* 1MB */
 #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512)
 #endif
-
-#ifdef CONFIG_MTD_NOR_FLASH
-#define CONFIG_SYS_FLASH_BASE           WEIM_ARB_BASE_ADDR
-#define CONFIG_SYS_FLASH_SECT_SIZE      (128 * 1024)
-#define CONFIG_SYS_MAX_FLASH_SECT 256   /* max number of sectors on one chip */
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
-#endif
-
-#define CONFIG_SYS_FSL_USDHC_NUM	2
-
-/* NAND stuff */
-#define CONFIG_SYS_MAX_NAND_DEVICE     1
-#define CONFIG_SYS_NAND_BASE           0x40000000
-
-/* DMA stuff, needed for GPMI/MXS NAND support */
-
-/* PMIC */
-#define CONFIG_POWER_PFUZE100
-#define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
  
 #endif                         /* __MX6SABREAUTO_CONFIG_H */
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ * Copyright 2017-2018 NXP
  *
  * Configuration settings for the Freescale i.MX6Q SabreSD board.
  */
  
@@ -14,7 +15,16 @@
  
 #define CONFIG_MXC_UART_BASE	UART1_BASE
 #define CONSOLE_DEV		"ttymxc0"
+#define CONFIG_MMCROOT			"/dev/mmcblk2p2"  /* SDHC3 */
  
+#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6QP)
+#define PHYS_SDRAM_SIZE		(1u * 1024 * 1024 * 1024)
+#elif defined(CONFIG_MX6DL)
+#define PHYS_SDRAM_SIZE		(1u * 1024 * 1024 * 1024)
+#elif defined(CONFIG_MX6S)
+#define PHYS_SDRAM_SIZE		(512u * 1024 * 1024)
+#endif
+
 #include "mx6sabre_common.h"
  
 /* Falcon Mode */
@@ -28,6 +38,17 @@
  
 #define CONFIG_SYS_FSL_USDHC_NUM	3
  
+/*
+ * imx6 q/dl/solo pcie would be failed to work properly in kernel, if
+ * the pcie module is iniialized/enumerated both in uboot and linux
+ * kernel.
+ * rootcause:imx6 q/dl/solo pcie don't have the reset mechanism.
+ * it is only be RESET by the POR. So, the pcie module only be
+ * initialized/enumerated once in one POR.
+ * Set to use pcie in kernel defaultly, mask the pcie config here.
+ * Remove the mask freely, if the uboot pcie functions, rather than
+ * the kernel's, are required.
+ */
 #ifdef CONFIG_CMD_PCI
 #define CONFIG_PCI_SCAN_SHOW
 #define CONFIG_PCIE_IMX
@@ -35,10 +56,6 @@
 #define CONFIG_PCIE_IMX_POWER_GPIO	IMX_GPIO_NR(3, 19)
 #endif
  
-/* PMIC */
-#define CONFIG_POWER_PFUZE100
-#define CONFIG_POWER_PFUZE100_I2C_ADDR	0x08
-
 /* USB Configs */
 #ifdef CONFIG_CMD_USB
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
@@ -46,6 +63,25 @@
 #define CONFIG_MXC_USB_FLAGS		0
 #define CONFIG_USB_MAX_CONTROLLER_COUNT	1 /* Enabled USB controller number */
 #endif
+
+/*#define CONFIG_SPLASH_SCREEN*/
+/*#define CONFIG_MXC_EPDC*/
+
+/*
+ * SPLASH SCREEN Configs
+ */
+#if defined(CONFIG_MXC_EPDC)
+	/*
+	 * Framebuffer and LCD
+	 */
+	#define CONFIG_CMD_BMP
+	#undef LCD_TEST_PATTERN
+	/* #define CONFIG_SPLASH_IS_IN_MMC			1 */
+	#define LCD_BPP					LCD_MONOCHROME
+	/* #define CONFIG_SPLASH_SCREEN_ALIGN		1 */
+
+	#define CONFIG_WAVEFORM_BUF_SIZE		0x400000
+#endif /* CONFIG_SPLASH_SCREEN && CONFIG_MXC_EPDC */
  
 #endif                         /* __MX6SABRESD_CONFIG_H */
@@ -1842,6 +1842,7 @@
 CONFIG_SYS_SATA2
 CONFIG_SYS_SATA2_FLAGS
 CONFIG_SYS_SATA2_OFFSET
+CONFIG_SYS_SATA_ENV_DEV
 CONFIG_SYS_SATA_FAT_BOOT_PARTITION
 CONFIG_SYS_SBFHDR_DATA_OFFSET
 CONFIG_SYS_SBFHDR_SIZE
...	...	@@ -125,6 +125,30 @@
125	125	help
126	126	Set "Y" to enable the bee commands
127	127
	128	+config TARGET_MX6SABREAUTO_COMMON
	129	+ bool
	130	+ select BOARD_LATE_INIT
	131	+ select DM
	132	+ select DM_THERMAL
	133	+ select IMX_THERMAL
	134	+ select BOARD_EARLY_INIT_F
	135	+ select NXP_BOARD_REVISION
	136	+ imply CMD_DM
	137	+ select FSL_CAAM
	138	+ select ARCH_MISC_INIT
	139	+
	140	+config TARGET_MX6SABRESD_COMMON
	141	+ bool
	142	+ select BOARD_LATE_INIT
	143	+ select DM
	144	+ select DM_THERMAL
	145	+ select IMX_THERMAL
	146	+ select BOARD_EARLY_INIT_F
	147	+ select NXP_BOARD_REVISION
	148	+ imply CMD_DM
	149	+ select FSL_CAAM
	150	+ select ARCH_MISC_INIT
	151	+
128	152	choice
129	153	prompt "MX6 board select"
130	154	optional
...	...	@@ -387,6 +411,46 @@
387	411	imply CMD_DM
388	412	select FSL_CAAM
389	413	select ARCH_MISC_INIT
	414	+
	415	+config TARGET_MX6QSABREAUTO
	416	+ bool "mx6qsabreauto"
	417	+ select TARGET_MX6SABREAUTO_COMMON
	418	+ depends on MX6Q
	419	+
	420	+config TARGET_MX6QPSABREAUTO
	421	+ bool "mx6qpsabreauto"
	422	+ select TARGET_MX6SABREAUTO_COMMON
	423	+ depends on MX6QP
	424	+
	425	+config TARGET_MX6DLSABREAUTO
	426	+ bool "mx6dlsabreauto"
	427	+ select TARGET_MX6SABREAUTO_COMMON
	428	+ depends on MX6DL
	429	+
	430	+config TARGET_MX6SOLOSABREAUTO
	431	+ bool "mx6solosabreauto"
	432	+ select TARGET_MX6SABREAUTO_COMMON
	433	+ depends on MX6S
	434	+
	435	+config TARGET_MX6QSABRESD
	436	+ bool "mx6qsabresd"
	437	+ select TARGET_MX6SABRESD_COMMON
	438	+ depends on MX6Q
	439	+
	440	+config TARGET_MX6QPSABRESD
	441	+ bool "mx6qpsabresd"
	442	+ select TARGET_MX6SABRESD_COMMON
	443	+ depends on MX6QP
	444	+
	445	+config TARGET_MX6DLSABRESD
	446	+ bool "mx6dlsabresd"
	447	+ select TARGET_MX6SABRESD_COMMON
	448	+ depends on MX6DL
	449	+
	450	+config TARGET_MX6SOLOSABRESD
	451	+ bool "mx6solosabresd"
	452	+ select TARGET_MX6SABRESD_COMMON
	453	+ depends on MX6S
390	454
391	455	config TARGET_MX6SLEVK
392	456	bool "mx6slevk"
1		-if TARGET_MX6SABREAUTO
	1	+if TARGET_MX6SABREAUTO \|\| TARGET_MX6SABREAUTO_COMMON
2	2
3	3	config SYS_BOARD
4	4	default "mx6sabreauto"
...	...	@@ -9,5 +9,13 @@
9	9	config SYS_CONFIG_NAME
10	10	default "mx6sabreauto"
11	11
	12	+config SYS_TEXT_BASE
	13	+ default 0x17800000
	14	+
	15	+config NOR
	16	+ bool "Support for NOR flash"
	17	+ help
	18	+ The i.MX SoC supports having a NOR flash connected to the WEIM.
	19	+ Need to set this for NOR_BOOT.
12	20	endif
	1	+/*
	2	+ * Copyright (C) 2012-2016 Freescale Semiconductor, Inc.
	3	+ *
	4	+ * SPDX-License-Identifier: GPL-2.0+
	5	+ *
	6	+ * Refer doc/README.imximage for more details about how-to configure
	7	+ * and create imximage boot image
	8	+ *
	9	+ * The syntax is taken as close as possible with the kwbimage
	10	+ */
	11	+
	12	+#include <config.h>
	13	+
	14	+/* image version */
	15	+
	16	+IMAGE_VERSION 2
	17	+
	18	+/*
	19	+ * Boot Device : one of spi, sd, eimnor, nand, sata:
	20	+ * spinor: flash_offset: 0x0400
	21	+ * nand: flash_offset: 0x0400
	22	+ * sata: flash_offset: 0x0400
	23	+ * sd/mmc: flash_offset: 0x0400
	24	+ * eimnor: flash_offset: 0x1000
	25	+ */
	26	+
	27	+#if defined(CONFIG_NOR_BOOT)
	28	+BOOT_FROM nor
	29	+#else /* others has the same flash_offset as sd */
	30	+BOOT_FROM sd
	31	+#endif
	32	+
	33	+#ifdef CONFIG_USE_IMXIMG_PLUGIN
	34	+/PLUGIN plugin-binary-file IRAM_FREE_START_ADDR/
	35	+PLUGIN board/freescale/mx6sabreauto/plugin.bin 0x00907000
	36	+#else
	37	+
	38	+#ifdef CONFIG_IMX_HAB
	39	+CSF CONFIG_CSF_SIZE
	40	+#endif
	41	+
	42	+/*
	43	+ * Device Configuration Data (DCD)
	44	+ *
	45	+ * Each entry must have the format:
	46	+ * Addr-type Address Value
	47	+ *
	48	+ * where:
	49	+ * Addr-type register length (1,2 or 4 bytes)
	50	+ * Address absolute address of the register
	51	+ * value value to be stored in the register
	52	+ */
	53	+DATA 4 0x020e0798 0x000C0000
	54	+DATA 4 0x020e0758 0x00000000
	55	+DATA 4 0x020e0588 0x00000030
	56	+DATA 4 0x020e0594 0x00000030
	57	+DATA 4 0x020e056c 0x00000030
	58	+DATA 4 0x020e0578 0x00000030
	59	+DATA 4 0x020e074c 0x00000030
	60	+DATA 4 0x020e057c 0x00000030
	61	+DATA 4 0x020e058c 0x00000000
	62	+DATA 4 0x020e059c 0x00000030
	63	+DATA 4 0x020e05a0 0x00000030
	64	+DATA 4 0x020e078c 0x00000030
	65	+DATA 4 0x020e0750 0x00020000
	66	+DATA 4 0x020e05a8 0x00000028
	67	+DATA 4 0x020e05b0 0x00000028
	68	+DATA 4 0x020e0524 0x00000028
	69	+DATA 4 0x020e051c 0x00000028
	70	+DATA 4 0x020e0518 0x00000028
	71	+DATA 4 0x020e050c 0x00000028
	72	+DATA 4 0x020e05b8 0x00000028
	73	+DATA 4 0x020e05c0 0x00000028
	74	+DATA 4 0x020e0774 0x00020000
	75	+DATA 4 0x020e0784 0x00000028
	76	+DATA 4 0x020e0788 0x00000028
	77	+DATA 4 0x020e0794 0x00000028
	78	+DATA 4 0x020e079c 0x00000028
	79	+DATA 4 0x020e07a0 0x00000028
	80	+DATA 4 0x020e07a4 0x00000028
	81	+DATA 4 0x020e07a8 0x00000028
	82	+DATA 4 0x020e0748 0x00000028
	83	+DATA 4 0x020e05ac 0x00000028
	84	+DATA 4 0x020e05b4 0x00000028
	85	+DATA 4 0x020e0528 0x00000028
	86	+DATA 4 0x020e0520 0x00000028
	87	+DATA 4 0x020e0514 0x00000028
	88	+DATA 4 0x020e0510 0x00000028
	89	+DATA 4 0x020e05bc 0x00000028
	90	+DATA 4 0x020e05c4 0x00000028
	91	+DATA 4 0x021b0800 0xa1390003
	92	+DATA 4 0x021b080c 0x001F001F
	93	+DATA 4 0x021b0810 0x001F001F
	94	+DATA 4 0x021b480c 0x001F001F
	95	+DATA 4 0x021b4810 0x001F001F
	96	+DATA 4 0x021b083c 0x43260335
	97	+DATA 4 0x021b0840 0x031A030B
	98	+DATA 4 0x021b483c 0x4323033B
	99	+DATA 4 0x021b4840 0x0323026F
	100	+DATA 4 0x021b0848 0x483D4545
	101	+DATA 4 0x021b4848 0x44433E48
	102	+DATA 4 0x021b0850 0x41444840
	103	+DATA 4 0x021b4850 0x4835483E
	104	+DATA 4 0x021b081c 0x33333333
	105	+DATA 4 0x021b0820 0x33333333
	106	+DATA 4 0x021b0824 0x33333333
	107	+DATA 4 0x021b0828 0x33333333
	108	+DATA 4 0x021b481c 0x33333333
	109	+DATA 4 0x021b4820 0x33333333
	110	+DATA 4 0x021b4824 0x33333333
	111	+DATA 4 0x021b4828 0x33333333
	112	+DATA 4 0x021b08b8 0x00000800
	113	+DATA 4 0x021b48b8 0x00000800
	114	+DATA 4 0x021b0004 0x00020036
	115	+DATA 4 0x021b0008 0x09444040
	116	+DATA 4 0x021b000c 0x8A8F7955
	117	+DATA 4 0x021b0010 0xFF328F64
	118	+DATA 4 0x021b0014 0x01FF00DB
	119	+DATA 4 0x021b0018 0x00001740
	120	+DATA 4 0x021b001c 0x00008000
	121	+DATA 4 0x021b002c 0x000026d2
	122	+DATA 4 0x021b0030 0x008F1023
	123	+DATA 4 0x021b0040 0x00000047
	124	+DATA 4 0x021b0000 0x841A0000
	125	+DATA 4 0x021b001c 0x04088032
	126	+DATA 4 0x021b001c 0x00008033
	127	+DATA 4 0x021b001c 0x00048031
	128	+DATA 4 0x021b001c 0x09408030
	129	+DATA 4 0x021b001c 0x04008040
	130	+DATA 4 0x021b0020 0x00005800
	131	+DATA 4 0x021b0818 0x00011117
	132	+DATA 4 0x021b4818 0x00011117
	133	+DATA 4 0x021b0004 0x00025576
	134	+DATA 4 0x021b0404 0x00011006
	135	+DATA 4 0x021b001c 0x00000000
	136	+
	137	+/* set the default clock gate to save power */
	138	+DATA 4 0x020c4068 0x00C03F3F
	139	+DATA 4 0x020c406c 0x0030FC03
	140	+DATA 4 0x020c4070 0x0FFFF000
	141	+DATA 4 0x020c4074 0x3FF00000
	142	+DATA 4 0x020c4078 0xFFFFF300
	143	+DATA 4 0x020c407c 0x0F0000F3
	144	+DATA 4 0x020c4080 0x00000FFF
	145	+
	146	+/* enable AXI cache for VDOA/VPU/IPU */
	147	+DATA 4 0x020e0010 0xF00000CF
	148	+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
	149	+DATA 4 0x020e0018 0x007F007F
	150	+DATA 4 0x020e001c 0x007F007F
	151	+#endif
	1	+/*
	2	+ * Copyright (C) 2013-2016 Freescale Semiconductor, Inc.
	3	+ * Jason Liu <r64343@freescale.com>
	4	+ *
	5	+ * SPDX-License-Identifier: GPL-2.0+
	6	+ *
	7	+ * Refer doc/README.imximage for more details about how-to configure
	8	+ * and create imximage boot image
	9	+ *
	10	+ * The syntax is taken as close as possible with the kwbimage
	11	+ */
	12	+
	13	+#include <config.h>
	14	+
	15	+/* image version */
	16	+
	17	+IMAGE_VERSION 2
	18	+
	19	+/*
	20	+ * Boot Device : one of spi, sd, eimnor, nand, sata:
	21	+ * spinor: flash_offset: 0x0400
	22	+ * nand: flash_offset: 0x0400
	23	+ * sata: flash_offset: 0x0400
	24	+ * sd/mmc: flash_offset: 0x0400
	25	+ * eimnor: flash_offset: 0x1000
	26	+ */
	27	+
	28	+#if defined(CONFIG_NOR_BOOT)
	29	+BOOT_FROM nor
	30	+#else /* others has the same flash_offset as sd */
	31	+BOOT_FROM sd
	32	+#endif
	33	+
	34	+#ifdef CONFIG_USE_IMXIMG_PLUGIN
	35	+/PLUGIN plugin-binary-file IRAM_FREE_START_ADDR/
	36	+PLUGIN board/freescale/mx6sabreauto/plugin.bin 0x00907000
	37	+#else
	38	+
	39	+#ifdef CONFIG_IMX_HAB
	40	+CSF CONFIG_CSF_SIZE
	41	+#endif
	42	+
	43	+/*
	44	+ * Device Configuration Data (DCD)
	45	+ *
	46	+ * Each entry must have the format:
	47	+ * Addr-type Address Value
	48	+ *
	49	+ * where:
	50	+ * Addr-type register length (1,2 or 4 bytes)
	51	+ * Address absolute address of the register
	52	+ * value value to be stored in the register
	53	+ */
	54	+DATA 4 0x020e0774 0x000C0000
	55	+DATA 4 0x020e0754 0x00000000
	56	+DATA 4 0x020e04ac 0x00000030
	57	+DATA 4 0x020e04b0 0x00000030
	58	+DATA 4 0x020e0464 0x00000030
	59	+DATA 4 0x020e0490 0x00000030
	60	+DATA 4 0x020e074c 0x00000030
	61	+DATA 4 0x020e0494 0x00000030
	62	+DATA 4 0x020e04a0 0x00000000
	63	+DATA 4 0x020e04b4 0x00000030
	64	+DATA 4 0x020e04b8 0x00000030
	65	+DATA 4 0x020e076c 0x00000030
	66	+DATA 4 0x020e0750 0x00020000
	67	+DATA 4 0x020e04bc 0x00000028
	68	+DATA 4 0x020e04c0 0x00000028
	69	+DATA 4 0x020e04c4 0x00000028
	70	+DATA 4 0x020e04c8 0x00000028
	71	+DATA 4 0x020e04cc 0x00000028
	72	+DATA 4 0x020e04d0 0x00000028
	73	+DATA 4 0x020e04d4 0x00000028
	74	+DATA 4 0x020e04d8 0x00000028
	75	+DATA 4 0x020e0760 0x00020000
	76	+DATA 4 0x020e0764 0x00000028
	77	+DATA 4 0x020e0770 0x00000028
	78	+DATA 4 0x020e0778 0x00000028
	79	+DATA 4 0x020e077c 0x00000028
	80	+DATA 4 0x020e0780 0x00000028
	81	+DATA 4 0x020e0784 0x00000028
	82	+DATA 4 0x020e078c 0x00000028
	83	+DATA 4 0x020e0748 0x00000028
	84	+DATA 4 0x020e0470 0x00000028
	85	+DATA 4 0x020e0474 0x00000028
	86	+DATA 4 0x020e0478 0x00000028
	87	+DATA 4 0x020e047c 0x00000028
	88	+DATA 4 0x020e0480 0x00000028
	89	+DATA 4 0x020e0484 0x00000028
	90	+DATA 4 0x020e0488 0x00000028
	91	+DATA 4 0x020e048c 0x00000028
	92	+DATA 4 0x021b0800 0xa1390003
	93	+DATA 4 0x021b080c 0x001F001F
	94	+DATA 4 0x021b0810 0x001F001F
	95	+DATA 4 0x021b480c 0x001F001F
	96	+DATA 4 0x021b4810 0x001F001F
	97	+DATA 4 0x021b083c 0x42190217
	98	+DATA 4 0x021b0840 0x017B017B
	99	+DATA 4 0x021b483c 0x4176017B
	100	+DATA 4 0x021b4840 0x015F016C
	101	+DATA 4 0x021b0848 0x4C4C4D4C
	102	+DATA 4 0x021b4848 0x4A4D4C48
	103	+DATA 4 0x021b0850 0x3F3F3F40
	104	+DATA 4 0x021b4850 0x3538382E
	105	+DATA 4 0x021b081c 0x33333333
	106	+DATA 4 0x021b0820 0x33333333
	107	+DATA 4 0x021b0824 0x33333333
	108	+DATA 4 0x021b0828 0x33333333
	109	+DATA 4 0x021b481c 0x33333333
	110	+DATA 4 0x021b4820 0x33333333
	111	+DATA 4 0x021b4824 0x33333333
	112	+DATA 4 0x021b4828 0x33333333
	113	+DATA 4 0x021b08b8 0x00000800
	114	+DATA 4 0x021b48b8 0x00000800
	115	+DATA 4 0x021b0004 0x00020025
	116	+DATA 4 0x021b0008 0x00333030
	117	+DATA 4 0x021b000c 0x676B5313
	118	+DATA 4 0x021b0010 0xB66E8B63
	119	+DATA 4 0x021b0014 0x01FF00DB
	120	+DATA 4 0x021b0018 0x00001740
	121	+DATA 4 0x021b001c 0x00008000
	122	+DATA 4 0x021b002c 0x000026d2
	123	+DATA 4 0x021b0030 0x006B1023
	124	+DATA 4 0x021b0040 0x00000047
	125	+DATA 4 0x021b0000 0x841A0000
	126	+DATA 4 0x021b001c 0x04008032
	127	+DATA 4 0x021b001c 0x00008033
	128	+DATA 4 0x021b001c 0x00048031
	129	+DATA 4 0x021b001c 0x05208030
	130	+DATA 4 0x021b001c 0x04008040
	131	+DATA 4 0x021b0020 0x00005800
	132	+DATA 4 0x021b0818 0x00011117
	133	+DATA 4 0x021b4818 0x00011117
	134	+DATA 4 0x021b0004 0x00025565
	135	+DATA 4 0x021b0404 0x00011006
	136	+DATA 4 0x021b001c 0x00000000
	137	+
	138	+/* set the default clock gate to save power */
	139	+DATA 4 0x020c4068 0x00C03F3F
	140	+DATA 4 0x020c406c 0x0030FC03
	141	+DATA 4 0x020c4070 0x0FFFF000
	142	+DATA 4 0x020c4074 0x3FF00000
	143	+DATA 4 0x020c4078 0xFFFFF300
	144	+DATA 4 0x020c407c 0x0F0000C3
	145	+DATA 4 0x020c4080 0x00000FFF
	146	+
	147	+/* enable AXI cache for VDOA/VPU/IPU */
	148	+DATA 4 0x020e0010 0xF00000CF
	149	+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
	150	+DATA 4 0x020e0018 0x007F007F
	151	+DATA 4 0x020e001c 0x007F007F
	152	+#endif
	1	+/*
	2	+ * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
	3	+ *
	4	+ * SPDX-License-Identifier: GPL-2.0+
	5	+ *
	6	+ * Refer doc/README.imximage for more details about how-to configure
	7	+ * and create imximage boot image
	8	+ *
	9	+ * The syntax is taken as close as possible with the kwbimage
	10	+ */
	11	+/* image version */
	12	+
	13	+#include <config.h>
	14	+
	15	+IMAGE_VERSION 2
	16	+
	17	+/*
	18	+ * Boot Device : one of spi, sd, eimnor, nand, sata:
	19	+ * spinor: flash_offset: 0x0400
	20	+ * nand: flash_offset: 0x0400
	21	+ * sata: flash_offset: 0x0400
	22	+ * sd/mmc: flash_offset: 0x0400
	23	+ * eimnor: flash_offset: 0x1000
	24	+ */
	25	+
	26	+#if defined(CONFIG_NOR_BOOT)
	27	+BOOT_FROM nor
	28	+#else /* others has the same flash_offset as sd */
	29	+BOOT_FROM sd
	30	+#endif
	31	+
	32	+#ifdef CONFIG_USE_IMXIMG_PLUGIN
	33	+/PLUGIN plugin-binary-file IRAM_FREE_START_ADDR/
	34	+PLUGIN board/freescale/mx6sabreauto/plugin.bin 0x00907000
	35	+#else
	36	+
	37	+#ifdef CONFIG_IMX_HAB
	38	+CSF CONFIG_CSF_SIZE
	39	+#endif
	40	+
	41	+/*
	42	+ * Device Configuration Data (DCD)
	43	+ *
	44	+ * Each entry must have the format:
	45	+ * Addr-type Address Value
	46	+ *
	47	+ * where:
	48	+ * Addr-type register length (1,2 or 4 bytes)
	49	+ * Address absolute address of the register
	50	+ * value value to be stored in the register
	51	+ */
	52	+DATA 4 0x020e0798 0x000C0000
	53	+DATA 4 0x020e0758 0x00000000
	54	+DATA 4 0x020e0588 0x00000030
	55	+DATA 4 0x020e0594 0x00000030
	56	+DATA 4 0x020e056c 0x00000030
	57	+DATA 4 0x020e0578 0x00000030
	58	+DATA 4 0x020e074c 0x00000030
	59	+DATA 4 0x020e057c 0x00000030
	60	+DATA 4 0x020e058c 0x00000000
	61	+DATA 4 0x020e059c 0x00000030
	62	+DATA 4 0x020e05a0 0x00000030
	63	+DATA 4 0x020e078c 0x00000030
	64	+DATA 4 0x020e0750 0x00020000
	65	+DATA 4 0x020e05a8 0x00000030
	66	+DATA 4 0x020e05b0 0x00000030
	67	+DATA 4 0x020e0524 0x00000030
	68	+DATA 4 0x020e051c 0x00000030
	69	+DATA 4 0x020e0518 0x00000030
	70	+DATA 4 0x020e050c 0x00000030
	71	+DATA 4 0x020e05b8 0x00000030
	72	+DATA 4 0x020e05c0 0x00000030
	73	+DATA 4 0x020e0774 0x00020000
	74	+DATA 4 0x020e0784 0x00000030
	75	+DATA 4 0x020e0788 0x00000030
	76	+DATA 4 0x020e0794 0x00000030
	77	+DATA 4 0x020e079c 0x00000030
	78	+DATA 4 0x020e07a0 0x00000030
	79	+DATA 4 0x020e07a4 0x00000030
	80	+DATA 4 0x020e07a8 0x00000030
	81	+DATA 4 0x020e0748 0x00000030
	82	+DATA 4 0x020e05ac 0x00000030
	83	+DATA 4 0x020e05b4 0x00000030
	84	+DATA 4 0x020e0528 0x00000030
	85	+DATA 4 0x020e0520 0x00000030
	86	+DATA 4 0x020e0514 0x00000030
	87	+DATA 4 0x020e0510 0x00000030
	88	+DATA 4 0x020e05bc 0x00000030
	89	+DATA 4 0x020e05c4 0x00000030
	90	+DATA 4 0x021b0800 0xa1390003
	91	+DATA 4 0x021b080c 0x001b001e
	92	+DATA 4 0x021b0810 0x002e0029
	93	+DATA 4 0x021b480c 0x001b002a
	94	+DATA 4 0x021b4810 0x0019002c
	95	+DATA 4 0x021b083c 0x43240334
	96	+DATA 4 0x021b0840 0x0324031a
	97	+DATA 4 0x021b483c 0x43340344
	98	+DATA 4 0x021b4840 0x03280276
	99	+DATA 4 0x021b0848 0x44383A3E
	100	+DATA 4 0x021b4848 0x3C3C3846
	101	+DATA 4 0x021b0850 0x2e303230
	102	+DATA 4 0x021b4850 0x38283E34
	103	+DATA 4 0x021b081c 0x33333333
	104	+DATA 4 0x021b0820 0x33333333
	105	+DATA 4 0x021b0824 0x33333333
	106	+DATA 4 0x021b0828 0x33333333
	107	+DATA 4 0x021b481c 0x33333333
	108	+DATA 4 0x021b4820 0x33333333
	109	+DATA 4 0x021b4824 0x33333333
	110	+DATA 4 0x021b4828 0x33333333
	111	+DATA 4 0x021b08c0 0x24912249
	112	+DATA 4 0x021b48c0 0x24914289
	113	+DATA 4 0x021b08b8 0x00000800
	114	+DATA 4 0x021b48b8 0x00000800
	115	+DATA 4 0x021b0004 0x00020036
	116	+DATA 4 0x021b0008 0x24444040
	117	+DATA 4 0x021b000c 0x898E7955
	118	+DATA 4 0x021b0010 0xFF320F64
	119	+DATA 4 0x021b0014 0x01FF00DB
	120	+DATA 4 0x021b0018 0x00001740
	121	+DATA 4 0x021b001c 0x00008000
	122	+
	123	+DATA 4 0x021b002c 0x000026d2
	124	+DATA 4 0x021b0030 0x008E1023
	125	+DATA 4 0x021b0040 0x00000047
	126	+DATA 4 0x021b0400 0x14420000
	127	+DATA 4 0x021b0000 0x841A0000
	128	+DATA 4 0x021b0890 0x00400C58
	129	+DATA 4 0x00bb0008 0x00000000
	130	+DATA 4 0x00bb000c 0x2891E41A
	131	+DATA 4 0x00bb0038 0x00000564
	132	+DATA 4 0x00bb0014 0x00000040
	133	+DATA 4 0x00bb0028 0x00000020
	134	+DATA 4 0x00bb002c 0x00000020
	135	+DATA 4 0x021b001c 0x04088032
	136	+DATA 4 0x021b001c 0x00008033
	137	+DATA 4 0x021b001c 0x00048031
	138	+DATA 4 0x021b001c 0x09408030
	139	+DATA 4 0x021b001c 0x04008040
	140	+DATA 4 0x021b0020 0x00005800
	141	+DATA 4 0x021b0818 0x00011117
	142	+DATA 4 0x021b4818 0x00011117
	143	+DATA 4 0x021b0004 0x00025576
	144	+DATA 4 0x021b0404 0x00011006
	145	+DATA 4 0x021b001c 0x00000000
	146	+/* set the default clock gate to save power */
	147	+DATA 4, 0x020c4068, 0x00C03F3F
	148	+DATA 4, 0x020c406c, 0x0030FC03
	149	+DATA 4, 0x020c4070, 0x0FFFF000
	150	+DATA 4, 0x020c4074, 0x3FF00000
	151	+DATA 4, 0x020c4078, 0xFFFFF300
	152	+DATA 4, 0x020c407c, 0x0F0000F3
	153	+DATA 4, 0x020c4080, 0x00000FFF
	154	+
	155	+/* enable AXI cache for VDOA/VPU/IPU */
	156	+DATA 4, 0x020e0010, 0xF00000CF
	157	+/* set IPU AXI-id1 Qos=0x1 AXI-id0/2/3 Qos=0x7 */
	158	+DATA 4, 0x020e0018, 0x77177717
	159	+DATA 4, 0x020e001c, 0x77177717
	160	+#endif
1	1	// SPDX-License-Identifier: GPL-2.0+
2	2	/*
3		- * Copyright (C) 2012 Freescale Semiconductor, Inc.
	3	+ * Copyright (C) 2012-2016 Freescale Semiconductor, Inc.
	4	+ * Copyright 2017 NXP
4	5	*
5	6	* Author: Fabio Estevam <fabio.estevam@freescale.com>
6	7	*/
...	...	@@ -36,6 +37,16 @@
36	37	#include <power/pfuze100_pmic.h>
37	38	#include "../common/pfuze.h"
38	39
	40	+#ifdef CONFIG_SATA
	41	+#include <asm/mach-imx/sata.h>
	42	+#endif
	43	+#ifdef CONFIG_FSL_FASTBOOT
	44	+#include <fsl_fastboot.h>
	45	+#ifdef CONFIG_ANDROID_RECOVERY
	46	+#include <recovery.h>
	47	+#endif
	48	+#endif /CONFIG_FSL_FASTBOOT/
	49	+
39	50	DECLARE_GLOBAL_DATA_PTR;
40	51
41	52	#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP \| \
...	...	@@ -46,6 +57,11 @@
46	57	PAD_CTL_SPEED_LOW \| PAD_CTL_DSE_80ohm \| \
47	58	PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
48	59
	60	+/Need more drive strength for SD1 slot on base board/
	61	+#define USDHC1_PAD_CTRL (PAD_CTL_PKE \| PAD_CTL_PUE \| \
	62	+ PAD_CTL_PUS_47K_UP \| PAD_CTL_SPEED_LOW \| \
	63	+ PAD_CTL_DSE_40ohm \| PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
	64	+
49	65	#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP \| \
50	66	PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| PAD_CTL_HYS)
51	67
52	68
...	...	@@ -60,10 +76,18 @@
60	76
61	77	#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
62	78
	79	+#define SPI_PAD_CTRL (PAD_CTL_HYS \| \
	80	+ PAD_CTL_PUS_100K_DOWN \| PAD_CTL_SPEED_MED \| \
	81	+ PAD_CTL_DSE_40ohm \| PAD_CTL_SRE_FAST)
	82	+
63	83	#define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE \| PAD_CTL_PUE \| \
64	84	PAD_CTL_PUS_100K_UP \| PAD_CTL_SPEED_MED \| \
65	85	PAD_CTL_DSE_40ohm \| PAD_CTL_SRE_FAST)
66	86
	87	+#define OTG_ID_PAD_CTRL (PAD_CTL_PKE \| PAD_CTL_PUE \| \
	88	+ PAD_CTL_PUS_47K_UP \| PAD_CTL_SPEED_LOW \| \
	89	+ PAD_CTL_DSE_80ohm \| PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
	90	+
67	91	#define I2C_PMIC 1
68	92
69	93	int dram_init(void)
70	94
71	95
72	96
73	97
74	98
75	99
76	100
77	101
78	102
...	...	@@ -78,65 +102,40 @@
78	102	IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA \| MUX_PAD_CTRL(UART_PAD_CTRL)),
79	103	};
80	104
81		-
	105	+#ifdef CONFIG_SYS_I2C_LEGACY
82	106	/* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
83		-static struct i2c_pads_info mx6q_i2c_pad_info1 = {
	107	+static struct i2c_pads_info i2c_pad_info1 = {
84	108	.scl = {
85		- .i2c_mode = MX6Q_PAD_EIM_EB2__I2C2_SCL \| PC,
86		- .gpio_mode = MX6Q_PAD_EIM_EB2__GPIO2_IO30 \| PC,
	109	+ .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL \| PC,
	110	+ .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 \| PC,
87	111	.gp = IMX_GPIO_NR(2, 30)
88	112	},
89	113	.sda = {
90		- .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA \| PC,
91		- .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 \| PC,
	114	+ .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA \| PC,
	115	+ .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 \| PC,
92	116	.gp = IMX_GPIO_NR(4, 13)
93	117	}
94	118	};
95	119
96		-static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
97		- .scl = {
98		- .i2c_mode = MX6DL_PAD_EIM_EB2__I2C2_SCL \| PC,
99		- .gpio_mode = MX6DL_PAD_EIM_EB2__GPIO2_IO30 \| PC,
100		- .gp = IMX_GPIO_NR(2, 30)
101		- },
102		- .sda = {
103		- .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA \| PC,
104		- .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 \| PC,
105		- .gp = IMX_GPIO_NR(4, 13)
106		- }
107		-};
108		-
109	120	#ifndef CONFIG_SYS_FLASH_CFI
110	121	/*
111	122	* I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
112	123	* Compass Sensor, Accelerometer, Res Touch
113	124	*/
114		-static struct i2c_pads_info mx6q_i2c_pad_info2 = {
	125	+static struct i2c_pads_info i2c_pad_info2 = {
115	126	.scl = {
116		- .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL \| PC,
117		- .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 \| PC,
	127	+ .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL \| PC,
	128	+ .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 \| PC,
118	129	.gp = IMX_GPIO_NR(1, 3)
119	130	},
120	131	.sda = {
121		- .i2c_mode = MX6Q_PAD_EIM_D18__I2C3_SDA \| PC,
122		- .gpio_mode = MX6Q_PAD_EIM_D18__GPIO3_IO18 \| PC,
	132	+ .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA \| PC,
	133	+ .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 \| PC,
123	134	.gp = IMX_GPIO_NR(3, 18)
124	135	}
125	136	};
126		-
127		-static struct i2c_pads_info mx6dl_i2c_pad_info2 = {
128		- .scl = {
129		- .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL \| PC,
130		- .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 \| PC,
131		- .gp = IMX_GPIO_NR(1, 3)
132		- },
133		- .sda = {
134		- .i2c_mode = MX6DL_PAD_EIM_D18__I2C3_SDA \| PC,
135		- .gpio_mode = MX6DL_PAD_EIM_D18__GPIO3_IO18 \| PC,
136		- .gp = IMX_GPIO_NR(3, 18)
137		- }
138		-};
139	137	#endif
	138	+#endif
140	139
141	140	static iomux_v3_cfg_t const i2c3_pads[] = {
142	141	IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
...	...	@@ -245,6 +244,26 @@
245	244	#endif
246	245
247	246
	247	+static void setup_iomux_uart(void)
	248	+{
	249	+ SETUP_IOMUX_PADS(uart4_pads);
	250	+}
	251	+
	252	+#ifdef CONFIG_FSL_ESDHC_IMX
	253	+#if !CONFIG_IS_ENABLED(DM_MMC)
	254	+static iomux_v3_cfg_t const usdhc1_pads[] = {
	255	+ /To avoid pin conflict with NAND, set usdhc1 to 4 pins/
	256	+ IOMUX_PADS(PAD_SD1_CLK__SD1_CLK \| MUX_PAD_CTRL(USDHC1_PAD_CTRL)),
	257	+ IOMUX_PADS(PAD_SD1_CMD__SD1_CMD \| MUX_PAD_CTRL(USDHC1_PAD_CTRL)),
	258	+ IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 \| MUX_PAD_CTRL(USDHC1_PAD_CTRL)),
	259	+ IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 \| MUX_PAD_CTRL(USDHC1_PAD_CTRL)),
	260	+ IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 \| MUX_PAD_CTRL(USDHC1_PAD_CTRL)),
	261	+ IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 \| MUX_PAD_CTRL(USDHC1_PAD_CTRL)),
	262	+
	263	+ /CD pin/
	264	+ IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	265	+};
	266	+
248	267	static iomux_v3_cfg_t const usdhc3_pads[] = {
249	268	IOMUX_PADS(PAD_SD3_CLK__SD3_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
250	269	IOMUX_PADS(PAD_SD3_CMD__SD3_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL)),
251	270
252	271
253	272
254	273
255	274
...	...	@@ -260,30 +279,71 @@
260	279	IOMUX_PADS(PAD_NANDF_CS2__GPIO6_IO15 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
261	280	};
262	281
263		-static void setup_iomux_uart(void)
264		-{
265		- SETUP_IOMUX_PADS(uart4_pads);
266		-}
	282	+#define USDHC1_CD_GPIO IMX_GPIO_NR(1, 1)
	283	+#define USDHC3_CD_GPIO IMX_GPIO_NR(6, 15)
267	284
268		-#ifdef CONFIG_FSL_ESDHC_IMX
269		-static struct fsl_esdhc_cfg usdhc_cfg[1] = {
	285	+static struct fsl_esdhc_cfg usdhc_cfg[2] = {
	286	+ {USDHC1_BASE_ADDR, 0, 4},
270	287	{USDHC3_BASE_ADDR},
271	288	};
272	289
273	290	int board_mmc_getcd(struct mmc *mmc)
274	291	{
275		- gpio_direction_input(IMX_GPIO_NR(6, 15));
276		- return !gpio_get_value(IMX_GPIO_NR(6, 15));
	292	+ struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
	293	+ int ret = 0;
	294	+
	295	+ switch (cfg->esdhc_base) {
	296	+ case USDHC1_BASE_ADDR:
	297	+ gpio_direction_input(USDHC1_CD_GPIO);
	298	+ ret = !gpio_get_value(USDHC1_CD_GPIO);
	299	+ break;
	300	+ case USDHC3_BASE_ADDR:
	301	+ gpio_direction_input(USDHC3_CD_GPIO);
	302	+ ret = !gpio_get_value(USDHC3_CD_GPIO);
	303	+ break;
	304	+ }
	305	+
	306	+ return ret;
277	307	}
278	308
279	309	int board_mmc_init(struct bd_info *bis)
280	310	{
281		- SETUP_IOMUX_PADS(usdhc3_pads);
	311	+ int i;
282	312
283		- usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
284		- return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
	313	+ /*
	314	+ * According to the board_mmc_init() the following map is done:
	315	+ * (U-boot device node) (Physical Port)
	316	+ * mmc0 USDHC1
	317	+ * mmc1 USDHC3
	318	+ */
	319	+ for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
	320	+ switch (i) {
	321	+ case 0:
	322	+ SETUP_IOMUX_PADS(usdhc1_pads);
	323	+ gpio_request(USDHC1_CD_GPIO, "usdhc1 cd");
	324	+ gpio_direction_input(USDHC1_CD_GPIO);
	325	+ usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
	326	+ break;
	327	+ case 1:
	328	+ SETUP_IOMUX_PADS(usdhc3_pads);
	329	+ gpio_request(USDHC3_CD_GPIO, "usdhc3 cd");
	330	+ gpio_direction_input(USDHC3_CD_GPIO);
	331	+ usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
	332	+ break;
	333	+ default:
	334	+ printf("Warning: you configured more USDHC controllers"
	335	+ "(%d) than supported by the board\n", i + 1);
	336	+ return 0;
	337	+ }
	338	+
	339	+ if (fsl_esdhc_initialize(bis, &usdhc_cfg[i]))
	340	+ printf("Warning: failed to initialize mmc dev %d\n", i);
	341	+ }
	342	+
	343	+ return 0;
285	344	}
286	345	#endif
	346	+#endif
287	347
288	348	#ifdef CONFIG_NAND_MXS
289	349	static iomux_v3_cfg_t gpmi_pads[] = {
...	...	@@ -321,6 +381,24 @@
321	381	}
322	382	#endif
323	383
	384	+static void setup_fec(void)
	385	+{
	386	+ int ret;
	387	+
	388	+ if (is_mx6dqp()) {
	389	+ /*
	390	+ * select ENET MAC0 TX clock from PLL
	391	+ */
	392	+ imx_iomux_set_gpr_register(5, 9, 1, 1);
	393	+ } else {
	394	+ imx_iomux_set_gpr_register(1, 21, 1, 1);
	395	+ }
	396	+
	397	+ ret = enable_fec_anatop_clock(0, ENET_125MHZ);
	398	+ if (ret)
	399	+ printf("Error fec anatop clock settings!\n");
	400	+}
	401	+
324	402	#ifdef CONFIG_REVISION_TAG
325	403	u32 get_board_rev(void)
326	404	{
...	...	@@ -403,7 +481,7 @@
403	481	.bus = -1,
404	482	.addr = 0,
405	483	.pixfmt = IPU_PIX_FMT_RGB24,
406		- .detect = detect_hdmi,
	484	+ .detect = NULL,
407	485	.enable = do_enable_hdmi,
408	486	.mode = {
409	487	.name = "HDMI",
...	...	@@ -428,8 +506,22 @@
428	506
429	507	static void setup_iomux_backlight(void)
430	508	{
431		- gpio_request(IMX_GPIO_NR(2, 9), "backlight");
432		- gpio_direction_output(IMX_GPIO_NR(2, 9), 1);
	509	+ int ret;
	510	+ struct gpio_desc desc;
	511	+
	512	+ ret = dm_gpio_lookup_name("GPIO2_9", &desc);
	513	+ if (ret) {
	514	+ printf("%s lookup GPIO2_9 failed ret = %d\n", __func__, ret);
	515	+ return;
	516	+ }
	517	+
	518	+ ret = dm_gpio_request(&desc, "backlight");
	519	+ if (ret) {
	520	+ printf("%s request backlight failed ret = %d\n", __func__, ret);
	521	+ return;
	522	+ }
	523	+
	524	+ dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT \| GPIOD_IS_OUT_ACTIVE);
433	525	SETUP_IOMUX_PADS(backlight_pads);
434	526	}
435	527
...	...	@@ -497,6 +589,24 @@
497	589	return 1;
498	590	}
499	591
	592	+#ifdef CONFIG_MXC_SPI
	593	+iomux_v3_cfg_t const ecspi1_pads[] = {
	594	+ IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK \| MUX_PAD_CTRL(SPI_PAD_CTRL)),
	595	+ IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO \| MUX_PAD_CTRL(SPI_PAD_CTRL)),
	596	+ IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI \| MUX_PAD_CTRL(SPI_PAD_CTRL)),
	597	+ IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	598	+ /* Steer logic */
	599	+ IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	600	+};
	601	+
	602	+void setup_spinor(void)
	603	+{
	604	+ SETUP_IOMUX_PADS(ecspi1_pads);
	605	+
	606	+ gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
	607	+}
	608	+#endif
	609	+
500	610	int board_early_init_f(void)
501	611	{
502	612	setup_iomux_uart();
503	613
504	614
505	615
506	616
507	617
508	618
509	619
510	620
511	621
512	622
513	623
514	624
515	625
516	626
517	627
518	628
519	629
520	630
...	...	@@ -513,65 +623,281 @@
513	623
514	624	int board_init(void)
515	625	{
	626	+ int ret;
	627	+ struct gpio_desc desc;
	628	+
516	629	/* address of boot parameters */
517	630	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
518	631
	632	+#ifdef CONFIG_SYS_I2C_LEGACY
519	633	/* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
520		- if (is_mx6dq() \|\| is_mx6dqp())
521		- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
522		- else
523		- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
524		- /* I2C 3 Steer */
525		- gpio_request(IMX_GPIO_NR(5, 4), "steer logic");
526		- gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
527		- SETUP_IOMUX_PADS(i2c3_pads);
	634	+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
528	635	#ifndef CONFIG_SYS_FLASH_CFI
529		- if (is_mx6dq() \|\| is_mx6dqp())
530		- setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2);
531		- else
532		- setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2);
	636	+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
533	637	#endif
534		- gpio_request(IMX_GPIO_NR(1, 15), "expander en");
535		- gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
	638	+#endif
	639	+
	640	+ /* I2C 3 Steer */
	641	+ ret = dm_gpio_lookup_name("GPIO5_4", &desc);
	642	+ if (ret) {
	643	+ printf("%s lookup GPIO5_4 failed ret = %d\n", __func__, ret);
	644	+ return -ENODEV;
	645	+ }
	646	+ ret = dm_gpio_request(&desc, "steer logic");
	647	+ if (ret) {
	648	+ printf("%s request steer logic failed ret = %d\n", __func__, ret);
	649	+ return -ENODEV;
	650	+ }
	651	+ dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT \| GPIOD_IS_OUT_ACTIVE);
	652	+ SETUP_IOMUX_PADS(i2c3_pads);
	653	+
	654	+ ret = dm_gpio_lookup_name("GPIO1_15", &desc);
	655	+ if (ret) {
	656	+ printf("%s lookup GPIO1_15 failed ret = %d\n", __func__, ret);
	657	+ return -ENODEV;
	658	+ }
	659	+ ret = dm_gpio_request(&desc, "expander en");
	660	+ if (ret) {
	661	+ printf("%s request steer logic failed ret = %d\n", __func__, ret);
	662	+ return -ENODEV;
	663	+ }
	664	+ dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT \| GPIOD_IS_OUT_ACTIVE);
536	665	SETUP_IOMUX_PADS(port_exp);
537	666
538	667	#ifdef CONFIG_VIDEO_IPUV3
539	668	setup_display();
540	669	#endif
541	670
	671	+#ifdef CONFIG_MXC_SPI
	672	+ setup_spinor();
	673	+#endif
	674	+
	675	+#ifdef CONFIG_SATA
	676	+ setup_sata();
	677	+#endif
	678	+
542	679	#ifdef CONFIG_MTD_NOR_FLASH
543	680	setup_iomux_eimnor();
544	681	#endif
545		- return 0;
546		-}
547	682
548		-#ifdef CONFIG_MXC_SPI
549		-int board_spi_cs_gpio(unsigned bus, unsigned cs)
550		-{
551		- return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
552		-}
	683	+#ifdef CONFIG_FEC_MXC
	684	+ setup_fec();
553	685	#endif
554	686
	687	+ return 0;
	688	+}
	689	+
	690	+#ifdef CONFIG_POWER_LEGACY
555	691	int power_init_board(void)
556	692	{
557		- struct pmic *p;
	693	+ struct pmic *pfuze;
558	694	unsigned int value;
	695	+ int ret;
559	696
560		- p = pfuze_common_init(I2C_PMIC);
561		- if (!p)
	697	+ pfuze = pfuze_common_init(I2C_PMIC);
	698	+ if (!pfuze)
562	699	return -ENODEV;
563	700
	701	+ if (is_mx6dqp())
	702	+ ret = pfuze_mode_init(pfuze, APS_APS);
	703	+ else
	704	+ ret = pfuze_mode_init(pfuze, APS_PFM);
	705	+
	706	+ if (ret < 0)
	707	+ return ret;
	708	+
564	709	if (is_mx6dqp()) {
	710	+ /* set SW1C staby volatage 1.075V*/
	711	+ pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &value);
	712	+ value &= ~0x3f;
	713	+ value \|= 0x1f;
	714	+ pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, value);
	715	+
	716	+ /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
	717	+ pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &value);
	718	+ value &= ~0xc0;
	719	+ value \|= 0x40;
	720	+ pmic_reg_write(pfuze, PFUZE100_SW1CCONF, value);
	721	+
565	722	/* set SW2 staby volatage 0.975V*/
566		- pmic_reg_read(p, PFUZE100_SW2STBY, &value);
	723	+ pmic_reg_read(pfuze, PFUZE100_SW2STBY, &value);
567	724	value &= ~0x3f;
568	725	value \|= 0x17;
569		- pmic_reg_write(p, PFUZE100_SW2STBY, value);
	726	+ pmic_reg_write(pfuze, PFUZE100_SW2STBY, value);
	727	+
	728	+ /* set SW2/VDDARM step ramp up time to from 16us to 4us/25mV */
	729	+ pmic_reg_read(pfuze, PFUZE100_SW2CONF, &value);
	730	+ value &= ~0xc0;
	731	+ value \|= 0x40;
	732	+ pmic_reg_write(pfuze, PFUZE100_SW2CONF, value);
	733	+ } else {
	734	+ /* set SW1AB staby volatage 0.975V*/
	735	+ pmic_reg_read(pfuze, PFUZE100_SW1ABSTBY, &value);
	736	+ value &= ~0x3f;
	737	+ value \|= 0x1b;
	738	+ pmic_reg_write(pfuze, PFUZE100_SW1ABSTBY, value);
	739	+
	740	+ /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
	741	+ pmic_reg_read(pfuze, PFUZE100_SW1ABCONF, &value);
	742	+ value &= ~0xc0;
	743	+ value \|= 0x40;
	744	+ pmic_reg_write(pfuze, PFUZE100_SW1ABCONF, value);
	745	+
	746	+ /* set SW1C staby volatage 0.975V*/
	747	+ pmic_reg_read(pfuze, PFUZE100_SW1CSTBY, &value);
	748	+ value &= ~0x3f;
	749	+ value \|= 0x1b;
	750	+ pmic_reg_write(pfuze, PFUZE100_SW1CSTBY, value);
	751	+
	752	+ /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
	753	+ pmic_reg_read(pfuze, PFUZE100_SW1CCONF, &value);
	754	+ value &= ~0xc0;
	755	+ value \|= 0x40;
	756	+ pmic_reg_write(pfuze, PFUZE100_SW1CCONF, value);
570	757	}
571	758
572		- return pfuze_mode_init(p, APS_PFM);
	759	+ return 0;
573	760	}
	761	+#elif defined(CONFIG_DM_PMIC_PFUZE100)
	762	+int power_init_board(void)
	763	+{
	764	+ struct udevice *dev;
	765	+ unsigned int reg;
	766	+ int ret;
574	767
	768	+ dev = pfuze_common_init();
	769	+ if (!dev)
	770	+ return -ENODEV;
	771	+
	772	+ if (is_mx6dqp())
	773	+ ret = pfuze_mode_init(dev, APS_APS);
	774	+ else
	775	+ ret = pfuze_mode_init(dev, APS_PFM);
	776	+ if (ret < 0)
	777	+ return ret;
	778	+
	779	+ if (is_mx6dqp()) {
	780	+ /* set SW1C staby volatage 1.075V*/
	781	+ reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY);
	782	+ reg &= ~0x3f;
	783	+ reg \|= 0x1f;
	784	+ pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg);
	785	+
	786	+ /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
	787	+ reg = pmic_reg_read(dev, PFUZE100_SW1CCONF);
	788	+ reg &= ~0xc0;
	789	+ reg \|= 0x40;
	790	+ pmic_reg_write(dev, PFUZE100_SW1CCONF, reg);
	791	+
	792	+ /* set SW2/VDDARM staby volatage 0.975V*/
	793	+ reg = pmic_reg_read(dev, PFUZE100_SW2STBY);
	794	+ reg &= ~0x3f;
	795	+ reg \|= 0x17;
	796	+ pmic_reg_write(dev, PFUZE100_SW2STBY, reg);
	797	+
	798	+ /* set SW2/VDDARM step ramp up time to from 16us to 4us/25mV */
	799	+ reg = pmic_reg_read(dev, PFUZE100_SW2CONF);
	800	+ reg &= ~0xc0;
	801	+ reg \|= 0x40;
	802	+ pmic_reg_write(dev, PFUZE100_SW2CONF, reg);
	803	+ } else {
	804	+ /* set SW1AB staby volatage 0.975V*/
	805	+ reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY);
	806	+ reg &= ~0x3f;
	807	+ reg \|= 0x1b;
	808	+ pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg);
	809	+
	810	+ /* set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
	811	+ reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF);
	812	+ reg &= ~0xc0;
	813	+ reg \|= 0x40;
	814	+ pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg);
	815	+
	816	+ /* set SW1C staby volatage 0.975V*/
	817	+ reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY);
	818	+ reg &= ~0x3f;
	819	+ reg \|= 0x1b;
	820	+ pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg);
	821	+
	822	+ /* set SW1C/VDDSOC step ramp up time to from 16us to 4us/25mV */
	823	+ reg = pmic_reg_read(dev, PFUZE100_SW1CCONF);
	824	+ reg &= ~0xc0;
	825	+ reg \|= 0x40;
	826	+ pmic_reg_write(dev, PFUZE100_SW1CCONF, reg);
	827	+ }
	828	+
	829	+ return 0;
	830	+}
	831	+#endif
	832	+
	833	+#ifdef CONFIG_LDO_BYPASS_CHECK
	834	+#ifdef CONFIG_POWER_LEGACY
	835	+void ldo_mode_set(int ldo_bypass)
	836	+{
	837	+ unsigned int value;
	838	+ struct pmic *p = pmic_get("PFUZE100");
	839	+
	840	+ if (!p) {
	841	+ printf("No PMIC found!\n");
	842	+ return;
	843	+ }
	844	+
	845	+ /* increase VDDARM/VDDSOC to support 1.2G chip */
	846	+ if (check_1_2G()) {
	847	+ ldo_bypass = 0; /* ldo_enable on 1.2G chip */
	848	+ printf("1.2G chip, increase VDDARM_IN/VDDSOC_IN\n");
	849	+
	850	+ if (is_mx6dqp()) {
	851	+ /* increase VDDARM to 1.425V */
	852	+ pmic_reg_read(p, PFUZE100_SW2VOL, &value);
	853	+ value &= ~0x3f;
	854	+ value \|= 0x29;
	855	+ pmic_reg_write(p, PFUZE100_SW2VOL, value);
	856	+ } else {
	857	+ /* increase VDDARM to 1.425V */
	858	+ pmic_reg_read(p, PFUZE100_SW1ABVOL, &value);
	859	+ value &= ~0x3f;
	860	+ value \|= 0x2d;
	861	+ pmic_reg_write(p, PFUZE100_SW1ABVOL, value);
	862	+ }
	863	+ /* increase VDDSOC to 1.425V */
	864	+ pmic_reg_read(p, PFUZE100_SW1CVOL, &value);
	865	+ value &= ~0x3f;
	866	+ value \|= 0x2d;
	867	+ pmic_reg_write(p, PFUZE100_SW1CVOL, value);
	868	+ }
	869	+}
	870	+#elif defined(CONFIG_DM_PMIC_PFUZE100)
	871	+void ldo_mode_set(int ldo_bypass)
	872	+{
	873	+ struct udevice *dev;
	874	+ int ret;
	875	+
	876	+ ret = pmic_get("pfuze100@8", &dev);
	877	+ if (ret == -ENODEV) {
	878	+ printf("No PMIC found!\n");
	879	+ return;
	880	+ }
	881	+
	882	+ /* increase VDDARM/VDDSOC to support 1.2G chip */
	883	+ if (check_1_2G()) {
	884	+ ldo_bypass = 0; /* ldo_enable on 1.2G chip */
	885	+ printf("1.2G chip, increase VDDARM_IN/VDDSOC_IN\n");
	886	+
	887	+ if (is_mx6dqp()) {
	888	+ /* increase VDDARM to 1.425V */
	889	+ pmic_clrsetbits(dev, PFUZE100_SW2VOL, 0x3f, 0x29);
	890	+ } else {
	891	+ /* increase VDDARM to 1.425V */
	892	+ pmic_clrsetbits(dev, PFUZE100_SW1ABVOL, 0x3f, 0x2d);
	893	+ }
	894	+ /* increase VDDSOC to 1.425V */
	895	+ pmic_clrsetbits(dev, PFUZE100_SW1CVOL, 0x3f, 0x2d);
	896	+ }
	897	+}
	898	+#endif
	899	+#endif
	900	+
575	901	#ifdef CONFIG_CMD_BMODE
576	902	static const struct boot_mode board_boot_modes[] = {
577	903	/* 4 bit bus width */
...	...	@@ -627,6 +953,49 @@
627	953	return 0;
628	954	}
629	955	#endif
	956	+
	957	+#ifdef CONFIG_FSL_FASTBOOT
	958	+#ifdef CONFIG_ANDROID_RECOVERY
	959	+
	960	+iomux_v3_cfg_t const recovery_key_pads[] = {
	961	+ IOMUX_PADS(PAD_DISP0_DAT20__GPIO5_IO14 \| MUX_PAD_CTRL(NO_PAD_CTRL)),
	962	+};
	963	+
	964	+int is_recovery_key_pressing(void)
	965	+{
	966	+ int button_pressed = 0;
	967	+ int ret;
	968	+ struct gpio_desc desc;
	969	+
	970	+ /* Check Recovery Combo Button press or not. */
	971	+ SETUP_IOMUX_PADS(recovery_key_pads);
	972	+
	973	+ ret = dm_gpio_lookup_name("GPIO5_14", &desc);
	974	+ if (ret) {
	975	+ printf("%s lookup GPIO5_14 failed ret = %d\n", __func__, ret);
	976	+ return;
	977	+ }
	978	+
	979	+ ret = dm_gpio_request(&desc, "volume_dn_key");
	980	+ if (ret) {
	981	+ printf("%s request volume_dn_key failed ret = %d\n", __func__, ret);
	982	+ return;
	983	+ }
	984	+
	985	+ dm_gpio_set_dir_flags(&desc, GPIOD_IS_IN);
	986	+
	987	+ if (dm_gpio_get_value(&desc) == 0) { /* VOL_DN key is low assert */
	988	+ button_pressed = 1;
	989	+ printf("Recovery key pressed\n");
	990	+ }
	991	+
	992	+ return button_pressed;
	993	+}
	994	+
	995	+#endif /CONFIG_ANDROID_RECOVERY/
	996	+
	997	+#endif /CONFIG_FSL_FASTBOOT/
	998	+
630	999
631	1000	#ifdef CONFIG_SPL_BUILD
632	1001	#include <asm/arch/mx6-ddr.h>
	1	+/*
	2	+ * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
	3	+ * Jason Liu <r64343@freescale.com>
	4	+ *
	5	+ * SPDX-License-Identifier: GPL-2.0+
	6	+ *
	7	+ * Refer docs/README.imxmage for more details about how-to configure
	8	+ * and create imximage boot image
	9	+ *
	10	+ * The syntax is taken as close as possible with the kwbimage
	11	+ */
	12	+
	13	+#include <config.h>
	14	+
	15	+/* image version */
	16	+
	17	+IMAGE_VERSION 2
	18	+
	19	+/*
	20	+ * Boot Device : one of spi, sd, eimnor, nand, sata:
	21	+ * spinor: flash_offset: 0x0400
	22	+ * nand: flash_offset: 0x0400
	23	+ * sata: flash_offset: 0x0400
	24	+ * sd/mmc: flash_offset: 0x0400
	25	+ * eimnor: flash_offset: 0x1000
	26	+ */
	27	+
	28	+#if defined(CONFIG_NOR_BOOT)
	29	+BOOT_FROM nor
	30	+#else /* others has the same flash_offset as sd */
	31	+BOOT_FROM sd
	32	+#endif
	33	+
	34	+#ifdef CONFIG_USE_IMXIMG_PLUGIN
	35	+/PLUGIN plugin-binary-file IRAM_FREE_START_ADDR/
	36	+PLUGIN board/freescale/mx6sabreauto/plugin.bin 0x00907000
	37	+#else
	38	+
	39	+#ifdef CONFIG_IMX_HAB
	40	+CSF CONFIG_CSF_SIZE
	41	+#endif
	42	+
	43	+/*
	44	+ * Device Configuration Data (DCD)
	45	+ *
	46	+ * Each entry must have the format:
	47	+ * Addr-type Address Value
	48	+ *
	49	+ * where:
	50	+ * Addr-type register length (1,2 or 4 bytes)
	51	+ * Address absolute address of the register
	52	+ * value value to be stored in the register
	53	+ */
	54	+DATA 4, 0x020e0774, 0x000C0000
	55	+DATA 4, 0x020e0754, 0x00000000
	56	+DATA 4, 0x020e04ac, 0x00000030
	57	+DATA 4, 0x020e04b0, 0x00000030
	58	+DATA 4, 0x020e0464, 0x00000030
	59	+DATA 4, 0x020e0490, 0x00000030
	60	+DATA 4, 0x020e074c, 0x00000030
	61	+DATA 4, 0x020e0494, 0x00000030
	62	+DATA 4, 0x020e04a0, 0x00000000
	63	+DATA 4, 0x020e04b4, 0x00000030
	64	+DATA 4, 0x020e04b8, 0x00000030
	65	+DATA 4, 0x020e076c, 0x00000030
	66	+DATA 4, 0x020e0750, 0x00020000
	67	+DATA 4, 0x020e04bc, 0x00000028
	68	+DATA 4, 0x020e04c0, 0x00000028
	69	+DATA 4, 0x020e04c4, 0x00000028
	70	+DATA 4, 0x020e04c8, 0x00000028
	71	+DATA 4, 0x020e0760, 0x00020000
	72	+DATA 4, 0x020e0764, 0x00000028
	73	+DATA 4, 0x020e0770, 0x00000028
	74	+DATA 4, 0x020e0778, 0x00000028
	75	+DATA 4, 0x020e077c, 0x00000028
	76	+DATA 4, 0x020e0470, 0x00000028
	77	+DATA 4, 0x020e0474, 0x00000028
	78	+DATA 4, 0x020e0478, 0x00000028
	79	+DATA 4, 0x020e047c, 0x00000028
	80	+DATA 4, 0x021b0800, 0xa1390003
	81	+DATA 4, 0x021b080c, 0x001F001F
	82	+DATA 4, 0x021b0810, 0x001F001F
	83	+DATA 4, 0x021b083c, 0x421C0216
	84	+DATA 4, 0x021b0840, 0x017B017A
	85	+DATA 4, 0x021b0848, 0x4B4A4E4C
	86	+DATA 4, 0x021b0850, 0x3F3F3334
	87	+DATA 4, 0x021b081c, 0x33333333
	88	+DATA 4, 0x021b0820, 0x33333333
	89	+DATA 4, 0x021b0824, 0x33333333
	90	+DATA 4, 0x021b0828, 0x33333333
	91	+DATA 4, 0x021b08b8, 0x00000800
	92	+DATA 4, 0x021b0004, 0x00020025
	93	+DATA 4, 0x021b0008, 0x00333030
	94	+DATA 4, 0x021b000c, 0x676B5313
	95	+DATA 4, 0x021b0010, 0xB66E8B63
	96	+DATA 4, 0x021b0014, 0x01FF00DB
	97	+DATA 4, 0x021b0018, 0x00001740
	98	+DATA 4, 0x021b001c, 0x00008000
	99	+DATA 4, 0x021b002c, 0x000026d2
	100	+DATA 4, 0x021b0030, 0x006B1023
	101	+DATA 4, 0x021b0040, 0x00000027
	102	+DATA 4, 0x021b0000, 0x84190000
	103	+DATA 4, 0x021b001c, 0x04008032
	104	+DATA 4, 0x021b001c, 0x00008033
	105	+DATA 4, 0x021b001c, 0x00048031
	106	+DATA 4, 0x021b001c, 0x05208030
	107	+DATA 4, 0x021b001c, 0x04008040
	108	+DATA 4, 0x021b0020, 0x00005800
	109	+DATA 4, 0x021b0818, 0x00011117
	110	+DATA 4, 0x021b0004, 0x00025565
	111	+DATA 4, 0x021b0404, 0x00011006
	112	+DATA 4, 0x021b001c, 0x00000000
	113	+
	114	+/* set the default clock gate to save power */
	115	+DATA 4, 0x020c4068, 0x00C03F3F
	116	+DATA 4, 0x020c406c, 0x0030FC03
	117	+DATA 4, 0x020c4070, 0x0FFFF000
	118	+DATA 4, 0x020c4074, 0x3FF00000
	119	+DATA 4, 0x020c4078, 0xFFFFF300
	120	+DATA 4, 0x020c407c, 0x0F0000C3
	121	+DATA 4, 0x020c4080, 0x00000FFF
	122	+
	123	+/* enable AXI cache for VDOA/VPU/IPU */
	124	+DATA 4, 0x020e0010, 0xF00000CF
	125	+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
	126	+DATA 4, 0x020e0018, 0x007F007F
	127	+DATA 4, 0x020e001c, 0x007F007F
	128	+#endif
1		-if TARGET_MX6SABRESD
	1	+if TARGET_MX6SABRESD \|\| TARGET_MX6SABRESD_COMMON
2	2
3	3	config SYS_BOARD
4	4	default "mx6sabresd"
...	...	@@ -8,6 +8,9 @@
8	8
9	9	config SYS_CONFIG_NAME
10	10	default "mx6sabresd"
	11	+
	12	+config SYS_TEXT_BASE
	13	+ default 0x17800000
11	14
12	15	endif
	1	+/*
	2	+ * Copyright (C) 2011-2016 Freescale Semiconductor, Inc.
	3	+ * Copyright 2017 NXP
	4	+ * Jason Liu <r64343@freescale.com>
	5	+ *
	6	+ * SPDX-License-Identifier: GPL-2.0+
	7	+ *
	8	+ * Refer doc/README.imximage for more details about how-to configure
	9	+ * and create imximage boot image
	10	+ *
	11	+ * The syntax is taken as close as possible with the kwbimage
	12	+ */
	13	+
	14	+#include <config.h>
	15	+
	16	+/* image version */
	17	+IMAGE_VERSION 2
	18	+
	19	+/*
	20	+ * Boot Device : one of
	21	+ * spi, sd (the board has no nand neither onenand)
	22	+ */
	23	+BOOT_FROM sd
	24	+
	25	+#ifdef CONFIG_USE_IMXIMG_PLUGIN
	26	+/PLUGIN plugin-binary-file IRAM_FREE_START_ADDR/
	27	+PLUGIN board/freescale/mx6sabresd/plugin.bin 0x00907000
	28	+#else
	29	+
	30	+#ifdef CONFIG_IMX_HAB
	31	+CSF CONFIG_CSF_SIZE
	32	+#endif
	33	+
	34	+/*
	35	+ * Device Configuration Data (DCD)
	36	+ *
	37	+ * Each entry must have the format:
	38	+ * Addr-type Address Value
	39	+ *
	40	+ * where:
	41	+ * Addr-type register length (1,2 or 4 bytes)
	42	+ * Address absolute address of the register
	43	+ * value value to be stored in the register
	44	+ */
	45	+DATA 4 0x020e0798 0x000C0000
	46	+DATA 4 0x020e0758 0x00000000
	47	+DATA 4 0x020e0588 0x00000030
	48	+DATA 4 0x020e0594 0x00000030
	49	+DATA 4 0x020e056c 0x00000030
	50	+DATA 4 0x020e0578 0x00000030
	51	+DATA 4 0x020e074c 0x00000030
	52	+DATA 4 0x020e057c 0x00000030
	53	+DATA 4 0x020e058c 0x00000000
	54	+DATA 4 0x020e059c 0x00000030
	55	+DATA 4 0x020e05a0 0x00000030
	56	+DATA 4 0x020e078c 0x00000030
	57	+DATA 4 0x020e0750 0x00020000
	58	+DATA 4 0x020e05a8 0x00000030
	59	+DATA 4 0x020e05b0 0x00000030
	60	+DATA 4 0x020e0524 0x00000030
	61	+DATA 4 0x020e051c 0x00000030
	62	+DATA 4 0x020e0518 0x00000030
	63	+DATA 4 0x020e050c 0x00000030
	64	+DATA 4 0x020e05b8 0x00000030
	65	+DATA 4 0x020e05c0 0x00000030
	66	+DATA 4 0x020e0774 0x00020000
	67	+DATA 4 0x020e0784 0x00000030
	68	+DATA 4 0x020e0788 0x00000030
	69	+DATA 4 0x020e0794 0x00000030
	70	+DATA 4 0x020e079c 0x00000030
	71	+DATA 4 0x020e07a0 0x00000030
	72	+DATA 4 0x020e07a4 0x00000030
	73	+DATA 4 0x020e07a8 0x00000030
	74	+DATA 4 0x020e0748 0x00000030
	75	+DATA 4 0x020e05ac 0x00000030
	76	+DATA 4 0x020e05b4 0x00000030
	77	+DATA 4 0x020e0528 0x00000030
	78	+DATA 4 0x020e0520 0x00000030
	79	+DATA 4 0x020e0514 0x00000030
	80	+DATA 4 0x020e0510 0x00000030
	81	+DATA 4 0x020e05bc 0x00000030
	82	+DATA 4 0x020e05c4 0x00000030
	83	+DATA 4 0x021b0800 0xa1390003
	84	+DATA 4 0x021b080c 0x001F001F
	85	+DATA 4 0x021b0810 0x001F001F
	86	+DATA 4 0x021b480c 0x001F001F
	87	+DATA 4 0x021b4810 0x001F001F
	88	+DATA 4 0x021b083c 0x43270338
	89	+DATA 4 0x021b0840 0x03200314
	90	+DATA 4 0x021b483c 0x431A032F
	91	+DATA 4 0x021b4840 0x03200263
	92	+DATA 4 0x021b0848 0x4B434748
	93	+DATA 4 0x021b4848 0x4445404C
	94	+DATA 4 0x021b0850 0x38444542
	95	+DATA 4 0x021b4850 0x4935493A
	96	+DATA 4 0x021b081c 0x33333333
	97	+DATA 4 0x021b0820 0x33333333
	98	+DATA 4 0x021b0824 0x33333333
	99	+DATA 4 0x021b0828 0x33333333
	100	+DATA 4 0x021b481c 0x33333333
	101	+DATA 4 0x021b4820 0x33333333
	102	+DATA 4 0x021b4824 0x33333333
	103	+DATA 4 0x021b4828 0x33333333
	104	+DATA 4 0x021b08b8 0x00000800
	105	+DATA 4 0x021b48b8 0x00000800
	106	+DATA 4 0x021b0004 0x00020036
	107	+DATA 4 0x021b0008 0x09444040
	108	+DATA 4 0x021b000c 0x555A7975
	109	+DATA 4 0x021b0010 0xFF538F64
	110	+DATA 4 0x021b0014 0x01FF00DB
	111	+DATA 4 0x021b0018 0x00001740
	112	+DATA 4 0x021b001c 0x00008000
	113	+DATA 4 0x021b002c 0x000026d2
	114	+DATA 4 0x021b0030 0x005A1023
	115	+DATA 4 0x021b0040 0x00000027
	116	+DATA 4 0x021b0000 0x831A0000
	117	+DATA 4 0x021b001c 0x04088032
	118	+DATA 4 0x021b001c 0x00008033
	119	+DATA 4 0x021b001c 0x00048031
	120	+DATA 4 0x021b001c 0x09408030
	121	+DATA 4 0x021b001c 0x04008040
	122	+DATA 4 0x021b0020 0x00005800
	123	+DATA 4 0x021b0818 0x00011117
	124	+DATA 4 0x021b4818 0x00011117
	125	+DATA 4 0x021b0004 0x00025576
	126	+DATA 4 0x021b0404 0x00011006
	127	+DATA 4 0x021b001c 0x00000000
	128	+
	129	+/* set the default clock gate to save power */
	130	+DATA 4 0x020c4068 0x00C03F3F
	131	+DATA 4 0x020c406c 0x0030FC03
	132	+DATA 4 0x020c4070 0x0FFFF000
	133	+DATA 4 0x020c4074 0x3FF00000
	134	+DATA 4 0x020c4078 0x00FFF300
	135	+DATA 4 0x020c407c 0x0F0000F3
	136	+DATA 4 0x020c4080 0x000003FF
	137	+
	138	+/* enable AXI cache for VDOA/VPU/IPU */
	139	+DATA 4 0x020e0010 0xF00000CF
	140	+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
	141	+DATA 4 0x020e0018 0x007F007F
	142	+DATA 4 0x020e001c 0x007F007F
	143	+
	144	+/*
	145	+ * Setup CCM_CCOSR register as follows:
	146	+ *
	147	+ * cko1_en = 1 --> CKO1 enabled
	148	+ * cko1_div = 111 --> divide by 8
	149	+ * cko1_sel = 1011 --> ahb_clk_root
	150	+ *
	151	+ * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
	152	+ */
	153	+DATA 4 0x020c4060 0x000000fb
	154	+#endif
1	1	/* SPDX-License-Identifier: GPL-2.0+ */
2	2	/*
3	3	* Copyright (C) 2012 Freescale Semiconductor, Inc.
	4	+ * Copyright 2018 NXP
4	5	*
5	6	* Configuration settings for the Freescale i.MX6Q SabreSD board.
6	7	*/
...	...	@@ -15,6 +16,39 @@
15	16	/* MMC Configs */
16	17	#define CONFIG_SYS_FSL_ESDHC_ADDR 0
17	18
	19	+#define CONFIG_FEC_MXC
	20	+#define CONFIG_FEC_XCV_TYPE RGMII
	21	+#define CONFIG_ETHPRIME "eth0"
	22	+
	23	+#define CONFIG_PHY_ATHEROS
	24	+
	25	+#ifdef CONFIG_MX6S
	26	+#define SYS_NOSMP "nosmp"
	27	+#else
	28	+#define SYS_NOSMP
	29	+#endif
	30	+
	31	+#ifdef CONFIG_NAND_BOOT
	32	+#define MFG_NAND_PARTITION "mtdparts=8000000.nor:1m(boot),-(rootfs)\\;gpmi-nand:64m(nandboot),16m(nandkernel),16m(nanddtb),16m(nandtee),-(nandrootfs) "
	33	+#else
	34	+#define MFG_NAND_PARTITION ""
	35	+#endif
	36	+
	37	+#define CONFIG_MFG_ENV_SETTINGS \
	38	+ "mfgtool_args=setenv bootargs console=" CONSOLE_DEV ",115200 " \
	39	+ "rdinit=/linuxrc " \
	40	+ "g_mass_storage.stall=0 g_mass_storage.removable=1 " \
	41	+ "g_mass_storage.file=/fat g_mass_storage.ro=1 " \
	42	+ "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
	43	+ "g_mass_storage.iSerialNumber=\"\" "\
	44	+ "enable_wait_mode=off "\
	45	+ MFG_NAND_PARTITION \
	46	+ "\0" \
	47	+ "initrd_addr=0x12C00000\0" \
	48	+ "initrd_high=0xffffffff\0" \
	49	+ "bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
	50	+
	51	+
18	52	#ifdef CONFIG_SUPPORT_EMMC_BOOT
19	53	#define EMMC_ENV \
20	54	"emmcdev=2\0" \
21	55
22	56
...	...	@@ -35,10 +69,75 @@
35	69	#define EMMC_ENV ""
36	70	#endif
37	71
	72	+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
	73	+
	74	+#if defined(CONFIG_NAND_BOOT)
	75	+ /*
	76	+ * The dts also enables the WEIN NOR which is mtd0.
	77	+ * So the partions' layout for NAND is:
	78	+ * mtd1: 16M (uboot)
	79	+ * mtd2: 16M (kernel)
	80	+ * mtd3: 16M (dtb)
	81	+ * mtd4: left (rootfs)
	82	+ */
38	83	#define CONFIG_EXTRA_ENV_SETTINGS \
	84	+ CONFIG_MFG_ENV_SETTINGS \
	85	+ "fdt_addr=0x18000000\0" \
	86	+ "fdt_high=0xffffffff\0" \
	87	+ "console=" CONSOLE_DEV "\0" \
	88	+ "bootargs=console=" CONSOLE_DEV ",115200 ubi.mtd=6 " \
	89	+ "root=ubi0:nandrootfs rootfstype=ubifs " \
	90	+ MFG_NAND_PARTITION \
	91	+ "\0" \
	92	+ "bootcmd=nand read ${loadaddr} 0x4000000 0xc00000;"\
	93	+ "nand read ${fdt_addr} 0x5000000 0x100000;"\
	94	+ "bootz ${loadaddr} - ${fdt_addr}\0"
	95	+
	96	+#elif defined(CONFIG_SATA_BOOT)
	97	+
	98	+#define CONFIG_EXTRA_ENV_SETTINGS \
	99	+ CONFIG_MFG_ENV_SETTINGS \
	100	+ "image=zImage\0" \
	101	+ "fdt_file=undefined\0" \
	102	+ "fdt_addr=0x18000000\0" \
	103	+ "fdt_high=0xffffffff\0" \
	104	+ "findfdt="\
	105	+ "if test $fdt_file = undefined; then " \
	106	+ "if test $board_name = SABREAUTO && test $board_rev = MX6QP; then " \
	107	+ "setenv fdt_file imx6qp-sabreauto.dtb; fi; " \
	108	+ "if test $board_name = SABREAUTO && test $board_rev = MX6Q; then " \
	109	+ "setenv fdt_file imx6q-sabreauto.dtb; fi; " \
	110	+ "if test $board_name = SABREAUTO && test $board_rev = MX6DL; then " \
	111	+ "setenv fdt_file imx6dl-sabreauto.dtb; fi; " \
	112	+ "if test $board_name = SABRESD && test $board_rev = MX6QP; then " \
	113	+ "setenv fdt_file imx6qp-sabresd.dtb; fi; " \
	114	+ "if test $board_name = SABRESD && test $board_rev = MX6Q; then " \
	115	+ "setenv fdt_file imx6q-sabresd.dtb; fi; " \
	116	+ "if test $board_name = SABRESD && test $board_rev = MX6DL; then " \
	117	+ "setenv fdt_file imx6dl-sabresd.dtb; fi; " \
	118	+ "if test $fdt_file = undefined; then " \
	119	+ "echo WARNING: Could not determine dtb to use; " \
	120	+ "fi; " \
	121	+ "fi;\0" \
	122	+ "findtee="\
	123	+ "bootargs=console=" CONSOLE_DEV ",115200 \0"\
	124	+ "bootargs_sata=setenv bootargs ${bootargs} " \
	125	+ "root=/dev/sda2 rootwait rw \0" \
	126	+ "bootcmd_sata=run bootargs_sata; sata init; " \
	127	+ "run findfdt;" \
	128	+ "fatload sata 0:1 ${loadaddr} ${image}; " \
	129	+ "fatload sata 0:1 ${fdt_addr} ${fdt_file}; " \
	130	+ "bootz ${loadaddr} - ${fdt_addr} \0" \
	131	+ "bootcmd=run bootcmd_sata \0"
	132	+
	133	+#else
	134	+
	135	+#define CONFIG_EXTRA_ENV_SETTINGS \
	136	+ CONFIG_MFG_ENV_SETTINGS \
	137	+ "epdc_waveform=epdc_splash.bin\0" \
39	138	"script=boot.scr\0" \
40	139	"image=zImage\0" \
41		- "fdtfile=undefinedfile=undefined\0" \" \
	140	+ "fdt_file=undefinedfile=undefined\0" \" \
42	141	"fdt_addr=0x18000000\0" \
43	142	"boot_fdt=try\0" \
44	143	"ip_dyn=yes\0" \
...	...	@@ -53,6 +152,8 @@
53	152	"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \
54	153	"mmcpart=1\0" \
55	154	"finduuid=part uuid mmc ${mmcdev}:2 uuid\0" \
	155	+ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
	156	+ "mmcautodetect=yes\0" \
56	157	"update_sd_firmware=" \
57	158	"if test ${ip_dyn} = yes; then " \
58	159	"setenv get_cmd dhcp; " \
...	...	@@ -67,8 +168,9 @@
67	168	"fi; " \
68	169	"fi\0" \
69	170	EMMC_ENV \
70		- "mmcargs=setenv bootargs console=${console},${baudrate} " \
71		- "root=PARTUUID=${uuid} rootwait rw\0" \
	171	+ "smp=" SYS_NOSMP "\0"\
	172	+ "mmcargs=setenv bootargs console=${console},${baudrate} ${smp} " \
	173	+ "root=${mmcroot}\0" \
72	174	"loadbootscript=" \
73	175	"load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script} \|\| " \
74	176	"load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${script};\0" \
75	177
...	...	@@ -76,10 +178,9 @@
76	178	"source\0" \
77	179	"loadimage=load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image} \|\| " \
78	180	"load mmc ${mmcdev}:${mmcpart} ${loadaddr} boot/${image}\0" \
79		- "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdtfile} \|\| " \
80		- "load mmc ${mmcdev}:${mmcpart} ${fdt_addr} boot/${fdtfile}\0" \
	181	+ "loadfdt=load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file} \|\| " \
	182	+ "load mmc ${mmcdev}:${mmcpart} ${fdt_addr} boot/${fdt_file}\0" \
81	183	"mmcboot=echo Booting from mmc ...; " \
82		- "run finduuid; " \
83	184	"run mmcargs; " \
84	185	"if test ${boot_fdt} = yes \|\| test ${boot_fdt} = try; then " \
85	186	"if run loadfdt; then " \
...	...	@@ -94,7 +195,7 @@
94	195	"else " \
95	196	"bootz; " \
96	197	"fi;\0" \
97		- "netargs=setenv bootargs console=${console},${baudrate} " \
	198	+ "netargs=setenv bootargs console=${console},${baudrate} ${smp} " \
98	199	"root=/dev/nfs " \
99	200	"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
100	201	"netboot=echo Booting from net ...; " \
...	...	@@ -106,7 +207,7 @@
106	207	"fi; " \
107	208	"${get_cmd} ${image}; " \
108	209	"if test ${boot_fdt} = yes \|\| test ${boot_fdt} = try; then " \
109		- "if ${get_cmd} ${fdt_addr} ${fdtfile}; then " \
	210	+ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
110	211	"bootz ${loadaddr} - ${fdt_addr}; " \
111	212	"else " \
112	213	"if test ${boot_fdt} = try; then " \
113	214
114	215
115	216
116	217
117	218
118	219
119	220
...	...	@@ -119,23 +220,25 @@
119	220	"bootz; " \
120	221	"fi;\0" \
121	222	"findfdt="\
122		- "if test $fdtfile = undefined; then " \
	223	+ "if test $fdt_file = undefined; then " \
123	224	"if test $board_name = SABREAUTO && test $board_rev = MX6QP; then " \
124		- "setenv fdtfile imx6qp-sabreauto.dtb; fi; " \
	225	+ "setenv fdt_file imx6qp-sabreauto.dtb; fi; " \
125	226	"if test $board_name = SABREAUTO && test $board_rev = MX6Q; then " \
126		- "setenv fdtfile imx6q-sabreauto.dtb; fi; " \
	227	+ "setenv fdt_file imx6q-sabreauto.dtb; fi; " \
127	228	"if test $board_name = SABREAUTO && test $board_rev = MX6DL; then " \
128		- "setenv fdtfile imx6dl-sabreauto.dtb; fi; " \
	229	+ "setenv fdt_file imx6dl-sabreauto.dtb; fi; " \
129	230	"if test $board_name = SABRESD && test $board_rev = MX6QP; then " \
130		- "setenv fdtfile imx6qp-sabresd.dtb; fi; " \
	231	+ "setenv fdt_file imx6qp-sabresd.dtb; fi; " \
131	232	"if test $board_name = SABRESD && test $board_rev = MX6Q; then " \
132		- "setenv fdtfile imx6q-sabresd.dtb; fi; " \
	233	+ "setenv fdt_file imx6q-sabresd.dtb; fi; " \
133	234	"if test $board_name = SABRESD && test $board_rev = MX6DL; then " \
134		- "setenv fdtfile imx6dl-sabresd.dtb; fi; " \
135		- "if test $fdtfile = undefined; then " \
	235	+ "setenv fdt_file imx6dl-sabresd.dtb; fi; " \
	236	+ "if test $fdt_file = undefined; then " \
136	237	"echo WARNING: Could not determine dtb to use; fi; " \
137	238	"fi;\0" \
138	239
	240	+#endif
	241	+
139	242	#define CONFIG_ARP_TIMEOUT 200UL
140	243
141	244	/* Physical Memory Map */
142	245
143	246
144	247
...	...	@@ -150,14 +253,54 @@
150	253	#define CONFIG_SYS_INIT_SP_ADDR \
151	254	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
152	255
153		-/* Environment organization */
	256	+#ifdef CONFIG_SATA
	257	+#define CONFIG_DWC_AHSATA
	258	+#define CONFIG_SYS_SATA_MAX_DEVICE 1
	259	+#define CONFIG_DWC_AHSATA_PORT_ID 0
	260	+#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR
	261	+#define CONFIG_LBA48
	262	+#define CONFIG_LIBATA
	263	+#endif
154	264
	265	+#ifdef CONFIG_MTD_NOR_FLASH
	266	+#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR
	267	+#define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024)
	268	+#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
	269	+#define CONFIG_SYS_FLASH_EMPTY_INFO
	270	+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	271	+#endif
	272	+
	273	+#ifdef CONFIG_NAND_MXS
	274	+
	275	+#define CONFIG_SYS_MAX_NAND_DEVICE 1
	276	+#define CONFIG_SYS_NAND_BASE 0x40000000
	277	+#define CONFIG_SYS_NAND_USE_FLASH_BBT
	278	+
	279	+/* DMA stuff, needed for GPMI/MXS NAND support */
	280	+#endif
	281	+
	282	+#if defined(CONFIG_ENV_IS_IN_SATA)
	283	+#define CONFIG_SYS_SATA_ENV_DEV 0
	284	+#define CONFIG_SYS_DCACHE_OFF /* remove when sata driver support cache */
	285	+#endif
	286	+
	287	+
	288	+/* PMIC */
	289	+#ifndef CONFIG_DM_PMIC
	290	+#define CONFIG_POWER_PFUZE100
	291	+#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
	292	+#endif
	293	+
155	294	/* Framebuffer */
156	295	#define CONFIG_VIDEO_BMP_LOGO
157	296	#define CONFIG_IMX_HDMI
158	297	#define CONFIG_IMX_VIDEO_SKIP
159	298
	299	+#if defined(CONFIG_ANDROID_SUPPORT)
	300	+#include "mx6sabreandroid_common.h"
	301	+#else
160	302	#define CONFIG_USBD_HS
161	303
	304	+#endif /* CONFIG_ANDROID_SUPPORT */
162	305	#endif /* __MX6QSABRE_COMMON_CONFIG_H */