Eric Lee / smarc-uboot

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Commit 4cb4e654cafabaa1ac180d37b00c8f6095dae9c9

Authored by TsiChung Liew
Committed by John Rigby
1 parent 10db3a17a2
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

ColdFire: Multiple fixes for M5282EVB 

Incorrect CFG_HZ value, change 1000000 to 1000.
Rename #waring to #warning. RAMBAR1 uses twice
in start.S, rename the later to FLASHBAR. Insert
nop for DRAM setup. And, env_offset in linker file.

Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>

Showing 5 changed files with 12 additions and 6 deletions Inline Diff

board/freescale/m5282evb/m5282evb.c
Diff comments   View file @ 4cb4e65
1 /* 1 /*
2 * (C) Copyright 2000-2003 2 * (C) Copyright 2000-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * 4 *
5 * See file CREDITS for list of people who contributed to this 5 * See file CREDITS for list of people who contributed to this
6 * project. 6 * project.
7 * 7 *
8 * This program is free software; you can redistribute it and/or 8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as 9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of 10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version. 11 * the License, or (at your option) any later version.
12 * 12 *
13 * This program is distributed in the hope that it will be useful, 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA 21 * MA 02111-1307 USA
22 */ 22 */
23 23
24 #include <common.h> 24 #include <common.h>
25 #include <asm/immap.h> 25 #include <asm/immap.h>
26 26
27 DECLARE_GLOBAL_DATA_PTR; 27 DECLARE_GLOBAL_DATA_PTR;
28 28
29 int checkboard (void) 29 int checkboard (void)
30 { 30 {
31 puts ("Board: Freescale M5282EVB Evaluation Board\n"); 31 puts ("Board: Freescale M5282EVB Evaluation Board\n");
32 return 0; 32 return 0;
33 } 33 }
34 34
35 phys_size_t initdram (int board_type) 35 phys_size_t initdram (int board_type)
36 { 36 {
37 u32 dramsize, i, dramclk; 37 u32 dramsize, i, dramclk;
38 38
39 dramsize = CFG_SDRAM_SIZE * 0x100000; 39 dramsize = CFG_SDRAM_SIZE * 0x100000;
40 for (i = 0x13; i < 0x20; i++) { 40 for (i = 0x13; i < 0x20; i++) {
41 if (dramsize == (1 << i)) 41 if (dramsize == (1 << i))
42 break; 42 break;
43 } 43 }
44 i--; 44 i--;
45 45
46 if (!(MCFSDRAMC_DACR0 & MCFSDRAMC_DACR_RE)) 46 if (!(MCFSDRAMC_DACR0 & MCFSDRAMC_DACR_RE))
47 { 47 {
48 dramclk = gd->bus_clk / (CFG_HZ * CFG_HZ); 48 dramclk = gd->bus_clk / (CFG_HZ * CFG_HZ);
49 49
50 /* Initialize DRAM Control Register: DCR */ 50 /* Initialize DRAM Control Register: DCR */
51 MCFSDRAMC_DCR = (0 51 MCFSDRAMC_DCR = (0
52 | MCFSDRAMC_DCR_RTIM_6 52 | MCFSDRAMC_DCR_RTIM_6
53 | MCFSDRAMC_DCR_RC((15 * dramclk)>>4)); 53 | MCFSDRAMC_DCR_RC((15 * dramclk)>>4));
54 asm("nop");
54 55
55 /* Initialize DACR0 */ 56 /* Initialize DACR0 */
56 MCFSDRAMC_DACR0 = (0 57 MCFSDRAMC_DACR0 = (0
57 | MCFSDRAMC_DACR_BASE(CFG_SDRAM_BASE) 58 | MCFSDRAMC_DACR_BASE(CFG_SDRAM_BASE)
58 | MCFSDRAMC_DACR_CASL(1) 59 | MCFSDRAMC_DACR_CASL(1)
59 | MCFSDRAMC_DACR_CBM(3) 60 | MCFSDRAMC_DACR_CBM(3)
60 | MCFSDRAMC_DACR_PS_32); 61 | MCFSDRAMC_DACR_PS_32);
62 asm("nop");
61 63
62 /* Initialize DMR0 */ 64 /* Initialize DMR0 */
63 MCFSDRAMC_DMR0 = (0 65 MCFSDRAMC_DMR0 = (0
64 | ((dramsize - 1) & 0xFFFC0000) 66 | ((dramsize - 1) & 0xFFFC0000)
65 | MCFSDRAMC_DMR_V); 67 | MCFSDRAMC_DMR_V);
68 asm("nop");
66 69
67 /* Set IP (bit 3) in DACR */ 70 /* Set IP (bit 3) in DACR */
68 MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP; 71 MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP;
72 asm("nop");
69 73
70 /* Wait 30ns to allow banks to precharge */ 74 /* Wait 30ns to allow banks to precharge */
71 for (i = 0; i < 5; i++) { 75 for (i = 0; i < 5; i++) {
72 asm ("nop"); 76 asm ("nop");
73 } 77 }
74 78
75 /* Write to this block to initiate precharge */ 79 /* Write to this block to initiate precharge */
76 *(u32 *)(CFG_SDRAM_BASE) = 0xA5A59696; 80 *(u32 *)(CFG_SDRAM_BASE) = 0xA5A59696;
81 asm("nop");
77 82
78 /* Set RE (bit 15) in DACR */ 83 /* Set RE (bit 15) in DACR */
79 MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE; 84 MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE;
85 asm("nop");
80 86
81 /* Wait for at least 8 auto refresh cycles to occur */ 87 /* Wait for at least 8 auto refresh cycles to occur */
82 for (i = 0; i < 2000; i++) { 88 for (i = 0; i < 2000; i++) {
83 asm(" nop"); 89 asm(" nop");
84 } 90 }
85 91
86 /* Finish the configuration by issuing the IMRS. */ 92 /* Finish the configuration by issuing the IMRS. */
87 MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS; 93 MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS;
94 asm("nop");
88 95
89 /* Write to the SDRAM Mode Register */ 96 /* Write to the SDRAM Mode Register */
90 *(u32 *)(CFG_SDRAM_BASE + 0x400) = 0xA5A59696; 97 *(u32 *)(CFG_SDRAM_BASE + 0x400) = 0xA5A59696;
91 } 98 }
92 return dramsize; 99 return dramsize;
93 } 100 }
94 101
board/freescale/m5282evb/u-boot.lds
Diff comments   View file @ 4cb4e65
1 /* 1 /*
2 * (C) Copyright 2000-2003 2 * (C) Copyright 2000-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * 4 *
5 * See file CREDITS for list of people who contributed to this 5 * See file CREDITS for list of people who contributed to this
6 * project. 6 * project.
7 * 7 *
8 * This program is free software; you can redistribute it and/or 8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as 9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of 10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version. 11 * the License, or (at your option) any later version.
12 * 12 *
13 * This program is distributed in the hope that it will be useful, 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA 21 * MA 02111-1307 USA
22 */ 22 */
23 23
24 OUTPUT_ARCH(m68k) 24 OUTPUT_ARCH(m68k)
25 /* Do we need any of these for elf? 25 /* Do we need any of these for elf?
26 __DYNAMIC = 0; */ 26 __DYNAMIC = 0; */
27 SECTIONS 27 SECTIONS
28 { 28 {
29 /* Read-only sections, merged into text segment: */ 29 /* Read-only sections, merged into text segment: */
30 . = + SIZEOF_HEADERS; 30 . = + SIZEOF_HEADERS;
31 .interp : { *(.interp) } 31 .interp : { *(.interp) }
32 .hash : { *(.hash) } 32 .hash : { *(.hash) }
33 .dynsym : { *(.dynsym) } 33 .dynsym : { *(.dynsym) }
34 .dynstr : { *(.dynstr) } 34 .dynstr : { *(.dynstr) }
35 .rel.text : { *(.rel.text) } 35 .rel.text : { *(.rel.text) }
36 .rela.text : { *(.rela.text) } 36 .rela.text : { *(.rela.text) }
37 .rel.data : { *(.rel.data) } 37 .rel.data : { *(.rel.data) }
38 .rela.data : { *(.rela.data) } 38 .rela.data : { *(.rela.data) }
39 .rel.rodata : { *(.rel.rodata) } 39 .rel.rodata : { *(.rel.rodata) }
40 .rela.rodata : { *(.rela.rodata) } 40 .rela.rodata : { *(.rela.rodata) }
41 .rel.got : { *(.rel.got) } 41 .rel.got : { *(.rel.got) }
42 .rela.got : { *(.rela.got) } 42 .rela.got : { *(.rela.got) }
43 .rel.ctors : { *(.rel.ctors) } 43 .rel.ctors : { *(.rel.ctors) }
44 .rela.ctors : { *(.rela.ctors) } 44 .rela.ctors : { *(.rela.ctors) }
45 .rel.dtors : { *(.rel.dtors) } 45 .rel.dtors : { *(.rel.dtors) }
46 .rela.dtors : { *(.rela.dtors) } 46 .rela.dtors : { *(.rela.dtors) }
47 .rel.bss : { *(.rel.bss) } 47 .rel.bss : { *(.rel.bss) }
48 .rela.bss : { *(.rela.bss) } 48 .rela.bss : { *(.rela.bss) }
49 .rel.plt : { *(.rel.plt) } 49 .rel.plt : { *(.rel.plt) }
50 .rela.plt : { *(.rela.plt) } 50 .rela.plt : { *(.rela.plt) }
51 .init : { *(.init) } 51 .init : { *(.init) }
52 .plt : { *(.plt) } 52 .plt : { *(.plt) }
53 .text : 53 .text :
54 { 54 {
55 /* WARNING - the following is hand-optimized to fit within */ 55 /* WARNING - the following is hand-optimized to fit within */
56 /* the sector layout of our flash chips! XXX FIXME XXX */ 56 /* the sector layout of our flash chips! XXX FIXME XXX */
57 57
58 cpu/mcf52x2/start.o (.text) 58 cpu/mcf52x2/start.o (.text)
59 common/dlmalloc.o (.text) 59 common/dlmalloc.o (.text)
60 lib_generic/string.o (.text) 60 lib_generic/string.o (.text)
61 lib_generic/vsprintf.o (.text) 61 lib_generic/vsprintf.o (.text)
62 lib_generic/crc32.o (.text) 62 lib_generic/crc32.o (.text)
63 lib_generic/zlib.o (.text)
64 63
65 /* . = env_offset; */ 64 . = env_offset;
66 common/environment.o(.text) 65 common/environment.o(.text)
67 66
68 *(.text) 67 *(.text)
69 *(.fixup) 68 *(.fixup)
70 *(.got1) 69 *(.got1)
71 } 70 }
72 _etext = .; 71 _etext = .;
73 PROVIDE (etext = .); 72 PROVIDE (etext = .);
74 .rodata : 73 .rodata :
75 { 74 {
76 *(.rodata) 75 *(.rodata)
77 *(.rodata1) 76 *(.rodata1)
78 } 77 }
79 .fini : { *(.fini) } =0 78 .fini : { *(.fini) } =0
80 .ctors : { *(.ctors) } 79 .ctors : { *(.ctors) }
81 .dtors : { *(.dtors) } 80 .dtors : { *(.dtors) }
82 81
83 /* Read-write section, merged into data segment: */ 82 /* Read-write section, merged into data segment: */
84 . = (. + 0x00FF) & 0xFFFFFF00; 83 . = (. + 0x00FF) & 0xFFFFFF00;
85 _erotext = .; 84 _erotext = .;
86 PROVIDE (erotext = .); 85 PROVIDE (erotext = .);
87 .reloc : 86 .reloc :
88 { 87 {
89 __got_start = .; 88 __got_start = .;
90 *(.got) 89 *(.got)
91 __got_end = .; 90 __got_end = .;
92 _GOT2_TABLE_ = .; 91 _GOT2_TABLE_ = .;
93 *(.got2) 92 *(.got2)
94 _FIXUP_TABLE_ = .; 93 _FIXUP_TABLE_ = .;
95 *(.fixup) 94 *(.fixup)
96 } 95 }
97 __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; 96 __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
98 __fixup_entries = (. - _FIXUP_TABLE_)>>2; 97 __fixup_entries = (. - _FIXUP_TABLE_)>>2;
99 98
100 .data : 99 .data :
101 { 100 {
102 *(.data) 101 *(.data)
103 *(.data1) 102 *(.data1)
104 *(.sdata) 103 *(.sdata)
105 *(.sdata2) 104 *(.sdata2)
106 *(.dynamic) 105 *(.dynamic)
107 CONSTRUCTORS 106 CONSTRUCTORS
108 } 107 }
109 _edata = .; 108 _edata = .;
110 PROVIDE (edata = .); 109 PROVIDE (edata = .);
111 110
112 . = .; 111 . = .;
113 __u_boot_cmd_start = .; 112 __u_boot_cmd_start = .;
114 .u_boot_cmd : { *(.u_boot_cmd) } 113 .u_boot_cmd : { *(.u_boot_cmd) }
115 __u_boot_cmd_end = .; 114 __u_boot_cmd_end = .;
116 115
117 . = .; 116 . = .;
118 __start___ex_table = .; 117 __start___ex_table = .;
119 __ex_table : { *(__ex_table) } 118 __ex_table : { *(__ex_table) }
120 __stop___ex_table = .; 119 __stop___ex_table = .;
121 120
122 . = ALIGN(256); 121 . = ALIGN(256);
123 __init_begin = .; 122 __init_begin = .;
124 .text.init : { *(.text.init) } 123 .text.init : { *(.text.init) }
125 .data.init : { *(.data.init) } 124 .data.init : { *(.data.init) }
126 . = ALIGN(256); 125 . = ALIGN(256);
127 __init_end = .; 126 __init_end = .;
128 127
129 __bss_start = .; 128 __bss_start = .;
130 .bss (NOLOAD) : 129 .bss (NOLOAD) :
131 { 130 {
132 _sbss = .; 131 _sbss = .;
133 *(.sbss) *(.scommon) 132 *(.sbss) *(.scommon)
134 *(.dynbss) 133 *(.dynbss)
135 *(.bss) 134 *(.bss)
136 *(COMMON) 135 *(COMMON)
137 . = ALIGN(4); 136 . = ALIGN(4);
138 _ebss = .; 137 _ebss = .;
139 } 138 }
140 _end = . ; 139 _end = . ;
141 PROVIDE (end = .); 140 PROVIDE (end = .);
142 } 141 }
143 142
cpu/mcf52x2/cpu_init.c
Diff comments   View file @ 4cb4e65
1 /* 1 /*
2 * (C) Copyright 2003 2 * (C) Copyright 2003
3 * Josef Baumgartner <josef.baumgartner@telex.de> 3 * Josef Baumgartner <josef.baumgartner@telex.de>
4 * 4 *
5 * MCF5282 additionals 5 * MCF5282 additionals
6 * (C) Copyright 2005 6 * (C) Copyright 2005
7 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de> 7 * BuS Elektronik GmbH & Co. KG <esw@bus-elektronik.de>
8 * 8 *
9 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 9 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
10 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 10 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
11 * Hayden Fraser (Hayden.Fraser@freescale.com) 11 * Hayden Fraser (Hayden.Fraser@freescale.com)
12 * 12 *
13 * MCF5275 additions 13 * MCF5275 additions
14 * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com) 14 * Copyright (C) 2008 Arthur Shipkowski (art@videon-central.com)
15 * 15 *
16 * See file CREDITS for list of people who contributed to this 16 * See file CREDITS for list of people who contributed to this
17 * project. 17 * project.
18 * 18 *
19 * This program is free software; you can redistribute it and/or 19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License as 20 * modify it under the terms of the GNU General Public License as
21 * published by the Free Software Foundation; either version 2 of 21 * published by the Free Software Foundation; either version 2 of
22 * the License, or (at your option) any later version. 22 * the License, or (at your option) any later version.
23 * 23 *
24 * This program is distributed in the hope that it will be useful, 24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of 25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details. 27 * GNU General Public License for more details.
28 * 28 *
29 * You should have received a copy of the GNU General Public License 29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software 30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 31 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 * MA 02111-1307 USA 32 * MA 02111-1307 USA
33 */ 33 */
34 34
35 #include <common.h> 35 #include <common.h>
36 #include <watchdog.h> 36 #include <watchdog.h>
37 #include <asm/immap.h> 37 #include <asm/immap.h>
38 38
39 #if defined(CONFIG_M5253) 39 #if defined(CONFIG_M5253)
40 /* 40 /*
41 * Breath some life into the CPU... 41 * Breath some life into the CPU...
42 * 42 *
43 * Set up the memory map, 43 * Set up the memory map,
44 * initialize a bunch of registers, 44 * initialize a bunch of registers,
45 * initialize the UPM's 45 * initialize the UPM's
46 */ 46 */
47 void cpu_init_f(void) 47 void cpu_init_f(void)
48 { 48 {
49 mbar_writeByte(MCFSIM_MPARK, 0x40); /* 5249 Internal Core takes priority over DMA */ 49 mbar_writeByte(MCFSIM_MPARK, 0x40); /* 5249 Internal Core takes priority over DMA */
50 mbar_writeByte(MCFSIM_SYPCR, 0x00); 50 mbar_writeByte(MCFSIM_SYPCR, 0x00);
51 mbar_writeByte(MCFSIM_SWIVR, 0x0f); 51 mbar_writeByte(MCFSIM_SWIVR, 0x0f);
52 mbar_writeByte(MCFSIM_SWSR, 0x00); 52 mbar_writeByte(MCFSIM_SWSR, 0x00);
53 mbar_writeByte(MCFSIM_SWDICR, 0x00); 53 mbar_writeByte(MCFSIM_SWDICR, 0x00);
54 mbar_writeByte(MCFSIM_TIMER1ICR, 0x00); 54 mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
55 mbar_writeByte(MCFSIM_TIMER2ICR, 0x88); 55 mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
56 mbar_writeByte(MCFSIM_I2CICR, 0x00); 56 mbar_writeByte(MCFSIM_I2CICR, 0x00);
57 mbar_writeByte(MCFSIM_UART1ICR, 0x00); 57 mbar_writeByte(MCFSIM_UART1ICR, 0x00);
58 mbar_writeByte(MCFSIM_UART2ICR, 0x00); 58 mbar_writeByte(MCFSIM_UART2ICR, 0x00);
59 mbar_writeByte(MCFSIM_ICR6, 0x00); 59 mbar_writeByte(MCFSIM_ICR6, 0x00);
60 mbar_writeByte(MCFSIM_ICR7, 0x00); 60 mbar_writeByte(MCFSIM_ICR7, 0x00);
61 mbar_writeByte(MCFSIM_ICR8, 0x00); 61 mbar_writeByte(MCFSIM_ICR8, 0x00);
62 mbar_writeByte(MCFSIM_ICR9, 0x00); 62 mbar_writeByte(MCFSIM_ICR9, 0x00);
63 mbar_writeByte(MCFSIM_QSPIICR, 0x00); 63 mbar_writeByte(MCFSIM_QSPIICR, 0x00);
64 64
65 mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080); 65 mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
66 mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */ 66 mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
67 mbar2_writeByte(MCFSIM_SPURVEC, 0x00); 67 mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
68 68
69 /*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */ 69 /*mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); */ /* Enable a 1 cycle pre-drive cycle on CS1 */
70 70
71 /* 71 /*
72 * Setup chip selects... 72 * Setup chip selects...
73 */ 73 */
74 74
75 mbar_writeShort(MCFSIM_CSAR1, CFG_CSAR1); 75 mbar_writeShort(MCFSIM_CSAR1, CFG_CSAR1);
76 mbar_writeShort(MCFSIM_CSCR1, CFG_CSCR1); 76 mbar_writeShort(MCFSIM_CSCR1, CFG_CSCR1);
77 mbar_writeLong(MCFSIM_CSMR1, CFG_CSMR1); 77 mbar_writeLong(MCFSIM_CSMR1, CFG_CSMR1);
78 78
79 mbar_writeShort(MCFSIM_CSAR0, CFG_CSAR0); 79 mbar_writeShort(MCFSIM_CSAR0, CFG_CSAR0);
80 mbar_writeShort(MCFSIM_CSCR0, CFG_CSCR0); 80 mbar_writeShort(MCFSIM_CSCR0, CFG_CSCR0);
81 mbar_writeLong(MCFSIM_CSMR0, CFG_CSMR0); 81 mbar_writeLong(MCFSIM_CSMR0, CFG_CSMR0);
82 82
83 /* enable instruction cache now */ 83 /* enable instruction cache now */
84 icache_enable(); 84 icache_enable();
85 } 85 }
86 86
87 /*initialize higher level parts of CPU like timers */ 87 /*initialize higher level parts of CPU like timers */
88 int cpu_init_r(void) 88 int cpu_init_r(void)
89 { 89 {
90 return (0); 90 return (0);
91 } 91 }
92 92
93 void uart_port_conf(void) 93 void uart_port_conf(void)
94 { 94 {
95 /* Setup Ports: */ 95 /* Setup Ports: */
96 switch (CFG_UART_PORT) { 96 switch (CFG_UART_PORT) {
97 case 0: 97 case 0:
98 break; 98 break;
99 case 1: 99 case 1:
100 break; 100 break;
101 case 2: 101 case 2:
102 break; 102 break;
103 } 103 }
104 } 104 }
105 #endif /* #if defined(CONFIG_M5253) */ 105 #endif /* #if defined(CONFIG_M5253) */
106 106
107 #if defined(CONFIG_M5271) 107 #if defined(CONFIG_M5271)
108 void cpu_init_f(void) 108 void cpu_init_f(void)
109 { 109 {
110 #ifndef CONFIG_WATCHDOG 110 #ifndef CONFIG_WATCHDOG
111 /* Disable the watchdog if we aren't using it */ 111 /* Disable the watchdog if we aren't using it */
112 mbar_writeShort(MCF_WTM_WCR, 0); 112 mbar_writeShort(MCF_WTM_WCR, 0);
113 #endif 113 #endif
114 114
115 /* Set clockspeed to 100MHz */ 115 /* Set clockspeed to 100MHz */
116 mbar_writeShort(MCF_FMPLL_SYNCR, 116 mbar_writeShort(MCF_FMPLL_SYNCR,
117 MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0)); 117 MCF_FMPLL_SYNCR_MFD(0) | MCF_FMPLL_SYNCR_RFD(0));
118 while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK) ; 118 while (!mbar_readByte(MCF_FMPLL_SYNSR) & MCF_FMPLL_SYNSR_LOCK) ;
119 } 119 }
120 120
121 /* 121 /*
122 * initialize higher level parts of CPU like timers 122 * initialize higher level parts of CPU like timers
123 */ 123 */
124 int cpu_init_r(void) 124 int cpu_init_r(void)
125 { 125 {
126 return (0); 126 return (0);
127 } 127 }
128 128
129 void uart_port_conf(void) 129 void uart_port_conf(void)
130 { 130 {
131 /* Setup Ports: */ 131 /* Setup Ports: */
132 switch (CFG_UART_PORT) { 132 switch (CFG_UART_PORT) {
133 case 0: 133 case 0:
134 mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD | 134 mbar_writeShort(MCF_GPIO_PAR_UART, MCF_GPIO_PAR_UART_U0TXD |
135 MCF_GPIO_PAR_UART_U0RXD); 135 MCF_GPIO_PAR_UART_U0RXD);
136 break; 136 break;
137 case 1: 137 case 1:
138 mbar_writeShort(MCF_GPIO_PAR_UART, 138 mbar_writeShort(MCF_GPIO_PAR_UART,
139 MCF_GPIO_PAR_UART_U1RXD_UART1 | 139 MCF_GPIO_PAR_UART_U1RXD_UART1 |
140 MCF_GPIO_PAR_UART_U1TXD_UART1); 140 MCF_GPIO_PAR_UART_U1TXD_UART1);
141 break; 141 break;
142 case 2: 142 case 2:
143 mbar_writeShort(MCF_GPIO_PAR_UART, 0x3000); 143 mbar_writeShort(MCF_GPIO_PAR_UART, 0x3000);
144 break; 144 break;
145 } 145 }
146 } 146 }
147 #endif 147 #endif
148 148
149 #if defined(CONFIG_M5272) 149 #if defined(CONFIG_M5272)
150 /* 150 /*
151 * Breath some life into the CPU... 151 * Breath some life into the CPU...
152 * 152 *
153 * Set up the memory map, 153 * Set up the memory map,
154 * initialize a bunch of registers, 154 * initialize a bunch of registers,
155 * initialize the UPM's 155 * initialize the UPM's
156 */ 156 */
157 void cpu_init_f(void) 157 void cpu_init_f(void)
158 { 158 {
159 /* if we come from RAM we assume the CPU is 159 /* if we come from RAM we assume the CPU is
160 * already initialized. 160 * already initialized.
161 */ 161 */
162 #ifndef CONFIG_MONITOR_IS_IN_RAM 162 #ifndef CONFIG_MONITOR_IS_IN_RAM
163 volatile sysctrl_t *sysctrl = (sysctrl_t *) (CFG_MBAR); 163 volatile sysctrl_t *sysctrl = (sysctrl_t *) (CFG_MBAR);
164 volatile gpio_t *gpio = (gpio_t *) (MMAP_GPIO); 164 volatile gpio_t *gpio = (gpio_t *) (MMAP_GPIO);
165 volatile csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS); 165 volatile csctrl_t *csctrl = (csctrl_t *) (MMAP_FBCS);
166 166
167 sysctrl->sc_scr = CFG_SCR; 167 sysctrl->sc_scr = CFG_SCR;
168 sysctrl->sc_spr = CFG_SPR; 168 sysctrl->sc_spr = CFG_SPR;
169 169
170 /* Setup Ports: */ 170 /* Setup Ports: */
171 gpio->gpio_pacnt = CFG_PACNT; 171 gpio->gpio_pacnt = CFG_PACNT;
172 gpio->gpio_paddr = CFG_PADDR; 172 gpio->gpio_paddr = CFG_PADDR;
173 gpio->gpio_padat = CFG_PADAT; 173 gpio->gpio_padat = CFG_PADAT;
174 gpio->gpio_pbcnt = CFG_PBCNT; 174 gpio->gpio_pbcnt = CFG_PBCNT;
175 gpio->gpio_pbddr = CFG_PBDDR; 175 gpio->gpio_pbddr = CFG_PBDDR;
176 gpio->gpio_pbdat = CFG_PBDAT; 176 gpio->gpio_pbdat = CFG_PBDAT;
177 gpio->gpio_pdcnt = CFG_PDCNT; 177 gpio->gpio_pdcnt = CFG_PDCNT;
178 178
179 /* Memory Controller: */ 179 /* Memory Controller: */
180 csctrl->cs_br0 = CFG_BR0_PRELIM; 180 csctrl->cs_br0 = CFG_BR0_PRELIM;
181 csctrl->cs_or0 = CFG_OR0_PRELIM; 181 csctrl->cs_or0 = CFG_OR0_PRELIM;
182 182
183 #if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM)) 183 #if (defined(CFG_OR1_PRELIM) && defined(CFG_BR1_PRELIM))
184 csctrl->cs_br1 = CFG_BR1_PRELIM; 184 csctrl->cs_br1 = CFG_BR1_PRELIM;
185 csctrl->cs_or1 = CFG_OR1_PRELIM; 185 csctrl->cs_or1 = CFG_OR1_PRELIM;
186 #endif 186 #endif
187 187
188 #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM) 188 #if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
189 csctrl->cs_br2 = CFG_BR2_PRELIM; 189 csctrl->cs_br2 = CFG_BR2_PRELIM;
190 csctrl->cs_or2 = CFG_OR2_PRELIM; 190 csctrl->cs_or2 = CFG_OR2_PRELIM;
191 #endif 191 #endif
192 192
193 #if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM) 193 #if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM)
194 csctrl->cs_br3 = CFG_BR3_PRELIM; 194 csctrl->cs_br3 = CFG_BR3_PRELIM;
195 csctrl->cs_or3 = CFG_OR3_PRELIM; 195 csctrl->cs_or3 = CFG_OR3_PRELIM;
196 #endif 196 #endif
197 197
198 #if defined(CFG_OR4_PRELIM) && defined(CFG_BR4_PRELIM) 198 #if defined(CFG_OR4_PRELIM) && defined(CFG_BR4_PRELIM)
199 csctrl->cs_br4 = CFG_BR4_PRELIM; 199 csctrl->cs_br4 = CFG_BR4_PRELIM;
200 csctrl->cs_or4 = CFG_OR4_PRELIM; 200 csctrl->cs_or4 = CFG_OR4_PRELIM;
201 #endif 201 #endif
202 202
203 #if defined(CFG_OR5_PRELIM) && defined(CFG_BR5_PRELIM) 203 #if defined(CFG_OR5_PRELIM) && defined(CFG_BR5_PRELIM)
204 csctrl->cs_br5 = CFG_BR5_PRELIM; 204 csctrl->cs_br5 = CFG_BR5_PRELIM;
205 csctrl->cs_or5 = CFG_OR5_PRELIM; 205 csctrl->cs_or5 = CFG_OR5_PRELIM;
206 #endif 206 #endif
207 207
208 #if defined(CFG_OR6_PRELIM) && defined(CFG_BR6_PRELIM) 208 #if defined(CFG_OR6_PRELIM) && defined(CFG_BR6_PRELIM)
209 csctrl->cs_br6 = CFG_BR6_PRELIM; 209 csctrl->cs_br6 = CFG_BR6_PRELIM;
210 csctrl->cs_or6 = CFG_OR6_PRELIM; 210 csctrl->cs_or6 = CFG_OR6_PRELIM;
211 #endif 211 #endif
212 212
213 #if defined(CFG_OR7_PRELIM) && defined(CFG_BR7_PRELIM) 213 #if defined(CFG_OR7_PRELIM) && defined(CFG_BR7_PRELIM)
214 csctrl->cs_br7 = CFG_BR7_PRELIM; 214 csctrl->cs_br7 = CFG_BR7_PRELIM;
215 csctrl->cs_or7 = CFG_OR7_PRELIM; 215 csctrl->cs_or7 = CFG_OR7_PRELIM;
216 #endif 216 #endif
217 217
218 #endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */ 218 #endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
219 219
220 /* enable instruction cache now */ 220 /* enable instruction cache now */
221 icache_enable(); 221 icache_enable();
222 222
223 } 223 }
224 224
225 /* 225 /*
226 * initialize higher level parts of CPU like timers 226 * initialize higher level parts of CPU like timers
227 */ 227 */
228 int cpu_init_r(void) 228 int cpu_init_r(void)
229 { 229 {
230 return (0); 230 return (0);
231 } 231 }
232 232
233 void uart_port_conf(void) 233 void uart_port_conf(void)
234 { 234 {
235 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; 235 volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
236 236
237 /* Setup Ports: */ 237 /* Setup Ports: */
238 switch (CFG_UART_PORT) { 238 switch (CFG_UART_PORT) {
239 case 0: 239 case 0:
240 gpio->gpio_pbcnt &= ~(GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK); 240 gpio->gpio_pbcnt &= ~(GPIO_PBCNT_PB0MSK | GPIO_PBCNT_PB1MSK);
241 gpio->gpio_pbcnt |= (GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD); 241 gpio->gpio_pbcnt |= (GPIO_PBCNT_URT0_TXD | GPIO_PBCNT_URT0_RXD);
242 break; 242 break;
243 case 1: 243 case 1:
244 gpio->gpio_pdcnt &= ~(GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK); 244 gpio->gpio_pdcnt &= ~(GPIO_PDCNT_PD1MSK | GPIO_PDCNT_PD4MSK);
245 gpio->gpio_pdcnt |= (GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD); 245 gpio->gpio_pdcnt |= (GPIO_PDCNT_URT1_RXD | GPIO_PDCNT_URT1_TXD);
246 break; 246 break;
247 } 247 }
248 } 248 }
249 #endif /* #if defined(CONFIG_M5272) */ 249 #endif /* #if defined(CONFIG_M5272) */
250 250
251 #if defined(CONFIG_M5275) 251 #if defined(CONFIG_M5275)
252 252
253 /* 253 /*
254 * Breathe some life into the CPU... 254 * Breathe some life into the CPU...
255 * 255 *
256 * Set up the memory map, 256 * Set up the memory map,
257 * initialize a bunch of registers, 257 * initialize a bunch of registers,
258 * initialize the UPM's 258 * initialize the UPM's
259 */ 259 */
260 void cpu_init_f(void) 260 void cpu_init_f(void)
261 { 261 {
262 /* if we come from RAM we assume the CPU is 262 /* if we come from RAM we assume the CPU is
263 * already initialized. 263 * already initialized.
264 */ 264 */
265 265
266 #ifndef CONFIG_MONITOR_IS_IN_RAM 266 #ifndef CONFIG_MONITOR_IS_IN_RAM
267 volatile wdog_t *wdog_reg = (wdog_t *)(MMAP_WDOG); 267 volatile wdog_t *wdog_reg = (wdog_t *)(MMAP_WDOG);
268 volatile gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO); 268 volatile gpio_t *gpio_reg = (gpio_t *)(MMAP_GPIO);
269 volatile csctrl_t *csctrl_reg = (csctrl_t *)(MMAP_FBCS); 269 volatile csctrl_t *csctrl_reg = (csctrl_t *)(MMAP_FBCS);
270 270
271 /* Kill watchdog so we can initialize the PLL */ 271 /* Kill watchdog so we can initialize the PLL */
272 wdog_reg->wcr = 0; 272 wdog_reg->wcr = 0;
273 273
274 /* Memory Controller: */ 274 /* Memory Controller: */
275 /* Flash */ 275 /* Flash */
276 csctrl_reg->ar0 = CFG_AR0_PRELIM; 276 csctrl_reg->ar0 = CFG_AR0_PRELIM;
277 csctrl_reg->cr0 = CFG_CR0_PRELIM; 277 csctrl_reg->cr0 = CFG_CR0_PRELIM;
278 csctrl_reg->mr0 = CFG_MR0_PRELIM; 278 csctrl_reg->mr0 = CFG_MR0_PRELIM;
279 279
280 #if (defined(CFG_AR1_PRELIM) && defined(CFG_CR1_PRELIM) && defined(CFG_MR1_PRELIM)) 280 #if (defined(CFG_AR1_PRELIM) && defined(CFG_CR1_PRELIM) && defined(CFG_MR1_PRELIM))
281 csctrl_reg->ar1 = CFG_AR1_PRELIM; 281 csctrl_reg->ar1 = CFG_AR1_PRELIM;
282 csctrl_reg->cr1 = CFG_CR1_PRELIM; 282 csctrl_reg->cr1 = CFG_CR1_PRELIM;
283 csctrl_reg->mr1 = CFG_MR1_PRELIM; 283 csctrl_reg->mr1 = CFG_MR1_PRELIM;
284 #endif 284 #endif
285 285
286 #if (defined(CFG_AR2_PRELIM) && defined(CFG_CR2_PRELIM) && defined(CFG_MR2_PRELIM)) 286 #if (defined(CFG_AR2_PRELIM) && defined(CFG_CR2_PRELIM) && defined(CFG_MR2_PRELIM))
287 csctrl_reg->ar2 = CFG_AR2_PRELIM; 287 csctrl_reg->ar2 = CFG_AR2_PRELIM;
288 csctrl_reg->cr2 = CFG_CR2_PRELIM; 288 csctrl_reg->cr2 = CFG_CR2_PRELIM;
289 csctrl_reg->mr2 = CFG_MR2_PRELIM; 289 csctrl_reg->mr2 = CFG_MR2_PRELIM;
290 #endif 290 #endif
291 291
292 #if (defined(CFG_AR3_PRELIM) && defined(CFG_CR3_PRELIM) && defined(CFG_MR3_PRELIM)) 292 #if (defined(CFG_AR3_PRELIM) && defined(CFG_CR3_PRELIM) && defined(CFG_MR3_PRELIM))
293 csctrl_reg->ar3 = CFG_AR3_PRELIM; 293 csctrl_reg->ar3 = CFG_AR3_PRELIM;
294 csctrl_reg->cr3 = CFG_CR3_PRELIM; 294 csctrl_reg->cr3 = CFG_CR3_PRELIM;
295 csctrl_reg->mr3 = CFG_MR3_PRELIM; 295 csctrl_reg->mr3 = CFG_MR3_PRELIM;
296 #endif 296 #endif
297 297
298 #if (defined(CFG_AR4_PRELIM) && defined(CFG_CR4_PRELIM) && defined(CFG_MR4_PRELIM)) 298 #if (defined(CFG_AR4_PRELIM) && defined(CFG_CR4_PRELIM) && defined(CFG_MR4_PRELIM))
299 csctrl_reg->ar4 = CFG_AR4_PRELIM; 299 csctrl_reg->ar4 = CFG_AR4_PRELIM;
300 csctrl_reg->cr4 = CFG_CR4_PRELIM; 300 csctrl_reg->cr4 = CFG_CR4_PRELIM;
301 csctrl_reg->mr4 = CFG_MR4_PRELIM; 301 csctrl_reg->mr4 = CFG_MR4_PRELIM;
302 #endif 302 #endif
303 303
304 #if (defined(CFG_AR5_PRELIM) && defined(CFG_CR5_PRELIM) && defined(CFG_MR5_PRELIM)) 304 #if (defined(CFG_AR5_PRELIM) && defined(CFG_CR5_PRELIM) && defined(CFG_MR5_PRELIM))
305 csctrl_reg->ar5 = CFG_AR5_PRELIM; 305 csctrl_reg->ar5 = CFG_AR5_PRELIM;
306 csctrl_reg->cr5 = CFG_CR5_PRELIM; 306 csctrl_reg->cr5 = CFG_CR5_PRELIM;
307 csctrl_reg->mr5 = CFG_MR5_PRELIM; 307 csctrl_reg->mr5 = CFG_MR5_PRELIM;
308 #endif 308 #endif
309 309
310 #if (defined(CFG_AR6_PRELIM) && defined(CFG_CR6_PRELIM) && defined(CFG_MR6_PRELIM)) 310 #if (defined(CFG_AR6_PRELIM) && defined(CFG_CR6_PRELIM) && defined(CFG_MR6_PRELIM))
311 csctrl_reg->ar6 = CFG_AR6_PRELIM; 311 csctrl_reg->ar6 = CFG_AR6_PRELIM;
312 csctrl_reg->cr6 = CFG_CR6_PRELIM; 312 csctrl_reg->cr6 = CFG_CR6_PRELIM;
313 csctrl_reg->mr6 = CFG_MR6_PRELIM; 313 csctrl_reg->mr6 = CFG_MR6_PRELIM;
314 #endif 314 #endif
315 315
316 #if (defined(CFG_AR7_PRELIM) && defined(CFG_CR7_PRELIM) && defined(CFG_MR7_PRELIM)) 316 #if (defined(CFG_AR7_PRELIM) && defined(CFG_CR7_PRELIM) && defined(CFG_MR7_PRELIM))
317 csctrl_reg->ar7 = CFG_AR7_PRELIM; 317 csctrl_reg->ar7 = CFG_AR7_PRELIM;
318 csctrl_reg->cr7 = CFG_CR7_PRELIM; 318 csctrl_reg->cr7 = CFG_CR7_PRELIM;
319 csctrl_reg->mr7 = CFG_MR7_PRELIM; 319 csctrl_reg->mr7 = CFG_MR7_PRELIM;
320 #endif 320 #endif
321 321
322 #endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */ 322 #endif /* #ifndef CONFIG_MONITOR_IS_IN_RAM */
323 323
324 #ifdef CONFIG_FSL_I2C 324 #ifdef CONFIG_FSL_I2C
325 gpio_reg->par_feci2c = 0x000F; 325 gpio_reg->par_feci2c = 0x000F;
326 #endif 326 #endif
327 327
328 /* enable instruction cache now */ 328 /* enable instruction cache now */
329 icache_enable(); 329 icache_enable();
330 } 330 }
331 331
332 /* 332 /*
333 * initialize higher level parts of CPU like timers 333 * initialize higher level parts of CPU like timers
334 */ 334 */
335 int cpu_init_r(void) 335 int cpu_init_r(void)
336 { 336 {
337 return (0); 337 return (0);
338 } 338 }
339 339
340 void uart_port_conf(void) 340 void uart_port_conf(void)
341 { 341 {
342 volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO; 342 volatile gpio_t *gpio = (gpio_t *)MMAP_GPIO;
343 343
344 /* Setup Ports: */ 344 /* Setup Ports: */
345 switch (CFG_UART_PORT) { 345 switch (CFG_UART_PORT) {
346 case 0: 346 case 0:
347 gpio->par_uart |= UART0_ENABLE_MASK; 347 gpio->par_uart |= UART0_ENABLE_MASK;
348 break; 348 break;
349 case 1: 349 case 1:
350 gpio->par_uart |= UART1_ENABLE_MASK; 350 gpio->par_uart |= UART1_ENABLE_MASK;
351 break; 351 break;
352 case 2: 352 case 2:
353 gpio->par_uart |= UART2_ENABLE_MASK; 353 gpio->par_uart |= UART2_ENABLE_MASK;
354 break; 354 break;
355 } 355 }
356 } 356 }
357 #endif /* #if defined(CONFIG_M5275) */ 357 #endif /* #if defined(CONFIG_M5275) */
358 358
359 #if defined(CONFIG_M5282) 359 #if defined(CONFIG_M5282)
360 /* 360 /*
361 * Breath some life into the CPU... 361 * Breath some life into the CPU...
362 * 362 *
363 * Set up the memory map, 363 * Set up the memory map,
364 * initialize a bunch of registers, 364 * initialize a bunch of registers,
365 * initialize the UPM's 365 * initialize the UPM's
366 */ 366 */
367 void cpu_init_f(void) 367 void cpu_init_f(void)
368 { 368 {
369 #ifndef CONFIG_WATCHDOG 369 #ifndef CONFIG_WATCHDOG
370 /* disable watchdog if we aren't using it */ 370 /* disable watchdog if we aren't using it */
371 MCFWTM_WCR = 0; 371 MCFWTM_WCR = 0;
372 #endif 372 #endif
373 373
374 #ifndef CONFIG_MONITOR_IS_IN_RAM 374 #ifndef CONFIG_MONITOR_IS_IN_RAM
375 /* Set speed /PLL */ 375 /* Set speed /PLL */
376 MCFCLOCK_SYNCR = 376 MCFCLOCK_SYNCR =
377 MCFCLOCK_SYNCR_MFD(CFG_MFD) | MCFCLOCK_SYNCR_RFD(CFG_RFD); 377 MCFCLOCK_SYNCR_MFD(CFG_MFD) | MCFCLOCK_SYNCR_RFD(CFG_RFD);
378 while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ; 378 while (!(MCFCLOCK_SYNSR & MCFCLOCK_SYNSR_LOCK)) ;
379 379
380 MCFGPIO_PBCDPAR = 0xc0; 380 MCFGPIO_PBCDPAR = 0xc0;
381 381
382 /* Set up the GPIO ports */ 382 /* Set up the GPIO ports */
383 #ifdef CFG_PEPAR 383 #ifdef CFG_PEPAR
384 MCFGPIO_PEPAR = CFG_PEPAR; 384 MCFGPIO_PEPAR = CFG_PEPAR;
385 #endif 385 #endif
386 #ifdef CFG_PFPAR 386 #ifdef CFG_PFPAR
387 MCFGPIO_PFPAR = CFG_PFPAR; 387 MCFGPIO_PFPAR = CFG_PFPAR;
388 #endif 388 #endif
389 #ifdef CFG_PJPAR 389 #ifdef CFG_PJPAR
390 MCFGPIO_PJPAR = CFG_PJPAR; 390 MCFGPIO_PJPAR = CFG_PJPAR;
391 #endif 391 #endif
392 #ifdef CFG_PSDPAR 392 #ifdef CFG_PSDPAR
393 MCFGPIO_PSDPAR = CFG_PSDPAR; 393 MCFGPIO_PSDPAR = CFG_PSDPAR;
394 #endif 394 #endif
395 #ifdef CFG_PASPAR 395 #ifdef CFG_PASPAR
396 MCFGPIO_PASPAR = CFG_PASPAR; 396 MCFGPIO_PASPAR = CFG_PASPAR;
397 #endif 397 #endif
398 #ifdef CFG_PEHLPAR 398 #ifdef CFG_PEHLPAR
399 MCFGPIO_PEHLPAR = CFG_PEHLPAR; 399 MCFGPIO_PEHLPAR = CFG_PEHLPAR;
400 #endif 400 #endif
401 #ifdef CFG_PQSPAR 401 #ifdef CFG_PQSPAR
402 MCFGPIO_PQSPAR = CFG_PQSPAR; 402 MCFGPIO_PQSPAR = CFG_PQSPAR;
403 #endif 403 #endif
404 #ifdef CFG_PTCPAR 404 #ifdef CFG_PTCPAR
405 MCFGPIO_PTCPAR = CFG_PTCPAR; 405 MCFGPIO_PTCPAR = CFG_PTCPAR;
406 #endif 406 #endif
407 #ifdef CFG_PTDPAR 407 #ifdef CFG_PTDPAR
408 MCFGPIO_PTDPAR = CFG_PTDPAR; 408 MCFGPIO_PTDPAR = CFG_PTDPAR;
409 #endif 409 #endif
410 #ifdef CFG_PUAPAR 410 #ifdef CFG_PUAPAR
411 MCFGPIO_PUAPAR = CFG_PUAPAR; 411 MCFGPIO_PUAPAR = CFG_PUAPAR;
412 #endif 412 #endif
413 413
414 #ifdef CFG_DDRUA 414 #ifdef CFG_DDRUA
415 MCFGPIO_DDRUA = CFG_DDRUA; 415 MCFGPIO_DDRUA = CFG_DDRUA;
416 #endif 416 #endif
417 417
418 /* This is probably a bad place to setup chip selects, but everyone 418 /* This is probably a bad place to setup chip selects, but everyone
419 else is doing it! */ 419 else is doing it! */
420 420
421 #if defined(CFG_CS0_BASE) & defined(CFG_CS0_SIZE) & \ 421 #if defined(CFG_CS0_BASE) & defined(CFG_CS0_SIZE) & \
422 defined(CFG_CS0_WIDTH) & defined(CFG_CS0_WS) 422 defined(CFG_CS0_WIDTH) & defined(CFG_CS0_WS)
423 423
424 MCFCSM_CSAR0 = (CFG_CS0_BASE >> 16) & 0xFFFF; 424 MCFCSM_CSAR0 = (CFG_CS0_BASE >> 16) & 0xFFFF;
425 425
426 #if (CFG_CS0_WIDTH == 8) 426 #if (CFG_CS0_WIDTH == 8)
427 #define CFG_CS0_PS MCFCSM_CSCR_PS_8 427 #define CFG_CS0_PS MCFCSM_CSCR_PS_8
428 #elif (CFG_CS0_WIDTH == 16) 428 #elif (CFG_CS0_WIDTH == 16)
429 #define CFG_CS0_PS MCFCSM_CSCR_PS_16 429 #define CFG_CS0_PS MCFCSM_CSCR_PS_16
430 #elif (CFG_CS0_WIDTH == 32) 430 #elif (CFG_CS0_WIDTH == 32)
431 #define CFG_CS0_PS MCFCSM_CSCR_PS_32 431 #define CFG_CS0_PS MCFCSM_CSCR_PS_32
432 #else 432 #else
433 #error "CFG_CS0_WIDTH: Fault - wrong bus with for CS0" 433 #error "CFG_CS0_WIDTH: Fault - wrong bus with for CS0"
434 #endif 434 #endif
435 MCFCSM_CSCR0 = MCFCSM_CSCR_WS(CFG_CS0_WS) 435 MCFCSM_CSCR0 = MCFCSM_CSCR_WS(CFG_CS0_WS)
436 | CFG_CS0_PS | MCFCSM_CSCR_AA; 436 | CFG_CS0_PS | MCFCSM_CSCR_AA;
437 437
438 #if (CFG_CS0_RO != 0) 438 #if (CFG_CS0_RO != 0)
439 MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE - 1) 439 MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE - 1)
440 | MCFCSM_CSMR_WP | MCFCSM_CSMR_V; 440 | MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
441 #else 441 #else
442 MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE - 1) | MCFCSM_CSMR_V; 442 MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE - 1) | MCFCSM_CSMR_V;
443 #endif 443 #endif
444 #else 444 #else
445 #waring "Chip Select 0 are not initialized/used" 445 #warning "Chip Select 0 are not initialized/used"
446 #endif 446 #endif
447 447
448 #if defined(CFG_CS1_BASE) & defined(CFG_CS1_SIZE) & \ 448 #if defined(CFG_CS1_BASE) & defined(CFG_CS1_SIZE) & \
449 defined(CFG_CS1_WIDTH) & defined(CFG_CS1_WS) 449 defined(CFG_CS1_WIDTH) & defined(CFG_CS1_WS)
450 450
451 MCFCSM_CSAR1 = (CFG_CS1_BASE >> 16) & 0xFFFF; 451 MCFCSM_CSAR1 = (CFG_CS1_BASE >> 16) & 0xFFFF;
452 452
453 #if (CFG_CS1_WIDTH == 8) 453 #if (CFG_CS1_WIDTH == 8)
454 #define CFG_CS1_PS MCFCSM_CSCR_PS_8 454 #define CFG_CS1_PS MCFCSM_CSCR_PS_8
455 #elif (CFG_CS1_WIDTH == 16) 455 #elif (CFG_CS1_WIDTH == 16)
456 #define CFG_CS1_PS MCFCSM_CSCR_PS_16 456 #define CFG_CS1_PS MCFCSM_CSCR_PS_16
457 #elif (CFG_CS1_WIDTH == 32) 457 #elif (CFG_CS1_WIDTH == 32)
458 #define CFG_CS1_PS MCFCSM_CSCR_PS_32 458 #define CFG_CS1_PS MCFCSM_CSCR_PS_32
459 #else 459 #else
460 #error "CFG_CS1_WIDTH: Fault - wrong bus with for CS1" 460 #error "CFG_CS1_WIDTH: Fault - wrong bus with for CS1"
461 #endif 461 #endif
462 MCFCSM_CSCR1 = MCFCSM_CSCR_WS(CFG_CS1_WS) 462 MCFCSM_CSCR1 = MCFCSM_CSCR_WS(CFG_CS1_WS)
463 | CFG_CS1_PS | MCFCSM_CSCR_AA; 463 | CFG_CS1_PS | MCFCSM_CSCR_AA;
464 464
465 #if (CFG_CS1_RO != 0) 465 #if (CFG_CS1_RO != 0)
466 MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE - 1) 466 MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE - 1)
467 | MCFCSM_CSMR_WP | MCFCSM_CSMR_V; 467 | MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
468 #else 468 #else
469 MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE - 1) 469 MCFCSM_CSMR1 = MCFCSM_CSMR_BAM(CFG_CS1_SIZE - 1)
470 | MCFCSM_CSMR_V; 470 | MCFCSM_CSMR_V;
471 #endif 471 #endif
472 #else 472 #else
473 #warning "Chip Select 1 are not initialized/used" 473 #warning "Chip Select 1 are not initialized/used"
474 #endif 474 #endif
475 475
476 #if defined(CFG_CS2_BASE) & defined(CFG_CS2_SIZE) & \ 476 #if defined(CFG_CS2_BASE) & defined(CFG_CS2_SIZE) & \
477 defined(CFG_CS2_WIDTH) & defined(CFG_CS2_WS) 477 defined(CFG_CS2_WIDTH) & defined(CFG_CS2_WS)
478 478
479 MCFCSM_CSAR2 = (CFG_CS2_BASE >> 16) & 0xFFFF; 479 MCFCSM_CSAR2 = (CFG_CS2_BASE >> 16) & 0xFFFF;
480 480
481 #if (CFG_CS2_WIDTH == 8) 481 #if (CFG_CS2_WIDTH == 8)
482 #define CFG_CS2_PS MCFCSM_CSCR_PS_8 482 #define CFG_CS2_PS MCFCSM_CSCR_PS_8
483 #elif (CFG_CS2_WIDTH == 16) 483 #elif (CFG_CS2_WIDTH == 16)
484 #define CFG_CS2_PS MCFCSM_CSCR_PS_16 484 #define CFG_CS2_PS MCFCSM_CSCR_PS_16
485 #elif (CFG_CS2_WIDTH == 32) 485 #elif (CFG_CS2_WIDTH == 32)
486 #define CFG_CS2_PS MCFCSM_CSCR_PS_32 486 #define CFG_CS2_PS MCFCSM_CSCR_PS_32
487 #else 487 #else
488 #error "CFG_CS2_WIDTH: Fault - wrong bus with for CS2" 488 #error "CFG_CS2_WIDTH: Fault - wrong bus with for CS2"
489 #endif 489 #endif
490 MCFCSM_CSCR2 = MCFCSM_CSCR_WS(CFG_CS2_WS) 490 MCFCSM_CSCR2 = MCFCSM_CSCR_WS(CFG_CS2_WS)
491 | CFG_CS2_PS | MCFCSM_CSCR_AA; 491 | CFG_CS2_PS | MCFCSM_CSCR_AA;
492 492
493 #if (CFG_CS2_RO != 0) 493 #if (CFG_CS2_RO != 0)
494 MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE - 1) 494 MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE - 1)
495 | MCFCSM_CSMR_WP | MCFCSM_CSMR_V; 495 | MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
496 #else 496 #else
497 MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE - 1) 497 MCFCSM_CSMR2 = MCFCSM_CSMR_BAM(CFG_CS2_SIZE - 1)
498 | MCFCSM_CSMR_V; 498 | MCFCSM_CSMR_V;
499 #endif 499 #endif
500 #else 500 #else
501 #warning "Chip Select 2 are not initialized/used" 501 #warning "Chip Select 2 are not initialized/used"
502 #endif 502 #endif
503 503
504 #if defined(CFG_CS3_BASE) & defined(CFG_CS3_SIZE) & \ 504 #if defined(CFG_CS3_BASE) & defined(CFG_CS3_SIZE) & \
505 defined(CFG_CS3_WIDTH) & defined(CFG_CS3_WS) 505 defined(CFG_CS3_WIDTH) & defined(CFG_CS3_WS)
506 506
507 MCFCSM_CSAR3 = (CFG_CS3_BASE >> 16) & 0xFFFF; 507 MCFCSM_CSAR3 = (CFG_CS3_BASE >> 16) & 0xFFFF;
508 508
509 #if (CFG_CS3_WIDTH == 8) 509 #if (CFG_CS3_WIDTH == 8)
510 #define CFG_CS3_PS MCFCSM_CSCR_PS_8 510 #define CFG_CS3_PS MCFCSM_CSCR_PS_8
511 #elif (CFG_CS3_WIDTH == 16) 511 #elif (CFG_CS3_WIDTH == 16)
512 #define CFG_CS3_PS MCFCSM_CSCR_PS_16 512 #define CFG_CS3_PS MCFCSM_CSCR_PS_16
513 #elif (CFG_CS3_WIDTH == 32) 513 #elif (CFG_CS3_WIDTH == 32)
514 #define CFG_CS3_PS MCFCSM_CSCR_PS_32 514 #define CFG_CS3_PS MCFCSM_CSCR_PS_32
515 #else 515 #else
516 #error "CFG_CS3_WIDTH: Fault - wrong bus with for CS1" 516 #error "CFG_CS3_WIDTH: Fault - wrong bus with for CS1"
517 #endif 517 #endif
518 MCFCSM_CSCR3 = MCFCSM_CSCR_WS(CFG_CS3_WS) 518 MCFCSM_CSCR3 = MCFCSM_CSCR_WS(CFG_CS3_WS)
519 | CFG_CS3_PS | MCFCSM_CSCR_AA; 519 | CFG_CS3_PS | MCFCSM_CSCR_AA;
520 520
521 #if (CFG_CS3_RO != 0) 521 #if (CFG_CS3_RO != 0)
522 MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE - 1) 522 MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE - 1)
523 | MCFCSM_CSMR_WP | MCFCSM_CSMR_V; 523 | MCFCSM_CSMR_WP | MCFCSM_CSMR_V;
524 #else 524 #else
525 MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE - 1) 525 MCFCSM_CSMR3 = MCFCSM_CSMR_BAM(CFG_CS3_SIZE - 1)
526 | MCFCSM_CSMR_V; 526 | MCFCSM_CSMR_V;
527 #endif 527 #endif
528 #else 528 #else
529 #warning "Chip Select 3 are not initialized/used" 529 #warning "Chip Select 3 are not initialized/used"
530 #endif 530 #endif
531 531
532 #endif /* CONFIG_MONITOR_IS_IN_RAM */ 532 #endif /* CONFIG_MONITOR_IS_IN_RAM */
533 533
534 /* defer enabling cache until boot (see do_go) */ 534 /* defer enabling cache until boot (see do_go) */
535 /* icache_enable(); */ 535 /* icache_enable(); */
536 } 536 }
537 537
538 /* 538 /*
539 * initialize higher level parts of CPU like timers 539 * initialize higher level parts of CPU like timers
540 */ 540 */
541 int cpu_init_r(void) 541 int cpu_init_r(void)
542 { 542 {
543 return (0); 543 return (0);
544 } 544 }
545 545
546 void uart_port_conf(void) 546 void uart_port_conf(void)
547 { 547 {
548 /* Setup Ports: */ 548 /* Setup Ports: */
549 switch (CFG_UART_PORT) { 549 switch (CFG_UART_PORT) {
550 case 0: 550 case 0:
551 MCFGPIO_PUAPAR &= 0xFc; 551 MCFGPIO_PUAPAR &= 0xFc;
552 MCFGPIO_PUAPAR |= 0x03; 552 MCFGPIO_PUAPAR |= 0x03;
553 break; 553 break;
554 case 1: 554 case 1:
555 MCFGPIO_PUAPAR &= 0xF3; 555 MCFGPIO_PUAPAR &= 0xF3;
556 MCFGPIO_PUAPAR |= 0x0C; 556 MCFGPIO_PUAPAR |= 0x0C;
557 break; 557 break;
558 case 2: 558 case 2:
559 MCFGPIO_PASPAR &= 0xFF0F; 559 MCFGPIO_PASPAR &= 0xFF0F;
560 MCFGPIO_PASPAR |= 0x00A0; 560 MCFGPIO_PASPAR |= 0x00A0;
561 break; 561 break;
562 } 562 }
563 } 563 }
564 #endif 564 #endif
565 565
566 #if defined(CONFIG_M5249) 566 #if defined(CONFIG_M5249)
567 /* 567 /*
568 * Breath some life into the CPU... 568 * Breath some life into the CPU...
569 * 569 *
570 * Set up the memory map, 570 * Set up the memory map,
571 * initialize a bunch of registers, 571 * initialize a bunch of registers,
572 * initialize the UPM's 572 * initialize the UPM's
573 */ 573 */
574 void cpu_init_f(void) 574 void cpu_init_f(void)
575 { 575 {
576 /* 576 /*
577 * NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins 577 * NOTE: by setting the GPIO_FUNCTION registers, we ensure that the UART pins
578 * (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins 578 * (UART0: gpio 30,27, UART1: gpio 31, 28) will be used as UART pins
579 * which is their primary function. 579 * which is their primary function.
580 * ~Jeremy 580 * ~Jeremy
581 */ 581 */
582 mbar2_writeLong(MCFSIM_GPIO_FUNC, CFG_GPIO_FUNC); 582 mbar2_writeLong(MCFSIM_GPIO_FUNC, CFG_GPIO_FUNC);
583 mbar2_writeLong(MCFSIM_GPIO1_FUNC, CFG_GPIO1_FUNC); 583 mbar2_writeLong(MCFSIM_GPIO1_FUNC, CFG_GPIO1_FUNC);
584 mbar2_writeLong(MCFSIM_GPIO_EN, CFG_GPIO_EN); 584 mbar2_writeLong(MCFSIM_GPIO_EN, CFG_GPIO_EN);
585 mbar2_writeLong(MCFSIM_GPIO1_EN, CFG_GPIO1_EN); 585 mbar2_writeLong(MCFSIM_GPIO1_EN, CFG_GPIO1_EN);
586 mbar2_writeLong(MCFSIM_GPIO_OUT, CFG_GPIO_OUT); 586 mbar2_writeLong(MCFSIM_GPIO_OUT, CFG_GPIO_OUT);
587 mbar2_writeLong(MCFSIM_GPIO1_OUT, CFG_GPIO1_OUT); 587 mbar2_writeLong(MCFSIM_GPIO1_OUT, CFG_GPIO1_OUT);
588 588
589 /* 589 /*
590 * dBug Compliance: 590 * dBug Compliance:
591 * You can verify these values by using dBug's 'ird' 591 * You can verify these values by using dBug's 'ird'
592 * (Internal Register Display) command 592 * (Internal Register Display) command
593 * ~Jeremy 593 * ~Jeremy
594 * 594 *
595 */ 595 */
596 mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */ 596 mbar_writeByte(MCFSIM_MPARK, 0x30); /* 5249 Internal Core takes priority over DMA */
597 mbar_writeByte(MCFSIM_SYPCR, 0x00); 597 mbar_writeByte(MCFSIM_SYPCR, 0x00);
598 mbar_writeByte(MCFSIM_SWIVR, 0x0f); 598 mbar_writeByte(MCFSIM_SWIVR, 0x0f);
599 mbar_writeByte(MCFSIM_SWSR, 0x00); 599 mbar_writeByte(MCFSIM_SWSR, 0x00);
600 mbar_writeLong(MCFSIM_IMR, 0xfffffbff); 600 mbar_writeLong(MCFSIM_IMR, 0xfffffbff);
601 mbar_writeByte(MCFSIM_SWDICR, 0x00); 601 mbar_writeByte(MCFSIM_SWDICR, 0x00);
602 mbar_writeByte(MCFSIM_TIMER1ICR, 0x00); 602 mbar_writeByte(MCFSIM_TIMER1ICR, 0x00);
603 mbar_writeByte(MCFSIM_TIMER2ICR, 0x88); 603 mbar_writeByte(MCFSIM_TIMER2ICR, 0x88);
604 mbar_writeByte(MCFSIM_I2CICR, 0x00); 604 mbar_writeByte(MCFSIM_I2CICR, 0x00);
605 mbar_writeByte(MCFSIM_UART1ICR, 0x00); 605 mbar_writeByte(MCFSIM_UART1ICR, 0x00);
606 mbar_writeByte(MCFSIM_UART2ICR, 0x00); 606 mbar_writeByte(MCFSIM_UART2ICR, 0x00);
607 mbar_writeByte(MCFSIM_ICR6, 0x00); 607 mbar_writeByte(MCFSIM_ICR6, 0x00);
608 mbar_writeByte(MCFSIM_ICR7, 0x00); 608 mbar_writeByte(MCFSIM_ICR7, 0x00);
609 mbar_writeByte(MCFSIM_ICR8, 0x00); 609 mbar_writeByte(MCFSIM_ICR8, 0x00);
610 mbar_writeByte(MCFSIM_ICR9, 0x00); 610 mbar_writeByte(MCFSIM_ICR9, 0x00);
611 mbar_writeByte(MCFSIM_QSPIICR, 0x00); 611 mbar_writeByte(MCFSIM_QSPIICR, 0x00);
612 612
613 mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080); 613 mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080);
614 mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */ 614 mbar2_writeByte(MCFSIM_INTBASE, 0x40); /* Base interrupts at 64 */
615 mbar2_writeByte(MCFSIM_SPURVEC, 0x00); 615 mbar2_writeByte(MCFSIM_SPURVEC, 0x00);
616 mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */ 616 mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */
617 617
618 /* Setup interrupt priorities for gpio7 */ 618 /* Setup interrupt priorities for gpio7 */
619 /* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */ 619 /* mbar2_writeLong(MCFSIM_INTLEV5, 0x70000000); */
620 620
621 /* IDE Config registers */ 621 /* IDE Config registers */
622 mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); 622 mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020);
623 mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000); 623 mbar2_writeLong(MCFSIM_IDECONFIG2, 0x00000000);
624 624
625 /* 625 /*
626 * Setup chip selects... 626 * Setup chip selects...
627 */ 627 */
628 628
629 mbar_writeShort(MCFSIM_CSAR1, CFG_CSAR1); 629 mbar_writeShort(MCFSIM_CSAR1, CFG_CSAR1);
630 mbar_writeShort(MCFSIM_CSCR1, CFG_CSCR1); 630 mbar_writeShort(MCFSIM_CSCR1, CFG_CSCR1);
631 mbar_writeLong(MCFSIM_CSMR1, CFG_CSMR1); 631 mbar_writeLong(MCFSIM_CSMR1, CFG_CSMR1);
632 632
633 mbar_writeShort(MCFSIM_CSAR0, CFG_CSAR0); 633 mbar_writeShort(MCFSIM_CSAR0, CFG_CSAR0);
634 mbar_writeShort(MCFSIM_CSCR0, CFG_CSCR0); 634 mbar_writeShort(MCFSIM_CSCR0, CFG_CSCR0);
635 mbar_writeLong(MCFSIM_CSMR0, CFG_CSMR0); 635 mbar_writeLong(MCFSIM_CSMR0, CFG_CSMR0);
636 636
637 /* enable instruction cache now */ 637 /* enable instruction cache now */
638 icache_enable(); 638 icache_enable();
639 } 639 }
640 640
641 /* 641 /*
642 * initialize higher level parts of CPU like timers 642 * initialize higher level parts of CPU like timers
643 */ 643 */
644 int cpu_init_r(void) 644 int cpu_init_r(void)
645 { 645 {
646 return (0); 646 return (0);
647 } 647 }
648 648
649 void uart_port_conf(void) 649 void uart_port_conf(void)
650 { 650 {
651 /* Setup Ports: */ 651 /* Setup Ports: */
652 switch (CFG_UART_PORT) { 652 switch (CFG_UART_PORT) {
653 case 0: 653 case 0:
654 break; 654 break;
655 case 1: 655 case 1:
656 break; 656 break;
657 } 657 }
658 } 658 }
659 #endif /* #if defined(CONFIG_M5249) */ 659 #endif /* #if defined(CONFIG_M5249) */
660 660
1 /* 1 /*
2 * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de> 2 * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
3 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com> 3 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
4 * 4 *
5 * See file CREDITS for list of people who contributed to this 5 * See file CREDITS for list of people who contributed to this
6 * project. 6 * project.
7 * 7 *
8 * This program is free software; you can redistribute it and/or 8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as 9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of 10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version. 11 * the License, or (at your option) any later version.
12 * 12 *
13 * This program is distributed in the hope that it will be useful, 13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details. 16 * GNU General Public License for more details.
17 * 17 *
18 * You should have received a copy of the GNU General Public License 18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software 19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA 21 * MA 02111-1307 USA
22 */ 22 */
23 23
24 #include <config.h> 24 #include <config.h>
25 #include "version.h" 25 #include "version.h"
26 26
27 #ifndef CONFIG_IDENT_STRING 27 #ifndef CONFIG_IDENT_STRING
28 #define CONFIG_IDENT_STRING "" 28 #define CONFIG_IDENT_STRING ""
29 #endif 29 #endif
30 30
31 31
32 #define _START _start 32 #define _START _start
33 #define _FAULT _fault 33 #define _FAULT _fault
34 34
35 35
36 #define SAVE_ALL \ 36 #define SAVE_ALL \
37 move.w #0x2700,%sr; /* disable intrs */ \ 37 move.w #0x2700,%sr; /* disable intrs */ \
38 subl #60,%sp; /* space for 15 regs */ \ 38 subl #60,%sp; /* space for 15 regs */ \
39 moveml %d0-%d7/%a0-%a6,%sp@; \ 39 moveml %d0-%d7/%a0-%a6,%sp@; \
40 40
41 #define RESTORE_ALL \ 41 #define RESTORE_ALL \
42 moveml %sp@,%d0-%d7/%a0-%a6; \ 42 moveml %sp@,%d0-%d7/%a0-%a6; \
43 addl #60,%sp; /* space for 15 regs */ \ 43 addl #60,%sp; /* space for 15 regs */ \
44 rte 44 rte
45 45
46 /* If we come from a pre-loader we don't need an initial exception 46 /* If we come from a pre-loader we don't need an initial exception
47 * table. 47 * table.
48 */ 48 */
49 #if !defined(CONFIG_MONITOR_IS_IN_RAM) 49 #if !defined(CONFIG_MONITOR_IS_IN_RAM)
50 50
51 .text 51 .text
52 /* 52 /*
53 * Vector table. This is used for initial platform startup. 53 * Vector table. This is used for initial platform startup.
54 * These vectors are to catch any un-intended traps. 54 * These vectors are to catch any un-intended traps.
55 */ 55 */
56 _vectors: 56 _vectors:
57 57
58 .long 0x00000000 /* Flash offset is 0 until we setup CS0 */ 58 .long 0x00000000 /* Flash offset is 0 until we setup CS0 */
59 #if defined(CONFIG_M5282) && (TEXT_BASE == CFG_INT_FLASH_BASE) 59 #if defined(CONFIG_M5282) && (TEXT_BASE == CFG_INT_FLASH_BASE)
60 .long _start - TEXT_BASE 60 .long _start - TEXT_BASE
61 #else 61 #else
62 .long _START 62 .long _START
63 #endif 63 #endif
64 64
65 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 65 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
66 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 66 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
67 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 67 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
68 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 68 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
69 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 69 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
70 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 70 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
71 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 71 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
72 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 72 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
73 73
74 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 74 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
75 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 75 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
76 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 76 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
77 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 77 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
78 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 78 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
79 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 79 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
80 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 80 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
81 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 81 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
82 82
83 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 83 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
84 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 84 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
85 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 85 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
86 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 86 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
87 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 87 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
88 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 88 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
89 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 89 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
90 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 90 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
91 91
92 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 92 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
93 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 93 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
94 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 94 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
95 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 95 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
96 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 96 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
97 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 97 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
98 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 98 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
99 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT 99 .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
100 100
101 #endif 101 #endif
102 102
103 .text 103 .text
104 104
105 105
106 #if defined(CFG_INT_FLASH_BASE) && \ 106 #if defined(CFG_INT_FLASH_BASE) && \
107 (defined(CONFIG_M5282) || defined(CONFIG_M5281)) 107 (defined(CONFIG_M5282) || defined(CONFIG_M5281))
108 #if (TEXT_BASE == CFG_INT_FLASH_BASE) 108 #if (TEXT_BASE == CFG_INT_FLASH_BASE)
109 .long 0x55AA55AA,0xAA55AA55 /* CFM Backdoorkey */ 109 .long 0x55AA55AA,0xAA55AA55 /* CFM Backdoorkey */
110 .long 0xFFFFFFFF /* all sectors protected */ 110 .long 0xFFFFFFFF /* all sectors protected */
111 .long 0x00000000 /* supervisor/User restriction */ 111 .long 0x00000000 /* supervisor/User restriction */
112 .long 0x00000000 /* programm/data space restriction */ 112 .long 0x00000000 /* programm/data space restriction */
113 .long 0x00000000 /* Flash security */ 113 .long 0x00000000 /* Flash security */
114 #endif 114 #endif
115 #endif 115 #endif
116 .globl _start 116 .globl _start
117 _start: 117 _start:
118 nop 118 nop
119 nop 119 nop
120 move.w #0x2700,%sr 120 move.w #0x2700,%sr
121 121
122 #if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5253) 122 #if defined(CONFIG_M5272) || defined(CONFIG_M5249) || defined(CONFIG_M5253)
123 move.l #(CFG_MBAR + 1), %d0 /* set MBAR address + valid flag */ 123 move.l #(CFG_MBAR + 1), %d0 /* set MBAR address + valid flag */
124 move.c %d0, %MBAR 124 move.c %d0, %MBAR
125 125
126 /*** The 5249 has MBAR2 as well ***/ 126 /*** The 5249 has MBAR2 as well ***/
127 #ifdef CFG_MBAR2 127 #ifdef CFG_MBAR2
128 move.l #(CFG_MBAR2 + 1), %d0 /* Get MBAR2 address */ 128 move.l #(CFG_MBAR2 + 1), %d0 /* Get MBAR2 address */
129 movec %d0, #0xc0e /* Set MBAR2 */ 129 movec %d0, #0xc0e /* Set MBAR2 */
130 #endif 130 #endif
131 131
132 move.l #(CFG_INIT_RAM_ADDR + 1), %d0 132 move.l #(CFG_INIT_RAM_ADDR + 1), %d0
133 movec %d0, %RAMBAR0 133 movec %d0, %RAMBAR0
134 #endif /* CONFIG_M5272 || CONFIG_M5249 || CONFIG_M5253 */ 134 #endif /* CONFIG_M5272 || CONFIG_M5249 || CONFIG_M5253 */
135 135
136 #if defined(CONFIG_M5282) || defined(CONFIG_M5271) 136 #if defined(CONFIG_M5282) || defined(CONFIG_M5271)
137 /* Initialize IPSBAR */ 137 /* Initialize IPSBAR */
138 move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */ 138 move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */
139 move.l %d0, 0x40000000 139 move.l %d0, 0x40000000
140 140
141 /* Initialize RAMBAR1: locate SRAM and validate it */ 141 /* Initialize RAMBAR1: locate SRAM and validate it */
142 move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0 142 move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0
143 movec %d0, %RAMBAR1 143 movec %d0, %RAMBAR1
144 144
145 #if defined(CONFIG_M5282) 145 #if defined(CONFIG_M5282)
146 #if (TEXT_BASE == CFG_INT_FLASH_BASE) 146 #if (TEXT_BASE == CFG_INT_FLASH_BASE)
147 /* Setup code in SRAM to initialize FLASHBAR, if start from internal Flash */ 147 /* Setup code in SRAM to initialize FLASHBAR, if start from internal Flash */
148 148
149 move.l #(_flashbar_setup-CFG_INT_FLASH_BASE), %a0 149 move.l #(_flashbar_setup-CFG_INT_FLASH_BASE), %a0
150 move.l #(_flashbar_setup_end-CFG_INT_FLASH_BASE), %a1 150 move.l #(_flashbar_setup_end-CFG_INT_FLASH_BASE), %a1
151 move.l #(CFG_INIT_RAM_ADDR), %a2 151 move.l #(CFG_INIT_RAM_ADDR), %a2
152 _copy_flash: 152 _copy_flash:
153 move.l (%a0)+, (%a2)+ 153 move.l (%a0)+, (%a2)+
154 cmp.l %a0, %a1 154 cmp.l %a0, %a1
155 bgt.s _copy_flash 155 bgt.s _copy_flash
156 jmp CFG_INIT_RAM_ADDR 156 jmp CFG_INIT_RAM_ADDR
157 157
158 _flashbar_setup: 158 _flashbar_setup:
159 /* Initialize FLASHBAR: locate internal Flash and validate it */ 159 /* Initialize FLASHBAR: locate internal Flash and validate it */
160 move.l #(CFG_INT_FLASH_BASE + CFG_INT_FLASH_ENABLE), %d0 160 move.l #(CFG_INT_FLASH_BASE + CFG_INT_FLASH_ENABLE), %d0
161 movec %d0, %FLASHBAR 161 movec %d0, %FLASHBAR
162 jmp _after_flashbar_copy.L /* Force jump to absolute address */ 162 jmp _after_flashbar_copy.L /* Force jump to absolute address */
163 _flashbar_setup_end: 163 _flashbar_setup_end:
164 nop 164 nop
165 _after_flashbar_copy: 165 _after_flashbar_copy:
166 #else 166 #else
167 /* Setup code to initialize FLASHBAR, if start from external Memory */ 167 /* Setup code to initialize FLASHBAR, if start from external Memory */
168 move.l #(CFG_INT_FLASH_BASE + CFG_INT_FLASH_ENABLE), %d0 168 move.l #(CFG_INT_FLASH_BASE + CFG_INT_FLASH_ENABLE), %d0
169 movec %d0, %RAMBAR1 169 movec %d0, %FLASHBAR
170 #endif /* (TEXT_BASE == CFG_INT_FLASH_BASE) */ 170 #endif /* (TEXT_BASE == CFG_INT_FLASH_BASE) */
171 171
172 #endif 172 #endif
173 #endif 173 #endif
174 /* if we come from a pre-loader we have no exception table and 174 /* if we come from a pre-loader we have no exception table and
175 * therefore no VBR to set 175 * therefore no VBR to set
176 */ 176 */
177 #if !defined(CONFIG_MONITOR_IS_IN_RAM) 177 #if !defined(CONFIG_MONITOR_IS_IN_RAM)
178 #if defined(CONFIG_M5282) && (TEXT_BASE == CFG_INT_FLASH_BASE) 178 #if defined(CONFIG_M5282) && (TEXT_BASE == CFG_INT_FLASH_BASE)
179 move.l #CFG_INT_FLASH_BASE, %d0 179 move.l #CFG_INT_FLASH_BASE, %d0
180 #else 180 #else
181 move.l #CFG_FLASH_BASE, %d0 181 move.l #CFG_FLASH_BASE, %d0
182 #endif 182 #endif
183 movec %d0, %VBR 183 movec %d0, %VBR
184 #endif 184 #endif
185 185
186 #ifdef CONFIG_M5275 186 #ifdef CONFIG_M5275
187 /* Initialize IPSBAR */ 187 /* Initialize IPSBAR */
188 move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */ 188 move.l #(CFG_MBAR + 1), %d0 /* set IPSBAR address + valid flag */
189 move.l %d0, 0x40000000 189 move.l %d0, 0x40000000
190 /* movec %d0, %MBAR */ 190 /* movec %d0, %MBAR */
191 191
192 /* Initialize RAMBAR: locate SRAM and validate it */ 192 /* Initialize RAMBAR: locate SRAM and validate it */
193 move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0 193 move.l #(CFG_INIT_RAM_ADDR + 0x21), %d0
194 movec %d0, %RAMBAR1 194 movec %d0, %RAMBAR1
195 #endif 195 #endif
196 196
197 #if 0 197 #if 0
198 /* invalidate and disable cache */ 198 /* invalidate and disable cache */
199 move.l #0x01000000, %d0 /* Invalidate cache cmd */ 199 move.l #0x01000000, %d0 /* Invalidate cache cmd */
200 movec %d0, %CACR /* Invalidate cache */ 200 movec %d0, %CACR /* Invalidate cache */
201 move.l #0, %d0 201 move.l #0, %d0
202 movec %d0, %ACR0 202 movec %d0, %ACR0
203 movec %d0, %ACR1 203 movec %d0, %ACR1
204 #endif 204 #endif
205 205
206 /* set stackpointer to end of internal ram to get some stackspace for the first c-code */ 206 /* set stackpointer to end of internal ram to get some stackspace for the first c-code */
207 move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp 207 move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp
208 clr.l %sp@- 208 clr.l %sp@-
209 209
210 move.l #__got_start, %a5 /* put relocation table address to a5 */ 210 move.l #__got_start, %a5 /* put relocation table address to a5 */
211 211
212 bsr cpu_init_f /* run low-level CPU init code (from flash) */ 212 bsr cpu_init_f /* run low-level CPU init code (from flash) */
213 bsr board_init_f /* run low-level board init code (from flash) */ 213 bsr board_init_f /* run low-level board init code (from flash) */
214 214
215 /* board_init_f() does not return */ 215 /* board_init_f() does not return */
216 216
217 /*------------------------------------------------------------------------------*/ 217 /*------------------------------------------------------------------------------*/
218 218
219 /* 219 /*
220 * void relocate_code (addr_sp, gd, addr_moni) 220 * void relocate_code (addr_sp, gd, addr_moni)
221 * 221 *
222 * This "function" does not return, instead it continues in RAM 222 * This "function" does not return, instead it continues in RAM
223 * after relocating the monitor code. 223 * after relocating the monitor code.
224 * 224 *
225 * r3 = dest 225 * r3 = dest
226 * r4 = src 226 * r4 = src
227 * r5 = length in bytes 227 * r5 = length in bytes
228 * r6 = cachelinesize 228 * r6 = cachelinesize
229 */ 229 */
230 .globl relocate_code 230 .globl relocate_code
231 relocate_code: 231 relocate_code:
232 link.w %a6,#0 232 link.w %a6,#0
233 move.l 8(%a6), %sp /* set new stack pointer */ 233 move.l 8(%a6), %sp /* set new stack pointer */
234 234
235 move.l 12(%a6), %d0 /* Save copy of Global Data pointer */ 235 move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
236 move.l 16(%a6), %a0 /* Save copy of Destination Address */ 236 move.l 16(%a6), %a0 /* Save copy of Destination Address */
237 237
238 move.l #CFG_MONITOR_BASE, %a1 238 move.l #CFG_MONITOR_BASE, %a1
239 move.l #__init_end, %a2 239 move.l #__init_end, %a2
240 move.l %a0, %a3 240 move.l %a0, %a3
241 /* copy the code to RAM */ 241 /* copy the code to RAM */
242 1: 242 1:
243 move.l (%a1)+, (%a3)+ 243 move.l (%a1)+, (%a3)+
244 cmp.l %a1,%a2 244 cmp.l %a1,%a2
245 bgt.s 1b 245 bgt.s 1b
246 246
247 /* 247 /*
248 * We are done. Do not return, instead branch to second part of board 248 * We are done. Do not return, instead branch to second part of board
249 * initialization, now running from RAM. 249 * initialization, now running from RAM.
250 */ 250 */
251 move.l %a0, %a1 251 move.l %a0, %a1
252 add.l #(in_ram - CFG_MONITOR_BASE), %a1 252 add.l #(in_ram - CFG_MONITOR_BASE), %a1
253 jmp (%a1) 253 jmp (%a1)
254 254
255 in_ram: 255 in_ram:
256 256
257 clear_bss: 257 clear_bss:
258 /* 258 /*
259 * Now clear BSS segment 259 * Now clear BSS segment
260 */ 260 */
261 move.l %a0, %a1 261 move.l %a0, %a1
262 add.l #(_sbss - CFG_MONITOR_BASE),%a1 262 add.l #(_sbss - CFG_MONITOR_BASE),%a1
263 move.l %a0, %d1 263 move.l %a0, %d1
264 add.l #(_ebss - CFG_MONITOR_BASE),%d1 264 add.l #(_ebss - CFG_MONITOR_BASE),%d1
265 6: 265 6:
266 clr.l (%a1)+ 266 clr.l (%a1)+
267 cmp.l %a1,%d1 267 cmp.l %a1,%d1
268 bgt.s 6b 268 bgt.s 6b
269 269
270 /* 270 /*
271 * fix got table in RAM 271 * fix got table in RAM
272 */ 272 */
273 move.l %a0, %a1 273 move.l %a0, %a1
274 add.l #(__got_start - CFG_MONITOR_BASE),%a1 274 add.l #(__got_start - CFG_MONITOR_BASE),%a1
275 move.l %a1,%a5 /* * fix got pointer register a5 */ 275 move.l %a1,%a5 /* * fix got pointer register a5 */
276 276
277 move.l %a0, %a2 277 move.l %a0, %a2
278 add.l #(__got_end - CFG_MONITOR_BASE),%a2 278 add.l #(__got_end - CFG_MONITOR_BASE),%a2
279 279
280 7: 280 7:
281 move.l (%a1),%d1 281 move.l (%a1),%d1
282 sub.l #_start,%d1 282 sub.l #_start,%d1
283 add.l %a0,%d1 283 add.l %a0,%d1
284 move.l %d1,(%a1)+ 284 move.l %d1,(%a1)+
285 cmp.l %a2, %a1 285 cmp.l %a2, %a1
286 bne 7b 286 bne 7b
287 287
288 #if defined(CONFIG_M5281) || defined(CONFIG_M5282) 288 #if defined(CONFIG_M5281) || defined(CONFIG_M5282)
289 /* patch the 3 accesspoints to 3 ichache_state */ 289 /* patch the 3 accesspoints to 3 ichache_state */
290 /* quick and dirty */ 290 /* quick and dirty */
291 291
292 move.l %a0,%d1 292 move.l %a0,%d1
293 add.l #(icache_state - CFG_MONITOR_BASE),%d1 293 add.l #(icache_state - CFG_MONITOR_BASE),%d1
294 move.l %a0,%a1 294 move.l %a0,%a1
295 add.l #(icache_state_access_1+2 - CFG_MONITOR_BASE),%a1 295 add.l #(icache_state_access_1+2 - CFG_MONITOR_BASE),%a1
296 move.l %d1,(%a1) 296 move.l %d1,(%a1)
297 move.l %a0,%a1 297 move.l %a0,%a1
298 add.l #(icache_state_access_2+2 - CFG_MONITOR_BASE),%a1 298 add.l #(icache_state_access_2+2 - CFG_MONITOR_BASE),%a1
299 move.l %d1,(%a1) 299 move.l %d1,(%a1)
300 move.l %a0,%a1 300 move.l %a0,%a1
301 add.l #(icache_state_access_3+2 - CFG_MONITOR_BASE),%a1 301 add.l #(icache_state_access_3+2 - CFG_MONITOR_BASE),%a1
302 move.l %d1,(%a1) 302 move.l %d1,(%a1)
303 #endif 303 #endif
304 304
305 /* calculate relative jump to board_init_r in ram */ 305 /* calculate relative jump to board_init_r in ram */
306 move.l %a0, %a1 306 move.l %a0, %a1
307 add.l #(board_init_r - CFG_MONITOR_BASE), %a1 307 add.l #(board_init_r - CFG_MONITOR_BASE), %a1
308 308
309 /* set parameters for board_init_r */ 309 /* set parameters for board_init_r */
310 move.l %a0,-(%sp) /* dest_addr */ 310 move.l %a0,-(%sp) /* dest_addr */
311 move.l %d0,-(%sp) /* gd */ 311 move.l %d0,-(%sp) /* gd */
312 #if defined(DEBUG) && (TEXT_BASE != CFG_INT_FLASH_BASE) && \ 312 #if defined(DEBUG) && (TEXT_BASE != CFG_INT_FLASH_BASE) && \
313 defined(CFG_HALT_BEFOR_RAM_JUMP) 313 defined(CFG_HALT_BEFOR_RAM_JUMP)
314 halt 314 halt
315 #endif 315 #endif
316 jsr (%a1) 316 jsr (%a1)
317 317
318 /*------------------------------------------------------------------------------*/ 318 /*------------------------------------------------------------------------------*/
319 /* exception code */ 319 /* exception code */
320 .globl _fault 320 .globl _fault
321 _fault: 321 _fault:
322 jmp _fault 322 jmp _fault
323 323
324 .globl _exc_handler 324 .globl _exc_handler
325 _exc_handler: 325 _exc_handler:
326 SAVE_ALL 326 SAVE_ALL
327 movel %sp,%sp@- 327 movel %sp,%sp@-
328 bsr exc_handler 328 bsr exc_handler
329 addql #4,%sp 329 addql #4,%sp
330 RESTORE_ALL 330 RESTORE_ALL
331 331
332 .globl _int_handler 332 .globl _int_handler
333 _int_handler: 333 _int_handler:
334 SAVE_ALL 334 SAVE_ALL
335 movel %sp,%sp@- 335 movel %sp,%sp@-
336 bsr int_handler 336 bsr int_handler
337 addql #4,%sp 337 addql #4,%sp
338 RESTORE_ALL 338 RESTORE_ALL
339 339
340 /*------------------------------------------------------------------------------*/ 340 /*------------------------------------------------------------------------------*/
341 /* cache functions */ 341 /* cache functions */
342 #ifdef CONFIG_M5271 342 #ifdef CONFIG_M5271
343 .globl icache_enable 343 .globl icache_enable
344 icache_enable: 344 icache_enable:
345 move.l #0x01000000, %d0 /* Invalidate cache cmd */ 345 move.l #0x01000000, %d0 /* Invalidate cache cmd */
346 movec %d0, %CACR /* Invalidate cache */ 346 movec %d0, %CACR /* Invalidate cache */
347 move.l #(CFG_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */ 347 move.l #(CFG_SDRAM_BASE + 0xc000), %d0 /* Setup cache mask */
348 movec %d0, %ACR0 /* Enable cache */ 348 movec %d0, %ACR0 /* Enable cache */
349 349
350 move.l #0x80000200, %d0 /* Setup cache mask */ 350 move.l #0x80000200, %d0 /* Setup cache mask */
351 movec %d0, %CACR /* Enable cache */ 351 movec %d0, %CACR /* Enable cache */
352 nop 352 nop
353 353
354 move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1 354 move.l #(CFG_INIT_RAM_ADDR+CFG_INIT_RAM_END-8), %a1
355 moveq #1, %d0 355 moveq #1, %d0
356 move.l %d0, (%a1) 356 move.l %d0, (%a1)
357 rts 357 rts
358 #endif 358 #endif
359 359
360 #ifdef CONFIG_M5272 360 #ifdef CONFIG_M5272
361 .globl icache_enable 361 .globl icache_enable
362 icache_enable: 362 icache_enable:
363 move.l #0x01000000, %d0 /* Invalidate cache cmd */ 363 move.l #0x01000000, %d0 /* Invalidate cache cmd */
364 movec %d0, %CACR /* Invalidate cache */ 364 movec %d0, %CACR /* Invalidate cache */
365 move.l #0x0000c000, %d0 /* Setup cache mask */ 365 move.l #0x0000c000, %d0 /* Setup cache mask */
366 movec %d0, %ACR0 /* Enable cache */ 366 movec %d0, %ACR0 /* Enable cache */
367 move.l #0xff00c000, %d0 /* Setup cache mask */ 367 move.l #0xff00c000, %d0 /* Setup cache mask */
368 movec %d0, %ACR1 /* Enable cache */ 368 movec %d0, %ACR1 /* Enable cache */
369 move.l #0x80000100, %d0 /* Setup cache mask */ 369 move.l #0x80000100, %d0 /* Setup cache mask */
370 movec %d0, %CACR /* Enable cache */ 370 movec %d0, %CACR /* Enable cache */
371 moveq #1, %d0 371 moveq #1, %d0
372 move.l %d0, icache_state 372 move.l %d0, icache_state
373 rts 373 rts
374 #endif 374 #endif
375 375
376 #if defined(CONFIG_M5275) 376 #if defined(CONFIG_M5275)
377 /* 377 /*
378 * Instruction cache only 378 * Instruction cache only
379 */ 379 */
380 .globl icache_enable 380 .globl icache_enable
381 icache_enable: 381 icache_enable:
382 move.l #0x01400000, %d0 /* Invalidate cache cmd */ 382 move.l #0x01400000, %d0 /* Invalidate cache cmd */
383 movec %d0, %CACR /* Invalidate cache */ 383 movec %d0, %CACR /* Invalidate cache */
384 move.l #0x0000c000, %d0 /* Setup SDRAM caching */ 384 move.l #0x0000c000, %d0 /* Setup SDRAM caching */
385 movec %d0, %ACR0 /* Enable cache */ 385 movec %d0, %ACR0 /* Enable cache */
386 move.l #0x00000000, %d0 /* No other caching */ 386 move.l #0x00000000, %d0 /* No other caching */
387 movec %d0, %ACR1 /* Enable cache */ 387 movec %d0, %ACR1 /* Enable cache */
388 move.l #0x80400100, %d0 /* Setup cache mask */ 388 move.l #0x80400100, %d0 /* Setup cache mask */
389 movec %d0, %CACR /* Enable cache */ 389 movec %d0, %CACR /* Enable cache */
390 moveq #1, %d0 390 moveq #1, %d0
391 move.l %d0, icache_state 391 move.l %d0, icache_state
392 rts 392 rts
393 #endif 393 #endif
394 394
395 #ifdef CONFIG_M5282 395 #ifdef CONFIG_M5282
396 .globl icache_enable 396 .globl icache_enable
397 icache_enable: 397 icache_enable:
398 move.l #0x01000000, %d0 /* Invalidate cache cmd */ 398 move.l #0x01000000, %d0 /* Invalidate cache cmd */
399 movec %d0, %CACR /* Invalidate cache */ 399 movec %d0, %CACR /* Invalidate cache */
400 move.l #0x0000c000, %d0 /* Setup cache mask */ 400 move.l #0x0000c000, %d0 /* Setup cache mask */
401 movec %d0, %ACR0 /* Enable cache */ 401 movec %d0, %ACR0 /* Enable cache */
402 move.l #0xff00c000, %d0 /* Setup cache mask */ 402 move.l #0xff00c000, %d0 /* Setup cache mask */
403 movec %d0, %ACR1 /* Enable cache */ 403 movec %d0, %ACR1 /* Enable cache */
404 move.l #0x80400100, %d0 /* Setup cache mask, data cache disabel*/ 404 move.l #0x80400100, %d0 /* Setup cache mask, data cache disabel*/
405 movec %d0, %CACR /* Enable cache */ 405 movec %d0, %CACR /* Enable cache */
406 moveq #1, %d0 406 moveq #1, %d0
407 icache_state_access_1: 407 icache_state_access_1:
408 move.l %d0, icache_state 408 move.l %d0, icache_state
409 rts 409 rts
410 #endif 410 #endif
411 411
412 #if defined(CONFIG_M5249) || defined(CONFIG_M5253) 412 #if defined(CONFIG_M5249) || defined(CONFIG_M5253)
413 .globl icache_enable 413 .globl icache_enable
414 icache_enable: 414 icache_enable:
415 /* 415 /*
416 * Note: The 5249 Documentation doesn't give a bit position for CINV! 416 * Note: The 5249 Documentation doesn't give a bit position for CINV!
417 * From the 5272 and the 5307 documentation, I have deduced that it is 417 * From the 5272 and the 5307 documentation, I have deduced that it is
418 * probably CACR[24]. Should someone say something to Motorola? 418 * probably CACR[24]. Should someone say something to Motorola?
419 * ~Jeremy 419 * ~Jeremy
420 */ 420 */
421 move.l #0x01000000, %d0 /* Invalidate whole cache */ 421 move.l #0x01000000, %d0 /* Invalidate whole cache */
422 move.c %d0,%CACR 422 move.c %d0,%CACR
423 move.l #0xff00c000, %d0 /* Set FLASH cachable: always match (SM=0b10) */ 423 move.l #0xff00c000, %d0 /* Set FLASH cachable: always match (SM=0b10) */
424 move.c %d0, %ACR0 424 move.c %d0, %ACR0
425 move.l #0x0000c000, %d0 /* Set SDRAM cachable: always match (SM=0b10) */ 425 move.l #0x0000c000, %d0 /* Set SDRAM cachable: always match (SM=0b10) */
426 move.c %d0, %ACR1 426 move.c %d0, %ACR1
427 move.l #0x90000200, %d0 /* Set cache enable cmd */ 427 move.l #0x90000200, %d0 /* Set cache enable cmd */
428 move.c %d0,%CACR 428 move.c %d0,%CACR
429 moveq #1, %d0 429 moveq #1, %d0
430 move.l %d0, icache_state 430 move.l %d0, icache_state
431 rts 431 rts
432 #endif 432 #endif
433 433
434 .globl icache_disable 434 .globl icache_disable
435 icache_disable: 435 icache_disable:
436 move.l #0x00000100, %d0 /* Setup cache mask */ 436 move.l #0x00000100, %d0 /* Setup cache mask */
437 movec %d0, %CACR /* Enable cache */ 437 movec %d0, %CACR /* Enable cache */
438 clr.l %d0 /* Setup cache mask */ 438 clr.l %d0 /* Setup cache mask */
439 movec %d0, %ACR0 /* Enable cache */ 439 movec %d0, %ACR0 /* Enable cache */
440 movec %d0, %ACR1 /* Enable cache */ 440 movec %d0, %ACR1 /* Enable cache */
441 moveq #0, %d0 441 moveq #0, %d0
442 icache_state_access_2: 442 icache_state_access_2:
443 move.l %d0, icache_state 443 move.l %d0, icache_state
444 rts 444 rts
445 445
446 .globl icache_status 446 .globl icache_status
447 icache_status: 447 icache_status:
448 icache_state_access_3: 448 icache_state_access_3:
449 move.l #(icache_state), %a0 449 move.l #(icache_state), %a0
450 move.l (%a0), %d0 450 move.l (%a0), %d0
451 rts 451 rts
452 452
453 .data 453 .data
454 icache_state: 454 icache_state:
455 .long 0 /* cache is diabled on inirialization */ 455 .long 0 /* cache is diabled on inirialization */
456 456
457 .globl dcache_enable 457 .globl dcache_enable
458 dcache_enable: 458 dcache_enable:
459 /* dummy function */ 459 /* dummy function */
460 rts 460 rts
461 461
462 .globl dcache_disable 462 .globl dcache_disable
463 dcache_disable: 463 dcache_disable:
464 /* dummy function */ 464 /* dummy function */
465 rts 465 rts
466 466
467 .globl dcache_status 467 .globl dcache_status
468 dcache_status: 468 dcache_status:
469 /* dummy function */ 469 /* dummy function */
470 rts 470 rts
471 471
472 /*------------------------------------------------------------------------------*/ 472 /*------------------------------------------------------------------------------*/
473 473
474 .globl version_string 474 .globl version_string
475 version_string: 475 version_string:
476 .ascii U_BOOT_VERSION 476 .ascii U_BOOT_VERSION
477 .ascii " (", __DATE__, " - ", __TIME__, ")" 477 .ascii " (", __DATE__, " - ", __TIME__, ")"
478 .ascii CONFIG_IDENT_STRING, "\0" 478 .ascii CONFIG_IDENT_STRING, "\0"
479 .align 4 479 .align 4
480 480
include/configs/M5282EVB.h
Diff comments   View file @ 4cb4e65
1 /* 1 /*
2 * Configuation settings for the Motorola MC5282EVB board. 2 * Configuation settings for the Motorola MC5282EVB board.
3 * 3 *
4 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de> 4 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
5 * 5 *
6 * See file CREDITS for list of people who contributed to this 6 * See file CREDITS for list of people who contributed to this
7 * project. 7 * project.
8 * 8 *
9 * This program is free software; you can redistribute it and/or 9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as 10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of 11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version. 12 * the License, or (at your option) any later version.
13 * 13 *
14 * This program is distributed in the hope that it will be useful, 14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details. 17 * GNU General Public License for more details.
18 * 18 *
19 * You should have received a copy of the GNU General Public License 19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software 20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA 22 * MA 02111-1307 USA
23 */ 23 */
24 24
25 /* 25 /*
26 * board/config.h - configuration options, board specific 26 * board/config.h - configuration options, board specific
27 */ 27 */
28 28
29 #ifndef _CONFIG_M5282EVB_H 29 #ifndef _CONFIG_M5282EVB_H
30 #define _CONFIG_M5282EVB_H 30 #define _CONFIG_M5282EVB_H
31 31
32 /* 32 /*
33 * High Level Configuration Options 33 * High Level Configuration Options
34 * (easy to change) 34 * (easy to change)
35 */ 35 */
36 #define CONFIG_MCF52x2 /* define processor family */ 36 #define CONFIG_MCF52x2 /* define processor family */
37 #define CONFIG_M5282 /* define processor type */ 37 #define CONFIG_M5282 /* define processor type */
38 38
39 #define CONFIG_MCFTMR 39 #define CONFIG_MCFTMR
40 40
41 #define CONFIG_MCFUART 41 #define CONFIG_MCFUART
42 #define CFG_UART_PORT (0) 42 #define CFG_UART_PORT (0)
43 #define CONFIG_BAUDRATE 19200 43 #define CONFIG_BAUDRATE 19200
44 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } 44 #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
45 45
46 #undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */ 46 #undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
47 47
48 /* Configuration for environment 48 /* Configuration for environment
49 * Environment is embedded in u-boot in the second sector of the flash 49 * Environment is embedded in u-boot in the second sector of the flash
50 */ 50 */
51 #define CFG_ENV_ADDR 0xffe04000 51 #define CFG_ENV_ADDR 0xffe04000
52 #define CFG_ENV_SIZE 0x2000 52 #define CFG_ENV_SIZE 0x2000
53 #define CFG_ENV_IS_IN_FLASH 1 53 #define CFG_ENV_IS_IN_FLASH 1
54 54
55 /* 55 /*
56 * BOOTP options 56 * BOOTP options
57 */ 57 */
58 #define CONFIG_BOOTP_BOOTFILESIZE 58 #define CONFIG_BOOTP_BOOTFILESIZE
59 #define CONFIG_BOOTP_BOOTPATH 59 #define CONFIG_BOOTP_BOOTPATH
60 #define CONFIG_BOOTP_GATEWAY 60 #define CONFIG_BOOTP_GATEWAY
61 #define CONFIG_BOOTP_HOSTNAME 61 #define CONFIG_BOOTP_HOSTNAME
62 62
63 /* 63 /*
64 * Command line configuration. 64 * Command line configuration.
65 */ 65 */
66 #include <config_cmd_default.h> 66 #include <config_cmd_default.h>
67 #define CONFIG_CMD_NET 67 #define CONFIG_CMD_NET
68 #define CONFIG_CMD_PING 68 #define CONFIG_CMD_PING
69 #define CONFIG_CMD_MII 69 #define CONFIG_CMD_MII
70 70
71 #undef CONFIG_CMD_LOADS 71 #undef CONFIG_CMD_LOADS
72 #undef CONFIG_CMD_LOADB 72 #undef CONFIG_CMD_LOADB
73 73
74 #define CONFIG_MCFFEC 74 #define CONFIG_MCFFEC
75 #ifdef CONFIG_MCFFEC 75 #ifdef CONFIG_MCFFEC
76 # define CONFIG_NET_MULTI 1 76 # define CONFIG_NET_MULTI 1
77 # define CONFIG_MII 1 77 # define CONFIG_MII 1
78 # define CONFIG_MII_INIT 1 78 # define CONFIG_MII_INIT 1
79 # define CFG_DISCOVER_PHY 79 # define CFG_DISCOVER_PHY
80 # define CFG_RX_ETH_BUFFER 8 80 # define CFG_RX_ETH_BUFFER 8
81 # define CFG_FAULT_ECHO_LINK_DOWN 81 # define CFG_FAULT_ECHO_LINK_DOWN
82 82
83 # define CFG_FEC0_PINMUX 0 83 # define CFG_FEC0_PINMUX 0
84 # define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE 84 # define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE
85 # define MCFFEC_TOUT_LOOP 50000 85 # define MCFFEC_TOUT_LOOP 50000
86 /* If CFG_DISCOVER_PHY is not defined - hardcoded */ 86 /* If CFG_DISCOVER_PHY is not defined - hardcoded */
87 # ifndef CFG_DISCOVER_PHY 87 # ifndef CFG_DISCOVER_PHY
88 # define FECDUPLEX FULL 88 # define FECDUPLEX FULL
89 # define FECSPEED _100BASET 89 # define FECSPEED _100BASET
90 # else 90 # else
91 # ifndef CFG_FAULT_ECHO_LINK_DOWN 91 # ifndef CFG_FAULT_ECHO_LINK_DOWN
92 # define CFG_FAULT_ECHO_LINK_DOWN 92 # define CFG_FAULT_ECHO_LINK_DOWN
93 # endif 93 # endif
94 # endif /* CFG_DISCOVER_PHY */ 94 # endif /* CFG_DISCOVER_PHY */
95 #endif 95 #endif
96 96
97 #define CONFIG_BOOTDELAY 5 97 #define CONFIG_BOOTDELAY 5
98 #ifdef CONFIG_MCFFEC 98 #ifdef CONFIG_MCFFEC
99 # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 99 # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
100 # define CONFIG_IPADDR 192.162.1.2 100 # define CONFIG_IPADDR 192.162.1.2
101 # define CONFIG_NETMASK 255.255.255.0 101 # define CONFIG_NETMASK 255.255.255.0
102 # define CONFIG_SERVERIP 192.162.1.1 102 # define CONFIG_SERVERIP 192.162.1.1
103 # define CONFIG_GATEWAYIP 192.162.1.1 103 # define CONFIG_GATEWAYIP 192.162.1.1
104 # define CONFIG_OVERWRITE_ETHADDR_ONCE 104 # define CONFIG_OVERWRITE_ETHADDR_ONCE
105 #endif /* CONFIG_MCFFEC */ 105 #endif /* CONFIG_MCFFEC */
106 106
107 #define CONFIG_HOSTNAME M5272C3 107 #define CONFIG_HOSTNAME M5282EVB
108 #define CONFIG_EXTRA_ENV_SETTINGS \ 108 #define CONFIG_EXTRA_ENV_SETTINGS \
109 "netdev=eth0\0" \ 109 "netdev=eth0\0" \
110 "loadaddr=10000\0" \ 110 "loadaddr=10000\0" \
111 "u-boot=u-boot.bin\0" \ 111 "u-boot=u-boot.bin\0" \
112 "load=tftp ${loadaddr) ${u-boot}\0" \ 112 "load=tftp ${loadaddr) ${u-boot}\0" \
113 "upd=run load; run prog\0" \ 113 "upd=run load; run prog\0" \
114 "prog=prot off ffe00000 ffe3ffff;" \ 114 "prog=prot off ffe00000 ffe3ffff;" \
115 "era ffe00000 ffe3ffff;" \ 115 "era ffe00000 ffe3ffff;" \
116 "cp.b ${loadaddr} ffe00000 ${filesize};"\ 116 "cp.b ${loadaddr} ffe00000 ${filesize};"\
117 "save\0" \ 117 "save\0" \
118 "" 118 ""
119 119
120 #define CFG_PROMPT "-> " 120 #define CFG_PROMPT "-> "
121 #define CFG_LONGHELP /* undef to save memory */ 121 #define CFG_LONGHELP /* undef to save memory */
122 122
123 #if defined(CONFIG_CMD_KGDB) 123 #if defined(CONFIG_CMD_KGDB)
124 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ 124 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
125 #else 125 #else
126 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ 126 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
127 #endif 127 #endif
128 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ 128 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
129 #define CFG_MAXARGS 16 /* max number of command args */ 129 #define CFG_MAXARGS 16 /* max number of command args */
130 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ 130 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
131 131
132 #define CFG_LOAD_ADDR 0x20000 132 #define CFG_LOAD_ADDR 0x20000
133 133
134 #define CFG_MEMTEST_START 0x400 134 #define CFG_MEMTEST_START 0x400
135 #define CFG_MEMTEST_END 0x380000 135 #define CFG_MEMTEST_END 0x380000
136 136
137 #define CFG_HZ 1000000 137 #define CFG_HZ 1000
138 #define CFG_CLK 64000000 138 #define CFG_CLK 64000000
139 139
140 /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */ 140 /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
141 141
142 #define CFG_MFD 0x02 /* PLL Multiplication Factor Devider */ 142 #define CFG_MFD 0x02 /* PLL Multiplication Factor Devider */
143 #define CFG_RFD 0x00 /* PLL Reduce Frecuency Devider */ 143 #define CFG_RFD 0x00 /* PLL Reduce Frecuency Devider */
144 144
145 /* 145 /*
146 * Low Level Configuration Settings 146 * Low Level Configuration Settings
147 * (address mappings, register initial values, etc.) 147 * (address mappings, register initial values, etc.)
148 * You should know what you are doing if you make changes here. 148 * You should know what you are doing if you make changes here.
149 */ 149 */
150 #define CFG_MBAR 0x40000000 150 #define CFG_MBAR 0x40000000
151 151
152 /*----------------------------------------------------------------------- 152 /*-----------------------------------------------------------------------
153 * Definitions for initial stack pointer and data area (in DPRAM) 153 * Definitions for initial stack pointer and data area (in DPRAM)
154 */ 154 */
155 #define CFG_INIT_RAM_ADDR 0x20000000 155 #define CFG_INIT_RAM_ADDR 0x20000000
156 #define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */ 156 #define CFG_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */
157 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ 157 #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
158 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) 158 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
159 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET 159 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
160 160
161 /*----------------------------------------------------------------------- 161 /*-----------------------------------------------------------------------
162 * Start addresses for the final memory configuration 162 * Start addresses for the final memory configuration
163 * (Set up by the startup code) 163 * (Set up by the startup code)
164 * Please note that CFG_SDRAM_BASE _must_ start at 0 164 * Please note that CFG_SDRAM_BASE _must_ start at 0
165 */ 165 */
166 #define CFG_SDRAM_BASE 0x00000000 166 #define CFG_SDRAM_BASE 0x00000000
167 #define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */ 167 #define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
168 #define CFG_FLASH_BASE 0xffe00000 168 #define CFG_FLASH_BASE 0xffe00000
169 #define CFG_INT_FLASH_BASE 0xf0000000 169 #define CFG_INT_FLASH_BASE 0xf0000000
170 #define CFG_INT_FLASH_ENABLE 0x21 170 #define CFG_INT_FLASH_ENABLE 0x21
171 171
172 /* If M5282 port is fully implemented the monitor base will be behind 172 /* If M5282 port is fully implemented the monitor base will be behind
173 * the vector table. */ 173 * the vector table. */
174 #if (TEXT_BASE != CFG_INT_FLASH_BASE) 174 #if (TEXT_BASE != CFG_INT_FLASH_BASE)
175 #define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) 175 #define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
176 #else 176 #else
177 #define CFG_MONITOR_BASE (TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */ 177 #define CFG_MONITOR_BASE (TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */
178 #endif 178 #endif
179 179
180 #define CFG_MONITOR_LEN 0x20000 180 #define CFG_MONITOR_LEN 0x20000
181 #define CFG_MALLOC_LEN (256 << 10) 181 #define CFG_MALLOC_LEN (256 << 10)
182 #define CFG_BOOTPARAMS_LEN 64*1024 182 #define CFG_BOOTPARAMS_LEN 64*1024
183 183
184 /* 184 /*
185 * For booting Linux, the board info and command line data 185 * For booting Linux, the board info and command line data
186 * have to be in the first 8 MB of memory, since this is 186 * have to be in the first 8 MB of memory, since this is
187 * the maximum mapped by the Linux kernel during initialization ?? 187 * the maximum mapped by the Linux kernel during initialization ??
188 */ 188 */
189 #define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) 189 #define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20))
190 190
191 /*----------------------------------------------------------------------- 191 /*-----------------------------------------------------------------------
192 * FLASH organization 192 * FLASH organization
193 */ 193 */
194 #define CFG_FLASH_CFI 194 #define CFG_FLASH_CFI
195 #ifdef CFG_FLASH_CFI 195 #ifdef CFG_FLASH_CFI
196 196
197 # define CONFIG_FLASH_CFI_DRIVER 1 197 # define CONFIG_FLASH_CFI_DRIVER 1
198 # define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 198 # define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */
199 # define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT 199 # define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT
200 # define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ 200 # define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
201 # define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 201 # define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
202 # define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 202 # define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
203 # define CFG_FLASH_CHECKSUM 203 # define CFG_FLASH_CHECKSUM
204 # define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } 204 # define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
205 #endif 205 #endif
206 206
207 /*----------------------------------------------------------------------- 207 /*-----------------------------------------------------------------------
208 * Cache Configuration 208 * Cache Configuration
209 */ 209 */
210 #define CFG_CACHELINE_SIZE 16 210 #define CFG_CACHELINE_SIZE 16
211 211
212 /*----------------------------------------------------------------------- 212 /*-----------------------------------------------------------------------
213 * Memory bank definitions 213 * Memory bank definitions
214 */ 214 */
215 #define CFG_CS0_BASE CFG_FLASH_BASE 215 #define CFG_CS0_BASE CFG_FLASH_BASE
216 #define CFG_CS0_SIZE 2*1024*1024 216 #define CFG_CS0_SIZE 2*1024*1024
217 #define CFG_CS0_WIDTH 16 217 #define CFG_CS0_WIDTH 16
218 #define CFG_CS0_RO 0 218 #define CFG_CS0_RO 0
219 #define CFG_CS0_WS 6 219 #define CFG_CS0_WS 6
220 /* 220 /*
221 #define CFG_CS3_BASE 0xE0000000 221 #define CFG_CS3_BASE 0xE0000000
222 #define CFG_CS3_SIZE 1*1024*1024 222 #define CFG_CS3_SIZE 1*1024*1024
223 #define CFG_CS3_WIDTH 16 223 #define CFG_CS3_WIDTH 16
224 #define CFG_CS3_RO 0 224 #define CFG_CS3_RO 0
225 #define CFG_CS3_WS 6 225 #define CFG_CS3_WS 6
226 */ 226 */
227 /*----------------------------------------------------------------------- 227 /*-----------------------------------------------------------------------
228 * Port configuration 228 * Port configuration
229 */ 229 */
230 #define CFG_PACNT 0x0000000 /* Port A D[31:24] */ 230 #define CFG_PACNT 0x0000000 /* Port A D[31:24] */
231 #define CFG_PADDR 0x0000000 231 #define CFG_PADDR 0x0000000
232 #define CFG_PADAT 0x0000000 232 #define CFG_PADAT 0x0000000
233 233
234 #define CFG_PBCNT 0x0000000 /* Port B D[23:16] */ 234 #define CFG_PBCNT 0x0000000 /* Port B D[23:16] */
235 #define CFG_PBDDR 0x0000000 235 #define CFG_PBDDR 0x0000000
236 #define CFG_PBDAT 0x0000000 236 #define CFG_PBDAT 0x0000000
237 237
238 #define CFG_PCCNT 0x0000000 /* Port C D[15:08] */ 238 #define CFG_PCCNT 0x0000000 /* Port C D[15:08] */
239 #define CFG_PCDDR 0x0000000 239 #define CFG_PCDDR 0x0000000
240 #define CFG_PCDAT 0x0000000 240 #define CFG_PCDAT 0x0000000
241 241
242 #define CFG_PDCNT 0x0000000 /* Port D D[07:00] */ 242 #define CFG_PDCNT 0x0000000 /* Port D D[07:00] */
243 #define CFG_PCDDR 0x0000000 243 #define CFG_PCDDR 0x0000000
244 #define CFG_PCDAT 0x0000000 244 #define CFG_PCDAT 0x0000000
245 245
246 #define CFG_PEHLPAR 0xC0 246 #define CFG_PEHLPAR 0xC0
247 #define CFG_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */ 247 #define CFG_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */
248 #define CFG_DDRUA 0x05 248 #define CFG_DDRUA 0x05
249 #define CFG_PJPAR 0xFF; 249 #define CFG_PJPAR 0xFF;
250 250
251 #endif /* _CONFIG_M5282EVB_H */ 251 #endif /* _CONFIG_M5282EVB_H */
252 252