ColdFire: Multiple fixes for M5282EVB

Incorrect CFG_HZ value, change 1000000 to 1000. Rename #waring to #warning. RAMBAR1 uses twice in start.S, rename the later to FLASHBAR. Insert nop for DRAM setup. And, env_offset in linker file. Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>

ColdFire: Multiple fixes for M5282EVB
Incorrect CFG_HZ value, change 1000000 to 1000. Rename #waring to #warning. RAMBAR1 uses twice in start.S, rename the later to FLASHBAR. Insert nop for DRAM setup. And, env_offset in linker file. Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
TsiChung Liew · John Rigby
1 parent 10db3a17a2
Showing 5 changed files with 12 additions and 6 deletions Side-by-side Diff
board/freescale/m5282evb/m5282evb.c
board/freescale/m5282evb/u-boot.lds
cpu/mcf52x2/cpu_init.c
cpu/mcf52x2/start.S
include/configs/M5282EVB.h
@@ -51,6 +51,7 @@
 		MCFSDRAMC_DCR = (0
 			| MCFSDRAMC_DCR_RTIM_6
 			| MCFSDRAMC_DCR_RC((15 * dramclk)>>4));
+		asm("nop");
  
 		/* Initialize DACR0 */
 		MCFSDRAMC_DACR0 = (0
  
  
@@ -58,14 +59,17 @@
 			| MCFSDRAMC_DACR_CASL(1)
 			| MCFSDRAMC_DACR_CBM(3)
 			| MCFSDRAMC_DACR_PS_32);
+		asm("nop");
  
 		/* Initialize DMR0 */
 		MCFSDRAMC_DMR0 = (0
 			| ((dramsize - 1) & 0xFFFC0000)
 			| MCFSDRAMC_DMR_V);
+		asm("nop");
  
 		/* Set IP (bit 3) in DACR */
 		MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP;
+		asm("nop");
  
 		/* Wait 30ns to allow banks to precharge */
 		for (i = 0; i < 5; i++) {
  
@@ -74,9 +78,11 @@
  
 		/* Write to this block to initiate precharge */
 		*(u32 *)(CFG_SDRAM_BASE) = 0xA5A59696;
+		asm("nop");
  
 		/* Set RE (bit 15) in DACR */
 		MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE;
+		asm("nop");
  
 		/* Wait for at least 8 auto refresh cycles to occur */
 		for (i = 0; i < 2000; i++) {
@@ -85,6 +91,7 @@
  
 		/* Finish the configuration by issuing the IMRS. */
 		MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS;
+		asm("nop");
  
 		/* Write to the SDRAM Mode Register */
 		*(u32 *)(CFG_SDRAM_BASE + 0x400) = 0xA5A59696;
@@ -60,9 +60,8 @@
     lib_generic/string.o	(.text)
     lib_generic/vsprintf.o	(.text)
     lib_generic/crc32.o	(.text)
-    lib_generic/zlib.o	(.text)
  
-/*    . = env_offset; */
+    . = env_offset;
     common/environment.o(.text)
  
     *(.text)
@@ -442,7 +442,7 @@
 	MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE - 1) | MCFCSM_CSMR_V;
 #endif
 #else
-#waring "Chip Select 0 are not initialized/used"
+#warning "Chip Select 0 are not initialized/used"
 #endif
  
 #if defined(CFG_CS1_BASE) & defined(CFG_CS1_SIZE) & \
@@ -166,7 +166,7 @@
 #else
 	/* Setup code to initialize FLASHBAR, if start from external Memory */
 	move.l	#(CFG_INT_FLASH_BASE + CFG_INT_FLASH_ENABLE), %d0
-	movec	%d0, %RAMBAR1
+	movec	%d0, %FLASHBAR
 #endif /* (TEXT_BASE == CFG_INT_FLASH_BASE) */
  
 #endif
@@ -104,7 +104,7 @@
 #	define CONFIG_OVERWRITE_ETHADDR_ONCE
 #endif				/* CONFIG_MCFFEC */
  
-#define CONFIG_HOSTNAME		M5272C3
+#define CONFIG_HOSTNAME		M5282EVB
 #define CONFIG_EXTRA_ENV_SETTINGS		\
 	"netdev=eth0\0"				\
 	"loadaddr=10000\0"			\
@@ -134,7 +134,7 @@
 #define CFG_MEMTEST_START	0x400
 #define CFG_MEMTEST_END		0x380000
  
-#define CFG_HZ			1000000
+#define CFG_HZ			1000
 #define	CFG_CLK			64000000
  
 /* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
...	...	@@ -51,6 +51,7 @@
51	51	MCFSDRAMC_DCR = (0
52	52	\| MCFSDRAMC_DCR_RTIM_6
53	53	\| MCFSDRAMC_DCR_RC((15 * dramclk)>>4));
	54	+ asm("nop");
54	55
55	56	/* Initialize DACR0 */
56	57	MCFSDRAMC_DACR0 = (0
57	58
58	59
...	...	@@ -58,14 +59,17 @@
58	59	\| MCFSDRAMC_DACR_CASL(1)
59	60	\| MCFSDRAMC_DACR_CBM(3)
60	61	\| MCFSDRAMC_DACR_PS_32);
	62	+ asm("nop");
61	63
62	64	/* Initialize DMR0 */
63	65	MCFSDRAMC_DMR0 = (0
64	66	\| ((dramsize - 1) & 0xFFFC0000)
65	67	\| MCFSDRAMC_DMR_V);
	68	+ asm("nop");
66	69
67	70	/* Set IP (bit 3) in DACR */
68	71	MCFSDRAMC_DACR0 \|= MCFSDRAMC_DACR_IP;
	72	+ asm("nop");
69	73
70	74	/* Wait 30ns to allow banks to precharge */
71	75	for (i = 0; i < 5; i++) {
72	76
...	...	@@ -74,9 +78,11 @@
74	78
75	79	/* Write to this block to initiate precharge */
76	80	(u32 )(CFG_SDRAM_BASE) = 0xA5A59696;
	81	+ asm("nop");
77	82
78	83	/* Set RE (bit 15) in DACR */
79	84	MCFSDRAMC_DACR0 \|= MCFSDRAMC_DACR_RE;
	85	+ asm("nop");
80	86
81	87	/* Wait for at least 8 auto refresh cycles to occur */
82	88	for (i = 0; i < 2000; i++) {
...	...	@@ -85,6 +91,7 @@
85	91
86	92	/* Finish the configuration by issuing the IMRS. */
87	93	MCFSDRAMC_DACR0 \|= MCFSDRAMC_DACR_IMRS;
	94	+ asm("nop");
88	95
89	96	/* Write to the SDRAM Mode Register */
90	97	(u32 )(CFG_SDRAM_BASE + 0x400) = 0xA5A59696;
...	...	@@ -60,9 +60,8 @@
60	60	lib_generic/string.o (.text)
61	61	lib_generic/vsprintf.o (.text)
62	62	lib_generic/crc32.o (.text)
63		- lib_generic/zlib.o (.text)
64	63
65		-/* . = env_offset; */
	64	+ . = env_offset;
66	65	common/environment.o(.text)
67	66
68	67	*(.text)
...	...	@@ -442,7 +442,7 @@
442	442	MCFCSM_CSMR0 = MCFCSM_CSMR_BAM(CFG_CS0_SIZE - 1) \| MCFCSM_CSMR_V;
443	443	#endif
444	444	#else
445		-#waring "Chip Select 0 are not initialized/used"
	445	+#warning "Chip Select 0 are not initialized/used"
446	446	#endif
447	447
448	448	#if defined(CFG_CS1_BASE) & defined(CFG_CS1_SIZE) & \
...	...	@@ -166,7 +166,7 @@
166	166	#else
167	167	/* Setup code to initialize FLASHBAR, if start from external Memory */
168	168	move.l #(CFG_INT_FLASH_BASE + CFG_INT_FLASH_ENABLE), %d0
169		- movec %d0, %RAMBAR1
	169	+ movec %d0, %FLASHBAR
170	170	#endif /* (TEXT_BASE == CFG_INT_FLASH_BASE) */
171	171
172	172	#endif
...	...	@@ -104,7 +104,7 @@
104	104	# define CONFIG_OVERWRITE_ETHADDR_ONCE
105	105	#endif /* CONFIG_MCFFEC */
106	106
107		-#define CONFIG_HOSTNAME M5272C3
	107	+#define CONFIG_HOSTNAME M5282EVB
108	108	#define CONFIG_EXTRA_ENV_SETTINGS \
109	109	"netdev=eth0\0" \
110	110	"loadaddr=10000\0" \
...	...	@@ -134,7 +134,7 @@
134	134	#define CFG_MEMTEST_START 0x400
135	135	#define CFG_MEMTEST_END 0x380000
136	136
137		-#define CFG_HZ 1000000
	137	+#define CFG_HZ 1000
138	138	#define CFG_CLK 64000000
139	139
140	140	/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */