bcm281xx: add support for "USB OTG clock"

enable this clock with the following: clk_usb_otg_enable((void *)HSOTG_BASE_ADDR) Signed-off-by: Steve Rae <srae@broadcom.com> Reviewed-by: Felipe Balbi <balbi@ti.com>

bcm281xx: add support for "USB OTG clock"
enable this clock with the following: clk_usb_otg_enable((void *)HSOTG_BASE_ADDR) Signed-off-by: Steve Rae <srae@broadcom.com> Reviewed-by: Felipe Balbi <balbi@ti.com>
Steve Rae · Tom Rini
1 parent e38d1cb28c
Showing 6 changed files with 52 additions and 0 deletions Side-by-side Diff
arch/arm/cpu/armv7/bcm281xx/Makefile
arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c
arch/arm/cpu/armv7/bcm281xx/clk-usb-otg.c
arch/arm/cpu/armv7/kona-common/clk-stubs.c
arch/arm/include/asm/arch-bcm281xx/sysmap.h
arch/arm/include/asm/kona-common/clk.h
@@ -10,4 +10,5 @@
 obj-y	+= clk-sdio.o
 obj-y	+= clk-bsc.o
 obj-$(CONFIG_BCM_SF2_ETH) += clk-eth.o
+obj-y	+= clk-usb-otg.o
@@ -209,6 +209,10 @@
 	.gate		= SW_ONLY_GATE(0x0360, 20, 4),
 };
  
+static struct bus_clk_data usb_otg_ahb_data = {
+	.gate		= HW_SW_GATE_AUTO(0x0348, 16, 0, 1),
+};
+
 static struct bus_clk_data sdio1_ahb_data = {
 	.gate		= HW_SW_GATE_AUTO(0x0358, 16, 0, 1),
 };
@@ -331,6 +335,17 @@
  */
  
 /* KPM bus clocks */
+static struct bus_clock usb_otg_ahb_clk = {
+	.clk = {
+		.name = "usb_otg_ahb_clk",
+		.parent = &kpm_ccu_clk.clk,
+		.ops = &bus_clk_ops,
+		.ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+	},
+	.freq_tbl = master_ahb_freq_tbl,
+	.data = &usb_otg_ahb_data,
+};
+
 static struct bus_clock sdio1_ahb_clk = {
 	.clk = {
 		.name = "sdio1_ahb_clk",
@@ -541,6 +556,7 @@
 	CLK_LK(bsc2),
 	CLK_LK(bsc3),
 	/* Bus clocks */
+	CLK_LK(usb_otg_ahb),
 	CLK_LK(sdio1_ahb),
 	CLK_LK(sdio2_ahb),
 	CLK_LK(sdio3_ahb),
+/*
+ * Copyright 2014 Broadcom Corporation.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/errno.h>
+#include <asm/arch/sysmap.h>
+#include "clk-core.h"
+
+/* Enable appropriate clocks for the USB OTG port */
+int clk_usb_otg_enable(void *base)
+{
+	char *ahbstr;
+
+	switch ((u32) base) {
+	case HSOTG_BASE_ADDR:
+		ahbstr = "usb_otg_ahb_clk";
+		break;
+	default:
+		printf("%s: base 0x%p not found\n", __func__, base);
+		return -EINVAL;
+	}
+
+	return clk_get_and_enable(ahbstr);
+}
@@ -19,4 +19,9 @@
 {
 	return 0;
 }
+
+int __weak clk_usb_otg_enable(void *base)
+{
+	return 0;
+}
@@ -13,6 +13,8 @@
 #define ESUB_CLK_BASE_ADDR	0x38000000
 #define ESW_CONTRL_BASE_ADDR	0x38200000
 #define GPIO2_BASE_ADDR		0x35003000
+#define HSOTG_BASE_ADDR		0x3f120000
+#define HSOTG_CTRL_BASE_ADDR	0x3f130000
 #define KONA_MST_CLK_BASE_ADDR	0x3f001000
 #define KONA_SLV_CLK_BASE_ADDR	0x3e011000
 #define PMU_BSC_BASE_ADDR	0x3500d000
@@ -25,6 +25,7 @@
 struct clk *clk_get_parent(struct clk *clk);
 int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep);
 int clk_bsc_enable(void *base);
+int clk_usb_otg_enable(void *base);
  
 #endif
...	...	@@ -10,4 +10,5 @@
10	10	obj-y += clk-sdio.o
11	11	obj-y += clk-bsc.o
12	12	obj-$(CONFIG_BCM_SF2_ETH) += clk-eth.o
	13	+obj-y += clk-usb-otg.o
...	...	@@ -209,6 +209,10 @@
209	209	.gate = SW_ONLY_GATE(0x0360, 20, 4),
210	210	};
211	211
	212	+static struct bus_clk_data usb_otg_ahb_data = {
	213	+ .gate = HW_SW_GATE_AUTO(0x0348, 16, 0, 1),
	214	+};
	215	+
212	216	static struct bus_clk_data sdio1_ahb_data = {
213	217	.gate = HW_SW_GATE_AUTO(0x0358, 16, 0, 1),
214	218	};
...	...	@@ -331,6 +335,17 @@
331	335	*/
332	336
333	337	/* KPM bus clocks */
	338	+static struct bus_clock usb_otg_ahb_clk = {
	339	+ .clk = {
	340	+ .name = "usb_otg_ahb_clk",
	341	+ .parent = &kpm_ccu_clk.clk,
	342	+ .ops = &bus_clk_ops,
	343	+ .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
	344	+ },
	345	+ .freq_tbl = master_ahb_freq_tbl,
	346	+ .data = &usb_otg_ahb_data,
	347	+};
	348	+
334	349	static struct bus_clock sdio1_ahb_clk = {
335	350	.clk = {
336	351	.name = "sdio1_ahb_clk",
...	...	@@ -541,6 +556,7 @@
541	556	CLK_LK(bsc2),
542	557	CLK_LK(bsc3),
543	558	/* Bus clocks */
	559	+ CLK_LK(usb_otg_ahb),
544	560	CLK_LK(sdio1_ahb),
545	561	CLK_LK(sdio2_ahb),
546	562	CLK_LK(sdio3_ahb),
	1	+/*
	2	+ * Copyright 2014 Broadcom Corporation.
	3	+ *
	4	+ * SPDX-License-Identifier: GPL-2.0+
	5	+ */
	6	+
	7	+#include <common.h>
	8	+#include <asm/errno.h>
	9	+#include <asm/arch/sysmap.h>
	10	+#include "clk-core.h"
	11	+
	12	+/* Enable appropriate clocks for the USB OTG port */
	13	+int clk_usb_otg_enable(void *base)
	14	+{
	15	+ char *ahbstr;
	16	+
	17	+ switch ((u32) base) {
	18	+ case HSOTG_BASE_ADDR:
	19	+ ahbstr = "usb_otg_ahb_clk";
	20	+ break;
	21	+ default:
	22	+ printf("%s: base 0x%p not found\n", __func__, base);
	23	+ return -EINVAL;
	24	+ }
	25	+
	26	+ return clk_get_and_enable(ahbstr);
	27	+}
...	...	@@ -19,4 +19,9 @@
19	19	{
20	20	return 0;
21	21	}
	22	+
	23	+int __weak clk_usb_otg_enable(void *base)
	24	+{
	25	+ return 0;
	26	+}
...	...	@@ -13,6 +13,8 @@
13	13	#define ESUB_CLK_BASE_ADDR 0x38000000
14	14	#define ESW_CONTRL_BASE_ADDR 0x38200000
15	15	#define GPIO2_BASE_ADDR 0x35003000
	16	+#define HSOTG_BASE_ADDR 0x3f120000
	17	+#define HSOTG_CTRL_BASE_ADDR 0x3f130000
16	18	#define KONA_MST_CLK_BASE_ADDR 0x3f001000
17	19	#define KONA_SLV_CLK_BASE_ADDR 0x3e011000
18	20	#define PMU_BSC_BASE_ADDR 0x3500d000
...	...	@@ -25,6 +25,7 @@
25	25	struct clk clk_get_parent(struct clk clk);
26	26	int clk_sdio_enable(void base, u32 rate, u32 actual_ratep);
27	27	int clk_bsc_enable(void *base);
	28	+int clk_usb_otg_enable(void *base);
28	29
29	30	#endif